| commit | 817dbb43a06dee8ed9838d049cedf992c4c47321 | [log] [tgz] |
|---|---|---|
| author | dineshannayya <dinesh.annayya@gmail.com> | Thu Feb 10 12:31:15 2022 +0530 |
| committer | dineshannayya <dinesh.annayya@gmail.com> | Thu Feb 10 12:31:15 2022 +0530 |
| tree | 9a288e5f2db4944ca7051ecfcfc8da71337f8818 | |
| parent | edd716198950c7ba4bed0ef19f66e3686ed3410d [diff] |
git module update
diff --git a/.gitmodules b/.gitmodules index 9f8c7a0..df69a25 100644 --- a/.gitmodules +++ b/.gitmodules
@@ -4,6 +4,6 @@ [submodule "verilog/rtl/qspim"] path = verilog/rtl/qspim url = https://github.com/dineshannayya/qspim.git -[submodule "verilog/rtl/yifive/ycr1c1"] +[submodule "verilog/rtl/yifive/ycr1c"] path = verilog/rtl/yifive/ycr1c url = https://github.com/dineshannayya/ycr1c.git