test bench clean-up
diff --git a/Makefile b/Makefile
index f898ec3..aac51a9 100644
--- a/Makefile
+++ b/Makefile
@@ -16,7 +16,8 @@
CARAVEL_ROOT?=$(PWD)/caravel
PRECHECK_ROOT?=${HOME}/open_mpw_precheck
-SIM ?= RTL
+SIM?=RTL
+DUMP?=OFF
# Install lite version of caravel, (1): caravel-lite, (0): caravel
CARAVEL_LITE?=1
@@ -43,7 +44,7 @@
.PHONY: verify
verify:
cd ./verilog/dv/ && \
- export SIM=${SIM} && \
+ export SIM=${SIM} DUMP=${DUMP} && \
$(MAKE) -j$(THREADS)
# Install DV setup
@@ -55,7 +56,7 @@
DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
TARGET_PATH=$(shell pwd)
PDK_PATH=${PDK_ROOT}/sky130A
-VERIFY_COMMAND="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} && make"
+VERIFY_COMMAND="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} DUMP=${DUMP} && make"
$(DV_PATTERNS): verify-% : ./verilog/dv/%
@if [ ! -d "$(PDK_ROOT)" ]; then \
docker run -v ${TARGET_PATH}:${TARGET_PATH} \
diff --git a/README.md b/README.md
index 1d4882e..aaa083d 100644
--- a/README.md
+++ b/README.md
@@ -314,105 +314,53 @@
# SOC Pin Mapping
-Carvel SOC provides 38 GPIO pins for user functionality. Riscduino SOC GPIO Pin Mapping as follows
+Carvel SOC provides 38 GPIO pins for user functionality. Riscduino SOC GPIO Pin Mapping as follows vs ATMEGA328 and Arudino
<table>
- <tr>
- <td align="center"> GPIO Pin Number</td>
- <td align="center"> Direction</td>
- <td align="center"> Pad Name</td>
- <td align="center"> Block Name</td>
- </tr>
- <tr>
- <td align="center"> gpio[7:0]</td>
- <td align="center"> Inout</td>
- <td align="center"> SDRAM Data [7:0]</td>
- <td align="center"> SDRAM</td>
- </tr>
- <tr>
- <td align="center"> gpio[20:8]</td>
- <td align="center"> Output</td>
- <td align="center"> SDRAM Address [12:0]</td>
- <td align="center"> SDRAM</td>
- </tr>
- <tr>
- <td align="center"> gpio[22:21]</td>
- <td align="center"> Output</td>
- <td align="center"> SDRAM Bank Select [1:0]</td>
- <td align="center"> SDRAM</td>
- </tr>
- <tr>
- <td align="center"> gpio[23]</td>
- <td align="center"> Output</td>
- <td align="center"> SDRAM Byte Mask</td>
- <td align="center"> SDRAM</td>
- </tr>
- <tr>
- <td align="center"> gpio[24]</td>
- <td align="center"> Output</td>
- <td align="center"> SDRAM Write Enable</td>
- <td align="center"> SDRAM</td>
- </tr>
- <tr>
- <td align="center"> gpio[25]</td>
- <td align="center"> Output</td>
- <td align="center"> SDRAM CAS </td>
- <td align="center"> SDRAM</td>
- </tr>
- <tr>
- <td align="center"> gpio[26]</td>
- <td align="center"> Output</td>
- <td align="center"> SDRAM RAS </td>
- <td align="center"> SDRAM</td>
- </tr>
- <tr>
- <td align="center"> gpio[27]</td>
- <td align="center"> Output</td>
- <td align="center"> SDRAM Chip Select </td>
- <td align="center"> SDRAM</td>
- </tr>
- <tr>
- <td align="center"> gpio[28]</td>
- <td align="center"> Output</td>
- <td align="center"> SDRAM CKE </td>
- <td align="center"> SDRAM</td>
- </tr>
- <tr>
- <td align="center"> gpio[29]</td>
- <td align="center"> Inout</td>
- <td align="center"> SDRAM Clock</td>
- <td align="center"> SDRAM</td>
- </tr>
- <tr>
- <td align="center"> gpio[30]</td>
- <td align="center"> Output</td>
- <td align="center"> SPI Clock</td>
- <td align="center"> SPI</td>
- </tr>
- <tr>
- <td align="center"> gpio[31]</td>
- <td align="center"> Output</td>
- <td align="center"> SPI Chip Select</td>
- <td align="center"> SPI</td>
- </tr>
- <tr>
- <td align="center"> gpio[35:32]</td>
- <td align="center"> Inout</td>
- <td align="center"> SPI Data</td>
- <td align="center"> SPI</td>
- </tr>
- <tr>
- <td align="center"> gpio[36]</td>
- <td align="center"> Inout</td>
- <td align="center"> Uart TX/I2C CLK</td>
- <td align="center"> UART/I2C</td>
- </tr>
- <tr>
- <td align="center"> gpio[37]</td>
- <td align="center"> Inout</td>
- <td align="center"> Uart RX/I2C Data</td>
- <td align="center"> UART/I2C</td>
- </tr>
+ <tr align="center"> <td> ATMGA328 Pin No</td> <td> Functionality </td> <td> Arudino Pin Name</td> <td> Carvel Pin Mapping </td></tr>
+ <tr align="center"> <td> Pin-1 </td> <td> PC6/RESET </td> <td> </td> <td> digital_io[0] </td></tr>
+ <tr align="center"> <td> Pin-2 </td> <td> PD0/RXD </td> <td> D0 </td> <td> digital_io[1] </td></tr>
+ <tr align="center"> <td> Pin-3 </td> <td> PD1/TXD </td> <td> D1 </td> <td> digital_io[2] </td></tr>
+ <tr align="center"> <td> Pin-4 </td> <td> PD2/INT0 </td> <td> D2 </td> <td> digital_io[3] </td></tr>
+ <tr align="center"> <td> Pin-5 </td> <td> PD3/INT1/OC2B(PWM0) </td> <td> D3 </td> <td> digital_io[4] </td></tr>
+ <tr align="center"> <td> Pin-6 </td> <td> PD4 </td> <td> D4 </td> <td> digital_io[5] </td></tr>
+ <tr align="center"> <td> Pin-7 </td> <td> VCC </td> <td> </td> <td> - </td></tr>
+ <tr align="center"> <td> Pin-8 </td> <td> GND </td> <td> </td> <td> - </td></tr>
+ <tr align="center"> <td> Pin-9 </td> <td> PB6/XTAL1/TOSC1 </td> <td> </td> <td> digital_io[6] </td></tr>
+ <tr align="center"> <td> Pin-10 </td> <td> PB7/XTAL2/TOSC2 </td> <td> </td> <td> digital_io[7] </td></tr>
+ <tr align="center"> <td> Pin-11 </td> <td> PD5/OC0B(PWM1)/T1 </td> <td> D5 </td> <td> digital_io[8] </td></tr>
+ <tr align="center"> <td> Pin-12 </td> <td> PD6/OC0A(PWM2)/AIN0 </td> <td> D6 </td> <td> digital_io[9] /analog_io[2] </td></tr>
+ <tr align="center"> <td> Pin-13 </td> <td> PD7/A1N1 </td> <td> D7 </td> <td> digital_io[10]/analog_io[3] </td></tr>
+ <tr align="center"> <td> Pin-14 </td> <td> PB0/CLKO/ICP1 </td> <td> D8 </td> <td> digital_io[11] </td></tr>
+ <tr align="center"> <td> Pin-15 </td> <td> PB1/OC1A(PWM3) </td> <td> D9 </td> <td> digital_io[12] </td></tr>
+ <tr align="center"> <td> Pin-16 </td> <td> PB2/SS/OC1B(PWM4) </td> <td> D10 </td> <td> digital_io[13] </td></tr>
+ <tr align="center"> <td> Pin-17 </td> <td> PB3/MOSI/OC2A(PWM5) </td> <td> D11 </td> <td> digital_io[14] </td></tr>
+ <tr align="center"> <td> Pin-18 </td> <td> PB4/MISO </td> <td> D12 </td> <td> digital_io[15] </td></tr>
+ <tr align="center"> <td> Pin-19 </td> <td> PB5/SCK </td> <td> D13 </td> <td> digital_io[16] </td></tr>
+ <tr align="center"> <td> Pin-20 </td> <td> AVCC </td> <td> </td> <td> - </td></tr>
+ <tr align="center"> <td> Pin-21 </td> <td> AREF </td> <td> </td> <td> analog_io[10] </td></tr>
+ <tr align="center"> <td> Pin-22 </td> <td> GND </td> <td> </td> <td> - </td></tr>
+ <tr align="center"> <td> Pin-23 </td> <td> PC0/ADC0 </td> <td> A0 </td> <td> digital_io[18]/analog_io[11] </td></tr>
+ <tr align="center"> <td> Pin-24 </td> <td> PC1/ADC1 </td> <td> A1 </td> <td> digital_io[19]/analog_io[12] </td></tr>
+ <tr align="center"> <td> Pin-25 </td> <td> PC2/ADC2 </td> <td> A2 </td> <td> digital_io[20]/analog_io[13] </td></tr>
+ <tr align="center"> <td> Pin-26 </td> <td> PC3/ADC3 </td> <td> A3 </td> <td> digital_io[21]/analog_io[14] </td></tr>
+ <tr align="center"> <td> Pin-27 </td> <td> PC4/ADC4/SDA </td> <td> A4 </td> <td> digital_io[22]/analog_io[15] </td></tr>
+ <tr align="center"> <td> Pin-28 </td> <td> PC5/ADC5/SCL </td> <td> A5 </td> <td> digital_io[23]/analog_io[16] </td></tr>
+ <tr align="center"> <td colspan="4"> Additional Pad used for Externam ROM/RAM/USB </td></tr>
+ <tr align="center"> <td> Sflash </td> <td> sflash_sck </td> <td> </td> <td> digital_io[24] </td></tr>
+ <tr align="center"> <td> SFlash </td> <td> sflash_ss </td> <td> </td> <td> digital_io[25] </td></tr>
+ <tr align="center"> <td> SFlash </td> <td> sflash_io0 </td> <td> </td> <td> digital_io[26] </td></tr>
+ <tr align="center"> <td> SFlash </td> <td> sflash_io1 </td> <td> </td> <td> digital_io[27] </td></tr>
+ <tr align="center"> <td> SFlash </td> <td> sflash_io2 </td> <td> </td> <td> digital_io[28] </td></tr>
+ <tr align="center"> <td> SFlash </td> <td> sflash_io3 </td> <td> </td> <td> digital_io[29] </td></tr>
+ <tr align="center"> <td> SSRAM </td> <td> ssram_sck </td> <td> </td> <td> digital_io[30] </td></tr>
+ <tr align="center"> <td> SSRAM </td> <td> ssram_ss </td> <td> </td> <td> digital_io[31] </td></tr>
+ <tr align="center"> <td> SSRAM </td> <td> ssram_io0 </td> <td> </td> <td> digital_io[32] </td></tr>
+ <tr align="center"> <td> SSRAM </td> <td> ssram_io1 </td> <td> </td> <td> digital_io[33] </td></tr>
+ <tr align="center"> <td> SSRAM </td> <td> ssram_io2 </td> <td> </td> <td> digital_io[34] </td></tr>
+ <tr align="center"> <td> SSRAM </td> <td> ssram_io3 </td> <td> </td> <td> digital_io[35] </td></tr>
+ <tr align="center"> <td> usb1.1 </td> <td> usb_dp </td> <td> </td> <td> digital_io[36] </td></tr>
+ <tr align="center"> <td> usb1.1 </td> <td> usb_dn </td> <td> </td> <td> digital_io[37] </td></tr>
</table>
@@ -464,15 +412,45 @@
# Prerequisites
- Docker (ensure docker daemon is running) -- tested with version 19.03.12, but any recent version should suffice.
+## Step-1: Docker in ubuntu 20.04 version
+```bash
+ sudo apt update
+ sudo apt-get install apt-transport-https curl rtificates -agent software-properties-common
+ curl -fsSL https://download.docker.com/linux/ubuntu/gpg | sudo apt-key add -
+ sudo add-apt-repository "deb [arch=amd64] https://download.docker.com/linux/ubuntu focal stable"
+ sudo apt update
+ apt-cache policy docker-ce
+ sudo apt install docker-ce
-## Environment setting
+ #Add User Name to docker
+ sudo usermod -aG docker <your user name>
+ # Reboot the system to enable the docker setup
+```
+## Step-2: Update the Submodule, To to project area
+```bash
+ git submodule init
+ git submodule update
+```
+## Step-3: clone Openlane scripts under workarea
+```bash
+ git clone https://github.com/dineshannayya/OpenLane.git
+```
+## Step-4: Environment setting
- Note: PDK alreay installed inside the docker, no need to define the PDK_ROOT, This will be point to /opt/pdk path inside the docker
- if user define the PDK_ROOT path, then flow will use the user defined PDK PATH
+ if user define the PDK_ROOT path, then flow will use the user defined PDK PATH. Set these enviornmental variable in .bashrc file
```bash
export CARAVEL_ROOT=<Carvel Installed Path>
export OPENLANE_ROOT=<OpenLane Installed Path>
export IMAGE_NAME=dineshannayya/openlane:rc7
+ export PDK_ROOT=<PDK Installed PATH>
+ export PDK_PATH=<PDK Install Path>/sky130A
+```
+## Step-5: To install the PDK
+```bash
+ source ~/.bashrc
+ cd OpenLane
+ make pdk
```
# Tests preparation
@@ -494,6 +472,8 @@
make verify-user_spi
make verify-user_i2cm
make verify-user_risc_boot
+ make verify-wb_port SIM=RTL DUMP=OFF
+ make verify-wb_port SIM=RTL DUMP=ON
```
# Tool Sets
diff --git a/openlane/uart_i2cm_usb/base.sdc b/openlane/uart_i2cm_usb/base.sdc
index e5db97c..3d3a783 100644
--- a/openlane/uart_i2cm_usb/base.sdc
+++ b/openlane/uart_i2cm_usb/base.sdc
@@ -50,7 +50,6 @@
set_input_delay 2.0 -clock [get_clocks $::env(CORE_CLOCK_NAME)] {uart_rstn}
set_input_delay 2.0 -clock [get_clocks $::env(CORE_CLOCK_NAME)] {i2c_rstn}
set_input_delay 2.0 -clock [get_clocks $::env(CORE_CLOCK_NAME)] {usb_rstn}
-set_input_delay 2.0 -clock [get_clocks $::env(CORE_CLOCK_NAME)] {uart_i2c_usb_sel*}
set_input_delay $core_input_delay_value -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_cs*]
set_input_delay $core_input_delay_value -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_addr*]
diff --git a/openlane/uart_i2cm_usb/pin_order.cfg b/openlane/uart_i2cm_usb/pin_order.cfg
index 36b397b..cd4e00c 100644
--- a/openlane/uart_i2cm_usb/pin_order.cfg
+++ b/openlane/uart_i2cm_usb/pin_order.cfg
@@ -7,6 +7,10 @@
reg_cs
reg_wr
+reg_addr\[7\]
+reg_addr\[6\]
+reg_addr\[5\]
+reg_addr\[4\]
reg_addr\[3\]
reg_addr\[2\]
reg_addr\[1\]
@@ -83,8 +87,6 @@
uart_rstn
i2c_rstn
usb_rstn
-uart_i2c_usb_sel\[1\]
-uart_i2c_usb_sel\[0\]
scl_pad_i
scl_pad_o
scl_pad_oen_o
diff --git a/run_regress b/run_regress
new file mode 100644
index 0000000..a18199a
--- /dev/null
+++ b/run_regress
@@ -0,0 +1,6 @@
+make verify-wb_port
+make verify-user_spi
+make verify-user_i2cm
+make verify-user_uart
+make verify-user_risc_boot
+make verify-risc_boot
diff --git a/signoff/spi_master/OPENLANE_VERSION b/signoff/spi_master/OPENLANE_VERSION
index ad796aa..bab6e84 100644
--- a/signoff/spi_master/OPENLANE_VERSION
+++ b/signoff/spi_master/OPENLANE_VERSION
@@ -1 +1 @@
-openlane v0.21-6-gbc3b032
+openlane v0.21-9-g94fe743
diff --git a/signoff/spi_master/final_summary_report.csv b/signoff/spi_master/final_summary_report.csv
index 1c8a281..1349a9e 100644
--- a/signoff/spi_master/final_summary_report.csv
+++ b/signoff/spi_master/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/spi_master,spim_top,spi_master,Flow_completed,0h29m40s,0h16m11s,58500.0,0.26,29250.0,47,675.88,7605,0,0,0,0,0,0,0,0,1,-1,0,389393,66138,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,305945143,0.0,32.37,39.92,0.14,-1,-1,7541,7681,1272,1412,0,0,0,7605,245,0,169,100,1051,209,33,2443,1353,1292,24,460,3132,0,3592,100.0,10.0,10,AREA 0,4,50,1,100,100,0.45,0,sky130_fd_sc_hd,4,5
+0,/project/openlane/spi_master,spim_top,spi_master,Flow_completed,0h15m27s,0h6m28s,49784.61538461538,0.26,24892.30769230769,40,642.45,6472,0,0,0,0,0,0,0,0,2,-1,0,302442,55080,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,228497488,0.0,25.86,30.21,0.29,-1,-1,6415,6548,1120,1253,0,0,0,6472,243,0,125,93,756,212,32,1957,1213,1151,25,460,3132,0,3592,100.0,10.0,10,AREA 0,4,50,1,100,100,0.45,0,sky130_fd_sc_hd,4,5
diff --git a/signoff/uart_i2cm_usb/OPENLANE_VERSION b/signoff/uart_i2cm_usb/OPENLANE_VERSION
index ad796aa..bab6e84 100644
--- a/signoff/uart_i2cm_usb/OPENLANE_VERSION
+++ b/signoff/uart_i2cm_usb/OPENLANE_VERSION
@@ -1 +1 @@
-openlane v0.21-6-gbc3b032
+openlane v0.21-9-g94fe743
diff --git a/signoff/uart_i2cm_usb/final_summary_report.csv b/signoff/uart_i2cm_usb/final_summary_report.csv
index 4829488..ea00f72 100644
--- a/signoff/uart_i2cm_usb/final_summary_report.csv
+++ b/signoff/uart_i2cm_usb/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/uart_i2cm_usb,uart_i2c_usb_top,uart_i2cm_usb,Flow_completed,0h42m9s,0h23m0s,59219.047619047626,0.42,29609.523809523813,45,765.19,12436,0,0,0,0,0,0,0,0,0,-1,0,538778,100542,-2.99,-2.99,-2.96,-2.96,-3.03,-2.99,-2.99,-2.96,-2.96,-3.03,402935829,0.0,31.48,31.11,0.41,-1,-1,12415,12484,2256,2325,0,0,0,12436,363,10,209,250,2102,323,80,2681,2216,2171,28,498,5146,0,5644,76.74597083653109,13.03,10,AREA 0,4,50,1,100,100,0.45,0,sky130_fd_sc_hd,4,5
+0,/project/openlane/uart_i2cm_usb,uart_i2c_usb_top,uart_i2cm_usb,Flow_completed,0h27m5s,0h11m4s,59157.14285714286,0.42,29578.57142857143,45,751.94,12423,0,0,0,0,0,0,0,0,0,-1,0,522443,99881,-3.16,-3.16,-3.07,-3.07,-3.11,-91.08,-91.08,-91.67,-91.67,-91.56,390283627,0.0,31.24,29.46,0.31,-1,-1,12407,12476,2262,2331,0,0,0,12423,364,10,202,244,2118,325,79,2692,2224,2170,26,498,5146,0,5644,76.27765064836004,13.11,10,AREA 0,4,50,1,100,100,0.45,0,sky130_fd_sc_hd,4,5
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index ef20129..bc98a12 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h46m33s,0h5m18s,3.3079078455790785,10.2784,1.6539539227895392,0,531.62,17,0,0,0,0,0,0,0,0,1,-1,-1,1233053,4238,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.29,4.44,0.96,2.45,-1,902,1520,902,1520,0,0,0,17,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,80,0.55,0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h45m28s,0h6m19s,1.5566625155666252,10.2784,0.7783312577833126,0,530.74,8,0,0,0,0,0,0,0,0,3,-1,-1,1147543,4266,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.2,4.73,0.78,1.3,-1,870,1488,867,1485,0,0,0,8,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,120,120,0.55,0,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_interconnect/final_summary_report.csv b/signoff/wb_interconnect/final_summary_report.csv
index d183141..897ae64 100644
--- a/signoff/wb_interconnect/final_summary_report.csv
+++ b/signoff/wb_interconnect/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,Flow_completed,0h24m29s,0h4m56s,8169.69696969697,0.33,4084.848484848485,7,559.88,1348,0,0,0,0,0,0,0,0,0,-1,0,417538,17849,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,375201274,0.0,39.41,7.47,21.49,-1,-1,1074,1695,202,823,0,0,0,1348,240,0,73,15,135,0,0,176,447,428,11,94,3794,0,3888,100.0,10.0,10,AREA 0,4,50,1,180,180,0.5,0,sky130_fd_sc_hd,4,5
+0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,Flow_completed,0h28m1s,0h5m22s,8218.181818181818,0.33,4109.090909090909,7,563.42,1356,0,0,0,0,0,0,0,0,0,-1,0,423449,18327,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,378093628,0.0,39.98,7.52,21.72,-1,-1,1079,1703,202,826,0,0,0,1356,240,0,73,15,135,0,0,176,447,431,11,94,3794,0,3888,100.0,10.0,10,AREA 0,4,50,1,180,180,0.5,0,sky130_fd_sc_hd,4,5
diff --git a/verilog/dv/risc_boot/Makefile b/verilog/dv/risc_boot/Makefile
index dcb19ed..bd7c2e7 100644
--- a/verilog/dv/risc_boot/Makefile
+++ b/verilog/dv/risc_boot/Makefile
@@ -63,6 +63,7 @@
${GCC64_PREFIX}-objdump -D user_uart.elf > user_uart.dump
rm crt_tcm.o user_uart.o
ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
@@ -70,6 +71,15 @@
-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
-I $(UPRJ_INCLUDE_PATH4) \
$< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_AGENTS) \
+ -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
+ -I $(UPRJ_INCLUDE_PATH4) \
+ $< -o $@
+ endif
else
iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
diff --git a/verilog/dv/risc_boot/risc_boot.c b/verilog/dv/risc_boot/risc_boot.c
index e5253b2..3921642 100644
--- a/verilog/dv/risc_boot/risc_boot.c
+++ b/verilog/dv/risc_boot/risc_boot.c
@@ -23,22 +23,22 @@
#define reg_mprj_wbhost_reg0 (*(volatile uint32_t*)0x30800000)
-#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x30000000)
-#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x30000004)
-#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x30000008)
-#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x3000000C)
-#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x30000010)
-#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x30000014)
-#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x30000018)
-#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x3000001C)
-#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x30000020)
-#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x30000024)
-#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x30000028)
-#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x3000002C)
-#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x30000030)
-#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x30000034)
-#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30000038)
-#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3000003C)
+#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x30030000)
+#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x30030004)
+#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x30030008)
+#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x3003000C)
+#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x30030010)
+#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x30030014)
+#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x30030018)
+#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x3003001C)
+#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x30030020)
+#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x30030024)
+#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x30030028)
+#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x3003002C)
+#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x30030030)
+#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x30030034)
+#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30030038)
+#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3003003C)
#define reg_mprj_uart_reg0 (*(volatile uint32_t*)0x30010000)
#define reg_mprj_uart_reg1 (*(volatile uint32_t*)0x30010004)
@@ -172,16 +172,13 @@
// Remove Wishbone Reset
reg_mprj_wbhost_reg0 = 0x1;
- // SDRAM Config-2
- reg_mprj_globl_reg5 = 0x100019E;
-
-
- // SDRAM Config-1
- reg_mprj_globl_reg4 = 0x2F172242;
// Remove All Reset
reg_mprj_wbhost_reg0 = 0x1F;
+ // Enable UART Multi Functional Ports
+
+ reg_mprj_globl_reg14 = 0x100;
// configure the user uart
reg_mprj_uart_reg0 = 0x7;
diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v
index fca35ca..0d59657 100644
--- a/verilog/dv/risc_boot/risc_boot_tb.v
+++ b/verilog/dv/risc_boot/risc_boot_tb.v
@@ -297,12 +297,12 @@
// Connect Quad Flash to for usr Risc Core
//-----------------------------------------
- wire user_flash_clk = mprj_io[30];
- wire user_flash_csb = mprj_io[31];
- //tri user_flash_io0 = mprj_io[33];
- //tri user_flash_io1 = mprj_io[34];
- //tri user_flash_io2 = mprj_io[35];
- //tri user_flash_io3 = mprj_io[36];
+ wire user_flash_clk = mprj_io[24];
+ wire user_flash_csb = mprj_io[25];
+ //tri user_flash_io0 = mprj_io[26];
+ //tri user_flash_io1 = mprj_io[27];
+ //tri user_flash_io2 = mprj_io[28];
+ //tri user_flash_io3 = mprj_io[29];
// Quard flash
@@ -311,68 +311,24 @@
.TimingModel("S25FL512SAGMFI010_F_30pF"))
u_spi_flash_256mb (
// Data Inputs/Outputs
- .SI (mprj_io[32]),
- .SO (mprj_io[33]),
+ .SI (mprj_io[26]),
+ .SO (mprj_io[27]),
// Controls
.SCK (user_flash_clk),
.CSNeg (user_flash_csb),
- .WPNeg (mprj_io[34]),
- .HOLDNeg (mprj_io[35]),
+ .WPNeg (mprj_io[28]),
+ .HOLDNeg (mprj_io[29]),
.RSTNeg (RSTB)
);
-//------------------------------------------------
-// Integrate the SDRAM 8 BIT Memory
-// -----------------------------------------------
-
-tri [7:0] Dq ; // SDRAM Read/Write Data Bus
-wire [0:0] sdr_dqm ; // SDRAM DATA Mask
-wire [1:0] sdr_ba ; // SDRAM Bank Select
-wire [12:0] sdr_addr ; // SDRAM ADRESS
-wire sdr_cs_n ; // chip select
-wire sdr_cke ; // clock gate
-wire sdr_ras_n ; // ras
-wire sdr_cas_n ; // cas
-wire sdr_we_n ; // write enable
-wire sdram_clk ;
-
-//assign Dq[7:0] = mprj_io [7:0];
-assign sdr_addr[12:0] = mprj_io [20:8] ;
-assign sdr_ba[1:0] = mprj_io [22:21] ;
-assign sdr_dqm[0] = mprj_io [23] ;
-assign sdr_we_n = mprj_io [24] ;
-assign sdr_cas_n = mprj_io [25] ;
-assign sdr_ras_n = mprj_io [26] ;
-assign sdr_cs_n = mprj_io [27] ;
-assign sdr_cke = mprj_io [28] ;
-assign sdram_clk = mprj_io [29] ;
-
-// to fix the sdram interface timing issue
-wire #(2.0) sdram_clk_d = sdram_clk;
-
- // SDRAM 8bit
-mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
- .Dq (mprj_io [7:0] ) ,
- .Addr (sdr_addr[11:0] ),
- .Ba (sdr_ba ),
- .Clk (sdram_clk_d ),
- .Cke (sdr_cke ),
- .Cs_n (sdr_cs_n ),
- .Ras_n (sdr_ras_n ),
- .Cas_n (sdr_cas_n ),
- .We_n (sdr_we_n ),
- .Dqm (sdr_dqm )
- );
-
-
//---------------------------
// UART Agent integration
// --------------------------
wire uart_txd,uart_rxd;
-assign uart_txd = mprj_io[37];
-assign mprj_io[36] = uart_rxd ;
+assign uart_txd = mprj_io[2];
+assign mprj_io[1] = uart_rxd ;
uart_agent tb_uart(
.mclk (clock ),
diff --git a/verilog/dv/risc_boot/user_uart.c b/verilog/dv/risc_boot/user_uart.c
index b60311c..29805f7 100644
--- a/verilog/dv/risc_boot/user_uart.c
+++ b/verilog/dv/risc_boot/user_uart.c
@@ -35,15 +35,15 @@
#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30000038)
#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3000003C)
-#define reg_mprj_uart_reg0 (*(volatile uint32_t*)0x30010000)
-#define reg_mprj_uart_reg1 (*(volatile uint32_t*)0x30010004)
-#define reg_mprj_uart_reg2 (*(volatile uint32_t*)0x30010008)
-#define reg_mprj_uart_reg3 (*(volatile uint32_t*)0x3001000C)
-#define reg_mprj_uart_reg4 (*(volatile uint32_t*)0x30010010)
-#define reg_mprj_uart_reg5 (*(volatile uint32_t*)0x30010014)
-#define reg_mprj_uart_reg6 (*(volatile uint32_t*)0x30010018)
-#define reg_mprj_uart_reg7 (*(volatile uint32_t*)0x3001001C)
-#define reg_mprj_uart_reg8 (*(volatile uint32_t*)0x30010020)
+#define reg_mprj_uart_reg0 (*(volatile uint32_t*)0x10010000)
+#define reg_mprj_uart_reg1 (*(volatile uint32_t*)0x10010004)
+#define reg_mprj_uart_reg2 (*(volatile uint32_t*)0x10010008)
+#define reg_mprj_uart_reg3 (*(volatile uint32_t*)0x1001000C)
+#define reg_mprj_uart_reg4 (*(volatile uint32_t*)0x10010010)
+#define reg_mprj_uart_reg5 (*(volatile uint32_t*)0x10010014)
+#define reg_mprj_uart_reg6 (*(volatile uint32_t*)0x10010018)
+#define reg_mprj_uart_reg7 (*(volatile uint32_t*)0x1001001C)
+#define reg_mprj_uart_reg8 (*(volatile uint32_t*)0x10010020)
int main()
{
diff --git a/verilog/dv/user_i2cm/Makefile b/verilog/dv/user_i2cm/Makefile
index 089a877..c1654ac 100644
--- a/verilog/dv/user_i2cm/Makefile
+++ b/verilog/dv/user_i2cm/Makefile
@@ -64,6 +64,7 @@
${GCC64_PREFIX}-objdump -D user_uart.elf > user_uart.dump
rm crt_tcm.o user_uart.o
ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
@@ -71,6 +72,15 @@
-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
-I $(UPRJ_INCLUDE_PATH4) \
$< -o $@
+ else
+ iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_AGENTS) \
+ -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
+ -I $(UPRJ_INCLUDE_PATH4) \
+ $< -o $@
+ endif
else
iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
diff --git a/verilog/dv/user_i2cm/uprj_netlists.v b/verilog/dv/user_i2cm/uprj_netlists.v
index 647e7c5..0c7d867 100644
--- a/verilog/dv/user_i2cm/uprj_netlists.v
+++ b/verilog/dv/user_i2cm/uprj_netlists.v
@@ -28,7 +28,7 @@
`include "glbl_cfg.v"
`include "sdram.v"
`include "spi_master.v"
- `include "uart_i2cm.v"
+ `include "uart_i2cm_usb.v"
`include "wb_interconnect.v"
`include "user_project_wrapper.v"
`include "syntacore.v"
@@ -42,6 +42,19 @@
`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
+ `include"sar_adc/SAR.sv"
+ `include"sar_adc/ACMP.sv"
+ `include"sar_adc/sar_adc.sv"
+ `include"sar_adc/adc_reg.sv"
+ `include"sar_adc/DAC_8BIT.v"
+
+ `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+ `include "pinmux/src/pinmux.sv"
+ `include "pinmux/src/pinmux_reg.sv"
+ `include "pinmux/src/gpio_intr.sv"
+ `include "pinmux/src/pwm.sv"
+ `include "lib/pulse_gen_type1.sv"
+ `include "lib/pulse_gen_type2.sv"
`include "spi_master/src/spim_top.sv"
`include "spi_master/src/spim_if.sv"
@@ -76,18 +89,9 @@
`include "uart_i2c_usb/src/uart_i2c_usb.sv"
- `include "sdram_ctrl/src/top/sdrc_top.v"
- `include "sdram_ctrl/src/wb2sdrc/wb2sdrc.v"
- `include "lib/async_fifo.sv"
- `include "sdram_ctrl/src/core/sdrc_core.v"
- `include "sdram_ctrl/src/core/sdrc_bank_ctl.v"
- `include "sdram_ctrl/src/core/sdrc_bank_fsm.v"
- `include "sdram_ctrl/src/core/sdrc_bs_convert.v"
- `include "sdram_ctrl/src/core/sdrc_req_gen.v"
- `include "sdram_ctrl/src/core/sdrc_xfr_ctl.v"
-
`include "lib/registers.v"
`include "lib/clk_ctl.v"
+ `include "lib/async_fifo.sv"
`include "digital_core/src/glbl_cfg.sv"
`include "wb_host/src/wb_host.sv"
@@ -122,6 +126,7 @@
`include "syntacore/scr1/src/core/scr1_dmi.sv"
`include "syntacore/scr1/src/core/scr1_scu.sv"
+ `include "syntacore/scr1/src/top/scr1_imem_router.sv"
`include "syntacore/scr1/src/top/scr1_dmem_router.sv"
`include "syntacore/scr1/src/top/scr1_dp_memory.sv"
`include "syntacore/scr1/src/top/scr1_tcm.sv"
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v
index 650c9de..825dfc2 100644
--- a/verilog/dv/user_i2cm/user_i2cm_tb.v
+++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -72,7 +72,7 @@
`define ADDR_SPACE_UART 32'h3001_0000
-`define ADDR_SPACE_I2CM 32'h3001_0000
+`define ADDR_SPACE_I2CM 32'h3001_0040
module tb_top;
@@ -152,6 +152,9 @@
// Enable I2M Block & WB Reset and Enable I2CM Mux Select
wb_user_core_write('h3080_0000,'hA1);
+ // Enable I2C Multi Functional Ports
+ wb_user_core_write('h3003_0038,'h200);
+
repeat (100) @(posedge clock);
@(posedge clock);
@@ -460,22 +463,22 @@
// user core using the gpio pads
// ----------------------------------------------------
- wire flash_clk = io_out[30];
- wire flash_csb = io_out[31];
+ wire flash_clk = io_out[24];
+ wire flash_csb = io_out[25];
// Creating Pad Delay
- wire #1 io_oeb_32 = io_oeb[32];
- wire #1 io_oeb_33 = io_oeb[33];
- wire #1 io_oeb_34 = io_oeb[34];
- wire #1 io_oeb_35 = io_oeb[35];
- tri flash_io0 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz;
- tri flash_io1 = (io_oeb_33== 1'b0) ? io_out[33] : 1'bz;
- tri flash_io2 = (io_oeb_34== 1'b0) ? io_out[34] : 1'bz;
- tri flash_io3 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
+ wire #1 io_oeb_26 = io_oeb[26];
+ wire #1 io_oeb_27 = io_oeb[27];
+ wire #1 io_oeb_28 = io_oeb[28];
+ wire #1 io_oeb_29 = io_oeb[29];
+ tri flash_io0 = (io_oeb_26== 1'b0) ? io_out[26] : 1'bz;
+ tri flash_io1 = (io_oeb_27== 1'b0) ? io_out[27] : 1'bz;
+ tri flash_io2 = (io_oeb_28== 1'b0) ? io_out[28] : 1'bz;
+ tri flash_io3 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz;
- assign io_in[32] = flash_io0;
- assign io_in[33] = flash_io1;
- assign io_in[34] = flash_io2;
- assign io_in[35] = flash_io3;
+ assign io_in[26] = flash_io0;
+ assign io_in[27] = flash_io1;
+ assign io_in[28] = flash_io2;
+ assign io_in[29] = flash_io3;
// Quard flash
@@ -498,61 +501,15 @@
-//------------------------------------------------
-// Integrate the SDRAM 8 BIT Memory
-// -----------------------------------------------
-
-wire [7:0] Dq ; // SDRAM Read/Write Data Bus
-wire [0:0] sdr_dqm ; // SDRAM DATA Mask
-wire [1:0] sdr_ba ; // SDRAM Bank Select
-wire [12:0] sdr_addr ; // SDRAM ADRESS
-wire sdr_cs_n ; // chip select
-wire sdr_cke ; // clock gate
-wire sdr_ras_n ; // ras
-wire sdr_cas_n ; // cas
-wire sdr_we_n ; // write enable
-wire sdram_clk ;
-
-assign Dq[7:0] = (io_oeb[7:0] == 8'h0) ? io_out [7:0] : 8'hZZ;
-assign sdr_addr[12:0] = io_out [20:8] ;
-assign sdr_ba[1:0] = io_out [22:21] ;
-assign sdr_dqm[0] = io_out [23] ;
-assign sdr_we_n = io_out [24] ;
-assign sdr_cas_n = io_out [25] ;
-assign sdr_ras_n = io_out [26] ;
-assign sdr_cs_n = io_out [27] ;
-assign sdr_cke = io_out [28] ;
-assign sdram_clk = io_out [29] ;
-assign io_in[29] = sdram_clk;
-assign #(1) io_in[7:0] = Dq;
-
-// to fix the sdram interface timing issue
-wire #(1) sdram_clk_d = sdram_clk;
-
- // SDRAM 8bit
-mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
- .Dq (Dq ) ,
- .Addr (sdr_addr[11:0] ),
- .Ba (sdr_ba ),
- .Clk (sdram_clk_d ),
- .Cke (sdr_cke ),
- .Cs_n (sdr_cs_n ),
- .Ras_n (sdr_ras_n ),
- .Cas_n (sdr_cas_n ),
- .We_n (sdr_we_n ),
- .Dqm (sdr_dqm )
- );
-
-
//---------------------------
-// UART Agent integration
+// I2C
// --------------------------
tri scl,sda;
-assign scl = (io_oeb[36] == 1'b0) ? io_out[36]: 1'bz;
-assign sda = (io_oeb[37] == 1'b0) ? io_out[37] : 1'bz;
-assign io_in[37] = sda;
-assign io_in[36] = scl;
+assign sda = (io_oeb[22] == 1'b0) ? io_out[22] : 1'bz;
+assign scl = (io_oeb[23] == 1'b0) ? io_out[23]: 1'bz;
+assign io_in[22] = sda;
+assign io_in[23] = scl;
pullup p1(scl); // pullup scl line
pullup p2(sda); // pullup sda line
diff --git a/verilog/dv/user_i2cm/user_uart.c b/verilog/dv/user_i2cm/user_uart.c
index b60311c..b86f23b 100644
--- a/verilog/dv/user_i2cm/user_uart.c
+++ b/verilog/dv/user_i2cm/user_uart.c
@@ -18,23 +18,6 @@
#define SC_SIM_OUTPORT (0xf0000000)
#define uint32_t long
-#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x30000000)
-#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x30000004)
-#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x30000008)
-#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x3000000C)
-#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x30000010)
-#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x30000014)
-#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x30000018)
-#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x3000001C)
-#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x30000020)
-#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x30000024)
-#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x30000028)
-#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x3000002C)
-#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x30000030)
-#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x30000034)
-#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30000038)
-#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3000003C)
-
#define reg_mprj_uart_reg0 (*(volatile uint32_t*)0x30010000)
#define reg_mprj_uart_reg1 (*(volatile uint32_t*)0x30010004)
#define reg_mprj_uart_reg2 (*(volatile uint32_t*)0x30010008)
diff --git a/verilog/dv/user_risc_boot/Makefile b/verilog/dv/user_risc_boot/Makefile
index c01b1ed..3a03931 100644
--- a/verilog/dv/user_risc_boot/Makefile
+++ b/verilog/dv/user_risc_boot/Makefile
@@ -64,6 +64,7 @@
${GCC64_PREFIX}-objdump -D user_risc_boot.elf > user_risc_boot.dump
rm crt_tcm.o user_risc_boot.o
ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
@@ -71,6 +72,15 @@
-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
-I $(UPRJ_INCLUDE_PATH4) \
$< -o $@
+ else
+ iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_AGENTS) \
+ -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
+ -I $(UPRJ_INCLUDE_PATH4) \
+ $< -o $@
+ endif
else
iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
diff --git a/verilog/dv/user_risc_boot/uprj_netlists.v b/verilog/dv/user_risc_boot/uprj_netlists.v
index e53865f..0c7d867 100644
--- a/verilog/dv/user_risc_boot/uprj_netlists.v
+++ b/verilog/dv/user_risc_boot/uprj_netlists.v
@@ -34,6 +34,7 @@
`include "syntacore.v"
`include "wb_host.v"
`include "clk_skew_adjust.v"
+ `include "clk_buf.v"
`else
`include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
@@ -41,6 +42,19 @@
`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
+ `include"sar_adc/SAR.sv"
+ `include"sar_adc/ACMP.sv"
+ `include"sar_adc/sar_adc.sv"
+ `include"sar_adc/adc_reg.sv"
+ `include"sar_adc/DAC_8BIT.v"
+
+ `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+ `include "pinmux/src/pinmux.sv"
+ `include "pinmux/src/pinmux_reg.sv"
+ `include "pinmux/src/gpio_intr.sv"
+ `include "pinmux/src/pwm.sv"
+ `include "lib/pulse_gen_type1.sv"
+ `include "lib/pulse_gen_type2.sv"
`include "spi_master/src/spim_top.sv"
`include "spi_master/src/spim_if.sv"
@@ -75,18 +89,9 @@
`include "uart_i2c_usb/src/uart_i2c_usb.sv"
- `include "sdram_ctrl/src/top/sdrc_top.v"
- `include "sdram_ctrl/src/wb2sdrc/wb2sdrc.v"
- `include "lib/async_fifo.sv"
- `include "sdram_ctrl/src/core/sdrc_core.v"
- `include "sdram_ctrl/src/core/sdrc_bank_ctl.v"
- `include "sdram_ctrl/src/core/sdrc_bank_fsm.v"
- `include "sdram_ctrl/src/core/sdrc_bs_convert.v"
- `include "sdram_ctrl/src/core/sdrc_req_gen.v"
- `include "sdram_ctrl/src/core/sdrc_xfr_ctl.v"
-
`include "lib/registers.v"
`include "lib/clk_ctl.v"
+ `include "lib/async_fifo.sv"
`include "digital_core/src/glbl_cfg.sv"
`include "wb_host/src/wb_host.sv"
@@ -121,6 +126,7 @@
`include "syntacore/scr1/src/core/scr1_dmi.sv"
`include "syntacore/scr1/src/core/scr1_scu.sv"
+ `include "syntacore/scr1/src/top/scr1_imem_router.sv"
`include "syntacore/scr1/src/top/scr1_dmem_router.sv"
`include "syntacore/scr1/src/top/scr1_dp_memory.sv"
`include "syntacore/scr1/src/top/scr1_tcm.sv"
diff --git a/verilog/dv/user_risc_boot/user_risc_boot.c b/verilog/dv/user_risc_boot/user_risc_boot.c
index af9339d..63b2e6a 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot.c
+++ b/verilog/dv/user_risc_boot/user_risc_boot.c
@@ -18,22 +18,34 @@
#define SC_SIM_OUTPORT (0xf0000000)
#define uint32_t long
-#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x30000000)
-#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x30000004)
-#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x30000008)
-#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x3000000C)
-#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x30000010)
-#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x30000014)
-#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x30000018)
-#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x3000001C)
-#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x30000020)
-#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x30000024)
-#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x30000028)
-#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x3000002C)
-#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x30000030)
-#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x30000034)
-#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30000038)
-#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3000003C)
+#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10030000)
+#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10030004)
+#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10030008)
+#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1003000C)
+#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10030010)
+#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10030014)
+#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x10030018)
+#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x1003001C)
+#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x10030020)
+#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x10030024)
+#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x10030028)
+#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x1003002C)
+#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x10030030)
+#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x10030034)
+#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x10030038)
+#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x1003003C)
+#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x10030040)
+#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x10030044)
+#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x10030048)
+#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x1003004C)
+#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x10030050)
+#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x10030054)
+#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x10030058)
+#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x1003005C)
+#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x10030060)
+#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x10030064)
+#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x10030068)
+#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x1003006C)
int main()
{
@@ -45,12 +57,12 @@
//*out_ptr = 0xDDEEFF00;
// Write software Write & Read Register
- reg_mprj_globl_reg6 = 0x11223344;
- reg_mprj_globl_reg7 = 0x22334455;
- reg_mprj_globl_reg8 = 0x33445566;
- reg_mprj_globl_reg9 = 0x44556677;
- reg_mprj_globl_reg10 = 0x55667788;
- reg_mprj_globl_reg11 = 0x66778899;
+ reg_mprj_globl_reg22 = 0x11223344;
+ reg_mprj_globl_reg23 = 0x22334455;
+ reg_mprj_globl_reg24 = 0x33445566;
+ reg_mprj_globl_reg25 = 0x44556677;
+ reg_mprj_globl_reg26 = 0x55667788;
+ reg_mprj_globl_reg27 = 0x66778899;
//reg_mprj_globl_reg12 = 0x778899AA;
//reg_mprj_globl_reg13 = 0x8899AABB;
//reg_mprj_globl_reg14 = 0x99AABBCC;
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
index 82f0d44..aeb9867 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -29,8 +29,9 @@
//// user_risc_boot.c ////
//// 2. User Risc core uses Serial Flash and SDRAM to boot ////
//// 3. After successful boot, Risc core will write signature ////
-//// in to user register from 0x3000_0018 to 0x3000_002C ////
+//// in to user register from 0x1003_0058 to 0x1003_006C ////
//// 4. Through the External Wishbone Interface we read back ////
+//// from 0x3003_0058 to 0x3003_006C ////
//// and validate the user register to declared pass fail ////
//// ////
//// To Do: ////
@@ -136,17 +137,8 @@
repeat (10) @(posedge clock);
$display("Monitor: Standalone User Risc Boot Test Started");
- // Remove Wb Reset
- wb_user_core_write('h3080_0000,'h1);
-
- #1;
- //------------ SDRAM Config - 2
- wb_user_core_write('h3000_0014,'h100_019E);
-
- repeat (2) @(posedge clock);
- #1;
- //------------ SDRAM Config - 1
- wb_user_core_write('h3000_0010,'h2F17_2242);
+ // Remove Wb Reset
+ wb_user_core_write('h3080_0000,'h1);
repeat (2) @(posedge clock);
#1;
@@ -172,22 +164,22 @@
// 0x3000002C = 0x66778899;
test_fail = 0;
- wb_user_core_read(32'h30000018,read_data);
+ wb_user_core_read(32'h30030058,read_data);
if(read_data != 32'h11223344) test_fail = 1;
- wb_user_core_read(32'h3000001C,read_data);
+ wb_user_core_read(32'h3003005C,read_data);
if(read_data != 32'h22334455) test_fail = 1;
- wb_user_core_read(32'h30000020,read_data);
+ wb_user_core_read(32'h30030060,read_data);
if(read_data != 32'h33445566) test_fail = 1;
- wb_user_core_read(32'h30000024,read_data);
+ wb_user_core_read(32'h30030064,read_data);
if(read_data!= 32'h44556677) test_fail = 1;
- wb_user_core_read(32'h30000028,read_data);
+ wb_user_core_read(32'h30030068,read_data);
if(read_data!= 32'h55667788) test_fail = 1;
- wb_user_core_read(32'h3000002C,read_data) ;
+ wb_user_core_read(32'h3003006C,read_data) ;
if(read_data != 32'h66778899) test_fail = 1;
@@ -374,22 +366,22 @@
// user core using the gpio pads
// ----------------------------------------------------
- wire flash_clk = io_out[30];
- wire flash_csb = io_out[31];
+ wire flash_clk = io_out[24];
+ wire flash_csb = io_out[25];
// Creating Pad Delay
- wire #1 io_oeb_32 = io_oeb[32];
- wire #1 io_oeb_33 = io_oeb[33];
- wire #1 io_oeb_34 = io_oeb[34];
- wire #1 io_oeb_35 = io_oeb[35];
- tri flash_io0 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz;
- tri flash_io1 = (io_oeb_33== 1'b0) ? io_out[33] : 1'bz;
- tri flash_io2 = (io_oeb_34== 1'b0) ? io_out[34] : 1'bz;
- tri flash_io3 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
+ wire #1 io_oeb_26 = io_oeb[26];
+ wire #1 io_oeb_27 = io_oeb[27];
+ wire #1 io_oeb_28 = io_oeb[28];
+ wire #1 io_oeb_29 = io_oeb[29];
+ tri flash_io0 = (io_oeb_26== 1'b0) ? io_out[26] : 1'bz;
+ tri flash_io1 = (io_oeb_27== 1'b0) ? io_out[27] : 1'bz;
+ tri flash_io2 = (io_oeb_28== 1'b0) ? io_out[28] : 1'bz;
+ tri flash_io3 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz;
- assign io_in[32] = flash_io0;
- assign io_in[33] = flash_io1;
- assign io_in[34] = flash_io2;
- assign io_in[35] = flash_io3;
+ assign io_in[26] = flash_io0;
+ assign io_in[27] = flash_io1;
+ assign io_in[28] = flash_io2;
+ assign io_in[29] = flash_io3;
// Quard flash
@@ -411,51 +403,6 @@
-//------------------------------------------------
-// Integrate the SDRAM 8 BIT Memory
-// -----------------------------------------------
-
-wire [7:0] Dq ; // SDRAM Read/Write Data Bus
-wire [0:0] sdr_dqm ; // SDRAM DATA Mask
-wire [1:0] sdr_ba ; // SDRAM Bank Select
-wire [12:0] sdr_addr ; // SDRAM ADRESS
-wire sdr_cs_n ; // chip select
-wire sdr_cke ; // clock gate
-wire sdr_ras_n ; // ras
-wire sdr_cas_n ; // cas
-wire sdr_we_n ; // write enable
-wire sdram_clk ;
-
-assign Dq[7:0] = (io_oeb[7:0] == 8'h0) ? io_out [7:0] : 8'hZZ;
-assign sdr_addr[12:0] = io_out [20:8] ;
-assign sdr_ba[1:0] = io_out [22:21] ;
-assign sdr_dqm[0] = io_out [23] ;
-assign sdr_we_n = io_out [24] ;
-assign sdr_cas_n = io_out [25] ;
-assign sdr_ras_n = io_out [26] ;
-assign sdr_cs_n = io_out [27] ;
-assign sdr_cke = io_out [28] ;
-assign sdram_clk = io_out [29] ;
-assign io_in[29] = sdram_clk;
-assign #(1) io_in[7:0] = Dq;
-
-// to fix the sdram interface timing issue
-wire #(1) sdram_clk_d = sdram_clk;
-
- // SDRAM 8bit
-mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
- .Dq (Dq ) ,
- .Addr (sdr_addr[11:0] ),
- .Ba (sdr_ba ),
- .Clk (sdram_clk_d ),
- .Cke (sdr_cke ),
- .Cs_n (sdr_cs_n ),
- .Ras_n (sdr_ras_n ),
- .Cas_n (sdr_cas_n ),
- .We_n (sdr_we_n ),
- .Dqm (sdr_dqm )
- );
-
task wb_user_core_write;
input [31:0] address;
diff --git a/verilog/dv/user_spi/Makefile b/verilog/dv/user_spi/Makefile
index bc48c2a..96527bf 100644
--- a/verilog/dv/user_spi/Makefile
+++ b/verilog/dv/user_spi/Makefile
@@ -64,6 +64,7 @@
${GCC64_PREFIX}-objdump -D user_risc_boot.elf > user_risc_boot.dump
rm crt_tcm.o user_risc_boot.o
ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
@@ -71,6 +72,15 @@
-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
-I $(UPRJ_INCLUDE_PATH4) \
$< -o $@
+ else
+ iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_AGENTS) \
+ -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
+ -I $(UPRJ_INCLUDE_PATH4) \
+ $< -o $@
+ endif
else
iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
diff --git a/verilog/dv/user_spi/run_iverilog b/verilog/dv/user_spi/run_iverilog
index eb92eae..fedabc3 100755
--- a/verilog/dv/user_spi/run_iverilog
+++ b/verilog/dv/user_spi/run_iverilog
@@ -27,15 +27,17 @@
rm crt_tcm.o user_risc_boot.o
-#iverilog with waveform dump
-#iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $PDK_PATH -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/rtl -I ../ -I ../../../verilog -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_spi_tb.v -o user_spi_tb.vvp
#iverilog without Dump
-iverilog -g2005-sv -D WFDUMP -DFUNCTIONAL -DSIM -I $PDK_PATH -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/rtl -I ../ -I ../../../verilog -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_spi_tb.v -o user_spi_tb.vvp
+iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $PDK_PATH \
+-I ../../caravel/verilog/dv/caravel -I ../../caravel/verilog/rtl \
+-I ../model -I ../../../verilog/rtl -I ../../../verilog \
+-I ../agents \
+-I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I ../../../verilog/rtl/i2cm/src/includes \
+-I ../../../verilog/rtl/usb1_host/src/includes \
+user_spi_tb.v -o user_spi.vvp
-# GLS
-#iverilog -g2005-sv -D GL -D FUNCTIONAL -I $PDK_PATH -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/gl -I ../../../verilog -I /home/dinesha/workarea/pdk/sky130A -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_spi_tb.v -o user_spi_tb.vvp
-#
+
vvp user_spi_tb.vvp | tee test.log
diff --git a/verilog/dv/user_spi/uprj_netlists.v b/verilog/dv/user_spi/uprj_netlists.v
index 9e61482..0c7d867 100644
--- a/verilog/dv/user_spi/uprj_netlists.v
+++ b/verilog/dv/user_spi/uprj_netlists.v
@@ -42,6 +42,19 @@
`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
+ `include"sar_adc/SAR.sv"
+ `include"sar_adc/ACMP.sv"
+ `include"sar_adc/sar_adc.sv"
+ `include"sar_adc/adc_reg.sv"
+ `include"sar_adc/DAC_8BIT.v"
+
+ `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+ `include "pinmux/src/pinmux.sv"
+ `include "pinmux/src/pinmux_reg.sv"
+ `include "pinmux/src/gpio_intr.sv"
+ `include "pinmux/src/pwm.sv"
+ `include "lib/pulse_gen_type1.sv"
+ `include "lib/pulse_gen_type2.sv"
`include "spi_master/src/spim_top.sv"
`include "spi_master/src/spim_if.sv"
@@ -76,18 +89,9 @@
`include "uart_i2c_usb/src/uart_i2c_usb.sv"
- `include "sdram_ctrl/src/top/sdrc_top.v"
- `include "sdram_ctrl/src/wb2sdrc/wb2sdrc.v"
- `include "lib/async_fifo.sv"
- `include "sdram_ctrl/src/core/sdrc_core.v"
- `include "sdram_ctrl/src/core/sdrc_bank_ctl.v"
- `include "sdram_ctrl/src/core/sdrc_bank_fsm.v"
- `include "sdram_ctrl/src/core/sdrc_bs_convert.v"
- `include "sdram_ctrl/src/core/sdrc_req_gen.v"
- `include "sdram_ctrl/src/core/sdrc_xfr_ctl.v"
-
`include "lib/registers.v"
`include "lib/clk_ctl.v"
+ `include "lib/async_fifo.sv"
`include "digital_core/src/glbl_cfg.sv"
`include "wb_host/src/wb_host.sv"
@@ -122,6 +126,7 @@
`include "syntacore/scr1/src/core/scr1_dmi.sv"
`include "syntacore/scr1/src/core/scr1_scu.sv"
+ `include "syntacore/scr1/src/top/scr1_imem_router.sv"
`include "syntacore/scr1/src/top/scr1_dmem_router.sv"
`include "syntacore/scr1/src/top/scr1_dp_memory.sv"
`include "syntacore/scr1/src/top/scr1_tcm.sv"
diff --git a/verilog/dv/user_spi/user_risc_boot.c b/verilog/dv/user_spi/user_risc_boot.c
index af9339d..0711b7b 100644
--- a/verilog/dv/user_spi/user_risc_boot.c
+++ b/verilog/dv/user_spi/user_risc_boot.c
@@ -18,22 +18,34 @@
#define SC_SIM_OUTPORT (0xf0000000)
#define uint32_t long
-#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x30000000)
-#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x30000004)
-#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x30000008)
-#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x3000000C)
-#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x30000010)
-#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x30000014)
-#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x30000018)
-#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x3000001C)
-#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x30000020)
-#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x30000024)
-#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x30000028)
-#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x3000002C)
-#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x30000030)
-#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x30000034)
-#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30000038)
-#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3000003C)
+#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x30030000)
+#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x30030004)
+#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x30030008)
+#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x3003000C)
+#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x30030010)
+#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x30030014)
+#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x30030018)
+#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x3003001C)
+#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x30030020)
+#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x30030024)
+#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x30030028)
+#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x3003002C)
+#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x30030030)
+#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x30030034)
+#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30030038)
+#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3003003C)
+#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x30030040)
+#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x30030044)
+#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x30030048)
+#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x3003004C)
+#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x30030050)
+#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x30030054)
+#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x30030058)
+#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x3003005C)
+#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x30030060)
+#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x30030064)
+#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x30030068)
+#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x3003006C)
int main()
{
@@ -45,16 +57,12 @@
//*out_ptr = 0xDDEEFF00;
// Write software Write & Read Register
- reg_mprj_globl_reg6 = 0x11223344;
- reg_mprj_globl_reg7 = 0x22334455;
- reg_mprj_globl_reg8 = 0x33445566;
- reg_mprj_globl_reg9 = 0x44556677;
- reg_mprj_globl_reg10 = 0x55667788;
- reg_mprj_globl_reg11 = 0x66778899;
- //reg_mprj_globl_reg12 = 0x778899AA;
- //reg_mprj_globl_reg13 = 0x8899AABB;
- //reg_mprj_globl_reg14 = 0x99AABBCC;
- //reg_mprj_globl_reg15 = 0xAABBCCDD;
+ reg_mprj_globl_reg22 = 0x11223344;
+ reg_mprj_globl_reg23 = 0x22334455;
+ reg_mprj_globl_reg24 = 0x33445566;
+ reg_mprj_globl_reg25 = 0x44556677;
+ reg_mprj_globl_reg26 = 0x55667788;
+ reg_mprj_globl_reg27 = 0x66778899;
while(1) {}
return 0;
diff --git a/verilog/dv/user_spi/user_spi_tb.v b/verilog/dv/user_spi/user_spi_tb.v
index 15c0c2e..53b793f 100644
--- a/verilog/dv/user_spi/user_spi_tb.v
+++ b/verilog/dv/user_spi/user_spi_tb.v
@@ -24,14 +24,20 @@
//// ////
//// Description ////
//// This is a standalone test bench to validate the ////
-//// Digital core. ////
-//// 1. User Risc core is booted using compiled code of ////
-//// user_risc_boot.c ////
-//// 2. User Risc core uses Serial Flash and SDRAM to boot ////
-//// 3. After successful boot, Risc core will write signature ////
-//// in to user register from 0x3000_0018 to 0x3000_002C ////
-//// 4. Through the External Wishbone Interface we read back ////
-//// and validate the user register to declared pass fail ////
+//// Digital core flash access through External WB i/F. ////
+//// 1. Check SPI Read Identification ////
+//// 2. Check the Direct Memory Read (Qual/Single/Quad) ////
+//// 3. Direct SPI Memory Prefetch - 3DW ////
+//// 4. Direct SPI Memory Prefetch - 2DW ////
+//// 5. Direct SPI Memory Prefetch - 1DW ////
+//// 6. Direct SPI Memory Prefetch - 7DW ////
+//// 7. 1DW Indirect Read ////
+//// 8. 2DW Indirect Read ////
+//// 9. 3DW Indirect Read ////
+//// 10. 4DW Indirect Read ////
+//// 11. 5DW Indirect Read ////
+//// 12. 8DW Indirect Read ////
+//// 13. Sector Erase command + Page Write & Read Back ////
//// ////
//// To Do: ////
//// nothing ////
@@ -40,7 +46,7 @@
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//// Revision : ////
-//// 0.1 - 16th Feb 2021, Dinesh A ////
+//// 0.1 - 01 Oct 2021, Dinesh A ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
@@ -203,7 +209,7 @@
wb_user_core_read_check(32'h1000001C,read_data,32'h00190201);
$display("#############################################");
$display("Testing Direct SPI Memory Read ");
- $display(" SPI Mode: QDDR (Dual 4 but) ");
+ $display(" SPI Mode: QDDR (Dual 4 bit) ");
$display("Prefetch : 1DW, OPCODE:READ(0xED) ");
$display("SEQ: Command -> Address -> Read Data ");
$display("#############################################");
@@ -220,14 +226,14 @@
wb_user_core_read_check(32'h00000214,read_data,32'h00000313);
wb_user_core_read_check(32'h00000218,read_data,32'h00000393);
wb_user_core_read_check(32'h0000021C,read_data,32'h00000413);
- wb_user_core_read_check(32'h00000400,read_data,32'h11223737);
- wb_user_core_read_check(32'h00000404,read_data,32'h300007b7);
- wb_user_core_read_check(32'h00000408,read_data,32'h34470293);
- wb_user_core_read_check(32'h0000040C,read_data,32'h22334337);
- wb_user_core_read_check(32'h00000410,read_data,32'h0057ac23);
- wb_user_core_read_check(32'h00000414,read_data,32'h45530393);
- wb_user_core_read_check(32'h00000418,read_data,32'h33445537);
- wb_user_core_read_check(32'h0000041C,read_data,32'h0077ae23);
+ wb_user_core_read_check(32'h00000300,read_data,32'h0005A023);
+ wb_user_core_read_check(32'h00000304,read_data,32'h9DE30591);
+ wb_user_core_read_check(32'h00000308,read_data,32'h02B7FEE5);
+ wb_user_core_read_check(32'h0000030C,read_data,32'h43050049);
+ wb_user_core_read_check(32'h00000310,read_data,32'h0062A023);
+ wb_user_core_read_check(32'h00000314,read_data,32'h004902B7);
+ wb_user_core_read_check(32'h00000318,read_data,32'h00428293);
+ wb_user_core_read_check(32'h0000031C,read_data,32'h06300313);
$display("#############################################");
$display("Testing Direct SPI Memory Read ");
$display(" SPI Mode: Normal/Single Bit ");
@@ -246,14 +252,14 @@
wb_user_core_read_check(32'h00000214,read_data,32'h00000313);
wb_user_core_read_check(32'h00000218,read_data,32'h00000393);
wb_user_core_read_check(32'h0000021C,read_data,32'h00000413);
- wb_user_core_read_check(32'h00000400,read_data,32'h11223737);
- wb_user_core_read_check(32'h00000404,read_data,32'h300007b7);
- wb_user_core_read_check(32'h00000408,read_data,32'h34470293);
- wb_user_core_read_check(32'h0000040C,read_data,32'h22334337);
- wb_user_core_read_check(32'h00000410,read_data,32'h0057ac23);
- wb_user_core_read_check(32'h00000414,read_data,32'h45530393);
- wb_user_core_read_check(32'h00000418,read_data,32'h33445537);
- wb_user_core_read_check(32'h0000041C,read_data,32'h0077ae23);
+ wb_user_core_read_check(32'h00000300,read_data,32'h0005A023);
+ wb_user_core_read_check(32'h00000304,read_data,32'h9DE30591);
+ wb_user_core_read_check(32'h00000308,read_data,32'h02B7FEE5);
+ wb_user_core_read_check(32'h0000030C,read_data,32'h43050049);
+ wb_user_core_read_check(32'h00000310,read_data,32'h0062A023);
+ wb_user_core_read_check(32'h00000314,read_data,32'h004902B7);
+ wb_user_core_read_check(32'h00000318,read_data,32'h00428293);
+ wb_user_core_read_check(32'h0000031C,read_data,32'h06300313);
$display("#############################################");
$display("Testing Direct SPI Memory Read ");
$display(" SPI Mode: Normal/Single Bit ");
@@ -272,14 +278,14 @@
wb_user_core_read_check(32'h00000214,read_data,32'h00000313);
wb_user_core_read_check(32'h00000218,read_data,32'h00000393);
wb_user_core_read_check(32'h0000021C,read_data,32'h00000413);
- wb_user_core_read_check(32'h00000400,read_data,32'h11223737);
- wb_user_core_read_check(32'h00000404,read_data,32'h300007b7);
- wb_user_core_read_check(32'h00000408,read_data,32'h34470293);
- wb_user_core_read_check(32'h0000040C,read_data,32'h22334337);
- wb_user_core_read_check(32'h00000410,read_data,32'h0057ac23);
- wb_user_core_read_check(32'h00000414,read_data,32'h45530393);
- wb_user_core_read_check(32'h00000418,read_data,32'h33445537);
- wb_user_core_read_check(32'h0000041C,read_data,32'h0077ae23);
+ wb_user_core_read_check(32'h00000300,read_data,32'h0005A023);
+ wb_user_core_read_check(32'h00000304,read_data,32'h9DE30591);
+ wb_user_core_read_check(32'h00000308,read_data,32'h02B7FEE5);
+ wb_user_core_read_check(32'h0000030C,read_data,32'h43050049);
+ wb_user_core_read_check(32'h00000310,read_data,32'h0062A023);
+ wb_user_core_read_check(32'h00000314,read_data,32'h004902B7);
+ wb_user_core_read_check(32'h00000318,read_data,32'h00428293);
+ wb_user_core_read_check(32'h0000031C,read_data,32'h06300313);
$display("#############################################");
$display("Testing Direct SPI Memory Read ");
@@ -299,14 +305,14 @@
wb_user_core_read_check(32'h00000214,read_data,32'h00000313);
wb_user_core_read_check(32'h00000218,read_data,32'h00000393);
wb_user_core_read_check(32'h0000021C,read_data,32'h00000413);
- wb_user_core_read_check(32'h00000400,read_data,32'h11223737);
- wb_user_core_read_check(32'h00000404,read_data,32'h300007b7);
- wb_user_core_read_check(32'h00000408,read_data,32'h34470293);
- wb_user_core_read_check(32'h0000040C,read_data,32'h22334337);
- wb_user_core_read_check(32'h00000410,read_data,32'h0057ac23);
- wb_user_core_read_check(32'h00000414,read_data,32'h45530393);
- wb_user_core_read_check(32'h00000418,read_data,32'h33445537);
- wb_user_core_read_check(32'h0000041C,read_data,32'h0077ae23);
+ wb_user_core_read_check(32'h00000300,read_data,32'h0005A023);
+ wb_user_core_read_check(32'h00000304,read_data,32'h9DE30591);
+ wb_user_core_read_check(32'h00000308,read_data,32'h02B7FEE5);
+ wb_user_core_read_check(32'h0000030C,read_data,32'h43050049);
+ wb_user_core_read_check(32'h00000310,read_data,32'h0062A023);
+ wb_user_core_read_check(32'h00000314,read_data,32'h004902B7);
+ wb_user_core_read_check(32'h00000318,read_data,32'h00428293);
+ wb_user_core_read_check(32'h0000031C,read_data,32'h06300313);
$display("#############################################");
$display("Testing Direct SPI Memory Read with Prefetch");
@@ -326,14 +332,14 @@
wb_user_core_read_check(32'h00000214,read_data,32'h00000313);
wb_user_core_read_check(32'h00000218,read_data,32'h00000393);
wb_user_core_read_check(32'h0000021C,read_data,32'h00000413);
- wb_user_core_read_check(32'h00000400,read_data,32'h11223737);
- wb_user_core_read_check(32'h00000404,read_data,32'h300007b7);
- wb_user_core_read_check(32'h00000408,read_data,32'h34470293);
- wb_user_core_read_check(32'h0000040C,read_data,32'h22334337);
- wb_user_core_read_check(32'h00000410,read_data,32'h0057ac23);
- wb_user_core_read_check(32'h00000414,read_data,32'h45530393);
- wb_user_core_read_check(32'h00000418,read_data,32'h33445537);
- wb_user_core_read_check(32'h0000041C,read_data,32'h0077ae23);
+ wb_user_core_read_check(32'h00000300,read_data,32'h0005A023);
+ wb_user_core_read_check(32'h00000304,read_data,32'h9DE30591);
+ wb_user_core_read_check(32'h00000308,read_data,32'h02B7FEE5);
+ wb_user_core_read_check(32'h0000030C,read_data,32'h43050049);
+ wb_user_core_read_check(32'h00000310,read_data,32'h0062A023);
+ wb_user_core_read_check(32'h00000314,read_data,32'h004902B7);
+ wb_user_core_read_check(32'h00000318,read_data,32'h00428293);
+ wb_user_core_read_check(32'h0000031C,read_data,32'h06300313);
$display("#############################################");
$display("Testing Direct SPI Memory Read with Prefetch:3DW");
@@ -350,14 +356,14 @@
wb_user_core_read_check(32'h00000214,read_data,32'h00000313);
wb_user_core_read_check(32'h00000218,read_data,32'h00000393);
wb_user_core_read_check(32'h0000021C,read_data,32'h00000413);
- wb_user_core_read_check(32'h00000400,read_data,32'h11223737);
- wb_user_core_read_check(32'h00000404,read_data,32'h300007b7);
- wb_user_core_read_check(32'h00000408,read_data,32'h34470293);
- wb_user_core_read_check(32'h0000040C,read_data,32'h22334337);
- wb_user_core_read_check(32'h00000410,read_data,32'h0057ac23);
- wb_user_core_read_check(32'h00000414,read_data,32'h45530393);
- wb_user_core_read_check(32'h00000418,read_data,32'h33445537);
- wb_user_core_read_check(32'h0000041C,read_data,32'h0077ae23);
+ wb_user_core_read_check(32'h00000300,read_data,32'h0005A023);
+ wb_user_core_read_check(32'h00000304,read_data,32'h9DE30591);
+ wb_user_core_read_check(32'h00000308,read_data,32'h02B7FEE5);
+ wb_user_core_read_check(32'h0000030C,read_data,32'h43050049);
+ wb_user_core_read_check(32'h00000310,read_data,32'h0062A023);
+ wb_user_core_read_check(32'h00000314,read_data,32'h004902B7);
+ wb_user_core_read_check(32'h00000318,read_data,32'h00428293);
+ wb_user_core_read_check(32'h0000031C,read_data,32'h06300313);
$display("#############################################");
$display("Testing Direct SPI Memory Read with Prefetch:2DW");
@@ -374,14 +380,15 @@
wb_user_core_read_check(32'h00000214,read_data,32'h00000313);
wb_user_core_read_check(32'h00000218,read_data,32'h00000393);
wb_user_core_read_check(32'h0000021C,read_data,32'h00000413);
- wb_user_core_read_check(32'h00000400,read_data,32'h11223737);
- wb_user_core_read_check(32'h00000404,read_data,32'h300007b7);
- wb_user_core_read_check(32'h00000408,read_data,32'h34470293);
- wb_user_core_read_check(32'h0000040C,read_data,32'h22334337);
- wb_user_core_read_check(32'h00000410,read_data,32'h0057ac23);
- wb_user_core_read_check(32'h00000414,read_data,32'h45530393);
- wb_user_core_read_check(32'h00000418,read_data,32'h33445537);
- wb_user_core_read_check(32'h0000041C,read_data,32'h0077ae23);
+ wb_user_core_read_check(32'h00000300,read_data,32'h0005A023);
+ wb_user_core_read_check(32'h00000304,read_data,32'h9DE30591);
+ wb_user_core_read_check(32'h00000308,read_data,32'h02B7FEE5);
+ wb_user_core_read_check(32'h0000030C,read_data,32'h43050049);
+ wb_user_core_read_check(32'h00000310,read_data,32'h0062A023);
+ wb_user_core_read_check(32'h00000314,read_data,32'h004902B7);
+ wb_user_core_read_check(32'h00000318,read_data,32'h00428293);
+ wb_user_core_read_check(32'h0000031C,read_data,32'h06300313);
+
$display("#############################################");
$display("Testing Direct SPI Memory Read with Prefetch:1DW");
@@ -398,14 +405,14 @@
wb_user_core_read_check(32'h00000214,read_data,32'h00000313);
wb_user_core_read_check(32'h00000218,read_data,32'h00000393);
wb_user_core_read_check(32'h0000021C,read_data,32'h00000413);
- wb_user_core_read_check(32'h00000400,read_data,32'h11223737);
- wb_user_core_read_check(32'h00000404,read_data,32'h300007b7);
- wb_user_core_read_check(32'h00000408,read_data,32'h34470293);
- wb_user_core_read_check(32'h0000040C,read_data,32'h22334337);
- wb_user_core_read_check(32'h00000410,read_data,32'h0057ac23);
- wb_user_core_read_check(32'h00000414,read_data,32'h45530393);
- wb_user_core_read_check(32'h00000418,read_data,32'h33445537);
- wb_user_core_read_check(32'h0000041C,read_data,32'h0077ae23);
+ wb_user_core_read_check(32'h00000300,read_data,32'h0005A023);
+ wb_user_core_read_check(32'h00000304,read_data,32'h9DE30591);
+ wb_user_core_read_check(32'h00000308,read_data,32'h02B7FEE5);
+ wb_user_core_read_check(32'h0000030C,read_data,32'h43050049);
+ wb_user_core_read_check(32'h00000310,read_data,32'h0062A023);
+ wb_user_core_read_check(32'h00000314,read_data,32'h004902B7);
+ wb_user_core_read_check(32'h00000318,read_data,32'h00428293);
+ wb_user_core_read_check(32'h0000031C,read_data,32'h06300313);
$display("#############################################");
$display("Testing Direct SPI Memory Read with Prefetch:7DW");
@@ -422,14 +429,14 @@
wb_user_core_read_check(32'h00000214,read_data,32'h00000313);
wb_user_core_read_check(32'h00000218,read_data,32'h00000393);
wb_user_core_read_check(32'h0000021C,read_data,32'h00000413);
- wb_user_core_read_check(32'h00000400,read_data,32'h11223737);
- wb_user_core_read_check(32'h00000404,read_data,32'h300007b7);
- wb_user_core_read_check(32'h00000408,read_data,32'h34470293);
- wb_user_core_read_check(32'h0000040C,read_data,32'h22334337);
- wb_user_core_read_check(32'h00000410,read_data,32'h0057ac23);
- wb_user_core_read_check(32'h00000414,read_data,32'h45530393);
- wb_user_core_read_check(32'h00000418,read_data,32'h33445537);
- wb_user_core_read_check(32'h0000041C,read_data,32'h0077ae23);
+ wb_user_core_read_check(32'h00000300,read_data,32'h0005A023);
+ wb_user_core_read_check(32'h00000304,read_data,32'h9DE30591);
+ wb_user_core_read_check(32'h00000308,read_data,32'h02B7FEE5);
+ wb_user_core_read_check(32'h0000030C,read_data,32'h43050049);
+ wb_user_core_read_check(32'h00000310,read_data,32'h0062A023);
+ wb_user_core_read_check(32'h00000314,read_data,32'h004902B7);
+ wb_user_core_read_check(32'h00000318,read_data,32'h00428293);
+ wb_user_core_read_check(32'h0000031C,read_data,32'h06300313);
$display("#############################################");
$display(" Testing Single Word Indirect SPI Memory Read");
@@ -453,22 +460,22 @@
wb_user_core_read_check(32'h1000001C,read_data,32'h00000393);
wb_user_core_write(32'h10000014,32'h0000021C);
wb_user_core_read_check(32'h1000001C,read_data,32'h00000413);
- wb_user_core_write(32'h10000014,32'h00000400);
- wb_user_core_read_check(32'h1000001C,read_data,32'h11223737);
- wb_user_core_write(32'h10000014,32'h00000404);
- wb_user_core_read_check(32'h1000001C,read_data,32'h300007b7);
- wb_user_core_write(32'h10000014,32'h00000408);
- wb_user_core_read_check(32'h1000001C,read_data,32'h34470293);
- wb_user_core_write(32'h10000014,32'h0000040C);
- wb_user_core_read_check(32'h1000001C,read_data,32'h22334337);
- wb_user_core_write(32'h10000014,32'h00000410);
- wb_user_core_read_check(32'h1000001C,read_data,32'h0057ac23);
- wb_user_core_write(32'h10000014,32'h00000414);
- wb_user_core_read_check(32'h1000001C,read_data,32'h45530393);
- wb_user_core_write(32'h10000014,32'h00000418);
- wb_user_core_read_check(32'h1000001C,read_data,32'h33445537);
- wb_user_core_write(32'h10000014,32'h0000041C);
- wb_user_core_read_check(32'h1000001C,read_data,32'h0077ae23);
+ wb_user_core_write(32'h10000014,32'h00000300);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h0005A023);
+ wb_user_core_write(32'h10000014,32'h00000304);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h9DE30591);
+ wb_user_core_write(32'h10000014,32'h00000308);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h02B7FEE5);
+ wb_user_core_write(32'h10000014,32'h0000030C);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h43050049);
+ wb_user_core_write(32'h10000014,32'h00000310);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h0062A023);
+ wb_user_core_write(32'h10000014,32'h00000314);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h004902B7);
+ wb_user_core_write(32'h10000014,32'h00000318);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00428293);
+ wb_user_core_write(32'h10000014,32'h0000031C);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h06300313);
repeat (100) @(posedge clock);
$display("#############################################");
$display(" Testing Two Word Indirect SPI Memory Read");
@@ -488,18 +495,18 @@
wb_user_core_write(32'h10000014,32'h00000218);
wb_user_core_read_check(32'h1000001C,read_data,32'h00000393);
wb_user_core_read_check(32'h1000001C,read_data,32'h00000413);
- wb_user_core_write(32'h10000014,32'h00000400);
- wb_user_core_read_check(32'h1000001C,read_data,32'h11223737);
- wb_user_core_read_check(32'h1000001C,read_data,32'h300007b7);
- wb_user_core_write(32'h10000014,32'h00000408);
- wb_user_core_read_check(32'h1000001C,read_data,32'h34470293);
- wb_user_core_read_check(32'h1000001C,read_data,32'h22334337);
- wb_user_core_write(32'h10000014,32'h00000410);
- wb_user_core_read_check(32'h1000001C,read_data,32'h0057ac23);
- wb_user_core_read_check(32'h1000001C,read_data,32'h45530393);
- wb_user_core_write(32'h10000014,32'h00000418);
- wb_user_core_read_check(32'h1000001C,read_data,32'h33445537);
- wb_user_core_read_check(32'h1000001C,read_data,32'h0077ae23);
+ wb_user_core_write(32'h10000014,32'h00000300);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h0005A023);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h9DE30591);
+ wb_user_core_write(32'h10000014,32'h00000308);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h02B7FEE5);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h43050049);
+ wb_user_core_write(32'h10000014,32'h00000310);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h0062A023);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h004902B7);
+ wb_user_core_write(32'h10000014,32'h00000318);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00428293);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h06300313);
repeat (100) @(posedge clock);
$display("#############################################");
$display(" Testing Three Word Indirect SPI Memory Read");
@@ -515,14 +522,14 @@
wb_user_core_read_check(32'h1000001C,read_data,32'h00000213);
wb_user_core_read_check(32'h1000001C,read_data,32'h00000293);
wb_user_core_read_check(32'h1000001C,read_data,32'h00000313);
- wb_user_core_write(32'h10000014,32'h00000400);
- wb_user_core_read_check(32'h1000001C,read_data,32'h11223737);
- wb_user_core_read_check(32'h1000001C,read_data,32'h300007b7);
- wb_user_core_read_check(32'h1000001C,read_data,32'h34470293);
- wb_user_core_write(32'h10000014,32'h0000040C);
- wb_user_core_read_check(32'h1000001C,read_data,32'h22334337);
- wb_user_core_read_check(32'h1000001C,read_data,32'h0057ac23);
- wb_user_core_read_check(32'h1000001C,read_data,32'h45530393);
+ wb_user_core_write(32'h10000014,32'h00000300);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h0005A023);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h9DE30591);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h02B7FEE5);
+ wb_user_core_write(32'h10000014,32'h0000030C);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h43050049);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h0062A023);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h004902B7);
repeat (100) @(posedge clock);
$display("#############################################");
$display(" Testing Four Word Indirect SPI Memory Read");
@@ -540,16 +547,16 @@
wb_user_core_read_check(32'h1000001C,read_data,32'h00000313);
wb_user_core_read_check(32'h1000001C,read_data,32'h00000393);
wb_user_core_read_check(32'h1000001C,read_data,32'h00000413);
- wb_user_core_write(32'h10000014,32'h00000400);
- wb_user_core_read_check(32'h1000001C,read_data,32'h11223737);
- wb_user_core_read_check(32'h1000001C,read_data,32'h300007b7);
- wb_user_core_read_check(32'h1000001C,read_data,32'h34470293);
- wb_user_core_read_check(32'h1000001C,read_data,32'h22334337);
- wb_user_core_write(32'h10000014,32'h00000410);
- wb_user_core_read_check(32'h1000001C,read_data,32'h0057ac23);
- wb_user_core_read_check(32'h1000001C,read_data,32'h45530393);
- wb_user_core_read_check(32'h1000001C,read_data,32'h33445537);
- wb_user_core_read_check(32'h1000001C,read_data,32'h0077ae23);
+ wb_user_core_write(32'h10000014,32'h00000300);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h0005A023);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h9DE30591);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h02B7FEE5);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h43050049);
+ wb_user_core_write(32'h10000014,32'h00000310);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h0062A023);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h004902B7);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00428293);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h06300313);
repeat (100) @(posedge clock);
$display("#############################################");
$display(" Testing Five Word Indirect SPI Memory Read");
@@ -563,12 +570,12 @@
wb_user_core_read_check(32'h1000001C,read_data,32'h00000193);
wb_user_core_read_check(32'h1000001C,read_data,32'h00000213);
wb_user_core_read_check(32'h1000001C,read_data,32'h00000293);
- wb_user_core_write(32'h10000014,32'h00000400);
- wb_user_core_read_check(32'h1000001C,read_data,32'h11223737);
- wb_user_core_read_check(32'h1000001C,read_data,32'h300007b7);
- wb_user_core_read_check(32'h1000001C,read_data,32'h34470293);
- wb_user_core_read_check(32'h1000001C,read_data,32'h22334337);
- wb_user_core_read_check(32'h1000001C,read_data,32'h0057ac23);
+ wb_user_core_write(32'h10000014,32'h00000300);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h0005A023);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h9DE30591);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h02B7FEE5);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h43050049);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h0062A023);
$display("#############################################");
$display(" Testing Eight Word Indirect SPI Memory Read");
$display("#############################################");
@@ -584,15 +591,15 @@
wb_user_core_read_check(32'h1000001C,read_data,32'h00000313);
wb_user_core_read_check(32'h1000001C,read_data,32'h00000393);
wb_user_core_read_check(32'h1000001C,read_data,32'h00000413);
- wb_user_core_write(32'h10000014,32'h00000400);
- wb_user_core_read_check(32'h1000001C,read_data,32'h11223737);
- wb_user_core_read_check(32'h1000001C,read_data,32'h300007b7);
- wb_user_core_read_check(32'h1000001C,read_data,32'h34470293);
- wb_user_core_read_check(32'h1000001C,read_data,32'h22334337);
- wb_user_core_read_check(32'h1000001C,read_data,32'h0057ac23);
- wb_user_core_read_check(32'h1000001C,read_data,32'h45530393);
- wb_user_core_read_check(32'h1000001C,read_data,32'h33445537);
- wb_user_core_read_check(32'h1000001C,read_data,32'h0077ae23);
+ wb_user_core_write(32'h10000014,32'h00000300);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h0005A023);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h9DE30591);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h02B7FEE5);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h43050049);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h0062A023);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h004902B7);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h00428293);
+ wb_user_core_read_check(32'h1000001C,read_data,32'h06300313);
$display("#############################################");
$display(" Sector Erase Command ");
@@ -1236,25 +1243,25 @@
// user core using the gpio pads
// ----------------------------------------------------
- wire flash_clk = io_out[30];
- wire flash_csb = io_out[31];
+ wire flash_clk = io_out[24];
+ wire flash_csb = io_out[25];
// Creating Pad Delay
- wire #1 io_oeb_32 = io_oeb[32];
- wire #1 io_oeb_33 = io_oeb[33];
- wire #1 io_oeb_34 = io_oeb[34];
- wire #1 io_oeb_35 = io_oeb[35];
- tri flash_io0 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz;
- tri flash_io1 = (io_oeb_33== 1'b0) ? io_out[33] : 1'bz;
- tri flash_io2 = (io_oeb_34== 1'b0) ? io_out[34] : 1'bz;
- tri flash_io3 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
+ wire #1 io_oeb_26 = io_oeb[26];
+ wire #1 io_oeb_27 = io_oeb[27];
+ wire #1 io_oeb_28 = io_oeb[28];
+ wire #1 io_oeb_29 = io_oeb[29];
+ tri flash_io0 = (io_oeb_26== 1'b0) ? io_out[26] : 1'bz;
+ tri flash_io1 = (io_oeb_27== 1'b0) ? io_out[27] : 1'bz;
+ tri flash_io2 = (io_oeb_28== 1'b0) ? io_out[28] : 1'bz;
+ tri flash_io3 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz;
- assign io_in[32] = flash_io0;
- assign io_in[33] = flash_io1;
- assign io_in[34] = flash_io2;
- assign io_in[35] = flash_io3;
+ assign io_in[26] = flash_io0;
+ assign io_in[27] = flash_io1;
+ assign io_in[28] = flash_io2;
+ assign io_in[29] = flash_io3;
- // Quard flash
+ // Quad flash
s25fl256s #(.mem_file_name("user_risc_boot.hex"),
.otp_file_name("none"),
.TimingModel("S25FL512SAGMFI010_F_30pF"))
@@ -1273,50 +1280,6 @@
-//------------------------------------------------
-// Integrate the SDRAM 8 BIT Memory
-// -----------------------------------------------
-
-wire [7:0] Dq ; // SDRAM Read/Write Data Bus
-wire [0:0] sdr_dqm ; // SDRAM DATA Mask
-wire [1:0] sdr_ba ; // SDRAM Bank Select
-wire [12:0] sdr_addr ; // SDRAM ADRESS
-wire sdr_cs_n ; // chip select
-wire sdr_cke ; // clock gate
-wire sdr_ras_n ; // ras
-wire sdr_cas_n ; // cas
-wire sdr_we_n ; // write enable
-wire sdram_clk ;
-
-assign Dq[7:0] = (io_oeb[7:0] == 8'h0) ? io_out [7:0] : 8'hZZ;
-assign sdr_addr[12:0] = io_out [20:8] ;
-assign sdr_ba[1:0] = io_out [22:21] ;
-assign sdr_dqm[0] = io_out [23] ;
-assign sdr_we_n = io_out [24] ;
-assign sdr_cas_n = io_out [25] ;
-assign sdr_ras_n = io_out [26] ;
-assign sdr_cs_n = io_out [27] ;
-assign sdr_cke = io_out [28] ;
-assign sdram_clk = io_out [29] ;
-assign io_in[29] = sdram_clk;
-assign #(1) io_in[7:0] = Dq;
-
-// to fix the sdram interface timing issue
-wire #(1) sdram_clk_d = sdram_clk;
-
- // SDRAM 8bit
-mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
- .Dq (Dq ) ,
- .Addr (sdr_addr[11:0] ),
- .Ba (sdr_ba ),
- .Clk (sdram_clk_d ),
- .Cke (sdr_cke ),
- .Cs_n (sdr_cs_n ),
- .Ras_n (sdr_ras_n ),
- .Cas_n (sdr_cas_n ),
- .We_n (sdr_we_n ),
- .Dqm (sdr_dqm )
- );
task wb_user_core_write;
input [31:0] address;
diff --git a/verilog/dv/user_uart/Makefile b/verilog/dv/user_uart/Makefile
index 0e4b390..7ef5e6d 100644
--- a/verilog/dv/user_uart/Makefile
+++ b/verilog/dv/user_uart/Makefile
@@ -64,6 +64,7 @@
${GCC64_PREFIX}-objdump -D user_uart.elf > user_uart.dump
rm crt_tcm.o user_uart.o
ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
@@ -71,6 +72,15 @@
-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
-I $(UPRJ_INCLUDE_PATH4) \
$< -o $@
+ else
+ iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_AGENTS) \
+ -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
+ -I $(UPRJ_INCLUDE_PATH4) \
+ $< -o $@
+ endif
else
iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
diff --git a/verilog/dv/user_uart/uprj_netlists.v b/verilog/dv/user_uart/uprj_netlists.v
index 9e61482..0c7d867 100644
--- a/verilog/dv/user_uart/uprj_netlists.v
+++ b/verilog/dv/user_uart/uprj_netlists.v
@@ -42,6 +42,19 @@
`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
+ `include"sar_adc/SAR.sv"
+ `include"sar_adc/ACMP.sv"
+ `include"sar_adc/sar_adc.sv"
+ `include"sar_adc/adc_reg.sv"
+ `include"sar_adc/DAC_8BIT.v"
+
+ `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+ `include "pinmux/src/pinmux.sv"
+ `include "pinmux/src/pinmux_reg.sv"
+ `include "pinmux/src/gpio_intr.sv"
+ `include "pinmux/src/pwm.sv"
+ `include "lib/pulse_gen_type1.sv"
+ `include "lib/pulse_gen_type2.sv"
`include "spi_master/src/spim_top.sv"
`include "spi_master/src/spim_if.sv"
@@ -76,18 +89,9 @@
`include "uart_i2c_usb/src/uart_i2c_usb.sv"
- `include "sdram_ctrl/src/top/sdrc_top.v"
- `include "sdram_ctrl/src/wb2sdrc/wb2sdrc.v"
- `include "lib/async_fifo.sv"
- `include "sdram_ctrl/src/core/sdrc_core.v"
- `include "sdram_ctrl/src/core/sdrc_bank_ctl.v"
- `include "sdram_ctrl/src/core/sdrc_bank_fsm.v"
- `include "sdram_ctrl/src/core/sdrc_bs_convert.v"
- `include "sdram_ctrl/src/core/sdrc_req_gen.v"
- `include "sdram_ctrl/src/core/sdrc_xfr_ctl.v"
-
`include "lib/registers.v"
`include "lib/clk_ctl.v"
+ `include "lib/async_fifo.sv"
`include "digital_core/src/glbl_cfg.sv"
`include "wb_host/src/wb_host.sv"
@@ -122,6 +126,7 @@
`include "syntacore/scr1/src/core/scr1_dmi.sv"
`include "syntacore/scr1/src/core/scr1_scu.sv"
+ `include "syntacore/scr1/src/top/scr1_imem_router.sv"
`include "syntacore/scr1/src/top/scr1_dmem_router.sv"
`include "syntacore/scr1/src/top/scr1_dp_memory.sv"
`include "syntacore/scr1/src/top/scr1_tcm.sv"
diff --git a/verilog/dv/user_uart/user_uart.c b/verilog/dv/user_uart/user_uart.c
index b60311c..99e0204 100644
--- a/verilog/dv/user_uart/user_uart.c
+++ b/verilog/dv/user_uart/user_uart.c
@@ -18,32 +18,16 @@
#define SC_SIM_OUTPORT (0xf0000000)
#define uint32_t long
-#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x30000000)
-#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x30000004)
-#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x30000008)
-#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x3000000C)
-#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x30000010)
-#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x30000014)
-#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x30000018)
-#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x3000001C)
-#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x30000020)
-#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x30000024)
-#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x30000028)
-#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x3000002C)
-#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x30000030)
-#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x30000034)
-#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30000038)
-#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3000003C)
-#define reg_mprj_uart_reg0 (*(volatile uint32_t*)0x30010000)
-#define reg_mprj_uart_reg1 (*(volatile uint32_t*)0x30010004)
-#define reg_mprj_uart_reg2 (*(volatile uint32_t*)0x30010008)
-#define reg_mprj_uart_reg3 (*(volatile uint32_t*)0x3001000C)
-#define reg_mprj_uart_reg4 (*(volatile uint32_t*)0x30010010)
-#define reg_mprj_uart_reg5 (*(volatile uint32_t*)0x30010014)
-#define reg_mprj_uart_reg6 (*(volatile uint32_t*)0x30010018)
-#define reg_mprj_uart_reg7 (*(volatile uint32_t*)0x3001001C)
-#define reg_mprj_uart_reg8 (*(volatile uint32_t*)0x30010020)
+#define reg_mprj_uart_reg0 (*(volatile uint32_t*)0x10010000)
+#define reg_mprj_uart_reg1 (*(volatile uint32_t*)0x10010004)
+#define reg_mprj_uart_reg2 (*(volatile uint32_t*)0x10010008)
+#define reg_mprj_uart_reg3 (*(volatile uint32_t*)0x1001000C)
+#define reg_mprj_uart_reg4 (*(volatile uint32_t*)0x10010010)
+#define reg_mprj_uart_reg5 (*(volatile uint32_t*)0x10010014)
+#define reg_mprj_uart_reg6 (*(volatile uint32_t*)0x10010018)
+#define reg_mprj_uart_reg7 (*(volatile uint32_t*)0x1001001C)
+#define reg_mprj_uart_reg8 (*(volatile uint32_t*)0x10010020)
int main()
{
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index 6258f24..0a0b207 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -177,14 +177,8 @@
// Remove Wb Reset
wb_user_core_write('h3080_0000,'h1);
- #1;
- //------------ SDRAM Config - 2
- wb_user_core_write('h3000_0014,'h100_019E);
-
- repeat (2) @(posedge clock);
- #1;
- //------------ SDRAM Config - 1
- wb_user_core_write('h3000_0010,'h2F17_2242);
+ // Enable UART Multi Functional Ports
+ wb_user_core_write('h3003_0038,'h100);
repeat (2) @(posedge clock);
#1;
@@ -408,27 +402,29 @@
force u_top.u_wb_host.u_clkbuf_usb.VNB = VSS;
end
`endif
+
+
//------------------------------------------------------
// Integrate the Serial flash with qurd support to
// user core using the gpio pads
// ----------------------------------------------------
- wire flash_clk = io_out[30];
- wire flash_csb = io_out[31];
+ wire flash_clk = io_out[24];
+ wire flash_csb = io_out[25];
// Creating Pad Delay
- wire #1 io_oeb_32 = io_oeb[32];
- wire #1 io_oeb_33 = io_oeb[33];
- wire #1 io_oeb_34 = io_oeb[34];
- wire #1 io_oeb_35 = io_oeb[35];
- tri flash_io0 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz;
- tri flash_io1 = (io_oeb_33== 1'b0) ? io_out[33] : 1'bz;
- tri flash_io2 = (io_oeb_34== 1'b0) ? io_out[34] : 1'bz;
- tri flash_io3 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
+ wire #1 io_oeb_26 = io_oeb[26];
+ wire #1 io_oeb_27 = io_oeb[27];
+ wire #1 io_oeb_28 = io_oeb[28];
+ wire #1 io_oeb_29 = io_oeb[29];
+ tri flash_io0 = (io_oeb_26== 1'b0) ? io_out[26] : 1'bz;
+ tri flash_io1 = (io_oeb_27== 1'b0) ? io_out[27] : 1'bz;
+ tri flash_io2 = (io_oeb_28== 1'b0) ? io_out[28] : 1'bz;
+ tri flash_io3 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz;
- assign io_in[32] = flash_io0;
- assign io_in[33] = flash_io1;
- assign io_in[34] = flash_io2;
- assign io_in[35] = flash_io3;
+ assign io_in[26] = flash_io0;
+ assign io_in[27] = flash_io1;
+ assign io_in[28] = flash_io2;
+ assign io_in[29] = flash_io3;
// Quard flash
@@ -451,59 +447,14 @@
-//------------------------------------------------
-// Integrate the SDRAM 8 BIT Memory
-// -----------------------------------------------
-
-wire [7:0] Dq ; // SDRAM Read/Write Data Bus
-wire [0:0] sdr_dqm ; // SDRAM DATA Mask
-wire [1:0] sdr_ba ; // SDRAM Bank Select
-wire [12:0] sdr_addr ; // SDRAM ADRESS
-wire sdr_cs_n ; // chip select
-wire sdr_cke ; // clock gate
-wire sdr_ras_n ; // ras
-wire sdr_cas_n ; // cas
-wire sdr_we_n ; // write enable
-wire sdram_clk ;
-
-assign Dq[7:0] = (io_oeb[7:0] == 8'h0) ? io_out [7:0] : 8'hZZ;
-assign sdr_addr[12:0] = io_out [20:8] ;
-assign sdr_ba[1:0] = io_out [22:21] ;
-assign sdr_dqm[0] = io_out [23] ;
-assign sdr_we_n = io_out [24] ;
-assign sdr_cas_n = io_out [25] ;
-assign sdr_ras_n = io_out [26] ;
-assign sdr_cs_n = io_out [27] ;
-assign sdr_cke = io_out [28] ;
-assign sdram_clk = io_out [29] ;
-assign io_in[29] = sdram_clk;
-assign #(1) io_in[7:0] = Dq;
-
-// to fix the sdram interface timing issue
-wire #(1) sdram_clk_d = sdram_clk;
-
- // SDRAM 8bit
-mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
- .Dq (Dq ) ,
- .Addr (sdr_addr[11:0] ),
- .Ba (sdr_ba ),
- .Clk (sdram_clk_d ),
- .Cke (sdr_cke ),
- .Cs_n (sdr_cs_n ),
- .Ras_n (sdr_ras_n ),
- .Cas_n (sdr_cas_n ),
- .We_n (sdr_we_n ),
- .Dqm (sdr_dqm )
- );
-
//---------------------------
// UART Agent integration
// --------------------------
wire uart_txd,uart_rxd;
-assign uart_txd = io_out[37];
-assign io_in[36] = uart_rxd ;
+assign uart_txd = io_out[2];
+assign io_in[1] = uart_rxd ;
uart_agent tb_uart(
.mclk (clock ),
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile
index c0cd3d8..aecb8cf 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/wb_port/Makefile
@@ -40,6 +40,7 @@
## Simulation mode: RTL/GL
SIM?=RTL
+DUMP?=OFF
.SUFFIXES:
@@ -53,12 +54,21 @@
%.vvp: %_tb.v %.hex
ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
-I $(UPRJ_INCLUDE_PATH4) \
$< -o $@
+ else
+ iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
+ -I $(UPRJ_INCLUDE_PATH4) \
+ $< -o $@
+ endif
else
iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c
index 9292946..28c72cd 100644
--- a/verilog/dv/wb_port/wb_port.c
+++ b/verilog/dv/wb_port/wb_port.c
@@ -23,22 +23,34 @@
#define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
#define reg_mprj_wbhost_reg0 (*(volatile uint32_t*)0x30800000)
-#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x30000000)
-#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x30000004)
-#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x30000008)
-#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x3000000C)
-#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x30000010)
-#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x30000014)
-#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x30000018)
-#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x3000001C)
-#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x30000020)
-#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x30000024)
-#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x30000028)
-#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x3000002C)
-#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x30000030)
-#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x30000034)
-#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30000038)
-#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3000003C)
+#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x30030000)
+#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x30030004)
+#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x30030008)
+#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x3003000C)
+#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x30030010)
+#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x30030014)
+#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x30030018)
+#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x3003001C)
+#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x30030020)
+#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x30030024)
+#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x30030028)
+#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x3003002C)
+#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x30030030)
+#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x30030034)
+#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30030038)
+#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3003003C)
+#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x30030040)
+#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x30030044)
+#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x30030048)
+#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x3003004C)
+#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x30030050)
+#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x30030054)
+#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x30030058)
+#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x3003005C)
+#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x30030060)
+#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x30030064)
+#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x30030068)
+#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x3003006C)
/*
@@ -106,41 +118,30 @@
// Remove Wishbone Reset
reg_mprj_wbhost_reg0 = 0x1;
+ if (reg_mprj_globl_reg0 != 0x89490201) bFail = 1;
if (reg_mprj_globl_reg1 != 0xA55AA55A) bFail = 1;
- if (reg_mprj_globl_reg2 != 0xAABBCCDD) bFail = 1;
// Write software Write & Read Register
- reg_mprj_globl_reg6 = 0x11223344;
- reg_mprj_globl_reg7 = 0x22334455;
- reg_mprj_globl_reg8 = 0x33445566;
- reg_mprj_globl_reg9 = 0x44556677;
- reg_mprj_globl_reg10 = 0x55667788;
- reg_mprj_globl_reg11 = 0x66778899;
- reg_mprj_globl_reg12 = 0x778899AA;
- reg_mprj_globl_reg13 = 0x8899AABB;
- reg_mprj_globl_reg14 = 0x99AABBCC;
- reg_mprj_globl_reg15 = 0xAABBCCDD;
+ reg_mprj_globl_reg22 = 0x11223344;
+ reg_mprj_globl_reg23 = 0x22334455;
+ reg_mprj_globl_reg24 = 0x33445566;
+ reg_mprj_globl_reg25 = 0x44556677;
+ reg_mprj_globl_reg26 = 0x55667788;
+ reg_mprj_globl_reg27 = 0x66778899;
- if (reg_mprj_globl_reg6 != 0x11223344) bFail = 1;
+ if (reg_mprj_globl_reg22 != 0x11223344) bFail = 1;
if (bFail == 1) reg_mprj_datal = 0xAB610000;
- if (reg_mprj_globl_reg7 != 0x22334455) bFail = 1;
+ if (reg_mprj_globl_reg23 != 0x22334455) bFail = 1;
if (bFail == 1) reg_mprj_datal = 0xAB620000;
- if (reg_mprj_globl_reg8 != 0x33445566) bFail = 1;
+ if (reg_mprj_globl_reg24 != 0x33445566) bFail = 1;
if (bFail == 1) reg_mprj_datal = 0xAB630000;
- if (reg_mprj_globl_reg9 != 0x44556677) bFail = 1;
+ if (reg_mprj_globl_reg25 != 0x44556677) bFail = 1;
if (bFail == 1) reg_mprj_datal = 0xAB640000;
- if (reg_mprj_globl_reg10 != 0x55667788) bFail = 1;
+ if (reg_mprj_globl_reg26 != 0x55667788) bFail = 1;
if (bFail == 1) reg_mprj_datal = 0xAB650000;
- if (reg_mprj_globl_reg11 != 0x66778899) bFail = 1;
+ if (reg_mprj_globl_reg27 != 0x66778899) bFail = 1;
if (bFail == 1) reg_mprj_datal = 0xAB660000;
- if (reg_mprj_globl_reg12 != 0x778899AA) bFail = 1;
- if (bFail == 1) reg_mprj_datal = 0xAB670000;
- if (reg_mprj_globl_reg13 != 0x8899AABB) bFail = 1;
- if (bFail == 1) reg_mprj_datal = 0xAB680000;
- if (reg_mprj_globl_reg14 != 0x99AABBCC) bFail = 1;
- if (bFail == 1) reg_mprj_datal = 0xAB690000;
- if (reg_mprj_globl_reg15 != 0xAABBCCDD) bFail = 1;
if(bFail == 0) {
reg_mprj_datal = 0xAB6A0000;
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v
index aaef0a1..e0d9f40 100644
--- a/verilog/dv/wb_port/wb_port_tb.v
+++ b/verilog/dv/wb_port/wb_port_tb.v
@@ -54,6 +54,7 @@
$dumpvars(2, wb_port_tb.uut);
//$dumpvars(1, wb_port_tb.uut.mprj);
$dumpvars(1, wb_port_tb.uut.mprj.u_wb_host);
+ $dumpvars(2, wb_port_tb.uut.mprj.u_pinmux);
end
`endif
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv
index 2b284be..031f1c8 100755
--- a/verilog/rtl/pinmux/src/pinmux.sv
+++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -29,14 +29,14 @@
// SFLASH I/F
input logic sflash_sck,
input logic sflash_ss,
- input logic sflash_oen,
+ input logic [3:0] sflash_oen,
input logic [3:0] sflash_do,
output logic [3:0] sflash_di,
// SSRAM I/F
input logic ssram_sck,
input logic ssram_ss,
- input logic ssram_oen,
+ input logic [3:0] ssram_oen,
input logic [3:0] ssram_do,
output logic [3:0] ssram_di,
@@ -75,7 +75,6 @@
/* clock pulse */
//********************************************************
logic pulse1u_mclk ;// 1 UsSecond Pulse for waveform Generator
-logic pulse1m_mclk ;// 1MilliSecond Pulse for waveform Generator
logic pulse1s_mclk ;// 1Second Pulse for waveform Generator
logic [9:0] cfg_pulse_1us ;// 1us pulse generation config
@@ -344,14 +343,12 @@
* sflash_io1 digital_io[27]
* sflash_io2 digital_io[28]
* sflash_io3 digital_io[29]
-*
* ssram_sck digital_io[30]
* ssram_ss digital_io[31]
* ssram_io0 digital_io[32]
* ssram_io1 digital_io[33]
* ssram_io2 digital_io[34]
* ssram_io3 digital_io[35]
-*
* usb_dp digital_io[36]
* usb_dn digital_io[37]
****************************************************************
@@ -671,18 +668,18 @@
// Serial Flash
digital_io_oen[24] = 1'b0 ;
digital_io_oen[25] = 1'b0 ;
- digital_io_oen[26] = sflash_oen;
- digital_io_oen[27] = sflash_oen;
- digital_io_oen[28] = sflash_oen;
- digital_io_oen[29] = sflash_oen;
+ digital_io_oen[26] = sflash_oen[0];
+ digital_io_oen[27] = sflash_oen[1];
+ digital_io_oen[28] = sflash_oen[2];
+ digital_io_oen[29] = sflash_oen[3];
// Serail SRAM
digital_io_oen[30] = 1'b0 ;
digital_io_oen[31] = 1'b0 ;
- digital_io_oen[32] = ssram_oen;
- digital_io_oen[33] = ssram_oen;
- digital_io_oen[34] = ssram_oen;
- digital_io_oen[35] = ssram_oen;
+ digital_io_oen[32] = ssram_oen[0];
+ digital_io_oen[33] = ssram_oen[1];
+ digital_io_oen[34] = ssram_oen[2];
+ digital_io_oen[35] = ssram_oen[3];
// USB 1.1
digital_io_oen[36] = usb_oen;
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv
index eba780d..aea729f 100644
--- a/verilog/rtl/pinmux/src/pinmux_reg.sv
+++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -100,6 +100,12 @@
reg [31:0] reg_19; // PWN-3 Config
reg [31:0] reg_20; // PWN-4 Config
reg [31:0] reg_21; // PWN-5 Config
+reg [31:0] reg_22; // Software-Reg1
+reg [31:0] reg_23; // Software-Reg2
+reg [31:0] reg_24; // Software-Reg3
+reg [31:0] reg_25; // Software-Reg4
+reg [31:0] reg_26; // Software-Reg5
+reg [31:0] reg_27; // Software-Reg6
reg cs_int;
@@ -157,50 +163,34 @@
// register read enable and write enable decoding logic
//-----------------------------------------------------------------------
wire sw_wr_en_0 = sw_wr_en & (sw_addr == 5'h0);
-wire sw_rd_en_0 = sw_rd_en & (sw_addr == 5'h0);
wire sw_wr_en_1 = sw_wr_en & (sw_addr == 5'h1);
-wire sw_rd_en_1 = sw_rd_en & (sw_addr == 5'h1);
wire sw_wr_en_2 = sw_wr_en & (sw_addr == 5'h2);
-wire sw_rd_en_2 = sw_rd_en & (sw_addr == 5'h2);
wire sw_wr_en_3 = sw_wr_en & (sw_addr == 5'h3);
-wire sw_rd_en_3 = sw_rd_en & (sw_addr == 5'h3);
wire sw_wr_en_4 = sw_wr_en & (sw_addr == 5'h4);
-wire sw_rd_en_4 = sw_rd_en & (sw_addr == 5'h4);
wire sw_wr_en_5 = sw_wr_en & (sw_addr == 5'h5);
-wire sw_rd_en_5 = sw_rd_en & (sw_addr == 5'h5);
wire sw_wr_en_6 = sw_wr_en & (sw_addr == 5'h6);
-wire sw_rd_en_6 = sw_rd_en & (sw_addr == 5'h6);
wire sw_wr_en_7 = sw_wr_en & (sw_addr == 5'h7);
-wire sw_rd_en_7 = sw_rd_en & (sw_addr == 5'h7);
wire sw_wr_en_8 = sw_wr_en & (sw_addr == 5'h8);
-wire sw_rd_en_8 = sw_rd_en & (sw_addr == 5'h8);
wire sw_wr_en_9 = sw_wr_en & (sw_addr == 5'h9);
-wire sw_rd_en_9 = sw_rd_en & (sw_addr == 5'h9);
wire sw_wr_en_10 = sw_wr_en & (sw_addr == 5'hA);
-wire sw_rd_en_10 = sw_rd_en & (sw_addr == 5'hA);
wire sw_wr_en_11 = sw_wr_en & (sw_addr == 5'hB);
-wire sw_rd_en_11 = sw_rd_en & (sw_addr == 5'hB);
wire sw_wr_en_12 = sw_wr_en & (sw_addr == 5'hC);
-wire sw_rd_en_12 = sw_rd_en & (sw_addr == 5'hC);
wire sw_wr_en_13 = sw_wr_en & (sw_addr == 5'hD);
-wire sw_rd_en_13 = sw_rd_en & (sw_addr == 5'hD);
wire sw_wr_en_14 = sw_wr_en & (sw_addr == 5'hE);
-wire sw_rd_en_14 = sw_rd_en & (sw_addr == 5'hE);
wire sw_wr_en_15 = sw_wr_en & (sw_addr == 5'hF);
-wire sw_rd_en_15 = sw_rd_en & (sw_addr == 5'hF);
wire sw_wr_en_16 = sw_wr_en & (sw_addr == 5'h10);
-wire sw_rd_en_16 = sw_rd_en & (sw_addr == 5'h10);
wire sw_wr_en_17 = sw_wr_en & (sw_addr == 5'h11);
-wire sw_rd_en_17 = sw_rd_en & (sw_addr == 5'h11);
wire sw_wr_en_18 = sw_wr_en & (sw_addr == 5'h12);
-wire sw_rd_en_18 = sw_rd_en & (sw_addr == 5'h12);
wire sw_wr_en_19 = sw_wr_en & (sw_addr == 5'h13);
-wire sw_rd_en_19 = sw_rd_en & (sw_addr == 5'h13);
wire sw_wr_en_20 = sw_wr_en & (sw_addr == 5'h14);
-wire sw_rd_en_20 = sw_rd_en & (sw_addr == 5'h14);
wire sw_wr_en_21 = sw_wr_en & (sw_addr == 5'h15);
-wire sw_rd_en_21 = sw_rd_en & (sw_addr == 5'h15);
+wire sw_wr_en_22 = sw_wr_en & (sw_addr == 5'h16);
+wire sw_wr_en_23 = sw_wr_en & (sw_addr == 5'h17);
+wire sw_wr_en_24 = sw_wr_en & (sw_addr == 5'h18);
+wire sw_wr_en_25 = sw_wr_en & (sw_addr == 5'h19);
+wire sw_wr_en_26 = sw_wr_en & (sw_addr == 5'h1A);
+wire sw_wr_en_27 = sw_wr_en & (sw_addr == 5'h1B);
//-----------------------------------------------------------------------
@@ -626,6 +616,95 @@
);
+//-----------------------------------------
+// Software Reg-1
+// ----------------------------------------
+gen_32b_reg #(32'h0) u_reg_22 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_22 ),
+ .we (wr_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_22 )
+ );
+
+//-----------------------------------------
+// Software Reg-2
+// ----------------------------------------
+gen_32b_reg #(32'h0) u_reg_23 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_23 ),
+ .we (wr_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_23 )
+ );
+
+//-----------------------------------------
+// Software Reg-3
+// ----------------------------------------
+gen_32b_reg #(32'h0) u_reg_24 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_24 ),
+ .we (wr_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_24 )
+ );
+
+//-----------------------------------------
+// Software Reg-4
+// ----------------------------------------
+gen_32b_reg #(32'h0) u_reg_25 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_25 ),
+ .we (wr_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_25 )
+ );
+
+//-----------------------------------------
+// Software Reg-5
+// ----------------------------------------
+gen_32b_reg #(32'h0) u_reg_26 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_26 ),
+ .we (wr_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_26 )
+ );
+
+//-----------------------------------------
+// Software Reg-6
+// ----------------------------------------
+gen_32b_reg #(32'h0) u_reg_27 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_27 ),
+ .we (wr_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_27 )
+ );
//-----------------------------------------------------------------------
// Register Read Path Multiplexer instantiation
@@ -653,11 +732,17 @@
5'b01110 : reg_out [31:0] = reg_14 [31:0];
5'b01111 : reg_out [31:0] = reg_15 [31:0];
5'b10000 : reg_out [31:0] = reg_16 [31:0];
- 5'b10010 : reg_out [31:0] = reg_17 [31:0];
- 5'b10011 : reg_out [31:0] = reg_18 [31:0];
- 5'b10100 : reg_out [31:0] = reg_19 [31:0];
- 5'b10101 : reg_out [31:0] = reg_20 [31:0];
- 5'b10110 : reg_out [31:0] = reg_21 [31:0];
+ 5'b10001 : reg_out [31:0] = reg_17 [31:0];
+ 5'b10010 : reg_out [31:0] = reg_18 [31:0];
+ 5'b10011 : reg_out [31:0] = reg_19 [31:0];
+ 5'b10100 : reg_out [31:0] = reg_20 [31:0];
+ 5'b10101 : reg_out [31:0] = reg_21 [31:0];
+ 5'b10110 : reg_out [31:0] = reg_22 [31:0];
+ 5'b10111 : reg_out [31:0] = reg_23 [31:0];
+ 5'b11000 : reg_out [31:0] = reg_24 [31:0];
+ 5'b11001 : reg_out [31:0] = reg_25 [31:0];
+ 5'b11010 : reg_out [31:0] = reg_26 [31:0];
+ 5'b11011 : reg_out [31:0] = reg_27 [31:0];
default : reg_out [31:0] = 32'h0;
endcase
end
diff --git a/verilog/rtl/sar_adc/sar_adc.sv b/verilog/rtl/sar_adc/sar_adc.sv
index 6514e98..45b7dbd 100644
--- a/verilog/rtl/sar_adc/sar_adc.sv
+++ b/verilog/rtl/sar_adc/sar_adc.sv
@@ -27,7 +27,7 @@
input logic analog_dac_out, // DAC analog o/p for compare
// ACMP (HD) Ports
- input logic analog_din // (Analog)
+ input logic [5:0] analog_din // (Analog)
);
diff --git a/verilog/rtl/spi_master/src/spim_top.sv b/verilog/rtl/spi_master/src/spim_top.sv
index 02aacc7..e8b6320 100644
--- a/verilog/rtl/spi_master/src/spim_top.sv
+++ b/verilog/rtl/spi_master/src/spim_top.sv
@@ -121,7 +121,7 @@
output logic spi_clk,
output logic spi_csn0,// No hold fix for CS#, as it asserted much eariler than SPI clock
output logic [3:0] spi_sdo,
- output logic spi_oen
+ output logic [3:0] spi_oen
);
@@ -209,16 +209,10 @@
// SPI Interface moved inside to support carvel IO pad
// -------------------------------------------------------
-logic spi_clk;
-logic spi_csn0;
logic spi_csn1;
logic spi_csn2;
logic spi_csn3;
logic [1:0] spi_mode;
-logic spi_sdo0;
-logic spi_sdo1;
-logic spi_sdo2;
-logic spi_sdo3;
logic spi_en_tx;
logic spi_init_done;
logic [3:0] spi_sdo_int;
@@ -233,22 +227,26 @@
// ADDing Delay cells for Interface hold fix
sky130_fd_sc_hd__dlygate4sd3_1 u_delay1_sdio0 (.X(spi_sdo0_d1),.A(spi_sdo_int[0]));
sky130_fd_sc_hd__dlygate4sd3_1 u_delay2_sdio0 (.X(spi_sdo0_d2),.A(spi_sdo0_d1));
-sky130_fd_sc_hd__clkbuf_16 u_buf_sdio0 (.X(spi_sdo0),.A(spi_sdo0_d2));
+sky130_fd_sc_hd__clkbuf_16 u_buf_sdio0 (.X(spi_sdo[0]),.A(spi_sdo0_d2));
sky130_fd_sc_hd__dlygate4sd3_1 u_delay1_sdio1 (.X(spi_sdo1_d1),.A(spi_sdo_int[1]));
sky130_fd_sc_hd__dlygate4sd3_1 u_delay2_sdio1 (.X(spi_sdo1_d2),.A(spi_sdo1_d1));
-sky130_fd_sc_hd__clkbuf_16 u_buf_sdio1 (.X(spi_sdo1),.A(spi_sdo1_d2));
+sky130_fd_sc_hd__clkbuf_16 u_buf_sdio1 (.X(spi_sdo[1]),.A(spi_sdo1_d2));
sky130_fd_sc_hd__dlygate4sd3_1 u_delay1_sdio2 (.X(spi_sdo2_d1),.A(spi_sdo_int[2]));
sky130_fd_sc_hd__dlygate4sd3_1 u_delay2_sdio2 (.X(spi_sdo2_d2),.A(spi_sdo2_d1));
-sky130_fd_sc_hd__clkbuf_16 u_buf_sdio2 (.X(spi_sdo2),.A(spi_sdo2_d2));
+sky130_fd_sc_hd__clkbuf_16 u_buf_sdio2 (.X(spi_sdo[2]),.A(spi_sdo2_d2));
sky130_fd_sc_hd__dlygate4sd3_1 u_delay1_sdio3 (.X(spi_sdo3_d1),.A(spi_sdo_int[3]));
sky130_fd_sc_hd__dlygate4sd3_1 u_delay2_sdio3 (.X(spi_sdo3_d2),.A(spi_sdo3_d1));
-sky130_fd_sc_hd__clkbuf_16 u_buf_sdio3 (.X(spi_sdo3),.A(spi_sdo3_d2));
+sky130_fd_sc_hd__clkbuf_16 u_buf_sdio3 (.X(spi_sdo[3]),.A(spi_sdo3_d2));
-assign spi_oen = !spi_en_tx;
+assign #1 spi_oen[0] = !spi_en_tx; // SPI_DIO0
+assign #1 spi_oen[1] = !spi_en_tx; // SPI_DIO1
+assign #1 spi_oen[2] = (spi_mode == 0) ? 1 'b0 : !spi_en_tx; // HOLD
+assign #1 spi_oen[3] = (spi_mode == 0) ? 1 'b0 : !spi_en_tx; //
+
spim_if #( .WB_WIDTH(WB_WIDTH)) u_wb_if(
.mclk (mclk ),
diff --git a/verilog/rtl/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v b/verilog/rtl/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v
new file mode 100644
index 0000000..289a770
--- /dev/null
+++ b/verilog/rtl/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v
@@ -0,0 +1,114 @@
+// OpenRAM SRAM model
+// Words: 512
+// Word size: 32
+// Write size: 8
+
+module sky130_sram_2kbyte_1rw1r_32x512_8(
+`ifdef USE_POWER_PINS
+ vccd1,
+ vssd1,
+`endif
+// Port 0: RW
+ clk0,csb0,web0,wmask0,addr0,din0,dout0,
+// Port 1: R
+ clk1,csb1,addr1,dout1
+ );
+
+ parameter NUM_WMASKS = 4 ;
+ parameter DATA_WIDTH = 32 ;
+ parameter ADDR_WIDTH = 9 ;
+ parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+ // FIXME: This delay is arbitrary.
+ parameter DELAY = 3 ;
+ parameter VERBOSE = 0 ; //Set to 0 to only display warnings
+ parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
+
+`ifdef USE_POWER_PINS
+ inout vccd1;
+ inout vssd1;
+`endif
+ input clk0; // clock
+ input csb0; // active low chip select
+ input web0; // active low write control
+ input [NUM_WMASKS-1:0] wmask0; // write mask
+ input [ADDR_WIDTH-1:0] addr0;
+ input [DATA_WIDTH-1:0] din0;
+ output [DATA_WIDTH-1:0] dout0;
+ input clk1; // clock
+ input csb1; // active low chip select
+ input [ADDR_WIDTH-1:0] addr1;
+ output [DATA_WIDTH-1:0] dout1;
+
+ reg csb0_reg;
+ reg web0_reg;
+ reg [NUM_WMASKS-1:0] wmask0_reg;
+ reg [ADDR_WIDTH-1:0] addr0_reg;
+ reg [DATA_WIDTH-1:0] din0_reg;
+ reg [DATA_WIDTH-1:0] dout0;
+
+ // All inputs are registers
+ always @(posedge clk0)
+ begin
+ csb0_reg = csb0;
+ web0_reg = web0;
+ wmask0_reg = wmask0;
+ addr0_reg = addr0;
+ din0_reg = din0;
+ #(T_HOLD) dout0 = 32'bx;
+ if ( !csb0_reg && web0_reg && VERBOSE )
+ $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
+ if ( !csb0_reg && !web0_reg && VERBOSE )
+ $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
+ end
+
+ reg csb1_reg;
+ reg [ADDR_WIDTH-1:0] addr1_reg;
+ reg [DATA_WIDTH-1:0] dout1;
+
+ // All inputs are registers
+ always @(posedge clk1)
+ begin
+ csb1_reg = csb1;
+ addr1_reg = addr1;
+ if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
+ $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1);
+ #(T_HOLD) dout1 = 32'bx;
+ if ( !csb1_reg && VERBOSE )
+ $display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]);
+ end
+
+reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
+
+ // Memory Write Block Port 0
+ // Write Operation : When web0 = 0, csb0 = 0
+ always @ (negedge clk0)
+ begin : MEM_WRITE0
+ if ( !csb0_reg && !web0_reg ) begin
+ if (wmask0_reg[0])
+ mem[addr0_reg][7:0] = din0_reg[7:0];
+ if (wmask0_reg[1])
+ mem[addr0_reg][15:8] = din0_reg[15:8];
+ if (wmask0_reg[2])
+ mem[addr0_reg][23:16] = din0_reg[23:16];
+ if (wmask0_reg[3])
+ mem[addr0_reg][31:24] = din0_reg[31:24];
+ end
+ end
+
+ // Memory Read Block Port 0
+ // Read Operation : When web0 = 1, csb0 = 0
+ always @ (negedge clk0)
+ begin : MEM_READ0
+ if (!csb0_reg && web0_reg)
+ dout0 <= #(DELAY) mem[addr0_reg];
+ end
+
+ // Memory Read Block Port 1
+ // Read Operation : When web1 = 1, csb1 = 0
+ always @ (negedge clk1)
+ begin : MEM_READ1
+ if (!csb1_reg)
+ dout1 <= #(DELAY) mem[addr1_reg];
+ end
+
+endmodule
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld b/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld
index cb87b13..c49465e 100644
--- a/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld
+++ b/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld
@@ -27,10 +27,10 @@
MEMORY {
ROM (rxx) : ORIGIN = 0x0, LENGTH = 64K
- RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
+ TCM (rwx) : ORIGIN = 0x00480000, LENGTH = 2K
}
-STACK_SIZE = 1024;
+STACK_SIZE = 256;
CL_SIZE = 32;
@@ -59,7 +59,8 @@
*(sc_test_section)
. = ALIGN(CL_SIZE);
PROVIDE(__TEXT_END__ = .);
- } >ROM
+ } >TCM AT>ROM
+
.rodata ALIGN(CL_SIZE) : {
__global_pointer$ = . + 0x800;
@@ -67,7 +68,7 @@
. = ALIGN(CL_SIZE);
LONG(0x13);
. = ALIGN(CL_SIZE);
- } >ROM
+ } >TCM AT>ROM
/* data segment */
@@ -75,14 +76,13 @@
PROVIDE(__DATA_START__ = .);
*(.data .data.*)
. = ALIGN(CL_SIZE);
- }>RAM
-
+ } >TCM
.sdata ALIGN(CL_SIZE) : {
*(.sdata .sdata.* .gnu.linkonce.s.*)
. = ALIGN(CL_SIZE);
PROVIDE(__DATA_END__ = .);
- } >RAM
+ } >TCM
/* thread-local data segment */
.tdata ALIGN(CL_SIZE) : {
@@ -91,14 +91,14 @@
*(.tdata .tdata.*)
PROVIDE(_tdata_end = .);
. = ALIGN(CL_SIZE);
- } >RAM
+ } >TCM
.tbss ALIGN(CL_SIZE) : {
PROVIDE(_tbss_begin = .);
*(.tbss .tbss.*)
. = ALIGN(CL_SIZE);
PROVIDE(_tbss_end = .);
- } >RAM
+ } >TCM
/* bss segment */
.sbss ALIGN(CL_SIZE) : {
@@ -106,25 +106,25 @@
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon)
. = ALIGN(CL_SIZE);
- } >RAM
+ } >TCM
.bss ALIGN(CL_SIZE) : {
*(.dynbss) *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON)
. = ALIGN(CL_SIZE);
PROVIDE(__BSS_END__ = .);
- } >RAM
+ } >TCM
_end = .;
PROVIDE(__end = .);
/* End of uninitalized data segement */
- .stack ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE : {
+ .stack ORIGIN(TCM) + LENGTH(TCM) - STACK_SIZE : {
PROVIDE(__STACK_START__ = .);
. += STACK_SIZE;
PROVIDE(__C_STACK_TOP__ = .);
PROVIDE(__STACK_END__ = .);
- } >RAM
+ } >TCM
/DISCARD/ : {
*(.eh_frame .eh_frame.*)
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh
index c00ffe3..2810776 100644
--- a/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh
+++ b/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh
@@ -98,7 +98,7 @@
// `define SCR1_TDU_ICOUNT_EN // enable hardware triggers on instruction counter
`define SCR1_IPIC_EN // enable Integrated Programmable Interrupt Controller
`define SCR1_IPIC_SYNC_EN // enable IPIC synchronizer
-// `define SCR1_TCM_EN
+ `define SCR1_TCM_EN
`define SCR1_NEW_PC_REG // enable register in IFU for New_PC value
`define SCRC1_MPRF_STAGE // enabled register at Read path of MPRF
`elsif SCR1_CFG_RV32IC_BASE
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_intf.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_intf.sv
index b0efee3..dfe2904 100644
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_intf.sv
+++ b/verilog/rtl/syntacore/scr1/src/top/scr1_intf.sv
@@ -85,6 +85,21 @@
input logic trst_n,
`endif // SCR1_DBG_EN
+`ifndef SCR1_TCM_MEM
+ // SRAM PORT-0
+ output logic sram_csb0,
+ output logic sram_web0,
+ output logic [8:0] sram_addr0,
+ output logic [3:0] sram_wmask0,
+ output logic [31:0] sram_din0,
+ input logic [31:0] sram_dout0,
+
+ // SRAM PORT-1
+ output logic sram_csb1,
+ output logic [8:0] sram_addr1,
+ input logic [31:0] sram_dout1,
+`endif
+
input logic wb_rst_n, // Wish bone reset
input logic wb_clk, // wish bone clock
// Instruction Memory Interface
@@ -269,6 +284,22 @@
.clk (core_clk ),
.rst_n (core_rst_n_local),
+`ifndef SCR1_TCM_MEM
+ // SRAM PORT-0
+ .sram_csb0 (sram_csb0),
+ .sram_web0 (sram_web0),
+ .sram_addr0 (sram_addr0),
+ .sram_wmask0 (sram_wmask0),
+ .sram_din0 (sram_din0),
+ .sram_dout0 (sram_dout0),
+
+ // SRAM PORT-0
+ .sram_csb1 (sram_csb1),
+ .sram_addr1 (sram_addr1),
+ .sram_dout1 (sram_dout1),
+`endif
+
+
// Instruction interface to TCM
.imem_req_ack (tcm_imem_req_ack),
.imem_req (tcm_imem_req ),
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv
index 5a5d61e..48e6930 100644
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv
+++ b/verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv
@@ -32,6 +32,21 @@
input logic clk,
input logic rst_n,
+`ifndef SCR1_TCM_MEM
+ // SRAM PORT-0
+ output logic sram_csb0,
+ output logic sram_web0,
+ output logic [8:0] sram_addr0,
+ output logic [3:0] sram_wmask0,
+ output logic [31:0] sram_din0,
+ input logic [31:0] sram_dout0,
+
+ // SRAM PORT-1
+ output logic sram_csb1,
+ output logic [8:0] sram_addr1,
+ input logic [31:0] sram_dout1,
+`endif
+
// Core instruction interface
output logic imem_req_ack,
input logic imem_req,
@@ -89,10 +104,23 @@
//-------------------------------------------------------------------------------
// Memory data composing
//-------------------------------------------------------------------------------
-assign imem_rd = imem_req;
-assign dmem_rd = dmem_req & (dmem_cmd == SCR1_MEM_CMD_RD);
-assign dmem_wr = dmem_req & (dmem_cmd == SCR1_MEM_CMD_WR);
+`ifndef SCR1_TCM_MEM
+// connect the TCM memory to SRAM
+assign sram_csb1 =!imem_req;
+assign sram_addr1 = imem_addr[10:2];
+assign imem_rdata = sram_dout1;
+// SRAM Port 0 Control Generation
+assign sram_csb0 = !(dmem_req & ((dmem_cmd == SCR1_MEM_CMD_RD) | (dmem_cmd == SCR1_MEM_CMD_WR)));
+assign sram_web0 = !(dmem_req & (dmem_cmd == SCR1_MEM_CMD_WR));
+assign sram_addr0 = dmem_addr[10:2];
+assign sram_wmask0 = dmem_byteen;
+assign sram_din0 = dmem_writedata;
+assign dmem_rdata_local = sram_dout0;
+
+`endif
+
+//------------------------------
always_comb begin
dmem_writedata = dmem_wdata;
dmem_byteen = 4'b1111;
@@ -112,6 +140,7 @@
//-------------------------------------------------------------------------------
// Memory instantiation
//-------------------------------------------------------------------------------
+`ifdef SCR1_TCM_MEM
scr1_dp_memory #(
.SCR1_WIDTH ( 32 ),
.SCR1_SIZE ( SCR1_TCM_SIZE )
@@ -131,6 +160,8 @@
.qb ( dmem_rdata_local ),
.datab ( dmem_writedata )
);
+`endif
+
//-------------------------------------------------------------------------------
// Data memory output generation
//-------------------------------------------------------------------------------
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
index adc8f86..5c5a927 100644
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
+++ b/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
@@ -129,6 +129,22 @@
output logic tdo_en,
`endif // SCR1_DBG_EN
+`ifndef SCR1_TCM_MEM
+ // SRAM PORT-0
+ output logic sram_csb0,
+ output logic sram_web0,
+ output logic [8:0] sram_addr0,
+ output logic [3:0] sram_wmask0,
+ output logic [31:0] sram_din0,
+ input logic [31:0] sram_dout0,
+
+ // SRAM PORT-1
+ output logic sram_csb1,
+ output logic [8:0] sram_addr1,
+ input logic [31:0] sram_dout1,
+`endif
+
+
input logic wb_rst_n, // Wish bone reset
input logic wb_clk, // wish bone clock
// Instruction Memory Interface
@@ -258,6 +274,21 @@
.trst_n (trst_n),
`endif // SCR1_DBG_EN
+`ifndef SCR1_TCM_MEM
+ // SRAM PORT-0
+ .sram_csb0 (sram_csb0),
+ .sram_web0 (sram_web0),
+ .sram_addr0 (sram_addr0),
+ .sram_wmask0 (sram_wmask0),
+ .sram_din0 (sram_din0),
+ .sram_dout0 (sram_dout0),
+
+ // SRAM PORT-0
+ .sram_csb1 (sram_csb1),
+ .sram_addr1 (sram_addr1),
+ .sram_dout1 (sram_dout1),
+`endif
+
.wb_rst_n (wb_rst_n), // Wish bone reset
.wb_clk (wb_clk), // wish bone clock
diff --git a/verilog/rtl/uart_i2c_usb/src/uart_i2c_usb.sv b/verilog/rtl/uart_i2c_usb/src/uart_i2c_usb.sv
index 69b31d4..a089bb0 100644
--- a/verilog/rtl/uart_i2c_usb/src/uart_i2c_usb.sv
+++ b/verilog/rtl/uart_i2c_usb/src/uart_i2c_usb.sv
@@ -77,12 +77,11 @@
input logic usb_rstn , // async reset
input logic app_clk ,
input logic usb_clk , // 48Mhz usb clock
- input logic [1:0] uart_i2c_usb_sel, // Uart Or I2C Or USB Interface Select
// Reg Bus Interface Signal
input logic reg_cs,
input logic reg_wr,
- input logic [3:0] reg_addr,
+ input logic [7:0] reg_addr,
input logic [31:0] reg_wdata,
input logic reg_be,
@@ -125,16 +124,16 @@
// --------------------------------------
logic [7:0] reg_uart_rdata;
logic [7:0] reg_i2c_rdata;
-logic [31:0] reg_usb_rdata;
+logic [31:0] reg_usb_rdata;
logic reg_uart_ack;
logic reg_i2c_ack;
logic reg_usb_ack;
-assign reg_rdata = (uart_i2c_usb_sel == `SEL_UART) ? {24'h0,reg_uart_rdata} :
- (uart_i2c_usb_sel == `SEL_I2C) ? {24'h0,reg_i2c_rdata} : reg_usb_rdata;
-assign reg_ack = (uart_i2c_usb_sel == `SEL_UART) ? reg_uart_ack :
- (uart_i2c_usb_sel == `SEL_I2C) ? reg_i2c_ack : reg_usb_ack;
+assign reg_rdata = (reg_addr[7:6] == `SEL_UART) ? {24'h0,reg_uart_rdata} :
+ (reg_addr[7:6] == `SEL_I2C) ? {24'h0,reg_i2c_rdata} : reg_usb_rdata;
+assign reg_ack = (reg_addr[7:6] == `SEL_UART) ? reg_uart_ack :
+ (reg_addr[7:6] == `SEL_I2C) ? reg_i2c_ack : reg_usb_ack;
uart_core u_uart_core (
@@ -144,7 +143,7 @@
// Reg Bus Interface Signal
.reg_cs (reg_cs ),
.reg_wr (reg_wr ),
- .reg_addr (reg_addr[3:0] ),
+ .reg_addr (reg_addr[5:2] ),
.reg_wdata (reg_wdata[7:0] ),
.reg_be (reg_be ),
@@ -162,7 +161,7 @@
.wb_clk_i (app_clk ), // master clock input
.sresetn (1'b1 ), // synchronous reset
.aresetn (i2c_rstn ), // asynchronous reset
- .wb_adr_i (reg_addr[2:0] ), // lower address bits
+ .wb_adr_i (reg_addr[4:2] ), // lower address bits
.wb_dat_i (reg_wdata[7:0] ), // databus input
.wb_dat_o (reg_i2c_rdata ), // databus output
.wb_we_i (reg_wr ), // write enable input
@@ -201,8 +200,7 @@
.wbm_rst_n (usb_rstn ), // Regular Reset signal
.wbm_clk_i (app_clk ), // System clock
.wbm_stb_i (reg_cs ), // strobe/request
- .wbm_adr_i ({reg_addr[3:0],
- 2'b0} ), // address
+ .wbm_adr_i (reg_addr[5:0]), // address
.wbm_we_i (reg_wr ), // write
.wbm_dat_i (reg_wdata ), // data output
.wbm_sel_i (reg_be ), // byte enable
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 815677d..7610979 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -26,7 +26,6 @@
`include "libs.ref//sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__fakediode_2.v"
`include "glbl_cfg.v"
- `include "sdram.v"
`include "spi_master.v"
`include "uart_i2cm.v"
`include "wb_interconnect.v"
@@ -42,6 +41,20 @@
`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
+ `include"sar_adc/SAR.sv"
+ `include"sar_adc/ACMP.sv"
+ `include"sar_adc/sar_adc.sv"
+ `include"sar_adc/adc_reg.sv"
+ `include"sar_adc/DAC_8BIT.v"
+
+
+ `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+ `include "pinmux/src/pinmux.sv"
+ `include "pinmux/src/pinmux_reg.sv"
+ `include "pinmux/src/gpio_intr.sv"
+ `include "pinmux/src/pwm.sv"
+ `include "lib/pulse_gen_type1.sv"
+ `include "lib/pulse_gen_type2.sv"
`include "spi_master/src/spim_top.sv"
`include "spi_master/src/spim_if.sv"
@@ -76,16 +89,7 @@
`include "uart_i2c_usb/src/uart_i2c_usb.sv"
- `include "sdram_ctrl/src/top/sdrc_top.v"
- `include "sdram_ctrl/src/wb2sdrc/wb2sdrc.v"
`include "lib/async_fifo.sv"
- `include "sdram_ctrl/src/core/sdrc_core.v"
- `include "sdram_ctrl/src/core/sdrc_bank_ctl.v"
- `include "sdram_ctrl/src/core/sdrc_bank_fsm.v"
- `include "sdram_ctrl/src/core/sdrc_bs_convert.v"
- `include "sdram_ctrl/src/core/sdrc_req_gen.v"
- `include "sdram_ctrl/src/core/sdrc_xfr_ctl.v"
-
`include "lib/registers.v"
`include "lib/clk_ctl.v"
`include "digital_core/src/glbl_cfg.sv"
@@ -122,6 +126,7 @@
`include "syntacore/scr1/src/core/scr1_dmi.sv"
`include "syntacore/scr1/src/core/scr1_scu.sv"
+ `include "syntacore/scr1/src/top/scr1_imem_router.sv"
`include "syntacore/scr1/src/top/scr1_dmem_router.sv"
`include "syntacore/scr1/src/top/scr1_dp_memory.sv"
`include "syntacore/scr1/src/top/scr1_tcm.sv"
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index d5afe73..66d3db2 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -104,6 +104,8 @@
//// 2. Removed the SDRAM controlled ////
//// 3. Added PinMux ////
//// 4. Added SAR ADC for 6 channel ////
+//// 1.3 - 30th Sept 2021, Dinesh.A ////
+//// 2KB SRAM Interface added to RISC Core ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
@@ -327,7 +329,7 @@
// SFLASH I/F
wire sflash_sck ;
wire sflash_ss ;
-wire sflash_oen ;
+wire [3:0] sflash_oen ;
wire [3:0] sflash_do ;
wire [3:0] sflash_di ;
@@ -367,6 +369,23 @@
wire analog_dac_out ;
wire pulse1m_mclk ;
wire h_reset_n ;
+
+`ifndef SCR1_TCM_MEM
+// SRAM PORT-0 - DMEM I/F
+wire sram_csb0 ; // CS#
+wire sram_web0 ; // WE#
+wire [8:0] sram_addr0 ; // Address
+wire [3:0] sram_wmask0 ; // WMASK#
+wire [31:0] sram_din0 ; // Write Data
+wire [31:0] sram_dout0 ; // Read Data
+
+// SRAM PORT-1, IMEM I/F
+wire sram_csb1 ; // CS#
+wire [8:0] sram_addr1 ; // Address
+wire [31:0] sram_dout1 ; // Read Data
+`endif
+
+
/////////////////////////////////////////////////////////
// Clock Skew Ctrl
////////////////////////////////////////////////////////
@@ -469,6 +488,20 @@
// .test_mode (1'b0 ), // Moved inside IP
// .test_rst_n (1'b1 ), // Moved inside IP
+`ifndef SCR1_TCM_MEM
+ // SRAM PORT-0
+ .sram_csb0 (sram_csb0 ),
+ .sram_web0 (sram_web0 ),
+ .sram_addr0 (sram_addr0 ),
+ .sram_wmask0 (sram_wmask0 ),
+ .sram_din0 (sram_din0 ),
+ .sram_dout0 (sram_dout0 ),
+
+ // SRAM PORT-0
+ .sram_csb1 (sram_csb1 ),
+ .sram_addr1 (sram_addr1 ),
+ .sram_dout1 (sram_dout1 ),
+`endif
.wb_rst_n (wbd_int_rst_n ),
.wb_clk (wbd_clk_int ),
@@ -493,6 +526,30 @@
.wbd_dmem_err_i (wbd_riscv_dmem_err_o )
);
+`ifndef SCR1_TCM_MEM
+sky130_sram_2kbyte_1rw1r_32x512_8 u_sram_2kb(
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1),// User area 1 1.8V supply
+ .vssd1 (vssd1),// User area 1 digital ground
+`endif
+// Port 0: RW
+ .clk0 (cpu_clk),
+ .csb0 (sram_csb0),
+ .web0 (sram_web0),
+ .wmask0 (sram_wmask0),
+ .addr0 (sram_addr0),
+ .din0 (sram_din0),
+ .dout0 (sram_dout0),
+// Port 1: R
+ .clk1 (cpu_clk),
+ .csb1 (sram_csb1),
+ .addr1 (sram_addr1),
+ .dout1 (sram_dout1)
+ );
+
+`endif
+
+
/*********************************************************
* SPI Master
* This is an implementation of an SPI master that is controlled via an AXI bus.
@@ -620,39 +677,38 @@
.uart_rstn (uart_rst_n ), // uart reset
.i2c_rstn (i2c_rst_n ), // i2c reset
.usb_rstn (usb_rst_n ), // i2c reset
- .uart_i2c_usb_sel (uart_i2c_usb_sel ), // 0 - uart, 1 - I2C
.app_clk (wbd_clk_int ),
.usb_clk (usb_clk ),
// Reg Bus Interface Signal
- .reg_cs (wbd_uart_stb_o ),
- .reg_wr (wbd_uart_we_o ),
- .reg_addr (wbd_uart_adr_o[5:2] ),
- .reg_wdata (wbd_uart_dat_o ),
- .reg_be (wbd_uart_sel_o ),
+ .reg_cs (wbd_uart_stb_o ),
+ .reg_wr (wbd_uart_we_o ),
+ .reg_addr (wbd_uart_adr_o[7:0] ),
+ .reg_wdata (wbd_uart_dat_o ),
+ .reg_be (wbd_uart_sel_o ),
// Outputs
- .reg_rdata (wbd_uart_dat_i ),
- .reg_ack (wbd_uart_ack_i ),
+ .reg_rdata (wbd_uart_dat_i ),
+ .reg_ack (wbd_uart_ack_i ),
// Pad interface
- .scl_pad_i (i2cm_clk_i ),
- .scl_pad_o (i2cm_clk_o ),
- .scl_pad_oen_o (i2cm_clk_oen ),
+ .scl_pad_i (i2cm_clk_i ),
+ .scl_pad_o (i2cm_clk_o ),
+ .scl_pad_oen_o (i2cm_clk_oen ),
- .sda_pad_i (i2cm_data_i ),
- .sda_pad_o (i2cm_data_o ),
- .sda_padoen_o (i2cm_data_oen ),
+ .sda_pad_i (i2cm_data_i ),
+ .sda_pad_o (i2cm_data_o ),
+ .sda_padoen_o (i2cm_data_oen ),
- .uart_rxd (uart_rxd ),
- .uart_txd (uart_txd ),
+ .uart_rxd (uart_rxd ),
+ .uart_txd (uart_txd ),
- .usb_in_dp (usb_dp_i ),
- .usb_in_dn (usb_dn_i ),
+ .usb_in_dp (usb_dp_i ),
+ .usb_in_dn (usb_dn_i ),
- .usb_out_dp (usb_dp_o ),
- .usb_out_dn (usb_dn_o ),
- .usb_out_tx_oen (usb_oen )
+ .usb_out_dp (usb_dp_o ),
+ .usb_out_dn (usb_dn_o ),
+ .usb_out_tx_oen (usb_oen )
);
@@ -697,8 +753,8 @@
.ssram_sck (sflash_sck ),
.ssram_ss (sflash_ss ),
.ssram_oen (sflash_oen ),
- .ssram_do ( ),
- .ssram_di (sflash_di ),
+ .ssram_do (sflash_do ),
+ .ssram_di ( ),
// USB I/F
.usb_dp_o (usb_dp_o ),
@@ -722,8 +778,8 @@
// SPI MASTER
.spim_sck (sflash_sck ),
.spim_ss (sflash_ss ),
- .spim_miso ( ),
- .spim_mosi (sflash_di[0] ),
+ .spim_miso (sflash_do[0] ),
+ .spim_mosi ( ),
.pulse1m_mclk (pulse1m_mclk ),
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv
index 2daf54c..184e9b6 100644
--- a/verilog/rtl/wb_host/src/wb_host.sv
+++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -264,7 +264,7 @@
.data_out (reg_0[31:0])
);
-generic_register #(8,8'h30 ) u_bank_sel (
+generic_register #(8,8'h10 ) u_bank_sel (
.we ({8{sw_wr_en_1}} ),
.data_in (wbm_dat_i[7:0] ),
.reset_n (wbm_rst_n ),
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
index 05ed8f8..d7b7f7a 100644
--- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
+++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -225,38 +225,43 @@
// EXTERNAL MEMORY MAP
// 0x0000_0000 to 0x0FFF_FFFF - SPI FLASH MEMORY
// 0x1000_0000 to 0x1000_00FF - SPI REGISTER
-// 0x2000_0000 to 0x2FFF_FFFF - SDRAM
-// 0x3000_0000 to 0x3000_00FF - GLOBAL REGISTER
-// 0x3000_0000 to 0x3001_00FF - UART Register
+// 0x1001_0000 to 0x1001_003F - UART
+// 0x1001_0040 to 0x1001_007F - I2C
+// 0x1001_0080 to 0x1001_008F - USB
+// 0x1002_0000 to 0x1002_00FF - ADC
+// 0x1003_0000 to 0x1003_00FF - PINMUX
// 0x3080_0000 to 0x3080_00FF - WB HOST (This decoding happens at wb_host block)
// ---------------------------------------------------------------------------
//
-wire [3:0] m0_wbd_tid_i = (m0_wbd_adr_i[31:28] == 4'b0000 ) ? 4'b0000 :
- (m0_wbd_adr_i[31:28] == 4'b0001 ) ? 4'b0000 :
- (m0_wbd_adr_i[31:28] == 4'b0010 ) ? 4'b0001 :
- (m0_wbd_adr_i[31:16] == 16'h3000 ) ? 4'b0010 :
- (m0_wbd_adr_i[31:16] == 16'h3001 ) ? 4'b0011 : 4'b0000;
+wire [3:0] m0_wbd_tid_i = (m0_wbd_adr_i[31:28] == 4'b0000 ) ? 4'b0000 : // SPI
+ (m0_wbd_adr_i[31:16] == 16'h1000 ) ? 4'b0000 : // SPI REG
+ (m0_wbd_adr_i[31:16] == 16'h1001 ) ? 4'b0001 : // UART/I2C/USB
+ (m0_wbd_adr_i[31:16] == 16'h1002 ) ? 4'b0010 : // ADC
+ (m0_wbd_adr_i[31:16] == 16'h1003 ) ? 4'b0011 : // PINMUX
+ 4'b0000;
//------------------------------
// RISC Data Memory Map
// 0x0000_0000 to 0x0FFF_FFFF - SPI FLASH MEMORY
// 0x1000_0000 to 0x1000_00FF - SPI REGISTER
-// 0x2000_0000 to 0x2FFF_FFFF - SDRAM
-// 0x3000_0000 to 0x3000_00FF - GLOBAL REGISTER
-// 0x3000_0000 to 0x3001_00FF - UART Register
+// 0x1001_0000 to 0x1001_003F - UART
+// 0x1001_0040 to 0x1001_007F - I2
+// 0x1001_0080 to 0x1001_008F - USB
+// 0x1002_0000 to 0x1002_00FF - ADC
+// 0x1003_0000 to 0x1003_00FF - PINMUX
//-----------------------------
//
wire [3:0] m1_wbd_tid_i = (m1_wbd_adr_i[31:28] == 4'b0000 ) ? 4'b0000 :
- (m1_wbd_adr_i[31:28] == 4'b0001 ) ? 4'b0000 :
- (m1_wbd_adr_i[31:28] == 4'b0010 ) ? 4'b0001 :
- (m1_wbd_adr_i[31:16] == 16'h3000 ) ? 4'b0010 :
- (m1_wbd_adr_i[31:16] == 16'h3001 ) ? 4'b0011 : 4'b0000;
+ (m1_wbd_adr_i[31:16] == 16'h1000 ) ? 4'b0000 :
+ (m1_wbd_adr_i[31:16] == 16'h1001 ) ? 4'b0001 :
+ (m1_wbd_adr_i[31:16] == 16'h1002 ) ? 4'b0010 :
+ (m1_wbd_adr_i[31:16] == 16'h1003 ) ? 4'b0011 : 4'b0000;
wire [3:0] m2_wbd_tid_i = (m2_wbd_adr_i[31:28] == 4'b0000 ) ? 4'b0000 :
- (m2_wbd_adr_i[31:28] == 4'b0001 ) ? 4'b0000 :
- (m2_wbd_adr_i[31:28] == 4'b0010 ) ? 4'b0001 :
- (m2_wbd_adr_i[31:16] == 16'h3000 ) ? 4'b0010 :
- (m2_wbd_adr_i[31:16] == 16'h3001 ) ? 4'b0011 : 4'b0000;
+ (m2_wbd_adr_i[31:16] == 16'h1000 ) ? 4'b0000 :
+ (m2_wbd_adr_i[31:16] == 16'h1001 ) ? 4'b0001 :
+ (m2_wbd_adr_i[31:16] == 16'h1002 ) ? 4'b0010 :
+ (m2_wbd_adr_i[31:16] == 16'h1003 ) ? 4'b0011 : 4'b0000;
//----------------------------------------
// Master Mapping
// -------------------------------------
