wb_host rtl and openlane setup added
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
new file mode 100755
index 0000000..dcf2828
--- /dev/null
+++ b/openlane/wb_host/config.tcl
@@ -0,0 +1,58 @@
+# Global
+# ------
+
+set script_dir [file dirname [file normalize [info script]]]
+# Name
+
+set ::env(DESIGN_NAME) wb_host
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "wbm_clk_i wbs_clk_i"
+
+set ::env(SYNTH_MAX_FANOUT) 4
+
+# Sources
+# -------
+
+# Local sources + no2usb sources
+set ::env(VERILOG_FILES) "\
+ $script_dir/../../verilog/rtl/wb_host/src/wb_host.sv \
+ $script_dir/../../verilog/rtl/lib/async_fifo.sv \
+ $script_dir/../../verilog/rtl/lib/async_wb.sv \
+ $script_dir/../../verilog/rtl/lib/registers.v"
+
+#set ::env(SDC_FILE) "$script_dir/base.sdc"
+#set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+
+# Floorplanning
+# -------------
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 1000 200"
+
+
+
+set ::env(FP_PDN_VPITCH) 50
+#set ::env(PDN_CFG) $script_dir/pdn.tcl
+
+#set ::env(FP_VERTICAL_HALO) 6
+set ::env(PL_TARGET_DENSITY) 0.62
+set ::env(PL_TARGET_DENSITY_CELLS) 0.5
+set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 1
+#set ::env(CELL_PAD) 4
+
+set ::env(GLB_RT_TILES) 14
+set ::env(GLB_RT_MAXLAYER) 5
+
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+
diff --git a/openlane/wb_host/pin_order.cfg b/openlane/wb_host/pin_order.cfg
new file mode 100644
index 0000000..dca5594
--- /dev/null
+++ b/openlane/wb_host/pin_order.cfg
@@ -0,0 +1,684 @@
+#BUS_SORT
+
+#MANUAL_PLACE
+
+#E
+wbs_clk_i 0000 0 2
+
+
+
+
+#S
+wbm_clk_i 0000 0 2
+wbm_rst_i
+wbm_ack_o
+wbm_cyc_i
+wbm_stb_i
+wbm_we_i
+wbm_adr_i\[0\]
+wbm_dat_i\[0\]
+wbm_dat_o\[0\]
+wbm_sel_i\[0\]
+wbm_adr_i\[1\]
+wbm_dat_i\[1\]
+wbm_dat_o\[1\]
+wbm_sel_i\[1\]
+wbm_adr_i\[2\]
+wbm_dat_i\[2\]
+wbm_dat_o\[2\]
+wbm_sel_i\[2\]
+wbm_adr_i\[3\]
+wbm_dat_i\[3\]
+wbm_dat_o\[3\]
+wbm_sel_i\[3\]
+wbm_adr_i\[4\]
+wbm_dat_i\[4\]
+wbm_dat_o\[4\]
+wbm_adr_i\[5\]
+wbm_dat_i\[5\]
+wbm_dat_o\[5\]
+wbm_adr_i\[6\]
+wbm_dat_i\[6\]
+wbm_dat_o\[6\]
+wbm_adr_i\[7\]
+wbm_dat_i\[7\]
+wbm_dat_o\[7\]
+wbm_adr_i\[8\]
+wbm_dat_i\[8\]
+wbm_dat_o\[8\]
+wbm_adr_i\[9\]
+wbm_dat_i\[9\]
+wbm_dat_o\[9\]
+wbm_adr_i\[10\]
+wbm_dat_i\[10\]
+wbm_dat_o\[10\]
+wbm_adr_i\[11\]
+wbm_dat_i\[11\]
+wbm_dat_o\[11\]
+wbm_adr_i\[12\]
+wbm_dat_i\[12\]
+wbm_dat_o\[12\]
+wbm_adr_i\[13\]
+wbm_dat_i\[13\]
+wbm_dat_o\[13\]
+wbm_adr_i\[14\]
+wbm_dat_i\[14\]
+wbm_dat_o\[14\]
+wbm_adr_i\[15\]
+wbm_dat_i\[15\]
+wbm_dat_o\[15\]
+wbm_adr_i\[16\]
+wbm_dat_i\[16\]
+wbm_dat_o\[16\]
+wbm_adr_i\[17\]
+wbm_dat_i\[17\]
+wbm_dat_o\[17\]
+wbm_adr_i\[18\]
+wbm_dat_i\[18\]
+wbm_dat_o\[18\]
+wbm_adr_i\[19\]
+wbm_dat_i\[19\]
+wbm_dat_o\[19\]
+wbm_adr_i\[20\]
+wbm_dat_i\[20\]
+wbm_dat_o\[20\]
+wbm_adr_i\[21\]
+wbm_dat_i\[21\]
+wbm_dat_o\[21\]
+wbm_adr_i\[22\]
+wbm_dat_i\[22\]
+wbm_dat_o\[22\]
+wbm_adr_i\[23\]
+wbm_dat_i\[23\]
+wbm_dat_o\[23\]
+wbm_adr_i\[24\]
+wbm_dat_i\[24\]
+wbm_dat_o\[24\]
+wbm_adr_i\[25\]
+wbm_dat_i\[25\]
+wbm_dat_o\[25\]
+wbm_adr_i\[26\]
+wbm_dat_i\[26\]
+wbm_dat_o\[26\]
+wbm_adr_i\[27\]
+wbm_dat_i\[27\]
+wbm_dat_o\[27\]
+wbm_adr_i\[28\]
+wbm_dat_i\[28\]
+wbm_dat_o\[28\]
+wbm_adr_i\[29\]
+wbm_dat_i\[29\]
+wbm_dat_o\[29\]
+wbm_adr_i\[30\]
+wbm_dat_i\[30\]
+wbm_dat_o\[30\]
+wbm_adr_i\[31\]
+wbm_dat_i\[31\]
+wbm_dat_o\[31\]
+wbm_err_o
+
+la_data_in\[0\] 500 0 2
+la_data_out\[0\]
+la_oenb\[0\]
+la_data_in\[1\]
+la_data_out\[1\]
+la_oenb\[1\]
+la_data_in\[2\]
+la_data_out\[2\]
+la_oenb\[2\]
+la_data_in\[3\]
+la_data_out\[3\]
+la_oenb\[3\]
+la_data_in\[4\]
+la_data_out\[4\]
+la_oenb\[4\]
+la_data_in\[5\]
+la_data_out\[5\]
+la_oenb\[5\]
+la_data_in\[6\]
+la_data_out\[6\]
+la_oenb\[6\]
+la_data_in\[7\]
+la_data_out\[7\]
+la_oenb\[7\]
+la_data_in\[8\]
+la_data_out\[8\]
+la_oenb\[8\]
+la_data_in\[9\]
+la_data_out\[9\]
+la_oenb\[9\]
+la_data_in\[10\]
+la_data_out\[10\]
+la_oenb\[10\]
+la_data_in\[11\]
+la_data_out\[11\]
+la_oenb\[11\]
+la_data_in\[12\]
+la_data_out\[12\]
+la_oenb\[12\]
+la_data_in\[13\]
+la_data_out\[13\]
+la_oenb\[13\]
+la_data_in\[14\]
+la_data_out\[14\]
+la_oenb\[14\]
+la_data_in\[15\]
+la_data_out\[15\]
+la_oenb\[15\]
+la_data_in\[16\]
+la_data_out\[16\]
+la_oenb\[16\]
+la_data_in\[17\]
+la_data_out\[17\]
+la_oenb\[17\]
+la_data_in\[18\]
+la_data_out\[18\]
+la_oenb\[18\]
+la_data_in\[19\]
+la_data_out\[19\]
+la_oenb\[19\]
+la_data_in\[20\]
+la_data_out\[20\]
+la_oenb\[20\]
+la_data_in\[21\]
+la_data_out\[21\]
+la_oenb\[21\]
+la_data_in\[22\]
+la_data_out\[22\]
+la_oenb\[22\]
+la_data_in\[23\]
+la_data_out\[23\]
+la_oenb\[23\]
+la_data_in\[24\]
+la_data_out\[24\]
+la_oenb\[24\]
+la_data_in\[25\]
+la_data_out\[25\]
+la_oenb\[25\]
+la_data_in\[26\]
+la_data_out\[26\]
+la_oenb\[26\]
+la_data_in\[27\]
+la_data_out\[27\]
+la_oenb\[27\]
+la_data_in\[28\]
+la_data_out\[28\]
+la_oenb\[28\]
+la_data_in\[29\]
+la_data_out\[29\]
+la_oenb\[29\]
+la_data_in\[30\]
+la_data_out\[30\]
+la_oenb\[30\]
+la_data_in\[31\]
+la_data_out\[31\]
+la_oenb\[31\]
+la_data_in\[32\]
+la_data_out\[32\]
+la_oenb\[32\]
+la_data_in\[33\]
+la_data_out\[33\]
+la_oenb\[33\]
+la_data_in\[34\]
+la_data_out\[34\]
+la_oenb\[34\]
+la_data_in\[35\]
+la_data_out\[35\]
+la_oenb\[35\]
+la_data_in\[36\]
+la_data_out\[36\]
+la_oenb\[36\]
+la_data_in\[37\]
+la_data_out\[37\]
+la_oenb\[37\]
+la_data_in\[38\]
+la_data_out\[38\]
+la_oenb\[38\]
+la_data_in\[39\]
+la_data_out\[39\]
+la_oenb\[39\]
+la_data_in\[40\]
+la_data_out\[40\]
+la_oenb\[40\]
+la_data_in\[41\]
+la_data_out\[41\]
+la_oenb\[41\]
+la_data_in\[42\]
+la_data_out\[42\]
+la_oenb\[42\]
+la_data_in\[43\]
+la_data_out\[43\]
+la_oenb\[43\]
+la_data_in\[44\]
+la_data_out\[44\]
+la_oenb\[44\]
+la_data_in\[45\]
+la_data_out\[45\]
+la_oenb\[45\]
+la_data_in\[46\]
+la_data_out\[46\]
+la_oenb\[46\]
+la_data_in\[47\]
+la_data_out\[47\]
+la_oenb\[47\]
+la_data_in\[48\]
+la_data_out\[48\]
+la_oenb\[48\]
+la_data_in\[49\]
+la_data_out\[49\]
+la_oenb\[49\]
+la_data_in\[50\]
+la_data_out\[50\]
+la_oenb\[50\]
+la_data_in\[51\]
+la_data_out\[51\]
+la_oenb\[51\]
+la_data_in\[52\]
+la_data_out\[52\]
+la_oenb\[52\]
+la_data_in\[53\]
+la_data_out\[53\]
+la_oenb\[53\]
+la_data_in\[54\]
+la_data_out\[54\]
+la_oenb\[54\]
+la_data_in\[55\]
+la_data_out\[55\]
+la_oenb\[55\]
+la_data_in\[56\]
+la_data_out\[56\]
+la_oenb\[56\]
+la_data_in\[57\]
+la_data_out\[57\]
+la_oenb\[57\]
+la_data_in\[58\]
+la_data_out\[58\]
+la_oenb\[58\]
+la_data_in\[59\]
+la_data_out\[59\]
+la_oenb\[59\]
+la_data_in\[60\]
+la_data_out\[60\]
+la_oenb\[60\]
+la_data_in\[61\]
+la_data_out\[61\]
+la_oenb\[61\]
+la_data_in\[62\]
+la_data_out\[62\]
+la_oenb\[62\]
+la_data_in\[63\]
+la_data_out\[63\]
+la_oenb\[63\]
+la_data_in\[64\]
+la_data_out\[64\]
+la_oenb\[64\]
+la_data_in\[65\]
+la_data_out\[65\]
+la_oenb\[65\]
+la_data_in\[66\]
+la_data_out\[66\]
+la_oenb\[66\]
+la_data_in\[67\]
+la_data_out\[67\]
+la_oenb\[67\]
+la_data_in\[68\]
+la_data_out\[68\]
+la_oenb\[68\]
+la_data_in\[69\]
+la_data_out\[69\]
+la_oenb\[69\]
+la_data_in\[70\]
+la_data_out\[70\]
+la_oenb\[70\]
+la_data_in\[71\]
+la_data_out\[71\]
+la_oenb\[71\]
+la_data_in\[72\]
+la_data_out\[72\]
+la_oenb\[72\]
+la_data_in\[73\]
+la_data_out\[73\]
+la_oenb\[73\]
+la_data_in\[74\]
+la_data_out\[74\]
+la_oenb\[74\]
+la_data_in\[75\]
+la_data_out\[75\]
+la_oenb\[75\]
+la_data_in\[76\]
+la_data_out\[76\]
+la_oenb\[76\]
+la_data_in\[77\]
+la_data_out\[77\]
+la_oenb\[77\]
+la_data_in\[78\]
+la_data_out\[78\]
+la_oenb\[78\]
+la_data_in\[79\]
+la_data_out\[79\]
+la_oenb\[79\]
+la_data_in\[80\]
+la_data_out\[80\]
+la_oenb\[80\]
+la_data_in\[81\]
+la_data_out\[81\]
+la_oenb\[81\]
+la_data_in\[82\]
+la_data_out\[82\]
+la_oenb\[82\]
+la_data_in\[83\]
+la_data_out\[83\]
+la_oenb\[83\]
+la_data_in\[84\]
+la_data_out\[84\]
+la_oenb\[84\]
+la_data_in\[85\]
+la_data_out\[85\]
+la_oenb\[85\]
+la_data_in\[86\]
+la_data_out\[86\]
+la_oenb\[86\]
+la_data_in\[87\]
+la_data_out\[87\]
+la_oenb\[87\]
+la_data_in\[88\]
+la_data_out\[88\]
+la_oenb\[88\]
+la_data_in\[89\]
+la_data_out\[89\]
+la_oenb\[89\]
+la_data_in\[90\]
+la_data_out\[90\]
+la_oenb\[90\]
+la_data_in\[91\]
+la_data_out\[91\]
+la_oenb\[91\]
+la_data_in\[92\]
+la_data_out\[92\]
+la_oenb\[92\]
+la_data_in\[93\]
+la_data_out\[93\]
+la_oenb\[93\]
+la_data_in\[94\]
+la_data_out\[94\]
+la_oenb\[94\]
+la_data_in\[95\]
+la_data_out\[95\]
+la_oenb\[95\]
+la_data_in\[96\]
+la_data_out\[96\]
+la_oenb\[96\]
+la_data_in\[97\]
+la_data_out\[97\]
+la_oenb\[97\]
+la_data_in\[98\]
+la_data_out\[98\]
+la_oenb\[98\]
+la_data_in\[99\]
+la_data_out\[99\]
+la_oenb\[99\]
+la_data_in\[100\]
+la_data_out\[100\]
+la_oenb\[100\]
+la_data_in\[101\]
+la_data_out\[101\]
+la_oenb\[101\]
+la_data_in\[102\]
+la_data_out\[102\]
+la_oenb\[102\]
+la_data_in\[103\]
+la_data_out\[103\]
+la_oenb\[103\]
+la_data_in\[104\]
+la_data_out\[104\]
+la_oenb\[104\]
+la_data_in\[105\]
+la_data_out\[105\]
+la_oenb\[105\]
+la_data_in\[106\]
+la_data_out\[106\]
+la_oenb\[106\]
+la_data_in\[107\]
+la_data_out\[107\]
+la_oenb\[107\]
+la_data_in\[108\]
+la_data_out\[108\]
+la_oenb\[108\]
+la_data_in\[109\]
+la_data_out\[109\]
+la_oenb\[109\]
+la_data_in\[110\]
+la_data_out\[110\]
+la_oenb\[110\]
+la_data_in\[111\]
+la_data_out\[111\]
+la_oenb\[111\]
+la_data_in\[112\]
+la_data_out\[112\]
+la_oenb\[112\]
+la_data_in\[113\]
+la_data_out\[113\]
+la_oenb\[113\]
+la_data_in\[114\]
+la_data_out\[114\]
+la_oenb\[114\]
+la_data_in\[115\]
+la_data_out\[115\]
+la_oenb\[115\]
+la_data_in\[116\]
+la_data_out\[116\]
+la_oenb\[116\]
+la_data_in\[117\]
+la_data_out\[117\]
+la_oenb\[117\]
+la_data_in\[118\]
+la_data_out\[118\]
+la_oenb\[118\]
+la_data_in\[119\]
+la_data_out\[119\]
+la_oenb\[119\]
+la_data_in\[120\]
+la_data_out\[120\]
+la_oenb\[120\]
+la_data_in\[121\]
+la_data_out\[121\]
+la_oenb\[121\]
+la_data_in\[122\]
+la_data_out\[122\]
+la_oenb\[122\]
+la_data_in\[123\]
+la_data_out\[123\]
+la_oenb\[123\]
+la_data_in\[124\]
+la_data_out\[124\]
+la_oenb\[124\]
+la_data_in\[125\]
+la_data_out\[125\]
+la_oenb\[125\]
+la_data_in\[126\]
+la_data_out\[126\]
+la_oenb\[126\]
+la_data_in\[127\]
+la_data_out\[127\]
+la_oenb\[127\]
+
+#N
+wbs_stb_o 0000 0 2
+wbs_we_o
+wbs_adr_o\[31\]
+wbs_adr_o\[30\]
+wbs_adr_o\[29\]
+wbs_adr_o\[28\]
+wbs_adr_o\[27\]
+wbs_adr_o\[26\]
+wbs_adr_o\[25\]
+wbs_adr_o\[24\]
+wbs_adr_o\[23\]
+wbs_adr_o\[22\]
+wbs_adr_o\[21\]
+wbs_adr_o\[20\]
+wbs_adr_o\[19\]
+wbs_adr_o\[18\]
+wbs_adr_o\[17\]
+wbs_adr_o\[16\]
+wbs_adr_o\[15\]
+wbs_adr_o\[14\]
+wbs_adr_o\[13\]
+wbs_adr_o\[12\]
+wbs_adr_o\[11\]
+wbs_adr_o\[10\]
+wbs_adr_o\[9\]
+wbs_adr_o\[8\]
+wbs_adr_o\[7\]
+wbs_adr_o\[6\]
+wbs_adr_o\[5\]
+wbs_adr_o\[4\]
+wbs_adr_o\[3\]
+wbs_adr_o\[2\]
+wbs_adr_o\[1\]
+wbs_adr_o\[0\]
+wbs_sel_o\[3\]
+wbs_sel_o\[2\]
+wbs_sel_o\[1\]
+wbs_sel_o\[0\]
+wbs_dat_o\[31\]
+wbs_dat_o\[30\]
+wbs_dat_o\[29\]
+wbs_dat_o\[28\]
+wbs_dat_o\[27\]
+wbs_dat_o\[26\]
+wbs_dat_o\[25\]
+wbs_dat_o\[24\]
+wbs_dat_o\[23\]
+wbs_dat_o\[22\]
+wbs_dat_o\[21\]
+wbs_dat_o\[20\]
+wbs_dat_o\[19\]
+wbs_dat_o\[18\]
+wbs_dat_o\[17\]
+wbs_dat_o\[16\]
+wbs_dat_o\[15\]
+wbs_dat_o\[14\]
+wbs_dat_o\[13\]
+wbs_dat_o\[12\]
+wbs_dat_o\[11\]
+wbs_dat_o\[10\]
+wbs_dat_o\[9\]
+wbs_dat_o\[8\]
+wbs_dat_o\[7\]
+wbs_dat_o\[6\]
+wbs_dat_o\[5\]
+wbs_dat_o\[4\]
+wbs_dat_o\[3\]
+wbs_dat_o\[2\]
+wbs_dat_o\[1\]
+wbs_dat_o\[0\]
+wbs_dat_i\[31\]
+wbs_dat_i\[30\]
+wbs_dat_i\[29\]
+wbs_dat_i\[28\]
+wbs_dat_i\[27\]
+wbs_dat_i\[26\]
+wbs_dat_i\[25\]
+wbs_dat_i\[24\]
+wbs_dat_i\[23\]
+wbs_dat_i\[22\]
+wbs_dat_i\[21\]
+wbs_dat_i\[20\]
+wbs_dat_i\[19\]
+wbs_dat_i\[18\]
+wbs_dat_i\[17\]
+wbs_dat_i\[16\]
+wbs_dat_i\[15\]
+wbs_dat_i\[14\]
+wbs_dat_i\[13\]
+wbs_dat_i\[12\]
+wbs_dat_i\[11\]
+wbs_dat_i\[10\]
+wbs_dat_i\[9\]
+wbs_dat_i\[8\]
+wbs_dat_i\[7\]
+wbs_dat_i\[6\]
+wbs_dat_i\[5\]
+wbs_dat_i\[4\]
+wbs_dat_i\[3\]
+wbs_dat_i\[2\]
+wbs_dat_i\[1\]
+wbs_dat_i\[0\]
+wbs_ack_i
+wbs_err_i
+wbs_cyc_o
+
+cfg_glb_ctrl\[7\]
+cfg_glb_ctrl\[6\]
+cfg_glb_ctrl\[5\]
+cfg_glb_ctrl\[4\]
+cfg_glb_ctrl\[3\]
+cfg_glb_ctrl\[2\]
+cfg_glb_ctrl\[1\]
+cfg_glb_ctrl\[0\]
+cfg_clk_ctrl1\[31\]
+cfg_clk_ctrl1\[30\]
+cfg_clk_ctrl1\[29\]
+cfg_clk_ctrl1\[28\]
+cfg_clk_ctrl1\[27\]
+cfg_clk_ctrl1\[26\]
+cfg_clk_ctrl1\[25\]
+cfg_clk_ctrl1\[24\]
+cfg_clk_ctrl1\[23\]
+cfg_clk_ctrl1\[22\]
+cfg_clk_ctrl1\[21\]
+cfg_clk_ctrl1\[20\]
+cfg_clk_ctrl1\[19\]
+cfg_clk_ctrl1\[18\]
+cfg_clk_ctrl1\[17\]
+cfg_clk_ctrl1\[16\]
+cfg_clk_ctrl1\[15\]
+cfg_clk_ctrl1\[14\]
+cfg_clk_ctrl1\[13\]
+cfg_clk_ctrl1\[12\]
+cfg_clk_ctrl1\[11\]
+cfg_clk_ctrl1\[10\]
+cfg_clk_ctrl1\[9\]
+cfg_clk_ctrl1\[8\]
+cfg_clk_ctrl1\[7\]
+cfg_clk_ctrl1\[6\]
+cfg_clk_ctrl1\[5\]
+cfg_clk_ctrl1\[4\]
+cfg_clk_ctrl1\[3\]
+cfg_clk_ctrl1\[2\]
+cfg_clk_ctrl1\[1\]
+cfg_clk_ctrl1\[0\]
+cfg_clk_ctrl2\[31\]
+cfg_clk_ctrl2\[30\]
+cfg_clk_ctrl2\[29\]
+cfg_clk_ctrl2\[28\]
+cfg_clk_ctrl2\[27\]
+cfg_clk_ctrl2\[26\]
+cfg_clk_ctrl2\[25\]
+cfg_clk_ctrl2\[24\]
+cfg_clk_ctrl2\[23\]
+cfg_clk_ctrl2\[22\]
+cfg_clk_ctrl2\[21\]
+cfg_clk_ctrl2\[20\]
+cfg_clk_ctrl2\[19\]
+cfg_clk_ctrl2\[18\]
+cfg_clk_ctrl2\[17\]
+cfg_clk_ctrl2\[16\]
+cfg_clk_ctrl2\[15\]
+cfg_clk_ctrl2\[14\]
+cfg_clk_ctrl2\[13\]
+cfg_clk_ctrl2\[12\]
+cfg_clk_ctrl2\[11\]
+cfg_clk_ctrl2\[10\]
+cfg_clk_ctrl2\[9\]
+cfg_clk_ctrl2\[8\]
+cfg_clk_ctrl2\[7\]
+cfg_clk_ctrl2\[6\]
+cfg_clk_ctrl2\[5\]
+cfg_clk_ctrl2\[4\]
+cfg_clk_ctrl2\[3\]
+cfg_clk_ctrl2\[2\]
+cfg_clk_ctrl2\[1\]
+cfg_clk_ctrl2\[0\]
+
diff --git a/signoff/wb_host/OPENLANE_VERSION b/signoff/wb_host/OPENLANE_VERSION
new file mode 100644
index 0000000..a2633b1
--- /dev/null
+++ b/signoff/wb_host/OPENLANE_VERSION
@@ -0,0 +1 @@
+openlane rc7
diff --git a/signoff/wb_host/PDK_SOURCES b/signoff/wb_host/PDK_SOURCES
new file mode 100644
index 0000000..8b58bd5
--- /dev/null
+++ b/signoff/wb_host/PDK_SOURCES
@@ -0,0 +1,6 @@
+-ne openlane
+a68c95289612a361870acedb7f6478fcfae32e49
+-ne skywater-pdk
+f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7
+-ne open_pdks
+522a373441a865fee9d6e3783015b4445f11afe6
diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv
new file mode 100644
index 0000000..1116b1b
--- /dev/null
+++ b/signoff/wb_host/final_summary_report.csv
@@ -0,0 +1,2 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/wb_host,wb_host,wb_host,Flow_completed,0h6m30s,0h3m47s,35490.0,0.2,17745.0,28,592.36,3549,0,0,0,0,0,0,0,3,0,0,0,315592,33452,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,261952954,0.0,48.32,13.08,26.98,0.0,-1,3270,3912,529,1171,0,0,0,3549,85,0,5,9,30,27,13,915,660,813,16,130,2343,0,2473,100.0,10.0,10,AREA 0,4,50,1,50,153.18,0.62,0,sky130_fd_sc_hd,4,4
diff --git a/verilog/rtl/lib/async_wb.sv b/verilog/rtl/lib/async_wb.sv
new file mode 100644
index 0000000..48bce58
--- /dev/null
+++ b/verilog/rtl/lib/async_wb.sv
@@ -0,0 +1,188 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Async Wishbone Interface ////
+//// ////
+//// This file is part of the YIFive cores project ////
+//// http://www.opencores.org/cores/yifive/ ////
+//// ////
+//// Description ////
+//// This block does async Wishbone from one clock to other ////
+//// clock domain
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 25th Feb 2021, Dinesh A ////
+//// initial version ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+module async_wb (
+
+ // Master Port
+ input logic wbm_rst_n , // Regular Reset signal
+ input logic wbm_clk_i , // System clock
+ input logic wbm_cyc_i , // strobe/request
+ input logic wbm_stb_i , // strobe/request
+ input logic [31:0] wbm_adr_i , // address
+ input logic wbm_we_i , // write
+ input logic [31:0] wbm_dat_i , // data output
+ input logic [3:0] wbm_sel_i , // byte enable
+ output logic [31:0] wbm_dat_o , // data input
+ output logic wbm_ack_o , // acknowlegement
+ output logic wbm_err_o , // error
+
+ // Slave Port
+ input logic wbs_rst_n , // Regular Reset signal
+ input logic wbs_clk_i , // System clock
+ output logic wbs_cyc_o , // strobe/request
+ output logic wbs_stb_o , // strobe/request
+ output logic [31:0] wbs_adr_o , // address
+ output logic wbs_we_o , // write
+ output logic [31:0] wbs_dat_o , // data output
+ output logic [3:0] wbs_sel_o , // byte enable
+ input logic [31:0] wbs_dat_i , // data input
+ input logic wbs_ack_i , // acknowlegement
+ input logic wbs_err_i // error
+
+ );
+
+
+
+
+//-------------------------------------------------
+// Master Interface
+// -------------------------------------------------
+logic PendingRd ; // Pending Read Transaction
+logic m_cmd_wr_en ;
+logic [70:0] m_cmd_wr_data ;
+logic m_cmd_wr_full ;
+logic m_cmd_wr_afull ;
+
+logic m_resp_rd_empty ;
+logic m_resp_rd_aempty ;
+logic m_resp_rd_en ;
+logic [32:0] m_resp_rd_data ;
+
+// Master Write Interface
+
+
+assign m_cmd_wr_en = (!PendingRd) && wbm_stb_i && !m_cmd_wr_full && !m_cmd_wr_afull;
+
+assign m_cmd_wr_data = {wbm_cyc_i,wbm_stb_i,wbm_adr_i,wbm_we_i,wbm_dat_i,wbm_sel_i};
+
+always@(negedge wbm_rst_n or posedge wbm_clk_i)
+begin
+ if(wbm_rst_n == 0) begin
+ PendingRd <= 1'b0;
+ end else begin
+ if((!PendingRd) && wbm_stb_i && (!wbm_we_i)) begin
+ PendingRd <= 1'b1;
+ end else if(PendingRd && wbm_stb_i && (!wbm_we_i) && wbm_ack_o) begin
+ PendingRd <= 1'b0;
+ end
+ end
+end
+
+
+// Master Read Interface
+// For Write is feed through, if there is space in fifo the ack
+// For Read, Wait for Response Path FIFO status
+assign wbm_ack_o = (wbm_stb_i && wbm_we_i) ? m_cmd_wr_en : // Write Logic
+ (wbm_stb_i && (!wbm_we_i)) ? !m_resp_rd_empty : 1'b0; // Read Logic
+
+assign m_resp_rd_en = !m_resp_rd_empty;
+assign wbm_dat_o = m_resp_rd_data[31:0];
+assign wbm_err_o = m_resp_rd_data[32];
+
+
+//------------------------------
+// Slave Interface
+//-------------------------------
+
+logic [70:0] s_cmd_rd_data ;
+logic s_cmd_rd_empty ;
+logic s_cmd_rd_aempty ;
+logic s_cmd_rd_en ;
+logic s_resp_wr_en ;
+logic [32:0] s_resp_wr_data ;
+logic s_resp_wr_full ;
+logic s_resp_wr_afull ;
+
+
+// Read Interface
+assign {wbs_cyc_o,wbs_stb_o,wbs_adr_o,wbs_we_o,wbs_dat_o,wbs_sel_o} = (s_cmd_rd_empty) ? '0: s_cmd_rd_data;
+assign s_cmd_rd_en = wbs_ack_i;
+
+// Write Interface
+// response send only for read logic
+assign s_resp_wr_en = wbs_stb_o & (!wbs_we_o) & wbs_ack_i & !s_resp_wr_full;
+assign s_resp_wr_data = {wbs_err_i,wbs_dat_i};
+
+async_fifo #(.W(71), .DP(4), .WR_FAST(1), .RD_FAST(1)) u_cmd_if (
+ // Sync w.r.t WR clock
+ .wr_clk (wbm_clk_i ),
+ .wr_reset_n (wbm_rst_n ),
+ .wr_en (m_cmd_wr_en ),
+ .wr_data (m_cmd_wr_data ),
+ .full (m_cmd_wr_full ),
+ .afull (m_cmd_wr_afull ),
+
+ // Sync w.r.t RD Clock
+ .rd_clk (wbs_clk_i ),
+ .rd_reset_n (wbs_rst_n ),
+ .rd_en (s_cmd_rd_en ),
+ .empty (s_cmd_rd_empty ), // sync'ed to rd_clk
+ .aempty (s_cmd_rd_aempty ), // sync'ed to rd_clk
+ .rd_data (s_cmd_rd_data )
+ );
+
+async_fifo #(.W(33), .DP(4), .WR_FAST(1), .RD_FAST(1)) u_resp_if (
+ // Sync w.r.t WR clock
+ .wr_clk (wbs_clk_i ),
+ .wr_reset_n (wbs_rst_n ),
+ .wr_en (s_resp_wr_en ),
+ .wr_data (s_resp_wr_data ),
+ .full (s_resp_wr_full ),
+ .afull (s_resp_wr_afull ),
+
+ // Sync w.r.t RD Clock
+ .rd_clk (wbm_clk_i ),
+ .rd_reset_n (wbm_rst_n ),
+ .rd_en (m_resp_rd_en ),
+ .empty (m_resp_rd_empty ), // sync'ed to rd_clk
+ .aempty (m_resp_rd_aempty ), // sync'ed to rd_clk
+ .rd_data (m_resp_rd_data )
+ );
+
+
+
+endmodule
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv
new file mode 100644
index 0000000..c642421
--- /dev/null
+++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -0,0 +1,268 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Wishbone host Interface ////
+//// ////
+//// This file is part of the YIFive cores project ////
+//// http://www.opencores.org/cores/yifive/ ////
+//// ////
+//// Description ////
+//// This block does async Wishbone from one clock to other ////
+//// clock domain ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 25th Feb 2021, Dinesh A ////
+//// initial version ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+module wb_host (
+
+`ifdef USE_POWER_PINS
+ inout vccd1, // User area 1 1.8V supply
+ inout vssd1, // User area 1 digital ground
+`endif
+
+ // Master Port
+ input logic wbm_rst_i , // Regular Reset signal
+ input logic wbm_clk_i , // System clock
+ input logic wbm_cyc_i , // strobe/request
+ input logic wbm_stb_i , // strobe/request
+ input logic [31:0] wbm_adr_i , // address
+ input logic wbm_we_i , // write
+ input logic [31:0] wbm_dat_i , // data output
+ input logic [3:0] wbm_sel_i , // byte enable
+ output logic [31:0] wbm_dat_o , // data input
+ output logic wbm_ack_o , // acknowlegement
+ output logic wbm_err_o , // error
+
+ // Slave Port
+ output logic wbs_clk_i , // System clock
+ output logic wbs_cyc_o , // strobe/request
+ output logic wbs_stb_o , // strobe/request
+ output logic [31:0] wbs_adr_o , // address
+ output logic wbs_we_o , // write
+ output logic [31:0] wbs_dat_o , // data output
+ output logic [3:0] wbs_sel_o , // byte enable
+ input logic [31:0] wbs_dat_i , // data input
+ input logic wbs_ack_i , // acknowlegement
+ input logic wbs_err_i , // error
+
+ output logic [7:0] cfg_glb_ctrl ,
+ output logic [31:0] cfg_clk_ctrl1 ,
+ output logic [31:0] cfg_clk_ctrl2 ,
+
+ // Logic Analyzer Signals
+ input logic [127:0] la_data_in ,
+ output logic [127:0] la_data_out ,
+ input logic [127:0] la_oenb
+ );
+
+
+//--------------------------------
+// local dec
+//
+//--------------------------------
+logic wbm_rst_n;
+logic wbs_rst_n;
+logic [31:0] wbm_dat_int; // data input
+logic wbm_ack_int; // acknowlegement
+logic wbm_err_int; // error
+
+logic reg_sel ;
+logic [1:0] sw_addr ;
+logic sw_rd_en ;
+logic sw_wr_en ;
+logic [31:0] reg_rdata ;
+logic [31:0] reg_out ;
+logic reg_ack ;
+logic [7:0] config_reg ;
+logic [31:0] clk_ctrl1 ;
+logic [31:0] clk_ctrl2 ;
+logic sw_wr_en_0;
+logic sw_wr_en_1;
+logic sw_wr_en_2;
+logic sw_wr_en_3;
+logic [7:0] cfg_bank_sel;
+logic [31:0] wbm_adr_int;
+logic wbm_stb_int;
+
+
+assign wbm_rst_n = !wbm_rst_i;
+assign wbs_rst_n = !wbm_rst_i;
+
+assign wbs_clk_i = wbm_clk_i;
+
+assign wbm_dat_o = (reg_sel) ? reg_rdata : wbm_dat_int; // data input
+assign wbm_ack_o = (reg_sel) ? reg_ack : wbm_ack_int; // acknowlegement
+assign wbm_err_o = (reg_sel) ? 1'b0 : wbm_err_int; // error
+
+//-----------------------------------------------------------------------
+// Local register decide based on address[31] == 1
+//
+// Locally there register are define to control the reset and clock for user
+// area
+//-----------------------------------------------------------------------
+// caravel user space is 0x3000_0000 to 0x30FF_FFFF
+// So we have allocated
+// 0x3080_0000 - 0x3080_00FF - Assigned to WB Host Address Space
+// Since We need more than 16MB Address space to access SDRAM/SPI we have
+// added indirect MSB 8 bit address select option
+// So Address will be {Bank_Sel[7:0], wbm_adr_i[23:0}
+// ---------------------------------------------------------------------
+assign reg_sel = wbm_stb_i & (wbm_adr_i[23] == 1'b1);
+
+assign sw_addr = wbm_adr_i [3:2];
+assign sw_rd_en = reg_sel & !wbm_we_i;
+assign sw_wr_en = reg_sel & wbm_we_i;
+
+assign sw_wr_en_0 = sw_wr_en && (sw_addr==0);
+assign sw_wr_en_1 = sw_wr_en && (sw_addr==1);
+assign sw_wr_en_2 = sw_wr_en && (sw_addr==2);
+assign sw_wr_en_3 = sw_wr_en && (sw_addr==3);
+
+always @ (posedge wbm_clk_i or negedge wbm_rst_n)
+begin : preg_out_Seq
+ if (wbm_rst_n == 1'b0)
+ begin
+ reg_rdata <= 'h0;
+ reg_ack <= 1'b0;
+ end
+ else if (sw_rd_en && !reg_ack)
+ begin
+ reg_rdata <= reg_out ;
+ reg_ack <= 1'b1;
+ end
+ else if (sw_wr_en && !reg_ack)
+ reg_ack <= 1'b1;
+ else
+ begin
+ reg_ack <= 1'b0;
+ end
+end
+
+always @( *)
+begin
+ reg_out [31:0] = 8'd0;
+
+ case (sw_addr [1:0])
+ 2'b00 : reg_out [31:0] = {24'h0,cfg_glb_ctrl [7:0]};
+ 2'b01 : reg_out [31:0] = {24'h0,cfg_bank_sel [7:0]};
+ 2'b10 : reg_out [31:0] = cfg_clk_ctrl1 [31:0];
+ 2'b11 : reg_out [31:0] = cfg_clk_ctrl2 [31:0];
+ default : reg_out [31:0] = 'h0;
+ endcase
+end
+
+
+
+generic_register #(8,0 ) u_glb_ctrl (
+ .we ({8{sw_wr_en_0}} ),
+ .data_in (wbm_dat_i[7:0] ),
+ .reset_n (wbm_rst_n ),
+ .clk (wbm_clk_i ),
+
+ //List of Outs
+ .data_out (cfg_glb_ctrl[7:0] )
+ );
+
+generic_register #(8,8'h30 ) u_bank_sel (
+ .we ({8{sw_wr_en_1}} ),
+ .data_in (wbm_dat_i[7:0] ),
+ .reset_n (wbm_rst_n ),
+ .clk (wbm_clk_i ),
+
+ //List of Outs
+ .data_out (cfg_bank_sel[7:0] )
+ );
+
+
+generic_register #(32,0 ) u_clk_ctrl1 (
+ .we ({32{sw_wr_en_2}} ),
+ .data_in (wbm_dat_i[31:0] ),
+ .reset_n (wbm_rst_n ),
+ .clk (wbm_clk_i ),
+
+ //List of Outs
+ .data_out (cfg_clk_ctrl1[31:0])
+ );
+
+generic_register #(32,0 ) u_clk_ctrl2 (
+ .we ({32{sw_wr_en_3}} ),
+ .data_in (wbm_dat_i[31:0] ),
+ .reset_n (wbm_rst_n ),
+ .clk (wbm_clk_i ),
+
+ //List of Outs
+ .data_out (cfg_clk_ctrl2[31:0])
+ );
+
+
+assign wbm_stb_int = wbm_stb_i & !reg_sel;
+
+// Since design need more than 16MB address space, we have implemented
+// indirect access
+assign wbm_adr_int = {cfg_bank_sel[7:0],wbm_adr_i[23:0]};
+
+async_wb u_async_wb(
+// Master Port
+ .wbm_rst_n (wbm_rst_n ),
+ .wbm_clk_i (wbm_clk_i ),
+ .wbm_cyc_i (wbm_cyc_i ),
+ .wbm_stb_i (wbm_stb_int ),
+ .wbm_adr_i (wbm_adr_int ),
+ .wbm_we_i (wbm_we_i ),
+ .wbm_dat_i (wbm_dat_i ),
+ .wbm_sel_i (wbm_sel_i ),
+ .wbm_dat_o (wbm_dat_int ),
+ .wbm_ack_o (wbm_ack_int ),
+ .wbm_err_o (wbm_err_int ),
+
+// Slave Port
+ .wbs_rst_n (wbs_rst_n ),
+ .wbs_clk_i (wbs_clk_i ),
+ .wbs_cyc_o (wbs_cyc_o ),
+ .wbs_stb_o (wbs_stb_o ),
+ .wbs_adr_o (wbs_adr_o ),
+ .wbs_we_o (wbs_we_o ),
+ .wbs_dat_o (wbs_dat_o ),
+ .wbs_sel_o (wbs_sel_o ),
+ .wbs_dat_i (wbs_dat_i ),
+ .wbs_ack_i (wbs_ack_i ),
+ .wbs_err_i (wbs_err_i )
+
+ );
+
+
+
+
+endmodule
