synthesis with latest yosys with $ netname avoidance fix
diff --git a/openlane/syntacore/config.tcl b/openlane/syntacore/config.tcl
index 57ff230..1ce4c23 100755
--- a/openlane/syntacore/config.tcl
+++ b/openlane/syntacore/config.tcl
@@ -113,5 +113,5 @@
set ::env(FP_PDN_VPITCH) 100
set ::env(FP_PDN_HPITCH) 100
-set ::env(FP_PDN_VWIDTH) 5
-set ::env(FP_PDN_HWIDTH) 5
+set ::env(FP_PDN_VWIDTH) 3
+set ::env(FP_PDN_HWIDTH) 3
diff --git a/openlane/user_project_wrapper/mod.tcl b/openlane/user_project_wrapper/mod.tcl
index 0e97ab8..6eeebbe 100644
--- a/openlane/user_project_wrapper/mod.tcl
+++ b/openlane/user_project_wrapper/mod.tcl
@@ -57,9 +57,9 @@
link_design scr1_top_wb
write_verilog -remove_cells [get_lib_cells {sky130_fd_sc_hd__decap* sky130_fd_sc_hd__fill* sky130_fd_sc_hd__diode_* sky130_ef_sc_hd__fakediode* sky130_fd_sc_hd__tapvpwrvgnd*}] netlist/syntacore.v
-read_verilog ../../verilog/gl/uart.v
-link_design uart_core
-write_verilog -remove_cells [get_lib_cells {sky130_fd_sc_hd__decap* sky130_fd_sc_hd__fill* sky130_fd_sc_hd__diode_* sky130_ef_sc_hd__fakediode* sky130_fd_sc_hd__tapvpwrvgnd*}] netlist/uart.v
+read_verilog ../../verilog/gl/uart_i2cm_usb.v
+link_design uart_i2c_usb_top
+write_verilog -remove_cells [get_lib_cells {sky130_fd_sc_hd__decap* sky130_fd_sc_hd__fill* sky130_fd_sc_hd__diode_* sky130_ef_sc_hd__fakediode* sky130_fd_sc_hd__tapvpwrvgnd*}] netlist/uart_i2cm_usb.v
read_verilog ../../verilog/gl/wb_host.v
link_design wb_host
diff --git a/openlane/user_project_wrapper/sta.tcl b/openlane/user_project_wrapper/sta.tcl
index 3b72ab5..5be0cbe 100644
--- a/openlane/user_project_wrapper/sta.tcl
+++ b/openlane/user_project_wrapper/sta.tcl
@@ -37,7 +37,7 @@
read_verilog netlist/sdram.v
read_verilog netlist/spi_master.v
read_verilog netlist/syntacore.v
-read_verilog netlist/uart.v
+read_verilog netlist/uart_i2cm_usb.v
read_verilog netlist/wb_host.v
read_verilog netlist/wb_interconnect.v
read_verilog netlist/user_project_wrapper.v
@@ -55,10 +55,10 @@
read_spef -path u_skew_sd_ci ../../spef/clk_skew_adjust.spef
read_spef -path u_skew_sp_co ../../spef/clk_skew_adjust.spef
read_spef -path u_glbl_cfg ../../spef/glbl_cfg.spef
-read_spef -path u_riscv_top ../../spef/scr1_top_wb.spef
-read_spef -path u_sdram_ctrl ../../spef/sdrc_top.spef
-read_spef -path u_spi_master ../../spef/spim_top.spef
-read_spef -path u_uart_core ../../spef/uart_core.spef
+read_spef -path u_riscv_top ../../spef/syntacore.spef
+read_spef -path u_sdram_ctrl ../../spef/sdram.spef
+read_spef -path u_spi_master ../../spef/spi_master.spef
+read_spef -path u_uart_i2c_usb ../../spef/uart_i2cm_usb.spef
read_spef -path u_wb_host ../../spef/wb_host.spef
read_spef -path u_intercon ../../spef/wb_interconnect.spef
read_spef ../..//spef/user_project_wrapper.spef
diff --git a/signoff/clk_skew_adjust/OPENLANE_VERSION b/signoff/clk_skew_adjust/OPENLANE_VERSION
index b340faa..ad796aa 100644
--- a/signoff/clk_skew_adjust/OPENLANE_VERSION
+++ b/signoff/clk_skew_adjust/OPENLANE_VERSION
@@ -1 +1 @@
-openlane v0.21-5-gd475aa2
+openlane v0.21-6-gbc3b032
diff --git a/signoff/clk_skew_adjust/final_summary_report.csv b/signoff/clk_skew_adjust/final_summary_report.csv
index 817f52f..6c84744 100644
--- a/signoff/clk_skew_adjust/final_summary_report.csv
+++ b/signoff/clk_skew_adjust/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/clk_skew_adjust,clk_skew_adjust,clk_skew_adjust,Flow_completed,0h2m18s,0h1m16s,7500.0,0.01,3000.0,5,390.3,30,0,0,0,0,0,0,0,0,0,0,0,3073,206,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,0.0,7.17,7.3,0.0,-1,-1,32,35,32,35,0,0,0,30,0,0,0,0,0,0,0,0,-1,-1,-1,64,102,0,166,90.9090909090909,11,10,AREA 0,5,40,1,20,20,0.55,0,sky130_fd_sc_hd,4,3
+0,/project/openlane/clk_skew_adjust,clk_skew_adjust,clk_skew_adjust,Flow_completed,0h1m15s,0h0m36s,7500.0,0.01,3000.0,5,391.95,30,0,0,0,0,0,0,0,0,0,0,0,2812,197,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,0.0,6.42,6.62,0.0,-1,-1,32,35,32,35,0,0,0,30,0,0,0,0,0,0,0,0,-1,-1,-1,64,102,0,166,90.9090909090909,11,10,AREA 0,5,40,1,20,20,0.55,0,sky130_fd_sc_hd,4,3
diff --git a/signoff/glbl_cfg/OPENLANE_VERSION b/signoff/glbl_cfg/OPENLANE_VERSION
index b340faa..ad796aa 100644
--- a/signoff/glbl_cfg/OPENLANE_VERSION
+++ b/signoff/glbl_cfg/OPENLANE_VERSION
@@ -1 +1 @@
-openlane v0.21-5-gd475aa2
+openlane v0.21-6-gbc3b032
diff --git a/signoff/glbl_cfg/final_summary_report.csv b/signoff/glbl_cfg/final_summary_report.csv
index 5297ea2..68bccb3 100644
--- a/signoff/glbl_cfg/final_summary_report.csv
+++ b/signoff/glbl_cfg/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/glbl_cfg,glbl_cfg,glbl_cfg,Flow_completed,0h15m1s,0h9m17s,45883.33333333334,0.12,22941.66666666667,40,569.04,2753,0,0,0,0,0,0,0,0,0,-1,0,131923,23407,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,98939272,0.0,25.3,27.26,0.31,-1,-1,2637,2802,459,624,0,0,0,2753,1,0,3,0,471,0,0,562,577,533,10,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,5
+0,/project/openlane/glbl_cfg,glbl_cfg,glbl_cfg,Flow_completed,0h15m36s,0h9m28s,45883.33333333334,0.12,22941.66666666667,40,569.11,2753,0,0,0,0,0,0,0,0,0,-1,0,131923,23407,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,98939272,0.0,25.3,27.26,0.31,-1,-1,2637,2802,459,624,0,0,0,2753,1,0,3,0,471,0,0,562,577,533,10,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,5
diff --git a/signoff/sdram/OPENLANE_VERSION b/signoff/sdram/OPENLANE_VERSION
index b340faa..ad796aa 100644
--- a/signoff/sdram/OPENLANE_VERSION
+++ b/signoff/sdram/OPENLANE_VERSION
@@ -1 +1 @@
-openlane v0.21-5-gd475aa2
+openlane v0.21-6-gbc3b032
diff --git a/signoff/sdram/final_summary_report.csv b/signoff/sdram/final_summary_report.csv
index 78fe391..43b9118 100644
--- a/signoff/sdram/final_summary_report.csv
+++ b/signoff/sdram/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/sdram,sdrc_top,sdram,Flow_completed,0h23m46s,0h10m24s,41131.42857142857,0.35,20565.714285714286,30,676.02,7198,0,0,0,0,0,0,0,0,0,-1,0,316374,57011,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,245789185,0.0,25.77,16.71,2.77,-1,-1,7102,7361,1246,1505,0,0,0,7198,197,107,83,94,354,211,32,2289,1267,1186,27,350,4248,0,4598,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,5
+0,/project/openlane/sdram,sdrc_top,sdram,Flow_completed,0h16m1s,0h5m47s,41017.14285714286,0.35,20508.57142857143,30,667.97,7178,0,0,0,0,0,0,0,0,0,-1,0,323270,57447,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,249088125,0.0,26.22,17.06,2.92,-1,-1,7082,7341,1219,1478,0,0,0,7178,197,107,83,91,354,212,31,2289,1267,1186,27,350,4248,0,4598,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,5
diff --git a/signoff/spi_master/OPENLANE_VERSION b/signoff/spi_master/OPENLANE_VERSION
index b340faa..ad796aa 100644
--- a/signoff/spi_master/OPENLANE_VERSION
+++ b/signoff/spi_master/OPENLANE_VERSION
@@ -1 +1 @@
-openlane v0.21-5-gd475aa2
+openlane v0.21-6-gbc3b032
diff --git a/signoff/spi_master/final_summary_report.csv b/signoff/spi_master/final_summary_report.csv
index cc16099..1c8a281 100644
--- a/signoff/spi_master/final_summary_report.csv
+++ b/signoff/spi_master/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/spi_master,spim_top,spi_master,Flow_completed,0h25m31s,0h15m10s,58515.38461538461,0.26,29257.692307692305,47,663.95,7607,0,0,0,0,0,0,0,0,1,-1,0,385862,66191,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,302026706,0.0,31.95,39.67,0.0,-1,-1,7543,7683,1272,1412,0,0,0,7607,245,0,169,101,1053,212,32,2444,1353,1292,24,460,3132,0,3592,100.0,10.0,10,AREA 0,4,50,1,100,100,0.45,0,sky130_fd_sc_hd,4,5
+0,/project/openlane/spi_master,spim_top,spi_master,Flow_completed,0h29m40s,0h16m11s,58500.0,0.26,29250.0,47,675.88,7605,0,0,0,0,0,0,0,0,1,-1,0,389393,66138,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,305945143,0.0,32.37,39.92,0.14,-1,-1,7541,7681,1272,1412,0,0,0,7605,245,0,169,100,1051,209,33,2443,1353,1292,24,460,3132,0,3592,100.0,10.0,10,AREA 0,4,50,1,100,100,0.45,0,sky130_fd_sc_hd,4,5
diff --git a/signoff/syntacore/OPENLANE_VERSION b/signoff/syntacore/OPENLANE_VERSION
index b340faa..ad796aa 100644
--- a/signoff/syntacore/OPENLANE_VERSION
+++ b/signoff/syntacore/OPENLANE_VERSION
@@ -1 +1 @@
-openlane v0.21-5-gd475aa2
+openlane v0.21-6-gbc3b032
diff --git a/signoff/syntacore/final_summary_report.csv b/signoff/syntacore/final_summary_report.csv
index e27f4a4..33bb518 100644
--- a/signoff/syntacore/final_summary_report.csv
+++ b/signoff/syntacore/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/syntacore,scr1_top_wb,syntacore,Flow_completed,1h36m23s,0h30m17s,27898.958333333336,1.92,13949.479166666668,21,1262.02,26783,0,0,0,0,0,0,0,0,5,-1,0,1636827,256299,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,1285883388,0.0,23.06,15.08,4.68,0.82,-1,26606,26907,3393,3694,0,0,0,26783,739,68,674,587,2814,994,289,7964,3220,3184,73,866,24574,0,25440,100.0,10.0,10,AREA 0,4,50,1,100,100,0.45,0,sky130_fd_sc_hd,4,5
+0,/project/openlane/syntacore,scr1_top_wb,syntacore,Flow_completed,1h28m26s,0h25m23s,27737.5,1.92,13868.75,21,1242.11,26628,0,0,0,0,0,0,0,0,3,-1,0,1635488,254093,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,1302938503,0.0,22.86,15.12,5.14,0.39,-1,26451,26752,3329,3630,0,0,0,26628,699,68,654,587,2858,979,288,7955,3220,3184,64,866,24574,0,25440,100.0,10.0,10,AREA 0,4,50,1,100,100,0.45,0,sky130_fd_sc_hd,4,5
diff --git a/signoff/uart_i2cm_usb/OPENLANE_VERSION b/signoff/uart_i2cm_usb/OPENLANE_VERSION
index b340faa..ad796aa 100644
--- a/signoff/uart_i2cm_usb/OPENLANE_VERSION
+++ b/signoff/uart_i2cm_usb/OPENLANE_VERSION
@@ -1 +1 @@
-openlane v0.21-5-gd475aa2
+openlane v0.21-6-gbc3b032
diff --git a/signoff/uart_i2cm_usb/final_summary_report.csv b/signoff/uart_i2cm_usb/final_summary_report.csv
index 7a6690c..4829488 100644
--- a/signoff/uart_i2cm_usb/final_summary_report.csv
+++ b/signoff/uart_i2cm_usb/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/uart_i2cm_usb,uart_i2c_usb_top,uart_i2cm_usb,Flow_completed,0h31m58s,0h16m32s,59161.90476190476,0.42,29580.95238095238,45,754.52,12424,0,0,0,0,0,0,0,0,0,-1,0,540329,99860,-3.02,-3.02,-2.96,-2.96,-3.01,-3.02,-3.02,-2.96,-2.96,-3.01,401510839,0.0,31.6,31.27,0.13,-1,-1,12403,12472,2256,2325,0,0,0,12424,357,10,210,251,2101,326,79,2682,2216,2171,28,498,5146,0,5644,76.86395080707149,13.01,10,AREA 0,4,50,1,100,100,0.45,0,sky130_fd_sc_hd,4,5
+0,/project/openlane/uart_i2cm_usb,uart_i2c_usb_top,uart_i2cm_usb,Flow_completed,0h42m9s,0h23m0s,59219.047619047626,0.42,29609.523809523813,45,765.19,12436,0,0,0,0,0,0,0,0,0,-1,0,538778,100542,-2.99,-2.99,-2.96,-2.96,-3.03,-2.99,-2.99,-2.96,-2.96,-3.03,402935829,0.0,31.48,31.11,0.41,-1,-1,12415,12484,2256,2325,0,0,0,12436,363,10,209,250,2102,323,80,2681,2216,2171,28,498,5146,0,5644,76.74597083653109,13.03,10,AREA 0,4,50,1,100,100,0.45,0,sky130_fd_sc_hd,4,5
diff --git a/signoff/user_project_wrapper/OPENLANE_VERSION b/signoff/user_project_wrapper/OPENLANE_VERSION
index b340faa..f6da8d7 100644
--- a/signoff/user_project_wrapper/OPENLANE_VERSION
+++ b/signoff/user_project_wrapper/OPENLANE_VERSION
@@ -1 +1 @@
-openlane v0.21-5-gd475aa2
+openlane v0.21-7-gaaf334d
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index d580fe9..73ea77b 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h47m14s,0h5m13s,3.3079078455790785,10.2784,1.6539539227895392,0,531.78,17,0,0,0,0,0,0,0,0,1,-1,-1,1232948,4152,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.28,4.44,0.99,2.42,-1,902,1520,902,1520,0,0,0,17,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,80,0.55,0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h46m33s,0h5m14s,3.3079078455790785,10.2784,1.6539539227895392,0,533.76,17,0,0,0,0,0,0,0,0,1,-1,-1,1233065,4146,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.28,4.44,0.98,2.46,-1,902,1520,902,1520,0,0,0,17,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,80,0.55,0,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_host/OPENLANE_VERSION b/signoff/wb_host/OPENLANE_VERSION
index b340faa..ad796aa 100644
--- a/signoff/wb_host/OPENLANE_VERSION
+++ b/signoff/wb_host/OPENLANE_VERSION
@@ -1 +1 @@
-openlane v0.21-5-gd475aa2
+openlane v0.21-6-gbc3b032
diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv
index 83ed466..5f67206 100644
--- a/signoff/wb_host/final_summary_report.csv
+++ b/signoff/wb_host/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_host,wb_host,wb_host,Flow_completed,0h7m46s,0h4m7s,61420.0,0.1,30710.0,49,589.23,3071,0,0,0,0,0,0,0,0,0,-1,0,170439,26682,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,137139540,0.0,48.41,23.36,15.76,-1,-1,2926,3181,554,809,0,0,0,3071,78,0,3,11,50,27,10,797,605,773,14,130,1139,0,1269,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,5
+0,/project/openlane/wb_host,wb_host,wb_host,Flow_completed,0h14m53s,0h8m57s,61440.0,0.1,30720.0,49,566.65,3072,0,0,0,0,0,0,0,0,0,-1,0,171387,26278,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,136337953,0.0,47.59,23.94,17.04,-1,-1,2927,3182,554,809,0,0,0,3072,78,0,3,11,50,27,10,797,605,773,14,130,1139,0,1269,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,5
diff --git a/signoff/wb_interconnect/OPENLANE_VERSION b/signoff/wb_interconnect/OPENLANE_VERSION
index b340faa..ad796aa 100644
--- a/signoff/wb_interconnect/OPENLANE_VERSION
+++ b/signoff/wb_interconnect/OPENLANE_VERSION
@@ -1 +1 @@
-openlane v0.21-5-gd475aa2
+openlane v0.21-6-gbc3b032
diff --git a/signoff/wb_interconnect/final_summary_report.csv b/signoff/wb_interconnect/final_summary_report.csv
index d907829..32f2a54 100644
--- a/signoff/wb_interconnect/final_summary_report.csv
+++ b/signoff/wb_interconnect/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,Flow_completed,0h29m52s,0h7m59s,8309.090909090908,0.33,4154.545454545454,7,556.08,1371,0,0,0,0,0,0,0,0,0,-1,0,437660,18322,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,388524110,0.0,40.9,7.79,23.11,-1,-1,1097,1718,204,825,0,0,0,1371,244,0,75,15,135,0,0,180,455,438,11,94,3794,0,3888,100.0,10.0,10,AREA 0,4,50,1,180,180,0.5,0,sky130_fd_sc_hd,4,5
+0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,Flow_completed,0h29m17s,0h4m13s,8309.090909090908,0.33,4154.545454545454,7,552.64,1371,0,0,0,0,0,0,0,0,0,-1,0,437660,18322,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,388524110,0.0,40.9,7.79,23.11,-1,-1,1097,1718,204,825,0,0,0,1371,244,0,75,15,135,0,0,180,455,438,11,94,3794,0,3888,100.0,10.0,10,AREA 0,4,50,1,180,180,0.5,0,sky130_fd_sc_hd,4,5
diff --git a/verilog/dv/user_risc_boot/uprj_netlists.v b/verilog/dv/user_risc_boot/uprj_netlists.v
index 647e7c5..e53865f 100644
--- a/verilog/dv/user_risc_boot/uprj_netlists.v
+++ b/verilog/dv/user_risc_boot/uprj_netlists.v
@@ -28,13 +28,12 @@
`include "glbl_cfg.v"
`include "sdram.v"
`include "spi_master.v"
- `include "uart_i2cm.v"
+ `include "uart_i2cm_usb.v"
`include "wb_interconnect.v"
`include "user_project_wrapper.v"
`include "syntacore.v"
`include "wb_host.v"
`include "clk_skew_adjust.v"
- `include "clk_buf.v"
`else
`include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
index f7539a2..82f0d44 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -529,13 +529,13 @@
wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
wire [3:0] wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;
-wire wbd_uart_stb_i = u_top.u_uart_i2c.u_uart_core.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c.u_uart_core.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c.u_uart_core.reg_wr;
-wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c.u_uart_core.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c.u_uart_core.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c.u_uart_core.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c.u_uart_core.reg_be;
+wire wbd_uart_stb_i = u_top.u_uart_i2c_usb.reg_cs;
+wire wbd_uart_ack_o = u_top.u_uart_i2c_usb.reg_ack;
+wire wbd_uart_we_i = u_top.u_uart_i2c_usb.reg_wr;
+wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb.reg_addr;
+wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb.reg_wdata;
+wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb.reg_rdata;
+wire wbd_uart_sel_i = u_top.u_uart_i2c_usb.reg_be;
`endif
diff --git a/verilog/dv/user_spi/uprj_netlists.v b/verilog/dv/user_spi/uprj_netlists.v
index 647e7c5..9e61482 100644
--- a/verilog/dv/user_spi/uprj_netlists.v
+++ b/verilog/dv/user_spi/uprj_netlists.v
@@ -28,7 +28,7 @@
`include "glbl_cfg.v"
`include "sdram.v"
`include "spi_master.v"
- `include "uart_i2cm.v"
+ `include "uart_i2cm_usb.v"
`include "wb_interconnect.v"
`include "user_project_wrapper.v"
`include "syntacore.v"
diff --git a/verilog/dv/user_spi/user_spi_tb.v b/verilog/dv/user_spi/user_spi_tb.v
index 1a44919..15c0c2e 100644
--- a/verilog/dv/user_spi/user_spi_tb.v
+++ b/verilog/dv/user_spi/user_spi_tb.v
@@ -1425,13 +1425,13 @@
wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
wire [3:0] wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;
-wire wbd_uart_stb_i = u_top.u_uart_i2c.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c.reg_wr;
-wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c.reg_be;
+wire wbd_uart_stb_i = u_top.u_uart_i2c_usb.reg_cs;
+wire wbd_uart_ack_o = u_top.u_uart_i2c_usb.reg_ack;
+wire wbd_uart_we_i = u_top.u_uart_i2c_usb.reg_wr;
+wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb.reg_addr;
+wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb.reg_wdata;
+wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb.reg_rdata;
+wire wbd_uart_sel_i = u_top.u_uart_i2c_usb.reg_be;
`endif
diff --git a/verilog/dv/user_uart/uprj_netlists.v b/verilog/dv/user_uart/uprj_netlists.v
index 647e7c5..9e61482 100644
--- a/verilog/dv/user_uart/uprj_netlists.v
+++ b/verilog/dv/user_uart/uprj_netlists.v
@@ -28,7 +28,7 @@
`include "glbl_cfg.v"
`include "sdram.v"
`include "spi_master.v"
- `include "uart_i2cm.v"
+ `include "uart_i2cm_usb.v"
`include "wb_interconnect.v"
`include "user_project_wrapper.v"
`include "syntacore.v"
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index 3a70b08..6258f24 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -584,13 +584,13 @@
wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
wire [3:0] wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;
-wire wbd_uart_stb_i = u_top.u_uart_i2c.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c.reg_wr;
-wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c.reg_be;
+wire wbd_uart_stb_i = u_top.u_uart_i2c_usb.reg_cs;
+wire wbd_uart_ack_o = u_top.u_uart_i2c_usb.reg_ack;
+wire wbd_uart_we_i = u_top.u_uart_i2c_usb.reg_wr;
+wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb.reg_addr;
+wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb.reg_wdata;
+wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb.reg_rdata;
+wire wbd_uart_sel_i = u_top.u_uart_i2c_usb.reg_be;
`endif
