moved riscv core fom syntacore to yifive/ycr1
diff --git a/.gitmodules b/.gitmodules
index dcb776f..a8dbba9 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -4,3 +4,6 @@
[submodule "verilog/rtl/qspim"]
path = verilog/rtl/qspim
url = https://github.com/dineshannayya/qspim.git
+[submodule "verilog/rtl/yifive/ycr1"]
+ path = verilog/rtl/yifive/ycr1
+ url = https://github.com/dineshannayya/ycr1.git
diff --git a/Makefile b/Makefile
index aa23c0e..ba40f56 100644
--- a/Makefile
+++ b/Makefile
@@ -36,9 +36,9 @@
SUBMODULE?=1
#RISCV COMPLIANCE test Environment
-COREMARK_DIR = verilog/rtl/syntacore/scr1/dependencies/coremark
-RISCV_COMP_DIR = verilog/rtl/syntacore/scr1/dependencies/riscv-compliance
-RISCV_TEST_DIR = verilog/rtl/syntacore/scr1/dependencies/riscv-tests
+COREMARK_DIR = verilog/dv/riscv_regress/dependencies/coremark
+RISCV_COMP_DIR = verilog/dv/riscv_regress/dependencies/riscv-compliance
+RISCV_TEST_DIR = verilog/dv/riscv_regress/dependencies/riscv-tests
COREMARK_REPO = https://github.com/eembc/coremark
RISCV_COMP_REPO = https://github.com/riscv/riscv-compliance
diff --git a/openlane/mbist/base.sdc b/openlane/mbist/base.sdc
index 1f050a1..eb845a0 100644
--- a/openlane/mbist/base.sdc
+++ b/openlane/mbist/base.sdc
@@ -15,7 +15,6 @@
set_clock_transition 0.1500 [all_clocks]
set_clock_uncertainty -setup 0.2500 [all_clocks]
-
set_clock_uncertainty -hold 0.2500 [all_clocks]
set ::env(SYNTH_TIMING_DERATE) 0.05
diff --git a/openlane/pinmux/base.sdc b/openlane/pinmux/base.sdc
index cbbfba5..bea31b6 100644
--- a/openlane/pinmux/base.sdc
+++ b/openlane/pinmux/base.sdc
@@ -8,15 +8,10 @@
###############################################################################
create_clock -name mclk -period 10.0000 [get_ports {mclk}]
set_propagated_clock [get_clocks {mclk}]
-set_clock_uncertainty -rise_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -setup 0.2500
-set_clock_uncertainty -rise_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -setup 0.2500
-set_clock_uncertainty -fall_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -setup 0.2500
-set_clock_uncertainty -fall_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -setup 0.2500
-set_clock_uncertainty -rise_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -hold 0.2500
-set_clock_uncertainty -rise_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -hold 0.2500
-set_clock_uncertainty -fall_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -hold 0.2500
-set_clock_uncertainty -fall_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -hold 0.2500
+set_clock_transition 0.1500 [all_clocks]
+set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -hold 0.2500 [all_clocks]
set ::env(SYNTH_TIMING_DERATE) 0.05
puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
diff --git a/openlane/qspim/base.sdc b/openlane/qspim/base.sdc
index a9e2aaf..4166d36 100644
--- a/openlane/qspim/base.sdc
+++ b/openlane/qspim/base.sdc
@@ -22,22 +22,10 @@
set_case_analysis 0 [get_ports {cfg_cska_sp_co[0]}]
set_propagated_clock [get_clocks {spiclk}]
-set_clock_uncertainty -rise_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -hold 0.2500
-set_clock_uncertainty -rise_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -setup 0.2500
-set_clock_uncertainty -rise_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -hold 0.2500
-set_clock_uncertainty -rise_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -setup 0.2500
-set_clock_uncertainty -fall_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -hold 0.2500
-set_clock_uncertainty -fall_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -setup 0.2500
-set_clock_uncertainty -fall_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -hold 0.2500
-set_clock_uncertainty -fall_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -setup 0.2500
-set_clock_uncertainty -rise_from [get_clocks {spiclk}] -rise_to [get_clocks {spiclk}] -hold 0.2500
-set_clock_uncertainty -rise_from [get_clocks {spiclk}] -rise_to [get_clocks {spiclk}] -setup 0.2500
-set_clock_uncertainty -rise_from [get_clocks {spiclk}] -fall_to [get_clocks {spiclk}] -hold 0.2500
-set_clock_uncertainty -rise_from [get_clocks {spiclk}] -fall_to [get_clocks {spiclk}] -setup 0.2500
-set_clock_uncertainty -fall_from [get_clocks {spiclk}] -rise_to [get_clocks {spiclk}] -hold 0.2500
-set_clock_uncertainty -fall_from [get_clocks {spiclk}] -rise_to [get_clocks {spiclk}] -setup 0.2500
-set_clock_uncertainty -fall_from [get_clocks {spiclk}] -fall_to [get_clocks {spiclk}] -hold 0.2500
-set_clock_uncertainty -fall_from [get_clocks {spiclk}] -fall_to [get_clocks {spiclk}] -setup 0.2500
+
+set_clock_transition 0.1500 [all_clocks]
+set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -hold 0.2500 [all_clocks]
set ::env(SYNTH_TIMING_DERATE) 0.05
puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
diff --git a/openlane/qspim/config.tcl b/openlane/qspim/config.tcl
index a29839a..34b0101 100755
--- a/openlane/qspim/config.tcl
+++ b/openlane/qspim/config.tcl
@@ -41,7 +41,7 @@
# Local sources + no2usb sources
set ::env(VERILOG_FILES) "\
- $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
+ $script_dir/../../verilog/rtl/lib/clk_skew_adjust.gv \
$script_dir/../../verilog/rtl/lib/reset_sync.sv \
$script_dir/../../verilog/rtl/qspim/src/qspim_top.sv \
$script_dir/../../verilog/rtl/qspim/src/qspim_if.sv \
diff --git a/openlane/syntacore/config.tcl b/openlane/syntacore/config.tcl
deleted file mode 100755
index 57a674a..0000000
--- a/openlane/syntacore/config.tcl
+++ /dev/null
@@ -1,132 +0,0 @@
-# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-# Global
-# ------
-
-set script_dir [file dirname [file normalize [info script]]]
-# Name
-set ::env(DESIGN_NAME) scr1_top_wb
-
-set ::env(DESIGN_IS_CORE) "0"
-set ::env(FP_PDN_CORE_RING) "0"
-
-# Timing configuration
-set ::env(CLOCK_PERIOD) "10"
-set ::env(CLOCK_PORT) "wb_clk core_clk"
-
-set ::env(SYNTH_MAX_FANOUT) 4
-
-## CTS BUFFER
-set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
-set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
-set ::env(CLOCK_BUFFER_FANOUT) "8"
-
-# Sources
-# -------
-
-# Local sources + no2usb sources
-set ::env(VERILOG_FILES) "\
- $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
- $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv \
- $script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_core_top.sv \
- $script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_dm.sv \
- $script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_tapc_synchronizer.sv \
- $script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_clk_ctrl.sv \
- $script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_scu.sv \
- $script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_tapc.sv \
- $script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_tapc_shift_reg.sv \
- $script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_dmi.sv \
- $script_dir/../../verilog/rtl/syntacore/scr1/src/core/primitives/scr1_reset_cells.sv \
- $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv \
- $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv \
- $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv \
- $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv \
- $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv \
- $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv \
- $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mul.sv \
- $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_div.sv \
- $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv \
- $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv \
- $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv \
- $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_ipic.sv \
- $script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_dmem_router.sv \
- $script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_imem_router.sv \
- $script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv \
- $script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_timer.sv \
- $script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv \
- $script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv \
- $script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv \
- $script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_intf.sv \
- $script_dir/../../verilog/rtl/lib/async_fifo.sv "
-
-set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore/scr1/src/includes ]
-set ::env(SYNTH_READ_BLACKBOX_LIB) 1
-set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-
-set ::env(SDC_FILE) "$script_dir/base.sdc"
-set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
-#set ::env(SYNTH_DEFINES) [list SCR1_DBG_EN ]
-
-set ::env(LEC_ENABLE) 0
-
-set ::env(VDD_PIN) [list {vccd1}]
-set ::env(GND_PIN) [list {vssd1}]
-
-
-# --------
-# Floorplanning
-# -------------
-
-set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
-
-set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) [list 0.0 0.0 1520.0 520.0]
-
-
-# If you're going to use multiple power domains, then keep this disabled.
-set ::env(RUN_CVC) 0
-
-#set ::env(PDN_CFG) $script_dir/pdn.tcl
-
-
-set ::env(PL_TIME_DRIVEN) 1
-set ::env(PL_TARGET_DENSITY) "0.32"
-
-# helps in anteena fix
-set ::env(USE_ARC_ANTENNA_CHECK) "0"
-
-set ::env(FP_IO_VEXTEND) 4
-set ::env(FP_IO_HEXTEND) 4
-
-set ::env(FP_PDN_VPITCH) 100
-set ::env(FP_PDN_HPITCH) 100
-set ::env(FP_PDN_VWIDTH) 3
-set ::env(FP_PDN_HWIDTH) 3
-
-set ::env(GLB_RT_MAXLAYER) 5
-set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
-set ::env(DIODE_INSERTION_STRATEGY) 4
-
-
-set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
-set ::env(QUIT_ON_MAGIC_DRC) "1"
-set ::env(QUIT_ON_LVS_ERROR) "0"
-set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
-
-#Need to cross-check why global timing opimization creating setup vio with hugh hold fix
-set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0"
-
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 97e8153..0f5a1c8 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -68,7 +68,7 @@
$proj_dir/../../verilog/gl/mbist.v \
$proj_dir/../../verilog/gl/uart_i2cm_usb_spi.v \
$proj_dir/../../verilog/gl/wb_host.v \
- $proj_dir/../../verilog/gl/syntacore.v \
+ $proj_dir/../../verilog/gl/yifive.v \
$proj_dir/../../verilog/rtl/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v \
"
@@ -79,7 +79,7 @@
$lef_root/uart_i2cm_usb_spi.lef \
$lef_root/wb_host.lef \
$lef_root/mbist.lef \
- $lef_root/syntacore.lef \
+ $lef_root/yifive.lef \
$lef_root/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
"
@@ -90,13 +90,13 @@
$gds_root/uart_i2cm_usb_spi.gds \
$gds_root/wb_host.gds \
$gds_root/mbist.gds \
- $gds_root/syntacore.gds \
+ $gds_root/yifive.gds \
$gds_root/sky130_sram_2kbyte_1rw1r_32x512_8.gds \
"
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-set ::env(VERILOG_INCLUDE_DIRS) [glob $proj_dir/../../verilog/rtl/syntacore/scr1/src/includes ]
+set ::env(VERILOG_INCLUDE_DIRS) [glob $proj_dir/../../verilog/rtl/yifive/ycr1/src/includes ]
set ::env(GLB_RT_MAXLAYER) 5
diff --git a/openlane/syntacore/base.sdc b/openlane/yifive/base.sdc
similarity index 82%
rename from openlane/syntacore/base.sdc
rename to openlane/yifive/base.sdc
index a811f4a..777ec2d 100644
--- a/openlane/syntacore/base.sdc
+++ b/openlane/yifive/base.sdc
@@ -9,30 +9,10 @@
create_clock -name core_clk -period 20.0000 [get_ports {core_clk}]
create_clock -name rtc_clk -period 40.0000 [get_ports {rtc_clk}]
create_clock -name wb_clk -period 10.0000 [get_ports {wb_clk}]
-set_clock_uncertainty -rise_from [get_clocks {core_clk}] -rise_to [get_clocks {core_clk}] -hold 0.2500
-set_clock_uncertainty -rise_from [get_clocks {core_clk}] -rise_to [get_clocks {core_clk}] -setup 0.2500
-set_clock_uncertainty -rise_from [get_clocks {core_clk}] -fall_to [get_clocks {core_clk}] -hold 0.2500
-set_clock_uncertainty -rise_from [get_clocks {core_clk}] -fall_to [get_clocks {core_clk}] -setup 0.2500
-set_clock_uncertainty -fall_from [get_clocks {core_clk}] -rise_to [get_clocks {core_clk}] -hold 0.2500
-set_clock_uncertainty -fall_from [get_clocks {core_clk}] -rise_to [get_clocks {core_clk}] -setup 0.2500
-set_clock_uncertainty -fall_from [get_clocks {core_clk}] -fall_to [get_clocks {core_clk}] -hold 0.2500
-set_clock_uncertainty -fall_from [get_clocks {core_clk}] -fall_to [get_clocks {core_clk}] -setup 0.2500
-set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}] -hold 0.2500
-set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}] -setup 0.2500
-set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}] -hold 0.2500
-set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}] -setup 0.2500
-set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}] -hold 0.2500
-set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}] -setup 0.2500
-set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}] -hold 0.2500
-set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}] -setup 0.2500
-set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}] -hold 0.2500
-set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}] -setup 0.2500
-set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}] -hold 0.2500
-set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}] -setup 0.2500
-set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}] -hold 0.2500
-set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}] -setup 0.2500
-set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}] -hold 0.2500
-set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}] -setup 0.2500
+
+set_clock_transition 0.1500 [all_clocks]
+set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -hold 0.2500 [all_clocks]
set ::env(SYNTH_TIMING_DERATE) 0.05
diff --git a/openlane/yifive/config.tcl b/openlane/yifive/config.tcl
new file mode 100755
index 0000000..ea4e6c9
--- /dev/null
+++ b/openlane/yifive/config.tcl
@@ -0,0 +1,132 @@
+# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+# Global
+# ------
+
+set script_dir [file dirname [file normalize [info script]]]
+# Name
+set ::env(DESIGN_NAME) ycr1_top_wb
+
+set ::env(DESIGN_IS_CORE) "0"
+set ::env(FP_PDN_CORE_RING) "0"
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "wb_clk core_clk"
+
+set ::env(SYNTH_MAX_FANOUT) 4
+
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+
+# Sources
+# -------
+
+# Local sources + no2usb sources
+set ::env(VERILOG_FILES) "\
+ $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
+ $script_dir/../../verilog/rtl/yifive/ycr1/src/core/pipeline/ycr1_pipe_top.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr1/src/core/ycr1_core_top.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr1/src/core/ycr1_dm.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr1/src/core/ycr1_tapc_synchronizer.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr1/src/core/ycr1_clk_ctrl.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr1/src/core/ycr1_scu.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr1/src/core/ycr1_tapc.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr1/src/core/ycr1_tapc_shift_reg.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr1/src/core/ycr1_dmi.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr1/src/core/primitives/ycr1_reset_cells.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr1/src/core/pipeline/ycr1_pipe_ifu.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr1/src/core/pipeline/ycr1_pipe_idu.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr1/src/core/pipeline/ycr1_pipe_exu.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr1/src/core/pipeline/ycr1_pipe_mprf.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr1/src/core/pipeline/ycr1_pipe_csr.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr1/src/core/pipeline/ycr1_pipe_ialu.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr1/src/core/pipeline/ycr1_pipe_mul.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr1/src/core/pipeline/ycr1_pipe_div.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr1/src/core/pipeline/ycr1_pipe_lsu.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr1/src/core/pipeline/ycr1_pipe_hdu.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr1/src/core/pipeline/ycr1_pipe_tdu.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr1/src/core/pipeline/ycr1_ipic.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr1/src/top/ycr1_dmem_router.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr1/src/top/ycr1_imem_router.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr1/src/top/ycr1_tcm.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr1/src/top/ycr1_timer.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr1/src/top/ycr1_top_wb.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr1/src/top/ycr1_dmem_wb.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr1/src/top/ycr1_imem_wb.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr1/src/top/ycr1_intf.sv \
+ $script_dir/../../verilog/rtl/lib/async_fifo.sv "
+
+set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr1/src/includes ]
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+
+set ::env(SDC_FILE) "$script_dir/base.sdc"
+set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+#set ::env(SYNTH_DEFINES) [list SCR1_DBG_EN ]
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+
+# --------
+# Floorplanning
+# -------------
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) [list 0.0 0.0 1520.0 520.0]
+
+
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
+
+#set ::env(PDN_CFG) $script_dir/pdn.tcl
+
+
+set ::env(PL_TIME_DRIVEN) 1
+set ::env(PL_TARGET_DENSITY) "0.32"
+
+# helps in anteena fix
+set ::env(USE_ARC_ANTENNA_CHECK) "0"
+
+set ::env(FP_IO_VEXTEND) 4
+set ::env(FP_IO_HEXTEND) 4
+
+set ::env(FP_PDN_VPITCH) 100
+set ::env(FP_PDN_HPITCH) 100
+set ::env(FP_PDN_VWIDTH) 3
+set ::env(FP_PDN_HWIDTH) 3
+
+set ::env(GLB_RT_MAXLAYER) 5
+set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "0"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
+
+#Need to cross-check why global timing opimization creating setup vio with hugh hold fix
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0"
+
diff --git a/openlane/syntacore/interactive.tcl b/openlane/yifive/interactive.tcl
similarity index 100%
rename from openlane/syntacore/interactive.tcl
rename to openlane/yifive/interactive.tcl
diff --git a/openlane/syntacore/pdn.tcl b/openlane/yifive/pdn.tcl
similarity index 100%
rename from openlane/syntacore/pdn.tcl
rename to openlane/yifive/pdn.tcl
diff --git a/openlane/syntacore/pin_order.cfg b/openlane/yifive/pin_order.cfg
similarity index 100%
rename from openlane/syntacore/pin_order.cfg
rename to openlane/yifive/pin_order.cfg
diff --git a/openlane/syntacore/sta.tcl b/openlane/yifive/sta.tcl
similarity index 100%
rename from openlane/syntacore/sta.tcl
rename to openlane/yifive/sta.tcl
diff --git a/signoff/pinmux/final_summary_report.csv b/signoff/pinmux/final_summary_report.csv
index d31ebe3..b79a2ba 100644
--- a/signoff/pinmux/final_summary_report.csv
+++ b/signoff/pinmux/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/pinmux,pinmux,pinmux,flow_completed,0h13m47s,-1,46109.09090909091,0.2475,23054.545454545456,27.06,702.63,5706,0,0,0,0,0,0,-1,1,0,-1,-1,428667,61634,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,317697885.0,6.86,43.74,33.48,10.88,0.31,-1,3574,8561,543,5529,0,0,0,4202,0,0,0,0,0,0,0,4,1343,1339,16,314,3259,0,3573,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/pinmux,pinmux,pinmux,flow_completed,0h12m14s,-1,46109.09090909091,0.2475,23054.545454545456,27.06,705.51,5706,0,0,0,0,0,0,-1,1,0,-1,-1,428849,61419,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,317651391.0,7.2,43.17,33.58,11.33,0.37,-1,3574,8561,543,5529,0,0,0,4202,0,0,0,0,0,0,0,4,1343,1339,16,314,3259,0,3573,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/qspim/final_summary_report.csv b/signoff/qspim/final_summary_report.csv
index b75a144..d9f5ae6 100644
--- a/signoff/qspim/final_summary_report.csv
+++ b/signoff/qspim/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/qspim,qspim_top,qspim,flow_completed,0h8m52s,-1,64727.27272727273,0.22,32363.636363636364,37.61,695.07,7120,0,0,0,0,0,0,-1,1,0,-1,-1,299102,62398,0.0,-4.31,-1,0.0,-1,0.0,-1599.52,-1,0.0,-1,205184440.0,6.62,33.96,32.07,0.54,1.34,-1,5860,8812,519,3470,0,0,0,6886,0,0,0,0,0,0,0,4,1764,2182,20,388,2940,0,3328,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.4,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/qspim,qspim_top,qspim,flow_completed,0h7m58s,-1,64718.181818181816,0.22,32359.090909090908,37.6,697.2,7119,0,0,0,0,0,0,-1,1,0,-1,-1,302344,62936,0.0,-4.31,-1,0.0,-1,0.0,-1696.2,-1,0.0,-1,205083381.0,6.96,34.06,32.84,0.5,1.23,-1,6040,8992,699,3650,0,0,0,6886,0,0,0,0,0,0,0,4,1764,2182,20,388,2940,0,3328,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.4,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 4f25320..63019bd 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h40m7s,-1,2.529576587795766,10.2784,1.264788293897883,-1,530.05,13,0,0,0,0,0,0,-1,0,0,-1,-1,1176096,8164,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40144.36,3.16,3.65,0.41,0.64,-1,271,2532,271,2532,0,0,0,13,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,90,0.55,0.0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h39m39s,-1,2.529576587795766,10.2784,1.264788293897883,-1,530.03,13,0,0,0,0,0,0,-1,0,0,-1,-1,1176087,8118,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40144.36,3.16,3.64,0.41,0.63,-1,271,2532,271,2532,0,0,0,13,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,90,0.55,0.0,sky130_fd_sc_hd,4,0
diff --git a/signoff/yifive/OPENLANE_VERSION b/signoff/yifive/OPENLANE_VERSION
new file mode 100644
index 0000000..80c7664
--- /dev/null
+++ b/signoff/yifive/OPENLANE_VERSION
@@ -0,0 +1 @@
+openlane N/A
diff --git a/signoff/yifive/PDK_SOURCES b/signoff/yifive/PDK_SOURCES
new file mode 100644
index 0000000..ca3684a
--- /dev/null
+++ b/signoff/yifive/PDK_SOURCES
@@ -0,0 +1,6 @@
+-ne openlane
+8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b
+-ne skywater-pdk
+c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+-ne open_pdks
+14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
diff --git a/signoff/yifive/final_summary_report.csv b/signoff/yifive/final_summary_report.csv
new file mode 100644
index 0000000..bc3a2be
--- /dev/null
+++ b/signoff/yifive/final_summary_report.csv
@@ -0,0 +1,2 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/yifive,ycr1_top_wb,yifive,flow_completed,0h38m35s,-1,53646.25506072874,0.7904,26823.12753036437,30.96,1188.15,21201,0,-1,-1,-1,-1,0,-1,1,0,-1,-1,1626736,237479,-1.77,-17.38,-1,0.0,-1,-2145.74,-21120.0,-1,0.0,-1,1293377672.0,0.0,62.57,24.05,22.6,0.0,-1,18589,30059,1068,12431,0,0,0,21971,0,0,0,0,0,0,0,4,5240,5924,49,366,10822,0,11188,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.32,0.0,sky130_fd_sc_hd,4,4
diff --git a/sta/scripts/caravel_timing.tcl b/sta/scripts/caravel_timing.tcl
index 92b3b08..d872e0b 100644
--- a/sta/scripts/caravel_timing.tcl
+++ b/sta/scripts/caravel_timing.tcl
@@ -44,7 +44,7 @@
# User project netlist
read_verilog $::env(USER_ROOT)/verilog/gl/qspim.v
- read_verilog $::env(USER_ROOT)/verilog/gl/syntacore.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/yifive.v
read_verilog $::env(USER_ROOT)/verilog/gl/uart_i2cm_usb_spi.v
read_verilog $::env(USER_ROOT)/verilog/gl/wb_host.v
read_verilog $::env(USER_ROOT)/verilog/gl/wb_interconnect.v
@@ -146,7 +146,7 @@
## User Project Spef
read_spef -path mprj/u_mbist $::env(USER_ROOT)/spef/mbist_top.spef
- read_spef -path mprj/u_riscv_top $::env(USER_ROOT)/spef/scr1_top_wb.spef
+ read_spef -path mprj/u_riscv_top $::env(USER_ROOT)/spef/ycr1_top_wb.spef
read_spef -path mprj/u_pinmux $::env(USER_ROOT)/spef/pinmux.spef
read_spef -path mprj/u_qspi_master $::env(USER_ROOT)/spef/qspim_top.spef
read_spef -path mprj/u_uart_i2c_usb_spi $::env(USER_ROOT)/spef/uart_i2c_usb_spi_top.spef
diff --git a/verilog/dv/firmware/LICENSE b/verilog/dv/firmware/LICENSE
new file mode 100644
index 0000000..48fe522
--- /dev/null
+++ b/verilog/dv/firmware/LICENSE
@@ -0,0 +1,24 @@
+Copyright (c) 2012-2015, The Regents of the University of California (Regents).
+All Rights Reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+3. Neither the name of the Regents nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
+SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
+OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS
+BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
+HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
+MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
diff --git a/verilog/dv/firmware/common.mk b/verilog/dv/firmware/common.mk
new file mode 100644
index 0000000..6075f73
--- /dev/null
+++ b/verilog/dv/firmware/common.mk
@@ -0,0 +1,66 @@
+# //////////////////////////////////////////////////////////////////////////////
+# // SPDX-FileCopyrightText: 2021, Dinesh Annayya
+# //
+# // Licensed under the Apache License, Version 2.0 (the "License");
+# // you may not use this file except in compliance with the License.
+# // You may obtain a copy of the License at
+# //
+# // http://www.apache.org/licenses/LICENSE-2.0
+# //
+# // Unless required by applicable law or agreed to in writing, software
+# // distributed under the License is distributed on an "AS IS" BASIS,
+# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# // See the License for the specific language governing permissions and
+# // limitations under the License.
+# // SPDX-License-Identifier: Apache-2.0
+# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+# // //////////////////////////////////////////////////////////////////////////
+
+ADD_ASM_MACRO ?= -D__ASSEMBLY__=1
+
+FLAGS = -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las $(ADD_FLAGS)
+FLAGS_STR = "$(FLAGS)"
+
+CFLAGS_COMMON = -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=$(TCM)
+CFLAGS_ARCH = -Wa,-march=rv32$(ARCH) -march=rv32$(ARCH) -mabi=$(ABI)
+
+CFLAGS := $(FLAGS) $(EXT_CFLAGS) \
+$(CFLAGS_COMMON) \
+$(CFLAGS_ARCH) \
+-DFLAGS_STR=\"$(FLAGS_STR)\" \
+$(ADD_CFLAGS)
+
+LDFLAGS ?= -nostartfiles -nostdlib -lc -lgcc -march=rv32$(ARCH) -mabi=$(ABI)
+
+ifeq (,$(findstring 0,$(TCM)))
+ld_script ?= $(inc_dir)/link_tcm.ld
+asm_src ?= crt_tcm.S
+else
+ld_script ?= $(inc_dir)/link.ld
+asm_src ?= crt.S
+endif
+
+VPATH += $(src_dir) $(inc_dir) $(ADD_VPATH)
+incs += -I$(src_dir) -I$(inc_dir) $(ADD_incs)
+
+c_objs := $(addprefix $(bld_dir)/,$(patsubst %.c, %.o, $(c_src)))
+asm_objs := $(addprefix $(bld_dir)/,$(patsubst %.S, %.o, $(asm_src)))
+
+$(bld_dir)/%.o: %.S
+ $(RISCV_GCC) $(CFLAGS) $(ADD_ASM_MACRO) -c $(incs) $< -o $@
+
+$(bld_dir)/%.o: %.c
+ $(RISCV_GCC) $(CFLAGS) -c $(incs) $< -o $@
+
+$(bld_dir)/%.elf: $(ld_script) $(c_objs) $(asm_objs)
+ $(RISCV_GCC) -o $@ -T $^ $(LDFLAGS)
+
+$(bld_dir)/%.hex: $(bld_dir)/%.elf
+ $(RISCV_ROM_OBJCOPY) $^ $@
+ $(RISCV_RAM_OBJCOPY) $^ $@.ram
+ #assign 0x0048_0xxx to 0x0000_0xxx to map to TCM Memory
+ sed -i 's/@00480/@00000/g' $@.ram
+
+
+$(bld_dir)/%.dump: $(bld_dir)/%.elf
+ $(RISCV_OBJDUMP) $^ > $@
diff --git a/verilog/dv/firmware/crt.S b/verilog/dv/firmware/crt.S
new file mode 100644
index 0000000..d50cb6b
--- /dev/null
+++ b/verilog/dv/firmware/crt.S
@@ -0,0 +1,160 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021, Dinesh Annayya ////
+// ////
+// Licensed under the Apache License, Version 2.0 (the "License"); ////
+// you may not use this file except in compliance with the License. ////
+// You may obtain a copy of the License at ////
+// ////
+// http://www.apache.org/licenses/LICENSE-2.0 ////
+// ////
+// Unless required by applicable law or agreed to in writing, software ////
+// distributed under the License is distributed on an "AS IS" BASIS, ////
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.///
+// See the License for the specific language governing permissions and ////
+// limitations under the License. ////
+// SPDX-License-Identifier: Apache-2.0 ////
+// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> ////
+//////////////////////////////////////////////////////////////////////////////
+
+#include "riscv_csr_encoding.h"
+#include "sc_test.h"
+
+# define LREG lw
+# define SREG sw
+# define REGBYTES 4
+
+ .globl _start
+ .globl main
+ .globl trap_entry
+ .globl handle_trap
+ .globl sc_exit
+ .weak trap_entry, handle_trap
+
+ .text
+ .org (64*3)
+ .balign 64
+machine_trap_entry:
+ j trap_entry
+
+ .balign 64
+
+_start:
+#ifndef __RVE_EXT
+ zero_int_regs 1, 31
+#else
+ zero_int_regs 1, 15
+#endif
+ # Global pointer init
+ .option push
+ .option norelax
+ la gp, __global_pointer$
+ .option pop
+ # clear bss
+ la a1, __BSS_START__
+ la a2, __BSS_END__
+ j 4f
+3: sw zero, 0(a1)
+ add a1, a1, 4
+4: bne a1, a2, 3b
+ la sp, __C_STACK_TOP__
+
+ // Timer init
+ li t0, mtime_ctrl
+ li t1, (1 << YCR1_MTIME_CTRL_EN) // enable, use internal clock
+ sw t1, (t0)
+ li t0, mtime_div
+ li t1, (100-1) // divide by 100
+ sw t1, (t0)
+ li t0, mtimecmp
+ li t1, -1
+ sw t1, (t0) // max value for mtimecmp
+ sw t1, 4(t0)
+
+ li a0, 0
+ li a1, 0
+ jal main
+ j sc_exit
+
+trap_entry:
+ addi sp, sp, -272
+
+ SREG x1, 1*REGBYTES(sp)
+ SREG x2, 2*REGBYTES(sp)
+ SREG x3, 3*REGBYTES(sp)
+ SREG x4, 4*REGBYTES(sp)
+ SREG x5, 5*REGBYTES(sp)
+ SREG x6, 6*REGBYTES(sp)
+ SREG x7, 7*REGBYTES(sp)
+ SREG x8, 8*REGBYTES(sp)
+ SREG x9, 9*REGBYTES(sp)
+ SREG x10, 10*REGBYTES(sp)
+ SREG x11, 11*REGBYTES(sp)
+ SREG x12, 12*REGBYTES(sp)
+ SREG x13, 13*REGBYTES(sp)
+ SREG x14, 14*REGBYTES(sp)
+ SREG x15, 15*REGBYTES(sp)
+#ifndef __RVE_EXT
+ SREG x16, 16*REGBYTES(sp)
+ SREG x17, 17*REGBYTES(sp)
+ SREG x18, 18*REGBYTES(sp)
+ SREG x19, 19*REGBYTES(sp)
+ SREG x20, 20*REGBYTES(sp)
+ SREG x21, 21*REGBYTES(sp)
+ SREG x22, 22*REGBYTES(sp)
+ SREG x23, 23*REGBYTES(sp)
+ SREG x24, 24*REGBYTES(sp)
+ SREG x25, 25*REGBYTES(sp)
+ SREG x26, 26*REGBYTES(sp)
+ SREG x27, 27*REGBYTES(sp)
+ SREG x28, 28*REGBYTES(sp)
+ SREG x29, 29*REGBYTES(sp)
+ SREG x30, 30*REGBYTES(sp)
+ SREG x31, 31*REGBYTES(sp)
+#endif // __RVE_EXT
+
+ csrr a0, mcause
+ csrr a1, mepc
+ mv a2, sp
+ jal handle_trap
+
+ LREG x1, 1*REGBYTES(sp)
+ LREG x2, 2*REGBYTES(sp)
+ LREG x3, 3*REGBYTES(sp)
+ LREG x4, 4*REGBYTES(sp)
+ LREG x5, 5*REGBYTES(sp)
+ LREG x6, 6*REGBYTES(sp)
+ LREG x7, 7*REGBYTES(sp)
+ LREG x8, 8*REGBYTES(sp)
+ LREG x9, 9*REGBYTES(sp)
+ LREG x10, 10*REGBYTES(sp)
+ LREG x11, 11*REGBYTES(sp)
+ LREG x12, 12*REGBYTES(sp)
+ LREG x13, 13*REGBYTES(sp)
+ LREG x14, 14*REGBYTES(sp)
+ LREG x15, 15*REGBYTES(sp)
+#ifndef __RVE_EXT
+ LREG x16, 16*REGBYTES(sp)
+ LREG x17, 17*REGBYTES(sp)
+ LREG x18, 18*REGBYTES(sp)
+ LREG x19, 19*REGBYTES(sp)
+ LREG x20, 20*REGBYTES(sp)
+ LREG x21, 21*REGBYTES(sp)
+ LREG x22, 22*REGBYTES(sp)
+ LREG x23, 23*REGBYTES(sp)
+ LREG x24, 24*REGBYTES(sp)
+ LREG x25, 25*REGBYTES(sp)
+ LREG x26, 26*REGBYTES(sp)
+ LREG x27, 27*REGBYTES(sp)
+ LREG x28, 28*REGBYTES(sp)
+ LREG x29, 29*REGBYTES(sp)
+ LREG x30, 30*REGBYTES(sp)
+ LREG x31, 31*REGBYTES(sp)
+#endif // __RVE_EXT
+
+ addi sp, sp, 272
+ mret
+
+handle_trap:
+ j SIM_EXIT
+
+// end of crt.S
diff --git a/verilog/dv/firmware/crt_tcm.S b/verilog/dv/firmware/crt_tcm.S
new file mode 100644
index 0000000..f1bcb65
--- /dev/null
+++ b/verilog/dv/firmware/crt_tcm.S
@@ -0,0 +1,171 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021, Dinesh Annayya ////
+// ////
+// Licensed under the Apache License, Version 2.0 (the "License"); ////
+// you may not use this file except in compliance with the License. ////
+// You may obtain a copy of the License at ////
+// ////
+// http://www.apache.org/licenses/LICENSE-2.0 ////
+// ////
+// Unless required by applicable law or agreed to in writing, software ////
+// distributed under the License is distributed on an "AS IS" BASIS, ////
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.///
+// See the License for the specific language governing permissions and ////
+// limitations under the License. ////
+// SPDX-License-Identifier: Apache-2.0 ////
+// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> ////
+//////////////////////////////////////////////////////////////////////////////
+
+#include "riscv_csr_encoding.h"
+#include "reloc.h"
+#include "sc_test.h"
+
+# define LREG lw
+# define SREG sw
+# define REGBYTES 4
+
+ .globl _start
+ .globl main
+ .globl trap_entry
+ .globl handle_trap
+ .globl sc_exit
+ .weak trap_entry, handle_trap
+
+ .section .text.init
+ .org (64*3)
+ .align 6;
+machine_trap_entry:
+ j trap_entry
+
+ .align 6
+_start:
+#ifndef __RVE_EXT
+ zero_int_regs 1, 31
+#else
+ zero_int_regs 1, 15
+#endif
+ # Global pointer init
+ .option push
+ .option norelax
+ la gp, __global_pointer$
+ .option pop
+
+ RELOC_PROC;
+
+ // init tdata
+ mv a1, tp
+ la a2, _tdata_end
+ j 6f
+5: lw a3, 0(a0)
+ sw a3, 0(a1)
+ add a0, a0, 4
+ add a1, a1, 4
+6: bne a0, a2, 5b
+ // clear tbss
+ j 8f
+7: sw zero, 0(a1)
+ add a1, a1, 4
+8: bne a1, a4, 7b
+
+ // Timer init
+ li t0, mtime_ctrl
+ li t1, (1 << YCR1_MTIME_CTRL_EN) // enable, use internal clock
+ sw t1, (t0)
+ li t0, mtime_div
+ li t1, (100-1) // divide by 100
+ sw t1, (t0)
+ li t0, mtimecmp
+ li t1, -1
+ sw t1, (t0) // max value for mtimecmp
+ sw t1, 4(t0)
+
+ li a0, 0
+ li a1, 0
+9: auipc t0, %pcrel_hi(main)
+ jalr t0, %pcrel_lo(9b)
+ la t0, sc_exit
+ //j sc_exit
+
+trap_entry:
+ addi sp, sp, -272
+
+ SREG x1, 1*REGBYTES(sp)
+ SREG x2, 2*REGBYTES(sp)
+ SREG x3, 3*REGBYTES(sp)
+ SREG x4, 4*REGBYTES(sp)
+ SREG x5, 5*REGBYTES(sp)
+ SREG x6, 6*REGBYTES(sp)
+ SREG x7, 7*REGBYTES(sp)
+ SREG x8, 8*REGBYTES(sp)
+ SREG x9, 9*REGBYTES(sp)
+ SREG x10, 10*REGBYTES(sp)
+ SREG x11, 11*REGBYTES(sp)
+ SREG x12, 12*REGBYTES(sp)
+ SREG x13, 13*REGBYTES(sp)
+ SREG x14, 14*REGBYTES(sp)
+ SREG x15, 15*REGBYTES(sp)
+#ifndef __RVE_EXT
+ SREG x16, 16*REGBYTES(sp)
+ SREG x17, 17*REGBYTES(sp)
+ SREG x18, 18*REGBYTES(sp)
+ SREG x19, 19*REGBYTES(sp)
+ SREG x20, 20*REGBYTES(sp)
+ SREG x21, 21*REGBYTES(sp)
+ SREG x22, 22*REGBYTES(sp)
+ SREG x23, 23*REGBYTES(sp)
+ SREG x24, 24*REGBYTES(sp)
+ SREG x25, 25*REGBYTES(sp)
+ SREG x26, 26*REGBYTES(sp)
+ SREG x27, 27*REGBYTES(sp)
+ SREG x28, 28*REGBYTES(sp)
+ SREG x29, 29*REGBYTES(sp)
+ SREG x30, 30*REGBYTES(sp)
+ SREG x31, 31*REGBYTES(sp)
+#endif // __RVE_EXT
+
+ csrr a0, mcause
+ csrr a1, mepc
+ mv a2, sp
+ jal handle_trap
+
+ LREG x1, 1*REGBYTES(sp)
+ LREG x2, 2*REGBYTES(sp)
+ LREG x3, 3*REGBYTES(sp)
+ LREG x4, 4*REGBYTES(sp)
+ LREG x5, 5*REGBYTES(sp)
+ LREG x6, 6*REGBYTES(sp)
+ LREG x7, 7*REGBYTES(sp)
+ LREG x8, 8*REGBYTES(sp)
+ LREG x9, 9*REGBYTES(sp)
+ LREG x10, 10*REGBYTES(sp)
+ LREG x11, 11*REGBYTES(sp)
+ LREG x12, 12*REGBYTES(sp)
+ LREG x13, 13*REGBYTES(sp)
+ LREG x14, 14*REGBYTES(sp)
+ LREG x15, 15*REGBYTES(sp)
+#ifndef __RVE_EXT
+ LREG x16, 16*REGBYTES(sp)
+ LREG x17, 17*REGBYTES(sp)
+ LREG x18, 18*REGBYTES(sp)
+ LREG x19, 19*REGBYTES(sp)
+ LREG x20, 20*REGBYTES(sp)
+ LREG x21, 21*REGBYTES(sp)
+ LREG x22, 22*REGBYTES(sp)
+ LREG x23, 23*REGBYTES(sp)
+ LREG x24, 24*REGBYTES(sp)
+ LREG x25, 25*REGBYTES(sp)
+ LREG x26, 26*REGBYTES(sp)
+ LREG x27, 27*REGBYTES(sp)
+ LREG x28, 28*REGBYTES(sp)
+ LREG x29, 29*REGBYTES(sp)
+ LREG x30, 30*REGBYTES(sp)
+ LREG x31, 31*REGBYTES(sp)
+#endif // __RVE_EXT
+
+ addi sp, sp, 272
+ mret
+
+handle_trap:
+ j SIM_EXIT
+
+// end of crt.S
diff --git a/verilog/dv/firmware/csr.h b/verilog/dv/firmware/csr.h
new file mode 100644
index 0000000..976f1fc
--- /dev/null
+++ b/verilog/dv/firmware/csr.h
@@ -0,0 +1,128 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021, Dinesh Annayya ////
+// ////
+// Licensed under the Apache License, Version 2.0 (the "License"); ////
+// you may not use this file except in compliance with the License. ////
+// You may obtain a copy of the License at ////
+// ////
+// http://www.apache.org/licenses/LICENSE-2.0 ////
+// ////
+// Unless required by applicable law or agreed to in writing, software ////
+// distributed under the License is distributed on an "AS IS" BASIS, ////
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.///
+// See the License for the specific language governing permissions and ////
+// limitations under the License. ////
+// SPDX-License-Identifier: Apache-2.0 ////
+// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> ////
+//////////////////////////////////////////////////////////////////////////////
+/// Architecture specific CSR's defs and inlines
+
+#ifndef YCR_CSR_H
+#define YCR_CSR_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#define __xstringify(s) __stringify(s)
+#define __stringify(s) #s
+
+#ifdef read_csr
+#undef read_csr
+#endif
+
+#ifdef write_csr
+#undef write_csr
+#endif
+
+#ifdef swap_csr
+#undef swap_csr
+#endif
+
+#ifdef set_csr
+#undef set_csr
+#endif
+
+#ifdef clear_csr
+#undef clear_csr
+#endif
+
+#ifdef rdtime
+#undef rdtime
+#endif
+
+#ifdef rdcycle
+#undef rdcycle
+#endif
+
+#ifdef rdinstret
+#undef rdinstret
+#endif
+
+#define read_csr(reg) \
+ ({ \
+ unsigned long __tmp; \
+ asm volatile ("csrr %0, " __xstringify(reg) : "=r"(__tmp)); \
+ __tmp; \
+ })
+
+#define write_csr(reg, val) \
+ do { \
+ if (__builtin_constant_p(val) && (val) == 0) \
+ asm volatile ("csrw " __xstringify(reg) ", zero" ::); \
+ else if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+ asm volatile ("csrw " __xstringify(reg) ", %0" :: "i"(val)); \
+ else \
+ asm volatile ("csrw " __xstringify(reg) ", %0" :: "r"(val)); \
+ } while (0)
+
+#define swap_csr(reg, val) \
+ ({ \
+ unsigned long __tmp; \
+ if (__builtin_constant_p(val) && (val) == 0) \
+ asm volatile ("csrrw %0, " __xstringify(reg) ", zero" : "=r"(__tmp) :); \
+ else if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+ asm volatile ("csrrw %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "i"(val)); \
+ else \
+ asm volatile ("csrrw %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "r"(val)); \
+ __tmp; \
+ })
+
+#define set_csr(reg, bit) \
+ ({ \
+ unsigned long __tmp; \
+ if (__builtin_constant_p(bit) && (bit) < 32) \
+ asm volatile ("csrrs %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "i"(bit)); \
+ else \
+ asm volatile ("csrrs %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "r"(bit)); \
+ __tmp; \
+ })
+
+#define clear_csr(reg, bit) \
+ ({ \
+ unsigned long __tmp; \
+ if (__builtin_constant_p(bit) && (bit) < 32) \
+ asm volatile ("csrrc %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "i"(bit)); \
+ else \
+ asm volatile ("csrrc %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "r"(bit)); \
+ __tmp; \
+ })
+
+#define rdtime() read_csr(time)
+#define rdcycle() read_csr(cycle)
+#define rdinstret() read_csr(instret)
+
+static inline unsigned long __attribute__((const)) cpuid()
+{
+ unsigned long res;
+ asm ("csrr %0, mcpuid" : "=r"(res));
+ return res;
+}
+
+static inline unsigned long __attribute__((const)) impid()
+{
+ unsigned long res;
+ asm ("csrr %0, mimpid" : "=r"(res));
+ return res;
+}
+
+#endif // YCR_CSR_H
diff --git a/verilog/dv/firmware/link.ld b/verilog/dv/firmware/link.ld
new file mode 100644
index 0000000..5d75e36
--- /dev/null
+++ b/verilog/dv/firmware/link.ld
@@ -0,0 +1,118 @@
+/*
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021, Dinesh Annayya ////
+// ////
+// Licensed under the Apache License, Version 2.0 (the "License"); ////
+// you may not use this file except in compliance with the License. ////
+// You may obtain a copy of the License at ////
+// ////
+// http://www.apache.org/licenses/LICENSE-2.0 ////
+// ////
+// Unless required by applicable law or agreed to in writing, software ////
+// distributed under the License is distributed on an "AS IS" BASIS, ////
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.///
+// See the License for the specific language governing permissions and ////
+// limitations under the License. ////
+// SPDX-License-Identifier: Apache-2.0 ////
+// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> ////
+//////////////////////////////////////////////////////////////////////////////
+**/
+/*
+* @brief bare metal tests' linker script
+*/
+
+OUTPUT_ARCH( "riscv" )
+ENTRY(_start)
+
+MEMORY {
+ ROM (rxx) : ORIGIN = 0x0, LENGTH = 64K
+ TCM (rwx) : ORIGIN = 0x00480000, LENGTH = 4K
+ RAM (rwx) : ORIGIN = 0x10030000, LENGTH = 8K
+}
+
+STACK_SIZE = 1024;
+
+CL_SIZE = 32;
+
+SECTIONS {
+
+ /* code segment */
+ .text.init 0 : {
+ FILL(0);
+ . = 0x100 - 12;
+ SIM_EXIT = .;
+ LONG(0x13);
+ SIM_STOP = .;
+ LONG(0x6F);
+ LONG(-1);
+ . = 0x100;
+ PROVIDE(__TEXT_START__ = .);
+ *(.text.init)
+ } >ROM
+
+ .text : {
+ *crt.o(.text .text.*)
+ *(.text .text.*)
+ *(sc_test_section)
+ . = ALIGN(CL_SIZE);
+ PROVIDE(__TEXT_END__ = .);
+ } >ROM
+
+ /* data segment */
+ .data : {
+ *(.data .data.*)
+ . = ALIGN(CL_SIZE);
+ } >TCM
+
+ .sdata : {
+ __global_pointer$ = . + 0x800;
+ *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*)
+ *(.sdata .sdata.* .gnu.linkonce.s.*)
+ . = ALIGN(CL_SIZE);
+ } >TCM
+
+ /* thread-local data segment */
+ .tdata : {
+ PROVIDE(_tls_data = .);
+ PROVIDE(_tdata_begin = .);
+ *(.tdata .tdata.*)
+ PROVIDE(_tdata_end = .);
+ . = ALIGN(CL_SIZE);
+ } >TCM
+
+ .tbss : {
+ PROVIDE(__BSS_START__ = .);
+ *(.tbss .tbss.*)
+ . = ALIGN(CL_SIZE);
+ PROVIDE(_tbss_end = .);
+ } >TCM
+
+ /* bss segment */
+ .sbss : {
+ *(.sbss .sbss.* .gnu.linkonce.sb.*)
+ *(.scommon)
+ } >RAM
+
+ .bss : {
+ *(.bss .bss.*)
+ . = ALIGN(CL_SIZE);
+ PROVIDE(__BSS_END__ = .);
+ } >RAM
+
+ _end = .;
+ PROVIDE(__end = .);
+
+ /* End of uninitalized data segement */
+
+ .stack ORIGIN(TCM) + LENGTH(TCM) - STACK_SIZE : {
+ FILL(0);
+ PROVIDE(__STACK_START__ = .);
+ . += STACK_SIZE;
+ PROVIDE(__C_STACK_TOP__ = .);
+ PROVIDE(__STACK_END__ = .);
+ } >TCM
+
+ /DISCARD/ : {
+ *(.eh_frame .eh_frame.*)
+ }
+}
diff --git a/verilog/dv/firmware/link_tcm.ld b/verilog/dv/firmware/link_tcm.ld
new file mode 100644
index 0000000..6b09881
--- /dev/null
+++ b/verilog/dv/firmware/link_tcm.ld
@@ -0,0 +1,131 @@
+/**
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021, Dinesh Annayya ////
+// ////
+// Licensed under the Apache License, Version 2.0 (the "License"); ////
+// you may not use this file except in compliance with the License. ////
+// You may obtain a copy of the License at ////
+// ////
+// http://www.apache.org/licenses/LICENSE-2.0 ////
+// ////
+// Unless required by applicable law or agreed to in writing, software ////
+// distributed under the License is distributed on an "AS IS" BASIS, ////
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.///
+// See the License for the specific language governing permissions and ////
+// limitations under the License. ////
+// SPDX-License-Identifier: Apache-2.0 ////
+// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> ////
+//////////////////////////////////////////////////////////////////////////////
+*/
+/*
+* @brief bare metal tests' linker script
+*/
+
+OUTPUT_ARCH( "riscv" )
+ENTRY(_start)
+
+MEMORY {
+ ROM (rxx) : ORIGIN = 0x0, LENGTH = 64K
+ TCM (rwx) : ORIGIN = 0x00480000, LENGTH = 4K
+}
+
+STACK_SIZE = 256;
+
+CL_SIZE = 32;
+
+SECTIONS {
+
+ /* code segment */
+ .text.init ORIGIN(ROM) : {
+ FILL(0);
+ . = 0x100 - 12;
+ SIM_EXIT = .;
+ LONG(0x13);
+ SIM_STOP = .;
+ LONG(0x6F);
+ LONG(-1);
+ . = 0x100;
+ *crt_tcm.o(.text .text.*)
+ *(.text.init)
+ . = ALIGN(CL_SIZE);
+ } >ROM
+
+ __reloc_start = .;
+
+ .text : {
+ PROVIDE(__TEXT_START__ = .);
+ *(.text .text.*)
+ *(sc_test_section)
+ . = ALIGN(CL_SIZE);
+ PROVIDE(__TEXT_END__ = .);
+ } >TCM AT>ROM
+
+
+ .rodata ALIGN(CL_SIZE) : {
+ __global_pointer$ = . + 0x800;
+ *(.rodata) *(.rodata.*) *(.gnu.linkonce.r.*)
+ . = ALIGN(CL_SIZE);
+ LONG(0x13);
+ . = ALIGN(CL_SIZE);
+ } >TCM AT>ROM
+
+
+ /* data segment */
+ .data ALIGN(CL_SIZE) : {
+ PROVIDE(__DATA_START__ = .);
+ *(.data .data.*)
+ . = ALIGN(CL_SIZE);
+ } >TCM
+
+ .sdata ALIGN(CL_SIZE) : {
+ *(.sdata .sdata.* .gnu.linkonce.s.*)
+ . = ALIGN(CL_SIZE);
+ PROVIDE(__DATA_END__ = .);
+ } >TCM
+
+ /* thread-local data segment */
+ .tdata ALIGN(CL_SIZE) : {
+ PROVIDE(_tls_data = .);
+ PROVIDE(_tdata_begin = .);
+ *(.tdata .tdata.*)
+ PROVIDE(_tdata_end = .);
+ . = ALIGN(CL_SIZE);
+ } >TCM
+
+ .tbss ALIGN(CL_SIZE) : {
+ PROVIDE(_tbss_begin = .);
+ *(.tbss .tbss.*)
+ . = ALIGN(CL_SIZE);
+ PROVIDE(_tbss_end = .);
+ } >TCM
+
+ /* bss segment */
+ .sbss ALIGN(CL_SIZE) : {
+ PROVIDE(__BSS_START__ = .);
+ *(.sbss .sbss.* .gnu.linkonce.sb.*)
+ *(.scommon)
+ . = ALIGN(CL_SIZE);
+ } >TCM
+
+ .bss ALIGN(CL_SIZE) : {
+ *(.dynbss) *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON)
+ . = ALIGN(CL_SIZE);
+ PROVIDE(__BSS_END__ = .);
+ } >TCM
+
+ _end = .;
+ PROVIDE(__end = .);
+
+ /* End of uninitalized data segement */
+
+ .stack ORIGIN(TCM) + LENGTH(TCM) - STACK_SIZE : {
+ PROVIDE(__STACK_START__ = .);
+ . += STACK_SIZE;
+ PROVIDE(__C_STACK_TOP__ = .);
+ PROVIDE(__STACK_END__ = .);
+ } >TCM
+
+ /DISCARD/ : {
+ *(.eh_frame .eh_frame.*)
+ }
+}
diff --git a/verilog/dv/firmware/reloc.h b/verilog/dv/firmware/reloc.h
new file mode 100644
index 0000000..b78167e
--- /dev/null
+++ b/verilog/dv/firmware/reloc.h
@@ -0,0 +1,56 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021, Dinesh Annayya ////
+// ////
+// Licensed under the Apache License, Version 2.0 (the "License"); ////
+// you may not use this file except in compliance with the License. ////
+// You may obtain a copy of the License at ////
+// ////
+// http://www.apache.org/licenses/LICENSE-2.0 ////
+// ////
+// Unless required by applicable law or agreed to in writing, software ////
+// distributed under the License is distributed on an "AS IS" BASIS, ////
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.///
+// See the License for the specific language governing permissions and ////
+// limitations under the License. ////
+// SPDX-License-Identifier: Apache-2.0 ////
+// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> ////
+//////////////////////////////////////////////////////////////////////////////
+
+
+#ifndef RELOC_H
+#define RELOC_H
+
+#if (TCM == 1)
+#define RELOC_PROC \
+ la a0, __reloc_start; \
+ la a1, __TEXT_START__; \
+ la a2, __DATA_END__; \
+ beq a0, a1, 21f; \
+ j 2f; \
+1: lw a3, 0(a0); \
+ sw a3, 0(a1); \
+ add a0, a0, 4; \
+ add a1, a1, 4; \
+2: bne a1, a2, 1b; \
+ /* clear bss */ \
+ la a2, __BSS_START__; \
+21: la a1, __BSS_END__; \
+ j 4f; \
+3: sw zero, 0(a2); \
+ add a2, a2, 4; \
+4: bne a1, a2, 3b; \
+ /* init stack */ \
+ la sp, __C_STACK_TOP__; \
+ /* init hart0 TLS */ \
+ la a0, _tdata_begin; \
+ la a2, _tbss_end; \
+ sub a1, a2, a0; \
+ la a4, __STACK_START__; \
+ sub tp, a4, a1;
+#else // #if TCM
+
+#define RELOC_PROC
+
+#endif // #else #if TCM
+
+#endif //
diff --git a/verilog/dv/firmware/riscv_csr_encoding.h b/verilog/dv/firmware/riscv_csr_encoding.h
new file mode 100644
index 0000000..09f5abb
--- /dev/null
+++ b/verilog/dv/firmware/riscv_csr_encoding.h
@@ -0,0 +1,1489 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021, Dinesh Annayya ////
+// ////
+// Licensed under the Apache License, Version 2.0 (the "License"); ////
+// you may not use this file except in compliance with the License. ////
+// You may obtain a copy of the License at ////
+// ////
+// http://www.apache.org/licenses/LICENSE-2.0 ////
+// ////
+// Unless required by applicable law or agreed to in writing, software ////
+// distributed under the License is distributed on an "AS IS" BASIS, ////
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.///
+// See the License for the specific language governing permissions and ////
+// limitations under the License. ////
+// SPDX-License-Identifier: Apache-2.0 ////
+// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> ////
+//////////////////////////////////////////////////////////////////////////////
+
+#ifndef RISCV_CSR_ENCODING_H
+#define RISCV_CSR_ENCODING_H
+
+#define MSTATUS_UIE 0x00000001
+#define MSTATUS_SIE 0x00000002
+#define MSTATUS_HIE 0x00000004
+#define MSTATUS_MIE 0x00000008
+#define MSTATUS_UPIE 0x00000010
+#define MSTATUS_SPIE 0x00000020
+#define MSTATUS_HPIE 0x00000040
+#define MSTATUS_MPIE 0x00000080
+#define MSTATUS_SPP 0x00000100
+#define MSTATUS_HPP 0x00000600
+#define MSTATUS_MPP 0x00001800
+#define MSTATUS_FS 0x00006000
+#define MSTATUS_XS 0x00018000
+#define MSTATUS_MPRV 0x00020000
+#define MSTATUS_SUM 0x00040000
+#define MSTATUS_MXR 0x00080000
+#define MSTATUS_TVM 0x00100000
+#define MSTATUS_TW 0x00200000
+#define MSTATUS_TSR 0x00400000
+#define MSTATUS32_SD 0x80000000
+#define MSTATUS_UXL 0x0000000300000000
+#define MSTATUS_SXL 0x0000000C00000000
+#define MSTATUS64_SD 0x8000000000000000
+
+#define SSTATUS_UIE 0x00000001
+#define SSTATUS_SIE 0x00000002
+#define SSTATUS_UPIE 0x00000010
+#define SSTATUS_SPIE 0x00000020
+#define SSTATUS_SPP 0x00000100
+#define SSTATUS_FS 0x00006000
+#define SSTATUS_XS 0x00018000
+#define SSTATUS_SUM 0x00040000
+#define SSTATUS_MXR 0x00080000
+#define SSTATUS32_SD 0x80000000
+#define SSTATUS_UXL 0x0000000300000000
+#define SSTATUS64_SD 0x8000000000000000
+
+#define DCSR_XDEBUGVER (3U<<30)
+#define DCSR_NDRESET (1<<29)
+#define DCSR_FULLRESET (1<<28)
+#define DCSR_EBREAKM (1<<15)
+#define DCSR_EBREAKH (1<<14)
+#define DCSR_EBREAKS (1<<13)
+#define DCSR_EBREAKU (1<<12)
+#define DCSR_STOPCYCLE (1<<10)
+#define DCSR_STOPTIME (1<<9)
+#define DCSR_CAUSE (7<<6)
+#define DCSR_DEBUGINT (1<<5)
+#define DCSR_HALT (1<<3)
+#define DCSR_STEP (1<<2)
+#define DCSR_PRV (3<<0)
+
+#define DCSR_CAUSE_NONE 0
+#define DCSR_CAUSE_SWBP 1
+#define DCSR_CAUSE_HWBP 2
+#define DCSR_CAUSE_DEBUGINT 3
+#define DCSR_CAUSE_STEP 4
+#define DCSR_CAUSE_HALT 5
+
+#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4))
+#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5))
+#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
+
+#define MCONTROL_SELECT (1<<19)
+#define MCONTROL_TIMING (1<<18)
+#define MCONTROL_ACTION (0x3f<<12)
+#define MCONTROL_CHAIN (1<<11)
+#define MCONTROL_MATCH (0xf<<7)
+#define MCONTROL_M (1<<6)
+#define MCONTROL_H (1<<5)
+#define MCONTROL_S (1<<4)
+#define MCONTROL_U (1<<3)
+#define MCONTROL_EXECUTE (1<<2)
+#define MCONTROL_STORE (1<<1)
+#define MCONTROL_LOAD (1<<0)
+
+#define MCONTROL_TYPE_NONE 0
+#define MCONTROL_TYPE_MATCH 2
+
+#define MCONTROL_ACTION_DEBUG_EXCEPTION 0
+#define MCONTROL_ACTION_DEBUG_MODE 1
+#define MCONTROL_ACTION_TRACE_START 2
+#define MCONTROL_ACTION_TRACE_STOP 3
+#define MCONTROL_ACTION_TRACE_EMIT 4
+
+#define MCONTROL_MATCH_EQUAL 0
+#define MCONTROL_MATCH_NAPOT 1
+#define MCONTROL_MATCH_GE 2
+#define MCONTROL_MATCH_LT 3
+#define MCONTROL_MATCH_MASK_LOW 4
+#define MCONTROL_MATCH_MASK_HIGH 5
+
+#define MIP_SSIP (1 << IRQ_S_SOFT)
+#define MIP_HSIP (1 << IRQ_H_SOFT)
+#define MIP_MSIP (1 << IRQ_M_SOFT)
+#define MIP_STIP (1 << IRQ_S_TIMER)
+#define MIP_HTIP (1 << IRQ_H_TIMER)
+#define MIP_MTIP (1 << IRQ_M_TIMER)
+#define MIP_SEIP (1 << IRQ_S_EXT)
+#define MIP_HEIP (1 << IRQ_H_EXT)
+#define MIP_MEIP (1 << IRQ_M_EXT)
+
+#define SIP_SSIP MIP_SSIP
+#define SIP_STIP MIP_STIP
+
+#define PRV_U 0
+#define PRV_S 1
+#define PRV_H 2
+#define PRV_M 3
+
+#define SPTBR32_MODE 0x80000000
+#define SPTBR32_ASID 0x7FC00000
+#define SPTBR32_PPN 0x003FFFFF
+#define SPTBR64_MODE 0xF000000000000000
+#define SPTBR64_ASID 0x0FFFF00000000000
+#define SPTBR64_PPN 0x00000FFFFFFFFFFF
+
+#define SPTBR_MODE_OFF 0
+#define SPTBR_MODE_SV32 1
+#define SPTBR_MODE_SV39 8
+#define SPTBR_MODE_SV48 9
+#define SPTBR_MODE_SV57 10
+#define SPTBR_MODE_SV64 11
+
+#define PMP_R 0x01
+#define PMP_W 0x02
+#define PMP_X 0x04
+#define PMP_A 0x18
+#define PMP_L 0x80
+#define PMP_SHIFT 2
+
+#define PMP_TOR 0x08
+#define PMP_NA4 0x10
+#define PMP_NAPOT 0x18
+
+#define IRQ_S_SOFT 1
+#define IRQ_H_SOFT 2
+#define IRQ_M_SOFT 3
+#define IRQ_S_TIMER 5
+#define IRQ_H_TIMER 6
+#define IRQ_M_TIMER 7
+#define IRQ_S_EXT 9
+#define IRQ_H_EXT 10
+#define IRQ_M_EXT 11
+#define IRQ_COP 12
+#define IRQ_HOST 13
+
+#define DEFAULT_RSTVEC 0x00001000
+#define CLINT_BASE 0x02000000
+#define CLINT_SIZE 0x000c0000
+#define EXT_IO_BASE 0x40000000
+#define DRAM_BASE 0x80000000
+
+// page table entry (PTE) fields
+#define PTE_V 0x001 // Valid
+#define PTE_R 0x002 // Read
+#define PTE_W 0x004 // Write
+#define PTE_X 0x008 // Execute
+#define PTE_U 0x010 // User
+#define PTE_G 0x020 // Global
+#define PTE_A 0x040 // Accessed
+#define PTE_D 0x080 // Dirty
+#define PTE_SOFT 0x300 // Reserved for Software
+
+#define PTE_PPN_SHIFT 10
+
+#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
+
+#ifdef __riscv
+
+#if __riscv_xlen == 64
+# define MSTATUS_SD MSTATUS64_SD
+# define SSTATUS_SD SSTATUS64_SD
+# define RISCV_PGLEVEL_BITS 9
+# define SPTBR_MODE SPTBR64_MODE
+#else
+# define MSTATUS_SD MSTATUS32_SD
+# define SSTATUS_SD SSTATUS32_SD
+# define RISCV_PGLEVEL_BITS 10
+# define SPTBR_MODE SPTBR32_MODE
+#endif
+#define RISCV_PGSHIFT 12
+#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
+
+#ifndef __ASSEMBLER__
+
+#ifdef __GNUC__
+
+#define read_csr(reg) ({ unsigned long __tmp; \
+ asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+ __tmp; })
+
+#define write_csr(reg, val) ({ \
+ asm volatile ("csrw " #reg ", %0" :: "rK"(val)); })
+
+#define swap_csr(reg, val) ({ unsigned long __tmp; \
+ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \
+ __tmp; })
+
+#define set_csr(reg, bit) ({ unsigned long __tmp; \
+ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
+ __tmp; })
+
+#define clear_csr(reg, bit) ({ unsigned long __tmp; \
+ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
+ __tmp; })
+
+#define rdtime() read_csr(time)
+#define rdcycle() read_csr(cycle)
+#define rdinstret() read_csr(instret)
+
+#endif
+
+#endif
+
+#endif
+
+#endif
+/* Automatically generated by parse-opcodes. */
+#ifndef RISCV_ENCODING_H
+#define RISCV_ENCODING_H
+#define MATCH_BEQ 0x63
+#define MASK_BEQ 0x707f
+#define MATCH_BNE 0x1063
+#define MASK_BNE 0x707f
+#define MATCH_BLT 0x4063
+#define MASK_BLT 0x707f
+#define MATCH_BGE 0x5063
+#define MASK_BGE 0x707f
+#define MATCH_BLTU 0x6063
+#define MASK_BLTU 0x707f
+#define MATCH_BGEU 0x7063
+#define MASK_BGEU 0x707f
+#define MATCH_JALR 0x67
+#define MASK_JALR 0x707f
+#define MATCH_JAL 0x6f
+#define MASK_JAL 0x7f
+#define MATCH_LUI 0x37
+#define MASK_LUI 0x7f
+#define MATCH_AUIPC 0x17
+#define MASK_AUIPC 0x7f
+#define MATCH_ADDI 0x13
+#define MASK_ADDI 0x707f
+#define MATCH_SLLI 0x1013
+#define MASK_SLLI 0xfc00707f
+#define MATCH_SLTI 0x2013
+#define MASK_SLTI 0x707f
+#define MATCH_SLTIU 0x3013
+#define MASK_SLTIU 0x707f
+#define MATCH_XORI 0x4013
+#define MASK_XORI 0x707f
+#define MATCH_SRLI 0x5013
+#define MASK_SRLI 0xfc00707f
+#define MATCH_SRAI 0x40005013
+#define MASK_SRAI 0xfc00707f
+#define MATCH_ORI 0x6013
+#define MASK_ORI 0x707f
+#define MATCH_ANDI 0x7013
+#define MASK_ANDI 0x707f
+#define MATCH_ADD 0x33
+#define MASK_ADD 0xfe00707f
+#define MATCH_SUB 0x40000033
+#define MASK_SUB 0xfe00707f
+#define MATCH_SLL 0x1033
+#define MASK_SLL 0xfe00707f
+#define MATCH_SLT 0x2033
+#define MASK_SLT 0xfe00707f
+#define MATCH_SLTU 0x3033
+#define MASK_SLTU 0xfe00707f
+#define MATCH_XOR 0x4033
+#define MASK_XOR 0xfe00707f
+#define MATCH_SRL 0x5033
+#define MASK_SRL 0xfe00707f
+#define MATCH_SRA 0x40005033
+#define MASK_SRA 0xfe00707f
+#define MATCH_OR 0x6033
+#define MASK_OR 0xfe00707f
+#define MATCH_AND 0x7033
+#define MASK_AND 0xfe00707f
+#define MATCH_ADDIW 0x1b
+#define MASK_ADDIW 0x707f
+#define MATCH_SLLIW 0x101b
+#define MASK_SLLIW 0xfe00707f
+#define MATCH_SRLIW 0x501b
+#define MASK_SRLIW 0xfe00707f
+#define MATCH_SRAIW 0x4000501b
+#define MASK_SRAIW 0xfe00707f
+#define MATCH_ADDW 0x3b
+#define MASK_ADDW 0xfe00707f
+#define MATCH_SUBW 0x4000003b
+#define MASK_SUBW 0xfe00707f
+#define MATCH_SLLW 0x103b
+#define MASK_SLLW 0xfe00707f
+#define MATCH_SRLW 0x503b
+#define MASK_SRLW 0xfe00707f
+#define MATCH_SRAW 0x4000503b
+#define MASK_SRAW 0xfe00707f
+#define MATCH_LB 0x3
+#define MASK_LB 0x707f
+#define MATCH_LH 0x1003
+#define MASK_LH 0x707f
+#define MATCH_LW 0x2003
+#define MASK_LW 0x707f
+#define MATCH_LD 0x3003
+#define MASK_LD 0x707f
+#define MATCH_LBU 0x4003
+#define MASK_LBU 0x707f
+#define MATCH_LHU 0x5003
+#define MASK_LHU 0x707f
+#define MATCH_LWU 0x6003
+#define MASK_LWU 0x707f
+#define MATCH_SB 0x23
+#define MASK_SB 0x707f
+#define MATCH_SH 0x1023
+#define MASK_SH 0x707f
+#define MATCH_SW 0x2023
+#define MASK_SW 0x707f
+#define MATCH_SD 0x3023
+#define MASK_SD 0x707f
+#define MATCH_FENCE 0xf
+#define MASK_FENCE 0x707f
+#define MATCH_FENCE_I 0x100f
+#define MASK_FENCE_I 0x707f
+#define MATCH_MUL 0x2000033
+#define MASK_MUL 0xfe00707f
+#define MATCH_MULH 0x2001033
+#define MASK_MULH 0xfe00707f
+#define MATCH_MULHSU 0x2002033
+#define MASK_MULHSU 0xfe00707f
+#define MATCH_MULHU 0x2003033
+#define MASK_MULHU 0xfe00707f
+#define MATCH_DIV 0x2004033
+#define MASK_DIV 0xfe00707f
+#define MATCH_DIVU 0x2005033
+#define MASK_DIVU 0xfe00707f
+#define MATCH_REM 0x2006033
+#define MASK_REM 0xfe00707f
+#define MATCH_REMU 0x2007033
+#define MASK_REMU 0xfe00707f
+#define MATCH_MULW 0x200003b
+#define MASK_MULW 0xfe00707f
+#define MATCH_DIVW 0x200403b
+#define MASK_DIVW 0xfe00707f
+#define MATCH_DIVUW 0x200503b
+#define MASK_DIVUW 0xfe00707f
+#define MATCH_REMW 0x200603b
+#define MASK_REMW 0xfe00707f
+#define MATCH_REMUW 0x200703b
+#define MASK_REMUW 0xfe00707f
+#define MATCH_AMOADD_W 0x202f
+#define MASK_AMOADD_W 0xf800707f
+#define MATCH_AMOXOR_W 0x2000202f
+#define MASK_AMOXOR_W 0xf800707f
+#define MATCH_AMOOR_W 0x4000202f
+#define MASK_AMOOR_W 0xf800707f
+#define MATCH_AMOAND_W 0x6000202f
+#define MASK_AMOAND_W 0xf800707f
+#define MATCH_AMOMIN_W 0x8000202f
+#define MASK_AMOMIN_W 0xf800707f
+#define MATCH_AMOMAX_W 0xa000202f
+#define MASK_AMOMAX_W 0xf800707f
+#define MATCH_AMOMINU_W 0xc000202f
+#define MASK_AMOMINU_W 0xf800707f
+#define MATCH_AMOMAXU_W 0xe000202f
+#define MASK_AMOMAXU_W 0xf800707f
+#define MATCH_AMOSWAP_W 0x800202f
+#define MASK_AMOSWAP_W 0xf800707f
+#define MATCH_LR_W 0x1000202f
+#define MASK_LR_W 0xf9f0707f
+#define MATCH_SC_W 0x1800202f
+#define MASK_SC_W 0xf800707f
+#define MATCH_AMOADD_D 0x302f
+#define MASK_AMOADD_D 0xf800707f
+#define MATCH_AMOXOR_D 0x2000302f
+#define MASK_AMOXOR_D 0xf800707f
+#define MATCH_AMOOR_D 0x4000302f
+#define MASK_AMOOR_D 0xf800707f
+#define MATCH_AMOAND_D 0x6000302f
+#define MASK_AMOAND_D 0xf800707f
+#define MATCH_AMOMIN_D 0x8000302f
+#define MASK_AMOMIN_D 0xf800707f
+#define MATCH_AMOMAX_D 0xa000302f
+#define MASK_AMOMAX_D 0xf800707f
+#define MATCH_AMOMINU_D 0xc000302f
+#define MASK_AMOMINU_D 0xf800707f
+#define MATCH_AMOMAXU_D 0xe000302f
+#define MASK_AMOMAXU_D 0xf800707f
+#define MATCH_AMOSWAP_D 0x800302f
+#define MASK_AMOSWAP_D 0xf800707f
+#define MATCH_LR_D 0x1000302f
+#define MASK_LR_D 0xf9f0707f
+#define MATCH_SC_D 0x1800302f
+#define MASK_SC_D 0xf800707f
+#define MATCH_ECALL 0x73
+#define MASK_ECALL 0xffffffff
+#define MATCH_EBREAK 0x100073
+#define MASK_EBREAK 0xffffffff
+#define MATCH_URET 0x200073
+#define MASK_URET 0xffffffff
+#define MATCH_SRET 0x10200073
+#define MASK_SRET 0xffffffff
+#define MATCH_MRET 0x30200073
+#define MASK_MRET 0xffffffff
+#define MATCH_DRET 0x7b200073
+#define MASK_DRET 0xffffffff
+#define MATCH_SFENCE_VMA 0x12000073
+#define MASK_SFENCE_VMA 0xfe007fff
+#define MATCH_WFI 0x10500073
+#define MASK_WFI 0xffffffff
+#define MATCH_CSRRW 0x1073
+#define MASK_CSRRW 0x707f
+#define MATCH_CSRRS 0x2073
+#define MASK_CSRRS 0x707f
+#define MATCH_CSRRC 0x3073
+#define MASK_CSRRC 0x707f
+#define MATCH_CSRRWI 0x5073
+#define MASK_CSRRWI 0x707f
+#define MATCH_CSRRSI 0x6073
+#define MASK_CSRRSI 0x707f
+#define MATCH_CSRRCI 0x7073
+#define MASK_CSRRCI 0x707f
+#define MATCH_FADD_S 0x53
+#define MASK_FADD_S 0xfe00007f
+#define MATCH_FSUB_S 0x8000053
+#define MASK_FSUB_S 0xfe00007f
+#define MATCH_FMUL_S 0x10000053
+#define MASK_FMUL_S 0xfe00007f
+#define MATCH_FDIV_S 0x18000053
+#define MASK_FDIV_S 0xfe00007f
+#define MATCH_FSGNJ_S 0x20000053
+#define MASK_FSGNJ_S 0xfe00707f
+#define MATCH_FSGNJN_S 0x20001053
+#define MASK_FSGNJN_S 0xfe00707f
+#define MATCH_FSGNJX_S 0x20002053
+#define MASK_FSGNJX_S 0xfe00707f
+#define MATCH_FMIN_S 0x28000053
+#define MASK_FMIN_S 0xfe00707f
+#define MATCH_FMAX_S 0x28001053
+#define MASK_FMAX_S 0xfe00707f
+#define MATCH_FSQRT_S 0x58000053
+#define MASK_FSQRT_S 0xfff0007f
+#define MATCH_FADD_D 0x2000053
+#define MASK_FADD_D 0xfe00007f
+#define MATCH_FSUB_D 0xa000053
+#define MASK_FSUB_D 0xfe00007f
+#define MATCH_FMUL_D 0x12000053
+#define MASK_FMUL_D 0xfe00007f
+#define MATCH_FDIV_D 0x1a000053
+#define MASK_FDIV_D 0xfe00007f
+#define MATCH_FSGNJ_D 0x22000053
+#define MASK_FSGNJ_D 0xfe00707f
+#define MATCH_FSGNJN_D 0x22001053
+#define MASK_FSGNJN_D 0xfe00707f
+#define MATCH_FSGNJX_D 0x22002053
+#define MASK_FSGNJX_D 0xfe00707f
+#define MATCH_FMIN_D 0x2a000053
+#define MASK_FMIN_D 0xfe00707f
+#define MATCH_FMAX_D 0x2a001053
+#define MASK_FMAX_D 0xfe00707f
+#define MATCH_FCVT_S_D 0x40100053
+#define MASK_FCVT_S_D 0xfff0007f
+#define MATCH_FCVT_D_S 0x42000053
+#define MASK_FCVT_D_S 0xfff0007f
+#define MATCH_FSQRT_D 0x5a000053
+#define MASK_FSQRT_D 0xfff0007f
+#define MATCH_FADD_Q 0x6000053
+#define MASK_FADD_Q 0xfe00007f
+#define MATCH_FSUB_Q 0xe000053
+#define MASK_FSUB_Q 0xfe00007f
+#define MATCH_FMUL_Q 0x16000053
+#define MASK_FMUL_Q 0xfe00007f
+#define MATCH_FDIV_Q 0x1e000053
+#define MASK_FDIV_Q 0xfe00007f
+#define MATCH_FSGNJ_Q 0x26000053
+#define MASK_FSGNJ_Q 0xfe00707f
+#define MATCH_FSGNJN_Q 0x26001053
+#define MASK_FSGNJN_Q 0xfe00707f
+#define MATCH_FSGNJX_Q 0x26002053
+#define MASK_FSGNJX_Q 0xfe00707f
+#define MATCH_FMIN_Q 0x2e000053
+#define MASK_FMIN_Q 0xfe00707f
+#define MATCH_FMAX_Q 0x2e001053
+#define MASK_FMAX_Q 0xfe00707f
+#define MATCH_FCVT_S_Q 0x40300053
+#define MASK_FCVT_S_Q 0xfff0007f
+#define MATCH_FCVT_Q_S 0x46000053
+#define MASK_FCVT_Q_S 0xfff0007f
+#define MATCH_FCVT_D_Q 0x42300053
+#define MASK_FCVT_D_Q 0xfff0007f
+#define MATCH_FCVT_Q_D 0x46100053
+#define MASK_FCVT_Q_D 0xfff0007f
+#define MATCH_FSQRT_Q 0x5e000053
+#define MASK_FSQRT_Q 0xfff0007f
+#define MATCH_FLE_S 0xa0000053
+#define MASK_FLE_S 0xfe00707f
+#define MATCH_FLT_S 0xa0001053
+#define MASK_FLT_S 0xfe00707f
+#define MATCH_FEQ_S 0xa0002053
+#define MASK_FEQ_S 0xfe00707f
+#define MATCH_FLE_D 0xa2000053
+#define MASK_FLE_D 0xfe00707f
+#define MATCH_FLT_D 0xa2001053
+#define MASK_FLT_D 0xfe00707f
+#define MATCH_FEQ_D 0xa2002053
+#define MASK_FEQ_D 0xfe00707f
+#define MATCH_FLE_Q 0xa6000053
+#define MASK_FLE_Q 0xfe00707f
+#define MATCH_FLT_Q 0xa6001053
+#define MASK_FLT_Q 0xfe00707f
+#define MATCH_FEQ_Q 0xa6002053
+#define MASK_FEQ_Q 0xfe00707f
+#define MATCH_FCVT_W_S 0xc0000053
+#define MASK_FCVT_W_S 0xfff0007f
+#define MATCH_FCVT_WU_S 0xc0100053
+#define MASK_FCVT_WU_S 0xfff0007f
+#define MATCH_FCVT_L_S 0xc0200053
+#define MASK_FCVT_L_S 0xfff0007f
+#define MATCH_FCVT_LU_S 0xc0300053
+#define MASK_FCVT_LU_S 0xfff0007f
+#define MATCH_FMV_X_W 0xe0000053
+#define MASK_FMV_X_W 0xfff0707f
+#define MATCH_FCLASS_S 0xe0001053
+#define MASK_FCLASS_S 0xfff0707f
+#define MATCH_FCVT_W_D 0xc2000053
+#define MASK_FCVT_W_D 0xfff0007f
+#define MATCH_FCVT_WU_D 0xc2100053
+#define MASK_FCVT_WU_D 0xfff0007f
+#define MATCH_FCVT_L_D 0xc2200053
+#define MASK_FCVT_L_D 0xfff0007f
+#define MATCH_FCVT_LU_D 0xc2300053
+#define MASK_FCVT_LU_D 0xfff0007f
+#define MATCH_FMV_X_D 0xe2000053
+#define MASK_FMV_X_D 0xfff0707f
+#define MATCH_FCLASS_D 0xe2001053
+#define MASK_FCLASS_D 0xfff0707f
+#define MATCH_FCVT_W_Q 0xc6000053
+#define MASK_FCVT_W_Q 0xfff0007f
+#define MATCH_FCVT_WU_Q 0xc6100053
+#define MASK_FCVT_WU_Q 0xfff0007f
+#define MATCH_FCVT_L_Q 0xc6200053
+#define MASK_FCVT_L_Q 0xfff0007f
+#define MATCH_FCVT_LU_Q 0xc6300053
+#define MASK_FCVT_LU_Q 0xfff0007f
+#define MATCH_FMV_X_Q 0xe6000053
+#define MASK_FMV_X_Q 0xfff0707f
+#define MATCH_FCLASS_Q 0xe6001053
+#define MASK_FCLASS_Q 0xfff0707f
+#define MATCH_FCVT_S_W 0xd0000053
+#define MASK_FCVT_S_W 0xfff0007f
+#define MATCH_FCVT_S_WU 0xd0100053
+#define MASK_FCVT_S_WU 0xfff0007f
+#define MATCH_FCVT_S_L 0xd0200053
+#define MASK_FCVT_S_L 0xfff0007f
+#define MATCH_FCVT_S_LU 0xd0300053
+#define MASK_FCVT_S_LU 0xfff0007f
+#define MATCH_FMV_W_X 0xf0000053
+#define MASK_FMV_W_X 0xfff0707f
+#define MATCH_FCVT_D_W 0xd2000053
+#define MASK_FCVT_D_W 0xfff0007f
+#define MATCH_FCVT_D_WU 0xd2100053
+#define MASK_FCVT_D_WU 0xfff0007f
+#define MATCH_FCVT_D_L 0xd2200053
+#define MASK_FCVT_D_L 0xfff0007f
+#define MATCH_FCVT_D_LU 0xd2300053
+#define MASK_FCVT_D_LU 0xfff0007f
+#define MATCH_FMV_D_X 0xf2000053
+#define MASK_FMV_D_X 0xfff0707f
+#define MATCH_FCVT_Q_W 0xd6000053
+#define MASK_FCVT_Q_W 0xfff0007f
+#define MATCH_FCVT_Q_WU 0xd6100053
+#define MASK_FCVT_Q_WU 0xfff0007f
+#define MATCH_FCVT_Q_L 0xd6200053
+#define MASK_FCVT_Q_L 0xfff0007f
+#define MATCH_FCVT_Q_LU 0xd6300053
+#define MASK_FCVT_Q_LU 0xfff0007f
+#define MATCH_FMV_Q_X 0xf6000053
+#define MASK_FMV_Q_X 0xfff0707f
+#define MATCH_FLW 0x2007
+#define MASK_FLW 0x707f
+#define MATCH_FLD 0x3007
+#define MASK_FLD 0x707f
+#define MATCH_FLQ 0x4007
+#define MASK_FLQ 0x707f
+#define MATCH_FSW 0x2027
+#define MASK_FSW 0x707f
+#define MATCH_FSD 0x3027
+#define MASK_FSD 0x707f
+#define MATCH_FSQ 0x4027
+#define MASK_FSQ 0x707f
+#define MATCH_FMADD_S 0x43
+#define MASK_FMADD_S 0x600007f
+#define MATCH_FMSUB_S 0x47
+#define MASK_FMSUB_S 0x600007f
+#define MATCH_FNMSUB_S 0x4b
+#define MASK_FNMSUB_S 0x600007f
+#define MATCH_FNMADD_S 0x4f
+#define MASK_FNMADD_S 0x600007f
+#define MATCH_FMADD_D 0x2000043
+#define MASK_FMADD_D 0x600007f
+#define MATCH_FMSUB_D 0x2000047
+#define MASK_FMSUB_D 0x600007f
+#define MATCH_FNMSUB_D 0x200004b
+#define MASK_FNMSUB_D 0x600007f
+#define MATCH_FNMADD_D 0x200004f
+#define MASK_FNMADD_D 0x600007f
+#define MATCH_FMADD_Q 0x6000043
+#define MASK_FMADD_Q 0x600007f
+#define MATCH_FMSUB_Q 0x6000047
+#define MASK_FMSUB_Q 0x600007f
+#define MATCH_FNMSUB_Q 0x600004b
+#define MASK_FNMSUB_Q 0x600007f
+#define MATCH_FNMADD_Q 0x600004f
+#define MASK_FNMADD_Q 0x600007f
+#define MATCH_C_NOP 0x1
+#define MASK_C_NOP 0xffff
+#define MATCH_C_ADDI16SP 0x6101
+#define MASK_C_ADDI16SP 0xef83
+#define MATCH_C_JR 0x8002
+#define MASK_C_JR 0xf07f
+#define MATCH_C_JALR 0x9002
+#define MASK_C_JALR 0xf07f
+#define MATCH_C_EBREAK 0x9002
+#define MASK_C_EBREAK 0xffff
+#define MATCH_C_LD 0x6000
+#define MASK_C_LD 0xe003
+#define MATCH_C_SD 0xe000
+#define MASK_C_SD 0xe003
+#define MATCH_C_ADDIW 0x2001
+#define MASK_C_ADDIW 0xe003
+#define MATCH_C_LDSP 0x6002
+#define MASK_C_LDSP 0xe003
+#define MATCH_C_SDSP 0xe002
+#define MASK_C_SDSP 0xe003
+#define MATCH_C_ADDI4SPN 0x0
+#define MASK_C_ADDI4SPN 0xe003
+#define MATCH_C_FLD 0x2000
+#define MASK_C_FLD 0xe003
+#define MATCH_C_LW 0x4000
+#define MASK_C_LW 0xe003
+#define MATCH_C_FLW 0x6000
+#define MASK_C_FLW 0xe003
+#define MATCH_C_FSD 0xa000
+#define MASK_C_FSD 0xe003
+#define MATCH_C_SW 0xc000
+#define MASK_C_SW 0xe003
+#define MATCH_C_FSW 0xe000
+#define MASK_C_FSW 0xe003
+#define MATCH_C_ADDI 0x1
+#define MASK_C_ADDI 0xe003
+#define MATCH_C_JAL 0x2001
+#define MASK_C_JAL 0xe003
+#define MATCH_C_LI 0x4001
+#define MASK_C_LI 0xe003
+#define MATCH_C_LUI 0x6001
+#define MASK_C_LUI 0xe003
+#define MATCH_C_SRLI 0x8001
+#define MASK_C_SRLI 0xec03
+#define MATCH_C_SRAI 0x8401
+#define MASK_C_SRAI 0xec03
+#define MATCH_C_ANDI 0x8801
+#define MASK_C_ANDI 0xec03
+#define MATCH_C_SUB 0x8c01
+#define MASK_C_SUB 0xfc63
+#define MATCH_C_XOR 0x8c21
+#define MASK_C_XOR 0xfc63
+#define MATCH_C_OR 0x8c41
+#define MASK_C_OR 0xfc63
+#define MATCH_C_AND 0x8c61
+#define MASK_C_AND 0xfc63
+#define MATCH_C_SUBW 0x9c01
+#define MASK_C_SUBW 0xfc63
+#define MATCH_C_ADDW 0x9c21
+#define MASK_C_ADDW 0xfc63
+#define MATCH_C_J 0xa001
+#define MASK_C_J 0xe003
+#define MATCH_C_BEQZ 0xc001
+#define MASK_C_BEQZ 0xe003
+#define MATCH_C_BNEZ 0xe001
+#define MASK_C_BNEZ 0xe003
+#define MATCH_C_SLLI 0x2
+#define MASK_C_SLLI 0xe003
+#define MATCH_C_FLDSP 0x2002
+#define MASK_C_FLDSP 0xe003
+#define MATCH_C_LWSP 0x4002
+#define MASK_C_LWSP 0xe003
+#define MATCH_C_FLWSP 0x6002
+#define MASK_C_FLWSP 0xe003
+#define MATCH_C_MV 0x8002
+#define MASK_C_MV 0xf003
+#define MATCH_C_ADD 0x9002
+#define MASK_C_ADD 0xf003
+#define MATCH_C_FSDSP 0xa002
+#define MASK_C_FSDSP 0xe003
+#define MATCH_C_SWSP 0xc002
+#define MASK_C_SWSP 0xe003
+#define MATCH_C_FSWSP 0xe002
+#define MASK_C_FSWSP 0xe003
+#define MATCH_CUSTOM0 0xb
+#define MASK_CUSTOM0 0x707f
+#define MATCH_CUSTOM0_RS1 0x200b
+#define MASK_CUSTOM0_RS1 0x707f
+#define MATCH_CUSTOM0_RS1_RS2 0x300b
+#define MASK_CUSTOM0_RS1_RS2 0x707f
+#define MATCH_CUSTOM0_RD 0x400b
+#define MASK_CUSTOM0_RD 0x707f
+#define MATCH_CUSTOM0_RD_RS1 0x600b
+#define MASK_CUSTOM0_RD_RS1 0x707f
+#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
+#define MASK_CUSTOM0_RD_RS1_RS2 0x707f
+#define MATCH_CUSTOM1 0x2b
+#define MASK_CUSTOM1 0x707f
+#define MATCH_CUSTOM1_RS1 0x202b
+#define MASK_CUSTOM1_RS1 0x707f
+#define MATCH_CUSTOM1_RS1_RS2 0x302b
+#define MASK_CUSTOM1_RS1_RS2 0x707f
+#define MATCH_CUSTOM1_RD 0x402b
+#define MASK_CUSTOM1_RD 0x707f
+#define MATCH_CUSTOM1_RD_RS1 0x602b
+#define MASK_CUSTOM1_RD_RS1 0x707f
+#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
+#define MASK_CUSTOM1_RD_RS1_RS2 0x707f
+#define MATCH_CUSTOM2 0x5b
+#define MASK_CUSTOM2 0x707f
+#define MATCH_CUSTOM2_RS1 0x205b
+#define MASK_CUSTOM2_RS1 0x707f
+#define MATCH_CUSTOM2_RS1_RS2 0x305b
+#define MASK_CUSTOM2_RS1_RS2 0x707f
+#define MATCH_CUSTOM2_RD 0x405b
+#define MASK_CUSTOM2_RD 0x707f
+#define MATCH_CUSTOM2_RD_RS1 0x605b
+#define MASK_CUSTOM2_RD_RS1 0x707f
+#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
+#define MASK_CUSTOM2_RD_RS1_RS2 0x707f
+#define MATCH_CUSTOM3 0x7b
+#define MASK_CUSTOM3 0x707f
+#define MATCH_CUSTOM3_RS1 0x207b
+#define MASK_CUSTOM3_RS1 0x707f
+#define MATCH_CUSTOM3_RS1_RS2 0x307b
+#define MASK_CUSTOM3_RS1_RS2 0x707f
+#define MATCH_CUSTOM3_RD 0x407b
+#define MASK_CUSTOM3_RD 0x707f
+#define MATCH_CUSTOM3_RD_RS1 0x607b
+#define MASK_CUSTOM3_RD_RS1 0x707f
+#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
+#define MASK_CUSTOM3_RD_RS1_RS2 0x707f
+#define CSR_FFLAGS 0x1
+#define CSR_FRM 0x2
+#define CSR_FCSR 0x3
+#define CSR_CYCLE 0xc00
+#define CSR_TIME 0xc01
+#define CSR_INSTRET 0xc02
+#define CSR_HPMCOUNTER3 0xc03
+#define CSR_HPMCOUNTER4 0xc04
+#define CSR_HPMCOUNTER5 0xc05
+#define CSR_HPMCOUNTER6 0xc06
+#define CSR_HPMCOUNTER7 0xc07
+#define CSR_HPMCOUNTER8 0xc08
+#define CSR_HPMCOUNTER9 0xc09
+#define CSR_HPMCOUNTER10 0xc0a
+#define CSR_HPMCOUNTER11 0xc0b
+#define CSR_HPMCOUNTER12 0xc0c
+#define CSR_HPMCOUNTER13 0xc0d
+#define CSR_HPMCOUNTER14 0xc0e
+#define CSR_HPMCOUNTER15 0xc0f
+#define CSR_HPMCOUNTER16 0xc10
+#define CSR_HPMCOUNTER17 0xc11
+#define CSR_HPMCOUNTER18 0xc12
+#define CSR_HPMCOUNTER19 0xc13
+#define CSR_HPMCOUNTER20 0xc14
+#define CSR_HPMCOUNTER21 0xc15
+#define CSR_HPMCOUNTER22 0xc16
+#define CSR_HPMCOUNTER23 0xc17
+#define CSR_HPMCOUNTER24 0xc18
+#define CSR_HPMCOUNTER25 0xc19
+#define CSR_HPMCOUNTER26 0xc1a
+#define CSR_HPMCOUNTER27 0xc1b
+#define CSR_HPMCOUNTER28 0xc1c
+#define CSR_HPMCOUNTER29 0xc1d
+#define CSR_HPMCOUNTER30 0xc1e
+#define CSR_HPMCOUNTER31 0xc1f
+#define CSR_SSTATUS 0x100
+#define CSR_SIE 0x104
+#define CSR_STVEC 0x105
+#define CSR_SCOUNTEREN 0x106
+#define CSR_SSCRATCH 0x140
+#define CSR_SEPC 0x141
+#define CSR_SCAUSE 0x142
+#define CSR_SBADADDR 0x143
+#define CSR_SIP 0x144
+#define CSR_SPTBR 0x180
+#define CSR_MSTATUS 0x300
+#define CSR_MISA 0x301
+#define CSR_MEDELEG 0x302
+#define CSR_MIDELEG 0x303
+#define CSR_MIE 0x304
+#define CSR_MTVEC 0x305
+#define CSR_MCOUNTEREN 0x306
+#define CSR_MSCRATCH 0x340
+#define CSR_MEPC 0x341
+#define CSR_MCAUSE 0x342
+#define CSR_MBADADDR 0x343
+#define CSR_MIP 0x344
+#define CSR_PMPCFG0 0x3a0
+#define CSR_PMPCFG1 0x3a1
+#define CSR_PMPCFG2 0x3a2
+#define CSR_PMPCFG3 0x3a3
+#define CSR_PMPADDR0 0x3b0
+#define CSR_PMPADDR1 0x3b1
+#define CSR_PMPADDR2 0x3b2
+#define CSR_PMPADDR3 0x3b3
+#define CSR_PMPADDR4 0x3b4
+#define CSR_PMPADDR5 0x3b5
+#define CSR_PMPADDR6 0x3b6
+#define CSR_PMPADDR7 0x3b7
+#define CSR_PMPADDR8 0x3b8
+#define CSR_PMPADDR9 0x3b9
+#define CSR_PMPADDR10 0x3ba
+#define CSR_PMPADDR11 0x3bb
+#define CSR_PMPADDR12 0x3bc
+#define CSR_PMPADDR13 0x3bd
+#define CSR_PMPADDR14 0x3be
+#define CSR_PMPADDR15 0x3bf
+#define CSR_TSELECT 0x7a0
+#define CSR_TDATA1 0x7a1
+#define CSR_TDATA2 0x7a2
+#define CSR_TDATA3 0x7a3
+#define CSR_DCSR 0x7b0
+#define CSR_DPC 0x7b1
+#define CSR_DSCRATCH 0x7b2
+#define CSR_MCYCLE 0xb00
+#define CSR_MINSTRET 0xb02
+#define CSR_MHPMCOUNTER3 0xb03
+#define CSR_MHPMCOUNTER4 0xb04
+#define CSR_MHPMCOUNTER5 0xb05
+#define CSR_MHPMCOUNTER6 0xb06
+#define CSR_MHPMCOUNTER7 0xb07
+#define CSR_MHPMCOUNTER8 0xb08
+#define CSR_MHPMCOUNTER9 0xb09
+#define CSR_MHPMCOUNTER10 0xb0a
+#define CSR_MHPMCOUNTER11 0xb0b
+#define CSR_MHPMCOUNTER12 0xb0c
+#define CSR_MHPMCOUNTER13 0xb0d
+#define CSR_MHPMCOUNTER14 0xb0e
+#define CSR_MHPMCOUNTER15 0xb0f
+#define CSR_MHPMCOUNTER16 0xb10
+#define CSR_MHPMCOUNTER17 0xb11
+#define CSR_MHPMCOUNTER18 0xb12
+#define CSR_MHPMCOUNTER19 0xb13
+#define CSR_MHPMCOUNTER20 0xb14
+#define CSR_MHPMCOUNTER21 0xb15
+#define CSR_MHPMCOUNTER22 0xb16
+#define CSR_MHPMCOUNTER23 0xb17
+#define CSR_MHPMCOUNTER24 0xb18
+#define CSR_MHPMCOUNTER25 0xb19
+#define CSR_MHPMCOUNTER26 0xb1a
+#define CSR_MHPMCOUNTER27 0xb1b
+#define CSR_MHPMCOUNTER28 0xb1c
+#define CSR_MHPMCOUNTER29 0xb1d
+#define CSR_MHPMCOUNTER30 0xb1e
+#define CSR_MHPMCOUNTER31 0xb1f
+#define CSR_MHPMEVENT3 0x323
+#define CSR_MHPMEVENT4 0x324
+#define CSR_MHPMEVENT5 0x325
+#define CSR_MHPMEVENT6 0x326
+#define CSR_MHPMEVENT7 0x327
+#define CSR_MHPMEVENT8 0x328
+#define CSR_MHPMEVENT9 0x329
+#define CSR_MHPMEVENT10 0x32a
+#define CSR_MHPMEVENT11 0x32b
+#define CSR_MHPMEVENT12 0x32c
+#define CSR_MHPMEVENT13 0x32d
+#define CSR_MHPMEVENT14 0x32e
+#define CSR_MHPMEVENT15 0x32f
+#define CSR_MHPMEVENT16 0x330
+#define CSR_MHPMEVENT17 0x331
+#define CSR_MHPMEVENT18 0x332
+#define CSR_MHPMEVENT19 0x333
+#define CSR_MHPMEVENT20 0x334
+#define CSR_MHPMEVENT21 0x335
+#define CSR_MHPMEVENT22 0x336
+#define CSR_MHPMEVENT23 0x337
+#define CSR_MHPMEVENT24 0x338
+#define CSR_MHPMEVENT25 0x339
+#define CSR_MHPMEVENT26 0x33a
+#define CSR_MHPMEVENT27 0x33b
+#define CSR_MHPMEVENT28 0x33c
+#define CSR_MHPMEVENT29 0x33d
+#define CSR_MHPMEVENT30 0x33e
+#define CSR_MHPMEVENT31 0x33f
+#define CSR_MVENDORID 0xf11
+#define CSR_MARCHID 0xf12
+#define CSR_MIMPID 0xf13
+#define CSR_MHARTID 0xf14
+#define CSR_CYCLEH 0xc80
+#define CSR_TIMEH 0xc81
+#define CSR_INSTRETH 0xc82
+#define CSR_HPMCOUNTER3H 0xc83
+#define CSR_HPMCOUNTER4H 0xc84
+#define CSR_HPMCOUNTER5H 0xc85
+#define CSR_HPMCOUNTER6H 0xc86
+#define CSR_HPMCOUNTER7H 0xc87
+#define CSR_HPMCOUNTER8H 0xc88
+#define CSR_HPMCOUNTER9H 0xc89
+#define CSR_HPMCOUNTER10H 0xc8a
+#define CSR_HPMCOUNTER11H 0xc8b
+#define CSR_HPMCOUNTER12H 0xc8c
+#define CSR_HPMCOUNTER13H 0xc8d
+#define CSR_HPMCOUNTER14H 0xc8e
+#define CSR_HPMCOUNTER15H 0xc8f
+#define CSR_HPMCOUNTER16H 0xc90
+#define CSR_HPMCOUNTER17H 0xc91
+#define CSR_HPMCOUNTER18H 0xc92
+#define CSR_HPMCOUNTER19H 0xc93
+#define CSR_HPMCOUNTER20H 0xc94
+#define CSR_HPMCOUNTER21H 0xc95
+#define CSR_HPMCOUNTER22H 0xc96
+#define CSR_HPMCOUNTER23H 0xc97
+#define CSR_HPMCOUNTER24H 0xc98
+#define CSR_HPMCOUNTER25H 0xc99
+#define CSR_HPMCOUNTER26H 0xc9a
+#define CSR_HPMCOUNTER27H 0xc9b
+#define CSR_HPMCOUNTER28H 0xc9c
+#define CSR_HPMCOUNTER29H 0xc9d
+#define CSR_HPMCOUNTER30H 0xc9e
+#define CSR_HPMCOUNTER31H 0xc9f
+#define CSR_MCYCLEH 0xb80
+#define CSR_MINSTRETH 0xb82
+#define CSR_MHPMCOUNTER3H 0xb83
+#define CSR_MHPMCOUNTER4H 0xb84
+#define CSR_MHPMCOUNTER5H 0xb85
+#define CSR_MHPMCOUNTER6H 0xb86
+#define CSR_MHPMCOUNTER7H 0xb87
+#define CSR_MHPMCOUNTER8H 0xb88
+#define CSR_MHPMCOUNTER9H 0xb89
+#define CSR_MHPMCOUNTER10H 0xb8a
+#define CSR_MHPMCOUNTER11H 0xb8b
+#define CSR_MHPMCOUNTER12H 0xb8c
+#define CSR_MHPMCOUNTER13H 0xb8d
+#define CSR_MHPMCOUNTER14H 0xb8e
+#define CSR_MHPMCOUNTER15H 0xb8f
+#define CSR_MHPMCOUNTER16H 0xb90
+#define CSR_MHPMCOUNTER17H 0xb91
+#define CSR_MHPMCOUNTER18H 0xb92
+#define CSR_MHPMCOUNTER19H 0xb93
+#define CSR_MHPMCOUNTER20H 0xb94
+#define CSR_MHPMCOUNTER21H 0xb95
+#define CSR_MHPMCOUNTER22H 0xb96
+#define CSR_MHPMCOUNTER23H 0xb97
+#define CSR_MHPMCOUNTER24H 0xb98
+#define CSR_MHPMCOUNTER25H 0xb99
+#define CSR_MHPMCOUNTER26H 0xb9a
+#define CSR_MHPMCOUNTER27H 0xb9b
+#define CSR_MHPMCOUNTER28H 0xb9c
+#define CSR_MHPMCOUNTER29H 0xb9d
+#define CSR_MHPMCOUNTER30H 0xb9e
+#define CSR_MHPMCOUNTER31H 0xb9f
+#define CAUSE_MISALIGNED_FETCH 0x0
+#define CAUSE_FETCH_ACCESS 0x1
+#define CAUSE_ILLEGAL_INSTRUCTION 0x2
+#define CAUSE_BREAKPOINT 0x3
+#define CAUSE_MISALIGNED_LOAD 0x4
+#define CAUSE_LOAD_ACCESS 0x5
+#define CAUSE_MISALIGNED_STORE 0x6
+#define CAUSE_STORE_ACCESS 0x7
+#define CAUSE_USER_ECALL 0x8
+#define CAUSE_SUPERVISOR_ECALL 0x9
+#define CAUSE_HYPERVISOR_ECALL 0xa
+#define CAUSE_MACHINE_ECALL 0xb
+#define CAUSE_FETCH_PAGE_FAULT 0xc
+#define CAUSE_LOAD_PAGE_FAULT 0xd
+#define CAUSE_STORE_PAGE_FAULT 0xf
+#endif
+#ifdef DECLARE_INSN
+DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
+DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
+DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
+DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
+DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
+DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
+DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
+DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
+DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
+DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
+DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
+DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
+DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
+DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
+DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
+DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
+DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
+DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
+DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
+DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
+DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
+DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
+DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
+DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
+DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
+DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
+DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
+DECLARE_INSN(or, MATCH_OR, MASK_OR)
+DECLARE_INSN(and, MATCH_AND, MASK_AND)
+DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
+DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
+DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
+DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
+DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
+DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
+DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
+DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
+DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
+DECLARE_INSN(lb, MATCH_LB, MASK_LB)
+DECLARE_INSN(lh, MATCH_LH, MASK_LH)
+DECLARE_INSN(lw, MATCH_LW, MASK_LW)
+DECLARE_INSN(ld, MATCH_LD, MASK_LD)
+DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
+DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
+DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
+DECLARE_INSN(sb, MATCH_SB, MASK_SB)
+DECLARE_INSN(sh, MATCH_SH, MASK_SH)
+DECLARE_INSN(sw, MATCH_SW, MASK_SW)
+DECLARE_INSN(sd, MATCH_SD, MASK_SD)
+DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
+DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
+DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
+DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
+DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
+DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
+DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
+DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
+DECLARE_INSN(rem, MATCH_REM, MASK_REM)
+DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
+DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
+DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
+DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
+DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
+DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
+DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
+DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
+DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
+DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
+DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
+DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
+DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
+DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
+DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
+DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
+DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
+DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
+DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
+DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
+DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
+DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
+DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
+DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
+DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
+DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
+DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
+DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
+DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
+DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
+DECLARE_INSN(uret, MATCH_URET, MASK_URET)
+DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
+DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
+DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
+DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA)
+DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
+DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
+DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
+DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
+DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
+DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
+DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
+DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
+DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
+DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
+DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
+DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
+DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
+DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
+DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
+DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
+DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
+DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
+DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
+DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
+DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
+DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
+DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
+DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
+DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
+DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
+DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
+DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
+DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
+DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q)
+DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q)
+DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q)
+DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q)
+DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q)
+DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q)
+DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q)
+DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q)
+DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q)
+DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q)
+DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S)
+DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q)
+DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D)
+DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q)
+DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
+DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
+DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
+DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
+DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
+DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
+DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q)
+DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q)
+DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q)
+DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
+DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
+DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
+DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
+DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W)
+DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
+DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
+DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
+DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
+DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
+DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
+DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
+DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q)
+DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q)
+DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q)
+DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q)
+DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q)
+DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q)
+DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
+DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
+DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
+DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
+DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X)
+DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
+DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
+DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
+DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
+DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
+DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W)
+DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU)
+DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L)
+DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU)
+DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X)
+DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
+DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
+DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ)
+DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
+DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
+DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ)
+DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
+DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
+DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
+DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
+DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
+DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
+DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
+DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
+DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q)
+DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q)
+DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q)
+DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q)
+DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)
+DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
+DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
+DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
+DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)
+DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
+DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
+DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
+DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
+DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
+DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
+DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
+DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
+DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW)
+DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD)
+DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
+DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW)
+DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
+DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
+DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
+DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
+DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
+DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
+DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI)
+DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
+DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
+DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR)
+DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND)
+DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
+DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
+DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
+DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
+DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
+DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
+DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP)
+DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
+DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP)
+DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
+DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
+DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP)
+DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
+DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP)
+DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
+DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
+DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
+DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
+DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
+DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
+DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
+DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
+DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
+DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
+DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
+DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
+DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
+DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
+DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
+DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
+DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
+DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
+DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
+DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
+DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
+DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
+DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
+DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
+#endif
+#ifdef DECLARE_CSR
+DECLARE_CSR(fflags, CSR_FFLAGS)
+DECLARE_CSR(frm, CSR_FRM)
+DECLARE_CSR(fcsr, CSR_FCSR)
+DECLARE_CSR(cycle, CSR_CYCLE)
+DECLARE_CSR(time, CSR_TIME)
+DECLARE_CSR(instret, CSR_INSTRET)
+DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3)
+DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4)
+DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5)
+DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6)
+DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7)
+DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8)
+DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9)
+DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10)
+DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11)
+DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12)
+DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13)
+DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14)
+DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15)
+DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16)
+DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17)
+DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18)
+DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19)
+DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20)
+DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21)
+DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22)
+DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23)
+DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24)
+DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25)
+DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26)
+DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27)
+DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28)
+DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29)
+DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30)
+DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)
+DECLARE_CSR(sstatus, CSR_SSTATUS)
+DECLARE_CSR(sie, CSR_SIE)
+DECLARE_CSR(stvec, CSR_STVEC)
+DECLARE_CSR(scounteren, CSR_SCOUNTEREN)
+DECLARE_CSR(sscratch, CSR_SSCRATCH)
+DECLARE_CSR(sepc, CSR_SEPC)
+DECLARE_CSR(scause, CSR_SCAUSE)
+DECLARE_CSR(sbadaddr, CSR_SBADADDR)
+DECLARE_CSR(sip, CSR_SIP)
+DECLARE_CSR(sptbr, CSR_SPTBR)
+DECLARE_CSR(mstatus, CSR_MSTATUS)
+DECLARE_CSR(misa, CSR_MISA)
+DECLARE_CSR(medeleg, CSR_MEDELEG)
+DECLARE_CSR(mideleg, CSR_MIDELEG)
+DECLARE_CSR(mie, CSR_MIE)
+DECLARE_CSR(mtvec, CSR_MTVEC)
+DECLARE_CSR(mcounteren, CSR_MCOUNTEREN)
+DECLARE_CSR(mscratch, CSR_MSCRATCH)
+DECLARE_CSR(mepc, CSR_MEPC)
+DECLARE_CSR(mcause, CSR_MCAUSE)
+DECLARE_CSR(mbadaddr, CSR_MBADADDR)
+DECLARE_CSR(mip, CSR_MIP)
+DECLARE_CSR(pmpcfg0, CSR_PMPCFG0)
+DECLARE_CSR(pmpcfg1, CSR_PMPCFG1)
+DECLARE_CSR(pmpcfg2, CSR_PMPCFG2)
+DECLARE_CSR(pmpcfg3, CSR_PMPCFG3)
+DECLARE_CSR(pmpaddr0, CSR_PMPADDR0)
+DECLARE_CSR(pmpaddr1, CSR_PMPADDR1)
+DECLARE_CSR(pmpaddr2, CSR_PMPADDR2)
+DECLARE_CSR(pmpaddr3, CSR_PMPADDR3)
+DECLARE_CSR(pmpaddr4, CSR_PMPADDR4)
+DECLARE_CSR(pmpaddr5, CSR_PMPADDR5)
+DECLARE_CSR(pmpaddr6, CSR_PMPADDR6)
+DECLARE_CSR(pmpaddr7, CSR_PMPADDR7)
+DECLARE_CSR(pmpaddr8, CSR_PMPADDR8)
+DECLARE_CSR(pmpaddr9, CSR_PMPADDR9)
+DECLARE_CSR(pmpaddr10, CSR_PMPADDR10)
+DECLARE_CSR(pmpaddr11, CSR_PMPADDR11)
+DECLARE_CSR(pmpaddr12, CSR_PMPADDR12)
+DECLARE_CSR(pmpaddr13, CSR_PMPADDR13)
+DECLARE_CSR(pmpaddr14, CSR_PMPADDR14)
+DECLARE_CSR(pmpaddr15, CSR_PMPADDR15)
+DECLARE_CSR(tselect, CSR_TSELECT)
+DECLARE_CSR(tdata1, CSR_TDATA1)
+DECLARE_CSR(tdata2, CSR_TDATA2)
+DECLARE_CSR(tdata3, CSR_TDATA3)
+DECLARE_CSR(dcsr, CSR_DCSR)
+DECLARE_CSR(dpc, CSR_DPC)
+DECLARE_CSR(dscratch, CSR_DSCRATCH)
+DECLARE_CSR(mcycle, CSR_MCYCLE)
+DECLARE_CSR(minstret, CSR_MINSTRET)
+DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3)
+DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4)
+DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5)
+DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6)
+DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7)
+DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8)
+DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9)
+DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10)
+DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11)
+DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12)
+DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13)
+DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14)
+DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15)
+DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16)
+DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17)
+DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18)
+DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19)
+DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20)
+DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21)
+DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22)
+DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23)
+DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24)
+DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25)
+DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26)
+DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27)
+DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28)
+DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29)
+DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30)
+DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31)
+DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3)
+DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4)
+DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5)
+DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6)
+DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7)
+DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8)
+DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9)
+DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10)
+DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11)
+DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12)
+DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13)
+DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14)
+DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15)
+DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16)
+DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17)
+DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18)
+DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19)
+DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20)
+DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21)
+DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22)
+DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23)
+DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24)
+DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25)
+DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26)
+DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27)
+DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28)
+DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29)
+DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30)
+DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31)
+DECLARE_CSR(mvendorid, CSR_MVENDORID)
+DECLARE_CSR(marchid, CSR_MARCHID)
+DECLARE_CSR(mimpid, CSR_MIMPID)
+DECLARE_CSR(mhartid, CSR_MHARTID)
+DECLARE_CSR(cycleh, CSR_CYCLEH)
+DECLARE_CSR(timeh, CSR_TIMEH)
+DECLARE_CSR(instreth, CSR_INSTRETH)
+DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H)
+DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H)
+DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H)
+DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H)
+DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H)
+DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H)
+DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H)
+DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H)
+DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H)
+DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H)
+DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H)
+DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H)
+DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H)
+DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H)
+DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H)
+DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H)
+DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H)
+DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H)
+DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H)
+DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H)
+DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H)
+DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H)
+DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H)
+DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H)
+DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H)
+DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H)
+DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
+DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
+DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
+DECLARE_CSR(mcycleh, CSR_MCYCLEH)
+DECLARE_CSR(minstreth, CSR_MINSTRETH)
+DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H)
+DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H)
+DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H)
+DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H)
+DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H)
+DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H)
+DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H)
+DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H)
+DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H)
+DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H)
+DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H)
+DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H)
+DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H)
+DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H)
+DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H)
+DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H)
+DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H)
+DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H)
+DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H)
+DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H)
+DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H)
+DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H)
+DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H)
+DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H)
+DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H)
+DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H)
+DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)
+DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)
+DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)
+#endif
+#ifdef DECLARE_CAUSE
+DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
+DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS)
+DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION)
+DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT)
+DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD)
+DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS)
+DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)
+DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS)
+DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)
+DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)
+DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)
+DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)
+DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT)
+DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT)
+DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT)
+#endif
+
+#include "ycr1_specific.h"
diff --git a/verilog/dv/firmware/riscv_macros.h b/verilog/dv/firmware/riscv_macros.h
new file mode 100644
index 0000000..d4fc8cb
--- /dev/null
+++ b/verilog/dv/firmware/riscv_macros.h
@@ -0,0 +1,835 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021, Dinesh Annayya ////
+// ////
+// Licensed under the Apache License, Version 2.0 (the "License"); ////
+// you may not use this file except in compliance with the License. ////
+// You may obtain a copy of the License at ////
+// ////
+// http://www.apache.org/licenses/LICENSE-2.0 ////
+// ////
+// Unless required by applicable law or agreed to in writing, software ////
+// distributed under the License is distributed on an "AS IS" BASIS, ////
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.///
+// See the License for the specific language governing permissions and ////
+// limitations under the License. ////
+// SPDX-License-Identifier: Apache-2.0 ////
+// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> ////
+//////////////////////////////////////////////////////////////////////////////
+
+#ifndef __RISCV_MACROS_H
+#define __RISCV_MACROS_H
+
+#include "riscv_csr_encoding.h"
+#include "sc_test.h"
+
+//-----------------------------------------------------------------------
+// Begin Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_RV64U \
+ .macro init; \
+ .endm
+
+#define RVTEST_RV64UF \
+ .macro init; \
+ RVTEST_FP_ENABLE; \
+ .endm
+
+#define RVTEST_RV32U \
+ .macro init; \
+ .endm
+
+#define RVTEST_RV32UF \
+ .macro init; \
+ RVTEST_FP_ENABLE; \
+ .endm
+
+#define RVTEST_RV64M \
+ .macro init; \
+ RVTEST_ENABLE_MACHINE; \
+ .endm
+
+#define RVTEST_RV64S \
+ .macro init; \
+ RVTEST_ENABLE_SUPERVISOR; \
+ .endm
+
+#define RVTEST_RV32M \
+ .macro init; \
+ RVTEST_ENABLE_MACHINE; \
+ .endm
+
+#define RVTEST_RV32S \
+ .macro init; \
+ RVTEST_ENABLE_SUPERVISOR; \
+ .endm
+
+#if __riscv_xlen == 64
+# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bgez a0, 1f; RVTEST_PASS; 1:
+#else
+# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1:
+#endif
+
+#define INIT_PMP \
+ la t0, 1f; \
+ csrw mtvec, t0; \
+ li t0, -1; /* Set up a PMP to permit all accesses */ \
+ csrw pmpaddr0, t0; \
+ li t0, PMP_NAPOT | PMP_R | PMP_W | PMP_X; \
+ csrw pmpcfg0, t0; \
+ .balign 4; \
+1:
+
+#define INIT_SPTBR \
+ la t0, 1f; \
+ csrw mtvec, t0; \
+ csrwi sptbr, 0; \
+ .balign 4; \
+1:
+
+#define DELEGATE_NO_TRAPS
+
+#define RVTEST_ENABLE_SUPERVISOR \
+ li a0, MSTATUS_MPP & (MSTATUS_MPP >> 1); \
+ csrs mstatus, a0; \
+ li a0, SIP_SSIP | SIP_STIP; \
+ csrs mideleg, a0; \
+
+#define RVTEST_ENABLE_MACHINE \
+ li a0, MSTATUS_MPP; \
+ csrs mstatus, a0; \
+
+#define RVTEST_FP_ENABLE \
+ li a0, MSTATUS_FS & (MSTATUS_FS >> 1); \
+ csrs mstatus, a0; \
+ csrwi fcsr, 0
+
+#define RISCV_MULTICORE_DISABLE \
+ csrr a0, mhartid; \
+ 1: bnez a0, 1b
+
+#define EXTRA_TVEC_USER
+#define EXTRA_TVEC_SUPERVISOR
+#define EXTRA_TVEC_HYPERVISOR
+#define EXTRA_TVEC_MACHINE
+#define EXTRA_INIT
+#define EXTRA_INIT_TIMER
+
+#define INTERRUPT_HANDLER j other_exception /* No interrupts should occur */
+
+#define RVTEST_CODE_BEGIN \
+ .section .text.init; \
+ .org 0xC0, 0x00; \
+ .balign 64; \
+ .weak stvec_handler; \
+ .weak mtvec_handler; \
+trap_vector: \
+ /* test whether the test came from pass/fail */ \
+ csrr a4, mcause; \
+ li a5, CAUSE_USER_ECALL; \
+ beq a4, a5, _report; \
+ li a5, CAUSE_SUPERVISOR_ECALL; \
+ beq a4, a5, _report; \
+ li a5, CAUSE_MACHINE_ECALL; \
+ beq a4, a5, _report; \
+ /* if an mtvec_handler is defined, jump to it */ \
+ la a4, mtvec_handler; \
+ beqz a4, 1f; \
+ jr a4; \
+ /* was it an interrupt or an exception? */ \
+1: csrr a4, mcause; \
+ bgez a4, handle_exception; \
+ INTERRUPT_HANDLER; \
+handle_exception: \
+ /* we don't know how to handle whatever the exception was */ \
+other_exception: \
+ /* some unhandlable exception occurred */ \
+ li a0, 0x1; \
+_report: \
+ j sc_exit; \
+ .balign 64; \
+ .globl _start; \
+_start: \
+ RISCV_MULTICORE_DISABLE; \
+ /*INIT_SPTBR;*/ \
+ /*INIT_PMP;*/ \
+ DELEGATE_NO_TRAPS; \
+ li TESTNUM, 0; \
+ la t0, trap_vector; \
+ csrw mtvec, t0; \
+ CHECK_XLEN; \
+ /* if an stvec_handler is defined, delegate exceptions to it */ \
+ la t0, stvec_handler; \
+ beqz t0, 1f; \
+ csrw stvec, t0; \
+ li t0, (1 << CAUSE_LOAD_PAGE_FAULT) | \
+ (1 << CAUSE_STORE_PAGE_FAULT) | \
+ (1 << CAUSE_FETCH_PAGE_FAULT) | \
+ (1 << CAUSE_MISALIGNED_FETCH) | \
+ (1 << CAUSE_USER_ECALL) | \
+ (1 << CAUSE_BREAKPOINT); \
+ csrw medeleg, t0; \
+ csrr t1, medeleg; \
+ bne t0, t1, other_exception; \
+1: csrwi mstatus, 0; \
+ init; \
+ EXTRA_INIT; \
+ EXTRA_INIT_TIMER; \
+ la t0, _run_test; \
+ csrw mepc, t0; \
+ csrr a0, mhartid; \
+ mret; \
+ .section .text; \
+_run_test:
+
+//-----------------------------------------------------------------------
+// End Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_CODE_END ecall: ecall
+
+//-----------------------------------------------------------------------
+// Pass/Fail Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_PASS \
+ fence; \
+ mv a1, TESTNUM; \
+ li a0, 0x0; \
+ ecall
+
+#define TESTNUM x28
+#define RVTEST_FAIL \
+ fence; \
+ mv a1, TESTNUM; \
+ li a0, 0x1; \
+ ecall
+
+//-----------------------------------------------------------------------
+// Data Section Macro
+//-----------------------------------------------------------------------
+
+#define EXTRA_DATA
+
+#define RVTEST_DATA_BEGIN \
+ EXTRA_DATA \
+ .pushsection .tohost,"aw",@progbits; \
+ .balign 64; .global tohost; tohost: .dword 0; \
+ .balign 64; .global fromhost; fromhost: .dword 0; \
+ .popsection; \
+ .balign 16; \
+ .global begin_regstate; begin_regstate: .dword 0; .dword 0; .dword 0; \
+ .balign 16; \
+ .global begin_signature; begin_signature:
+
+#define RVTEST_DATA_END .balign 16; .global end_signature; end_signature:
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+
+#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1))
+
+#define TEST_CASE( testnum, testreg, correctval, code... ) \
+test_ ## testnum: \
+ code; \
+ li x29, MASK_XLEN(correctval); \
+ li TESTNUM, testnum; \
+ bne testreg, x29, fail;
+
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+
+#define TEST_INSERT_NOPS_0
+#define TEST_INSERT_NOPS_1 nop; TEST_INSERT_NOPS_0
+#define TEST_INSERT_NOPS_2 nop; TEST_INSERT_NOPS_1
+#define TEST_INSERT_NOPS_3 nop; TEST_INSERT_NOPS_2
+#define TEST_INSERT_NOPS_4 nop; TEST_INSERT_NOPS_3
+#define TEST_INSERT_NOPS_5 nop; TEST_INSERT_NOPS_4
+#define TEST_INSERT_NOPS_6 nop; TEST_INSERT_NOPS_5
+#define TEST_INSERT_NOPS_7 nop; TEST_INSERT_NOPS_6
+#define TEST_INSERT_NOPS_8 nop; TEST_INSERT_NOPS_7
+#define TEST_INSERT_NOPS_9 nop; TEST_INSERT_NOPS_8
+#define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9
+
+
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+
+#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
+
+#define TEST_IMM_OP( testnum, inst, result, val1, imm ) \
+ TEST_CASE( testnum, x3, result, \
+ li x1, MASK_XLEN(val1); \
+ inst x3, x1, SEXT_IMM(imm); \
+ )
+
+#define TEST_IMM_OP_RVC( testnum, inst, result, val1, imm ) \
+ TEST_CASE( testnum, x1, result, \
+ li x1, val1; \
+ inst x1, imm; \
+ )
+
+#define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \
+ TEST_CASE( testnum, x1, result, \
+ li x1, MASK_XLEN(val1); \
+ inst x1, x1, SEXT_IMM(imm); \
+ )
+
+#define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
+ TEST_CASE( testnum, x6, result, \
+ li x4, 0; \
+1: li x1, MASK_XLEN(val1); \
+ inst x3, x1, SEXT_IMM(imm); \
+ TEST_INSERT_NOPS_ ## nop_cycles \
+ addi x6, x3, 0; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+ )
+
+#define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
+ TEST_CASE( testnum, x3, result, \
+ li x4, 0; \
+1: li x1, MASK_XLEN(val1); \
+ TEST_INSERT_NOPS_ ## nop_cycles \
+ inst x3, x1, SEXT_IMM(imm); \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+ )
+
+#define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \
+ TEST_CASE( testnum, x1, result, \
+ inst x1, x0, SEXT_IMM(imm); \
+ )
+
+#define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \
+ TEST_CASE( testnum, x0, 0, \
+ li x1, MASK_XLEN(val1); \
+ inst x0, x1, SEXT_IMM(imm); \
+ )
+
+#-----------------------------------------------------------------------
+# Tests for vector config instructions
+#-----------------------------------------------------------------------
+
+#define TEST_VSETCFGIVL( testnum, nxpr, nfpr, bank, vl, result ) \
+ TEST_CASE( testnum, x1, result, \
+ li x1, (bank << 12); \
+ vsetcfg x1,nxpr,nfpr; \
+ li x1, vl; \
+ vsetvl x1,x1; \
+ )
+
+#define TEST_VVCFG( testnum, nxpr, nfpr, bank, vl, result ) \
+ TEST_CASE( testnum, x1, result, \
+ li x1, (bank << 12) | (nfpr << 6) | nxpr; \
+ vsetcfg x1; \
+ li x1, vl; \
+ vsetvl x1,x1; \
+ )
+
+#define TEST_VSETVL( testnum, nxpr, nfpr, bank, vl, result ) \
+ TEST_CASE( testnum, x1, result, \
+ li x1, (bank << 12); \
+ vsetcfg x1,nxpr,nfpr; \
+ li x1, vl; \
+ vsetvl x1, x1; \
+ )
+
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+
+#define TEST_R_OP( testnum, inst, result, val1 ) \
+ TEST_CASE( testnum, x3, result, \
+ li x1, val1; \
+ inst x3, x1; \
+ )
+
+#define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \
+ TEST_CASE( testnum, x1, result, \
+ li x1, val1; \
+ inst x1, x1; \
+ )
+
+#define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \
+ TEST_CASE( testnum, x6, result, \
+ li x4, 0; \
+1: li x1, val1; \
+ inst x3, x1; \
+ TEST_INSERT_NOPS_ ## nop_cycles \
+ addi x6, x3, 0; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+ )
+
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+
+#define TEST_RR_OP( testnum, inst, result, val1, val2 ) \
+ TEST_CASE( testnum, x3, result, \
+ li x1, MASK_XLEN(val1); \
+ li x2, MASK_XLEN(val2); \
+ inst x3, x1, x2; \
+ )
+
+#define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \
+ TEST_CASE( testnum, x1, result, \
+ li x1, MASK_XLEN(val1); \
+ li x2, MASK_XLEN(val2); \
+ inst x1, x1, x2; \
+ )
+
+#define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \
+ TEST_CASE( testnum, x2, result, \
+ li x1, MASK_XLEN(val1); \
+ li x2, MASK_XLEN(val2); \
+ inst x2, x1, x2; \
+ )
+
+#define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \
+ TEST_CASE( testnum, x1, result, \
+ li x1, MASK_XLEN(val1); \
+ inst x1, x1, x1; \
+ )
+
+#define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \
+ TEST_CASE( testnum, x6, result, \
+ li x4, 0; \
+1: li x1, MASK_XLEN(val1); \
+ li x2, MASK_XLEN(val2); \
+ inst x3, x1, x2; \
+ TEST_INSERT_NOPS_ ## nop_cycles \
+ addi x6, x3, 0; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+ )
+
+#define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
+ TEST_CASE( testnum, x3, result, \
+ li x4, 0; \
+1: li x1, MASK_XLEN(val1); \
+ TEST_INSERT_NOPS_ ## src1_nops \
+ li x2, MASK_XLEN(val2); \
+ TEST_INSERT_NOPS_ ## src2_nops \
+ inst x3, x1, x2; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+ )
+
+#define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
+ TEST_CASE( testnum, x3, result, \
+ li x4, 0; \
+1: li x2, MASK_XLEN(val2); \
+ TEST_INSERT_NOPS_ ## src1_nops \
+ li x1, MASK_XLEN(val1); \
+ TEST_INSERT_NOPS_ ## src2_nops \
+ inst x3, x1, x2; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+ )
+
+#define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \
+ TEST_CASE( testnum, x2, result, \
+ li x1, MASK_XLEN(val); \
+ inst x2, x0, x1; \
+ )
+
+#define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \
+ TEST_CASE( testnum, x2, result, \
+ li x1, MASK_XLEN(val); \
+ inst x2, x1, x0; \
+ )
+
+#define TEST_RR_ZEROSRC12( testnum, inst, result ) \
+ TEST_CASE( testnum, x1, result, \
+ inst x1, x0, x0; \
+ )
+
+#define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \
+ TEST_CASE( testnum, x0, 0, \
+ li x1, MASK_XLEN(val1); \
+ li x2, MASK_XLEN(val2); \
+ inst x0, x1, x2; \
+ )
+
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+
+#define TEST_LD_OP( testnum, inst, result, offset, base ) \
+ TEST_CASE( testnum, x3, result, \
+ la x1, base; \
+ inst x3, offset(x1); \
+ )
+
+#define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \
+ TEST_CASE( testnum, x3, result, \
+ la x1, base; \
+ li x2, result; \
+ store_inst x2, offset(x1); \
+ load_inst x3, offset(x1); \
+ )
+
+#define TEST_LD_DEST_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ li x4, 0; \
+1: la x1, base; \
+ inst x3, offset(x1); \
+ TEST_INSERT_NOPS_ ## nop_cycles \
+ addi x6, x3, 0; \
+ li x29, result; \
+ bne x6, x29, fail; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b; \
+
+#define TEST_LD_SRC1_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ li x4, 0; \
+1: la x1, base; \
+ TEST_INSERT_NOPS_ ## nop_cycles \
+ inst x3, offset(x1); \
+ li x29, result; \
+ bne x3, x29, fail; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+
+#define TEST_ST_SRC12_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ li x4, 0; \
+1: li x1, result; \
+ TEST_INSERT_NOPS_ ## src1_nops \
+ la x2, base; \
+ TEST_INSERT_NOPS_ ## src2_nops \
+ store_inst x1, offset(x2); \
+ load_inst x3, offset(x2); \
+ li x29, result; \
+ bne x3, x29, fail; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+
+#define TEST_ST_SRC21_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ li x4, 0; \
+1: la x2, base; \
+ TEST_INSERT_NOPS_ ## src1_nops \
+ li x1, result; \
+ TEST_INSERT_NOPS_ ## src2_nops \
+ store_inst x1, offset(x2); \
+ load_inst x3, offset(x2); \
+ li x29, result; \
+ bne x3, x29, fail; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+
+#-----------------------------------------------------------------------
+# Test branch instructions
+#-----------------------------------------------------------------------
+
+#define TEST_BR1_OP_TAKEN( testnum, inst, val1 ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ li x1, val1; \
+ inst x1, 2f; \
+ bne x0, TESTNUM, fail; \
+1: bne x0, TESTNUM, 3f; \
+2: inst x1, 1b; \
+ bne x0, TESTNUM, fail; \
+3:
+
+#define TEST_BR1_OP_NOTTAKEN( testnum, inst, val1 ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ li x1, val1; \
+ inst x1, 1f; \
+ bne x0, TESTNUM, 2f; \
+1: bne x0, TESTNUM, fail; \
+2: inst x1, 1b; \
+3:
+
+#define TEST_BR1_SRC1_BYPASS( testnum, nop_cycles, inst, val1 ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ li x4, 0; \
+1: li x1, val1; \
+ TEST_INSERT_NOPS_ ## nop_cycles \
+ inst x1, fail; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+
+#define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2 ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ li x1, val1; \
+ li x2, val2; \
+ inst x1, x2, 2f; \
+ bne x0, TESTNUM, fail; \
+1: bne x0, TESTNUM, 3f; \
+2: inst x1, x2, 1b; \
+ bne x0, TESTNUM, fail; \
+3:
+
+#define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ li x1, val1; \
+ li x2, val2; \
+ inst x1, x2, 1f; \
+ bne x0, TESTNUM, 2f; \
+1: bne x0, TESTNUM, fail; \
+2: inst x1, x2, 1b; \
+3:
+
+#define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ li x4, 0; \
+1: li x1, val1; \
+ TEST_INSERT_NOPS_ ## src1_nops \
+ li x2, val2; \
+ TEST_INSERT_NOPS_ ## src2_nops \
+ inst x1, x2, fail; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+
+#define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ li x4, 0; \
+1: li x2, val2; \
+ TEST_INSERT_NOPS_ ## src1_nops \
+ li x1, val1; \
+ TEST_INSERT_NOPS_ ## src2_nops \
+ inst x1, x2, fail; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+
+#define TEST_JR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ li x4, 0; \
+1: la x6, 2f; \
+ TEST_INSERT_NOPS_ ## nop_cycles \
+ inst x6; \
+ bne x0, TESTNUM, fail; \
+2: addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+
+#define TEST_JALR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ li x4, 0; \
+1: la x6, 2f; \
+ TEST_INSERT_NOPS_ ## nop_cycles \
+ inst x19, x6, 0; \
+ bne x0, TESTNUM, fail; \
+2: addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+
+
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+
+#define qNaNf 0f:7fc00000
+#define sNaNf 0f:7f800001
+#define qNaN 0d:7ff8000000000000
+#define sNaN 0d:7ff0000000000001
+
+#define TEST_FP_OP_S_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ la a0, test_ ## testnum ## _data ;\
+ flw f0, 0(a0); \
+ flw f1, 4(a0); \
+ flw f2, 8(a0); \
+ lw a3, 12(a0); \
+ code; \
+ fsflags a1, x0; \
+ li a2, flags; \
+ bne a0, a3, fail; \
+ bne a1, a2, fail; \
+ j 2f; \
+ .balign 4; \
+ .data; \
+ test_ ## testnum ## _data: \
+ .float val1; \
+ .float val2; \
+ .float val3; \
+ .result; \
+ .text; \
+2:
+
+#define TEST_FP_OP_D_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ la a0, test_ ## testnum ## _data ;\
+ fld f0, 0(a0); \
+ fld f1, 8(a0); \
+ fld f2, 16(a0); \
+ ld a3, 24(a0); \
+ code; \
+ fsflags a1, x0; \
+ li a2, flags; \
+ bne a0, a3, fail; \
+ bne a1, a2, fail; \
+ j 2f; \
+ .data; \
+ .balign 8; \
+ test_ ## testnum ## _data: \
+ .double val1; \
+ .double val2; \
+ .double val3; \
+ .result; \
+ .text; \
+2:
+
+#define TEST_FCVT_S_D( testnum, result, val1 ) \
+ TEST_FP_OP_D_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \
+ fcvt.s.d f3, f0; fcvt.d.s f3, f3; fmv.x.d a0, f3)
+
+#define TEST_FCVT_D_S( testnum, result, val1 ) \
+ TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \
+ fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3)
+
+#define TEST_FP_OP1_S( testnum, inst, flags, result, val1 ) \
+ TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, 0.0, 0.0, \
+ inst f3, f0; fmv.x.s a0, f3)
+
+#define TEST_FP_OP1_D( testnum, inst, flags, result, val1 ) \
+ TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \
+ inst f3, f0; fmv.x.d a0, f3)
+
+#define TEST_FP_OP1_S_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
+ TEST_FP_OP_S_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
+ inst f3, f0; fmv.x.s a0, f3)
+
+#define TEST_FP_OP1_D_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
+ TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
+ inst f3, f0; fmv.x.d a0, f3)
+
+#define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \
+ TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, 0.0, \
+ inst f3, f0, f1; fmv.x.s a0, f3)
+
+#define TEST_FP_OP2_D( testnum, inst, flags, result, val1, val2 ) \
+ TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \
+ inst f3, f0, f1; fmv.x.d a0, f3)
+
+#define TEST_FP_OP3_S( testnum, inst, flags, result, val1, val2, val3 ) \
+ TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, val3, \
+ inst f3, f0, f1, f2; fmv.x.s a0, f3)
+
+#define TEST_FP_OP3_D( testnum, inst, flags, result, val1, val2, val3 ) \
+ TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, val3, \
+ inst f3, f0, f1, f2; fmv.x.d a0, f3)
+
+#define TEST_FP_INT_OP_S( testnum, inst, flags, result, val1, rm ) \
+ TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \
+ inst a0, f0, rm)
+
+#define TEST_FP_INT_OP_D( testnum, inst, flags, result, val1, rm ) \
+ TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
+ inst a0, f0, rm)
+
+#define TEST_FP_CMP_OP_S( testnum, inst, flags, result, val1, val2 ) \
+ TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, val2, 0.0, \
+ inst a0, f0, f1)
+
+#define TEST_FP_CMP_OP_D( testnum, inst, flags, result, val1, val2 ) \
+ TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \
+ inst a0, f0, f1)
+
+#define TEST_FCLASS_S(testnum, correct, input) \
+ TEST_CASE(testnum, a0, correct, li a0, input; fmv.s.x fa0, a0; \
+ fclass.s a0, fa0)
+
+#define TEST_FCLASS_D(testnum, correct, input) \
+ TEST_CASE(testnum, a0, correct, li a0, input; fmv.d.x fa0, a0; \
+ fclass.d a0, fa0)
+
+#define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ la a0, test_ ## testnum ## _data ;\
+ lw a3, 0(a0); \
+ li a0, val1; \
+ inst f0, a0; \
+ fsflags x0; \
+ fmv.x.s a0, f0; \
+ bne a0, a3, fail; \
+ j 1f; \
+ .balign 4; \
+ test_ ## testnum ## _data: \
+ .float result; \
+1:
+
+#define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ la a0, test_ ## testnum ## _data ;\
+ ld a3, 0(a0); \
+ li a0, val1; \
+ inst f0, a0; \
+ fsflags x0; \
+ fmv.x.d a0, f0; \
+ bne a0, a3, fail; \
+ j 1f; \
+ .balign 8; \
+ test_ ## testnum ## _data: \
+ .double result; \
+1:
+
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in TESTNUM)
+#-----------------------------------------------------------------------
+
+#define TEST_PASSFAIL \
+ bne x0, TESTNUM, pass; \
+fail: \
+ RVTEST_FAIL; \
+pass: \
+ RVTEST_PASS \
+
+
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+
+#define TEST_DATA
+
+#endif
+
diff --git a/verilog/dv/firmware/sc_print.c b/verilog/dv/firmware/sc_print.c
new file mode 100644
index 0000000..b736d42
--- /dev/null
+++ b/verilog/dv/firmware/sc_print.c
@@ -0,0 +1,296 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021, Dinesh Annayya ////
+// ////
+// Licensed under the Apache License, Version 2.0 (the "License"); ////
+// you may not use this file except in compliance with the License. ////
+// You may obtain a copy of the License at ////
+// ////
+// http://www.apache.org/licenses/LICENSE-2.0 ////
+// ////
+// Unless required by applicable law or agreed to in writing, software ////
+// distributed under the License is distributed on an "AS IS" BASIS, ////
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.///
+// See the License for the specific language governing permissions and ////
+// limitations under the License. ////
+// SPDX-License-Identifier: Apache-2.0 ////
+// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> ////
+//////////////////////////////////////////////////////////////////////////////
+
+#include <string.h>
+#include <stdarg.h>
+#include "sc_print.h"
+
+#define SC_SIM_OUTPORT (0xf0000000)
+#define CHAR_BIT (8)
+
+static void
+sc_puts(long str, long strlen) {
+ volatile char *out_ptr = (volatile char*)SC_SIM_OUTPORT;
+ const char *in_ptr = (const char*)str;
+ for (long len = strlen; len > 0; --len)
+ *out_ptr = *in_ptr++;
+}
+
+#undef putchar
+int
+putchar(int ch) {
+ static __thread char buf[64] __attribute__((aligned(64)));
+ static __thread int buflen = 0;
+
+ buf[buflen++] = ch;
+
+ if ( ch == '\n' || buflen == sizeof(buf) ) {
+ sc_puts((long)buf, buflen);
+ buflen = 0;
+ }
+
+ return 0;
+}
+
+static void
+printf_putch(int ch, void** data)
+{
+ putchar(ch);
+}
+
+static void
+print(const char *str)
+{
+ sc_puts((long)str, strlen(str));
+}
+
+
+static long long
+getint(va_list *ap, int lflag)
+{
+ if ( lflag >= 2 )
+ return va_arg(*ap, long long);
+ else if ( lflag )
+ return va_arg(*ap, long);
+ else
+ return va_arg(*ap, int);
+}
+
+
+static unsigned long long
+getuint(va_list *ap, int lflag)
+{
+ if ( lflag >= 2 )
+ return va_arg(*ap, unsigned long long);
+ else if ( lflag )
+ return va_arg(*ap, unsigned long);
+ else
+ return va_arg(*ap, unsigned int);
+}
+
+static inline void
+printnum(void(*putch)(int, void**),
+void **putdat,
+unsigned long long num,
+unsigned base,
+int width,
+int padc,
+int hex_A)
+{
+ unsigned digs[sizeof(num) * CHAR_BIT];
+ int pos = 0;
+
+ for ( ;; ) {
+ digs[pos++] = num % base;
+ if ( num < base )
+ break;
+ num /= base;
+ }
+
+ while ( width-- > pos )
+ putch(padc, putdat);
+
+ while ( pos-- > 0 )
+ putch(digs[pos] + (digs[pos] >= 10 ? hex_A - 10 : '0'), putdat);
+}
+
+static void
+vprintfmt(void(*putch)(int, void**), void **putdat, const char *fmt, va_list ap)
+{
+ register const char* p;
+ const char* last_fmt;
+ register int ch;
+ int err;
+ unsigned long long num;
+ int base;
+ int lflag;
+ int width;
+ int precision;
+ int altflag;
+ char padc;
+ int hex_A = 'a';
+ for ( ;; ) {
+ while ( (ch = *(unsigned char *)fmt) != '%' ) {
+ if ( ch == '\0' )
+ return;
+ ++fmt;
+ putch(ch, putdat);
+ }
+ ++fmt;
+
+ // Process a %-escape sequence
+ last_fmt = fmt;
+ padc = ' ';
+ width = -1;
+ precision = -1;
+ lflag = 0;
+ altflag = 0;
+
+reswitch:
+ switch ( ch = *(unsigned char *)fmt++ ) {
+ // flag to pad on the right
+ case '-':
+ padc = '-';
+ goto reswitch;
+
+ // flag to pad with 0's instead of spaces
+ case '0':
+ padc = '0';
+ goto reswitch;
+
+ // width field
+ case '1':
+ case '2':
+ case '3':
+ case '4':
+ case '5':
+ case '6':
+ case '7':
+ case '8':
+ case '9':
+ for ( precision = 0;; ++fmt ) {
+ precision = precision * 10 + ch - '0';
+ ch = *fmt;
+ if ( ch < '0' || ch > '9' )
+ break;
+ }
+ goto process_precision;
+
+ case '*':
+ precision = va_arg(ap, int);
+ goto process_precision;
+
+ case '.':
+ if ( width < 0 )
+ width = 0;
+ goto reswitch;
+
+ case '#':
+ altflag = 1;
+ goto reswitch;
+
+process_precision:
+ if ( width < 0 ) {
+ width = precision;
+ precision = -1;
+ }
+ goto reswitch;
+
+ // long flag (doubled for long long)
+ case 'l':
+ lflag++;
+ goto reswitch;
+
+ // character
+ case 'c':
+ putch(va_arg(ap, int), putdat);
+ break;
+
+ // string
+ case 's':
+ if ( (p = va_arg(ap, char *)) == NULL )
+ p = "(null)";
+ if ( width > 0 && padc != '-' )
+ for ( width -= strnlen(p, precision); width > 0; width-- )
+ putch(padc, putdat);
+ for ( ; (ch = *p) != '\0' && (precision < 0 || --precision >= 0); width-- ) {
+ putch(ch, putdat);
+ p++;
+ }
+ for ( ; width > 0; width-- )
+ putch(' ', putdat);
+ break;
+
+ // (signed) decimal
+ case 'd':
+ num = getint(&ap, lflag);
+ if ( (long long)num < 0 ) {
+ putch('-', putdat);
+ num = -(long long)num;
+ }
+ base = 10;
+ goto signed_number;
+
+ case 'f':
+ {
+ // #ifndef nopfloat
+ // double num = getdouble(&ap, lflag);
+ // printdoubleF(putch, putdat, num, width, precision, padc);
+ // #endif
+ }
+ break;
+
+ // unsigned decimal
+ case 'u':
+ base = 10;
+ goto unsigned_number;
+
+ // (unsigned) octal
+ case 'o':
+ // should do something with padding so it's always 3 octits
+ base = 8;
+ goto unsigned_number;
+
+ // pointer
+ case 'p':
+ // static_assert(sizeof(long) == sizeof(void*));
+ lflag = 1;
+ putch('0', putdat);
+ putch('x', putdat);
+ /* fall through to 'x' */
+
+ // (unsigned) hexadecimal
+ case 'x':
+ hex_A = 'a';
+ base = 16;
+ goto unsigned_number;
+
+ case 'X':
+ hex_A = 'A';
+ base = 16;
+unsigned_number:
+ num = getuint(&ap, lflag);
+signed_number:
+ printnum(putch, putdat, num, base, width, padc, hex_A);
+ break;
+
+ // escaped '%' character
+ case '%':
+ putch(ch, putdat);
+ break;
+
+ // unrecognized escape sequence - just print it literally
+ default:
+ putch('%', putdat);
+ fmt = last_fmt;
+ break;
+ }
+ }
+}
+
+int
+sc_printf(const char* fmt, ...)
+{
+ va_list ap;
+ va_start(ap, fmt);
+
+ vprintfmt(printf_putch, NULL, fmt, ap);
+
+ va_end(ap);
+ return 0; // incorrect return value, but who cares, anyway?
+}
diff --git a/verilog/dv/firmware/sc_print.h b/verilog/dv/firmware/sc_print.h
new file mode 100644
index 0000000..fad6b61
--- /dev/null
+++ b/verilog/dv/firmware/sc_print.h
@@ -0,0 +1,24 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021, Dinesh Annayya ////
+// ////
+// Licensed under the Apache License, Version 2.0 (the "License"); ////
+// you may not use this file except in compliance with the License. ////
+// You may obtain a copy of the License at ////
+// ////
+// http://www.apache.org/licenses/LICENSE-2.0 ////
+// ////
+// Unless required by applicable law or agreed to in writing, software ////
+// distributed under the License is distributed on an "AS IS" BASIS, ////
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.///
+// See the License for the specific language governing permissions and ////
+// limitations under the License. ////
+// SPDX-License-Identifier: Apache-2.0 ////
+// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> ////
+//////////////////////////////////////////////////////////////////////////////
+
+#ifndef SC_PRINT_H
+#define SC_PRINT_H
+
+extern int sc_printf(const char* fmt, ...);
+
+#endif // SC_PRINT_H
diff --git a/verilog/dv/firmware/sc_test.h b/verilog/dv/firmware/sc_test.h
new file mode 100644
index 0000000..6b6448a
--- /dev/null
+++ b/verilog/dv/firmware/sc_test.h
@@ -0,0 +1,62 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021, Dinesh Annayya ////
+// ////
+// Licensed under the Apache License, Version 2.0 (the "License"); ////
+// you may not use this file except in compliance with the License. ////
+// You may obtain a copy of the License at ////
+// ////
+// http://www.apache.org/licenses/LICENSE-2.0 ////
+// ////
+// Unless required by applicable law or agreed to in writing, software ////
+// distributed under the License is distributed on an "AS IS" BASIS, ////
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.///
+// See the License for the specific language governing permissions and ////
+// limitations under the License. ////
+// SPDX-License-Identifier: Apache-2.0 ////
+// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> ////
+//////////////////////////////////////////////////////////////////////////////
+
+#ifndef SC_TEST_H
+#define SC_TEST_H
+
+#if defined(__ASSEMBLER__)
+.altmacro
+
+.macro zero_int_reg regn
+mv x\regn, zero
+.endm
+
+.macro zero_int_regs reg_first, reg_last
+.set regn, \reg_first
+.rept \reg_last - \reg_first + 1
+zero_int_reg %(regn)
+.set regn, regn+1
+.endr
+.endm
+
+#define report_results(result) \
+li a0, result; \
+la t0, sc_exit; \
+jr t0;
+
+.pushsection sc_test_section, "ax"
+sc_exit: la t0, SIM_EXIT; jr t0;
+.balign 32
+.popsection
+#define sc_pass report_results(0x0)
+#define sc_fail report_results(0x1)
+
+#else
+
+extern void sc_exit(unsigned result, unsigned res0, unsigned res1, unsigned res2, unsigned res3)
+ __attribute__ ((noinline, noreturn));
+
+static inline void __attribute__ ((noreturn))
+report_results(unsigned result, unsigned res0, unsigned res1, unsigned res2, unsigned res3)
+{
+ sc_exit(result, res0, res1, res2, res3);
+}
+
+#endif
+
+#endif // SC_TEST_H
diff --git a/verilog/dv/firmware/ycr1_specific.h b/verilog/dv/firmware/ycr1_specific.h
new file mode 100644
index 0000000..0f8d70f
--- /dev/null
+++ b/verilog/dv/firmware/ycr1_specific.h
@@ -0,0 +1,38 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021, Dinesh Annayya ////
+// ////
+// Licensed under the Apache License, Version 2.0 (the "License"); ////
+// you may not use this file except in compliance with the License. ////
+// You may obtain a copy of the License at ////
+// ////
+// http://www.apache.org/licenses/LICENSE-2.0 ////
+// ////
+// Unless required by applicable law or agreed to in writing, software ////
+// distributed under the License is distributed on an "AS IS" BASIS, ////
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.///
+// See the License for the specific language governing permissions and ////
+// limitations under the License. ////
+// SPDX-License-Identifier: Apache-2.0 ////
+// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> ////
+//////////////////////////////////////////////////////////////////////////////
+
+#ifndef __YCR1__SPECIFIC
+#define __YCR1__SPECIFIC
+
+#define mcounten 0x7E0
+
+// Memory-mapped registers
+#define mtime_ctrl 0x00490000
+#define mtime_div 0x00490004
+#define mtime 0x00490008
+#define mtimeh 0x0049000C
+#define mtimecmp 0x00490010
+#define mtimecmph 0x00490014
+
+#define YCR1_MTIME_CTRL_EN 0
+#define YCR1_MTIME_CTRL_CLKSRC 1
+
+#define YCR1_MTIME_CTRL_WR_MASK 0x3
+#define YCR1_MTIME_DIV_WR_MASK 0x3FF
+
+#endif // _YCR1__SPECIFIC
diff --git a/verilog/dv/risc_boot/Makefile b/verilog/dv/risc_boot/Makefile
index da3fb1e..5b1146a 100644
--- a/verilog/dv/risc_boot/Makefile
+++ b/verilog/dv/risc_boot/Makefile
@@ -30,14 +30,14 @@
UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include
-## SYNTACORE FIRMWARE
-SYNTACORE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/rtl/syntacore/scr1/sim/tests/common
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware
## RISCV GCC
GCC_PATH?=/ef/apps/bin
GCC_PREFIX?=riscv32-unknown-elf
@@ -59,9 +59,9 @@
vvp: ${PATTERN:=.vvp}
%.vvp: %_tb.v %.hex
- ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(SYNTACORE_FIRMWARE_PATH) user_uart.c -o user_uart.o
- ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(SYNTACORE_FIRMWARE_PATH) $(SYNTACORE_FIRMWARE_PATH)/crt_tcm.S -o crt_tcm.o
- ${GCC64_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -T $(SYNTACORE_FIRMWARE_PATH)/link_tcm.ld user_uart.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -o user_uart.elf -N
+ ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_uart.c -o user_uart.o
+ ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt_tcm.S -o crt_tcm.o
+ ${GCC64_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -T $(YIFIVE_FIRMWARE_PATH)/link_tcm.ld user_uart.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -o user_uart.elf -N
${GCC64_PREFIX}-objcopy -O verilog user_uart.elf user_uart.hex
${GCC64_PREFIX}-objdump -D user_uart.elf > user_uart.dump
rm crt_tcm.o user_uart.o
diff --git a/verilog/dv/riscv_regress/Makefile b/verilog/dv/riscv_regress/Makefile
index 489b40e..8687043 100644
--- a/verilog/dv/riscv_regress/Makefile
+++ b/verilog/dv/riscv_regress/Makefile
@@ -133,7 +133,7 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = $(root_dir)/../model
UPRJ_BEHAVIOURAL_AGENTS = $(root_dir)/../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
@@ -143,9 +143,9 @@
top_module = user_risc_regress_tb
# TB Paths
-export sim_dir := $(UPRJ_RTL_PATH)/syntacore/scr1/sim
+export sim_dir := $(UPRJ_TESTS_PATH)
export tst_dir := $(sim_dir)/tests
-export inc_dir := $(tst_dir)/common
+export inc_dir := $(UPRJ_VERILOG_PATH)/dv/firmware
test_results := $(bld_dir)/test_results.txt
test_info := $(bld_dir)/test_info
@@ -174,14 +174,14 @@
ifeq (,$(findstring e,$(ARCH_lowercase)))
# These tests cannot be compiled for RVE
# Comment this target if you don't want to run the riscv_isa
- #TARGETS += riscv_isa
+ TARGETS += riscv_isa
# Comment this target if you don't want to run the riscv_compliance
#TARGETS += riscv_compliance
endif
# Comment this target if you don't want to run the isr_sample
-TARGETS += isr_sample
+#TARGETS += isr_sample
# Comment this target if you don't want to run the coremark
#TARGETS += coremark
@@ -190,7 +190,7 @@
#TARGETS += dhrystone21
# Comment this target if you don't want to run the hello test
-TARGETS += hello
+#TARGETS += hello
# Targets
diff --git a/verilog/dv/riscv_regress/tests/benchmarks/coremark/Makefile b/verilog/dv/riscv_regress/tests/benchmarks/coremark/Makefile
new file mode 100644
index 0000000..e60623b
--- /dev/null
+++ b/verilog/dv/riscv_regress/tests/benchmarks/coremark/Makefile
@@ -0,0 +1,26 @@
+src_dir := $(dir $(lastword $(MAKEFILE_LIST)))
+depend_dir := $(src_dir)/../../../dependencies/coremark
+
+ifeq ("$(ITERATIONS)","")
+ITERATIONS=1
+endif
+
+ADD_CFLAGS += -DITERATIONS=$(ITERATIONS)
+ADD_VPATH := $(depend_dir)
+ADD_incs := -I$(src_dir)/src -I$(depend_dir)
+
+c_src := core_portme.c sc_print.c
+coremark_src := ./src/core_list_join.c ./src/core_matrix.c ./src/core_main.c ./src/core_util.c ./src/core_state.c
+c_src += core_list_join.c core_matrix.c core_main.c core_util.c core_state.c
+
+include $(inc_dir)/common.mk
+
+
+default: log_requested_tgt $(bld_dir)/coremark.elf $(bld_dir)/coremark.hex $(bld_dir)/coremark.dump
+
+log_requested_tgt:
+ echo coremark.hex>> $(bld_dir)/test_info
+ echo $(inc_dir)/common.mk
+
+clean:
+ $(RM) $(c_objs) $(asm_objs) $(bld_dir)/coremark.hex $(bld_dir)/coremark.dump
diff --git a/verilog/dv/riscv_regress/tests/benchmarks/coremark/core_portme.c b/verilog/dv/riscv_regress/tests/benchmarks/coremark/core_portme.c
new file mode 100644
index 0000000..3c801f7
--- /dev/null
+++ b/verilog/dv/riscv_regress/tests/benchmarks/coremark/core_portme.c
@@ -0,0 +1,141 @@
+/*
+ File : core_portme.c
+*/
+/*
+ Author : Shay Gal-On, EEMBC
+ Legal : TODO!
+*/
+#include <stdio.h>
+#include <stdlib.h>
+#include "coremark.h"
+#include "core_portme.h"
+#include "riscv_csr_encoding.h"
+#include "sc_test.h"
+
+#if VALIDATION_RUN
+ volatile ee_s32 seed1_volatile=0x3415;
+ volatile ee_s32 seed2_volatile=0x3415;
+ volatile ee_s32 seed3_volatile=0x66;
+#endif
+#if PERFORMANCE_RUN
+ volatile ee_s32 seed1_volatile=0x0;
+ volatile ee_s32 seed2_volatile=0x0;
+ volatile ee_s32 seed3_volatile=0x66;
+#endif
+#if PROFILE_RUN
+ volatile ee_s32 seed1_volatile=0x8;
+ volatile ee_s32 seed2_volatile=0x8;
+ volatile ee_s32 seed3_volatile=0x8;
+#endif
+ volatile ee_s32 seed4_volatile=ITERATIONS;
+ volatile ee_s32 seed5_volatile=0;
+
+/* Porting : Timing functions
+ How to capture time and convert to seconds must be ported to whatever is supported by the platform.
+ e.g. Read value from on board RTC, read value from cpu clock cycles performance counter etc.
+ Sample implementation for standard time.h and windows.h definitions included.
+*/
+#if 1
+CORETIMETYPE barebones_clock() {
+ unsigned long n;
+ __asm__ __volatile__ (
+ "rdtime %0"
+ : "=r" (n));
+ return n;
+}
+#define CLOCKS_PER_SEC 10000000
+
+/* Define : TIMER_RES_DIVIDER
+ Divider to trade off timer resolution and total time that can be measured.
+
+ Use lower values to increase resolution, but make sure that overflow does not occur.
+ If there are issues with the return value overflowing, increase this value.
+ */
+/* #define NSECS_PER_SEC CLOCKS_PER_SEC */
+/* #define CORETIMETYPE clock_t */
+#define GETMYTIME(_t) (*_t=barebones_clock())
+#define MYTIMEDIFF(fin,ini) ((fin)-(ini))
+#define TIMER_RES_DIVIDER 1
+#define SAMPLE_TIME_IMPLEMENTATION 1
+#define EE_TICKS_PER_SEC (CLOCKS_PER_SEC / TIMER_RES_DIVIDER)
+#else
+
+#endif
+
+/** Define Host specific (POSIX), or target specific global time variables. */
+static CORETIMETYPE start_time_val, stop_time_val;
+
+/* Function : start_time
+ This function will be called right before starting the timed portion of the benchmark.
+
+ Implementation may be capturing a system timer (as implemented in the example code)
+ or zeroing some system parameters - e.g. setting the cpu clocks cycles to 0.
+*/
+void start_time(void) {
+ GETMYTIME(&start_time_val );
+}
+/* Function : stop_time
+ This function will be called right after ending the timed portion of the benchmark.
+
+ Implementation may be capturing a system timer (as implemented in the example code)
+ or other system parameters - e.g. reading the current value of cpu cycles counter.
+*/
+void stop_time(void) {
+ GETMYTIME(&stop_time_val );
+}
+/* Function : get_time
+ Return an abstract "ticks" number that signifies time on the system.
+
+ Actual value returned may be cpu cycles, milliseconds or any other value,
+ as long as it can be converted to seconds by <time_in_secs>.
+ This methodology is taken to accomodate any hardware or simulated platform.
+ The sample implementation returns millisecs by default,
+ and the resolution is controlled by <TIMER_RES_DIVIDER>
+*/
+CORE_TICKS get_time(void) {
+ CORE_TICKS elapsed=(CORE_TICKS)(MYTIMEDIFF(stop_time_val, start_time_val));
+ return elapsed;
+}
+/* Function : time_in_secs
+ Convert the value returned by get_time to seconds.
+
+ The <secs_ret> type is used to accomodate systems with no support for floating point.
+ Default implementation implemented by the EE_TICKS_PER_SEC macro above.
+*/
+secs_ret time_in_secs(CORE_TICKS ticks) {
+ secs_ret retval=((secs_ret)ticks) / (secs_ret)EE_TICKS_PER_SEC;
+ return retval;
+}
+
+ee_u32 default_num_contexts=1;
+
+/* Function : portable_init
+ Target specific initialization code
+ Test for some common mistakes.
+*/
+void portable_init(core_portable *p, int *argc, char *argv[])
+{
+ ee_printf("CoreMark 1.0\n");
+ if (sizeof(ee_ptr_int) != sizeof(ee_u8 *)) {
+ ee_printf("ERROR! Please define ee_ptr_int to a type that holds a pointer! (%u != %u)\n", sizeof(ee_ptr_int), sizeof(ee_u8 *));
+ }
+ if (sizeof(ee_u32) != 4) {
+ ee_printf("ERROR! Please define ee_u32 to a 32b unsigned type! (%u)\n", sizeof(ee_u32));
+ }
+ p->portable_id=1;
+}
+/* Function : portable_fini
+ Target specific final code
+*/
+void portable_fini(core_portable *p)
+{
+ p->portable_id=0;
+
+ report_results(0, 0, 0, 0, 0);
+
+ /* results[0].iterations * 10000000/(total_time) */
+
+ /* extern void tohost_exit(long code); */
+
+ /* tohost_exit(0); */
+}
diff --git a/verilog/dv/riscv_regress/tests/benchmarks/coremark/core_portme.h b/verilog/dv/riscv_regress/tests/benchmarks/coremark/core_portme.h
new file mode 100644
index 0000000..857930f
--- /dev/null
+++ b/verilog/dv/riscv_regress/tests/benchmarks/coremark/core_portme.h
@@ -0,0 +1,210 @@
+/* File : core_portme.h */
+
+/*
+ Author : Shay Gal-On, EEMBC
+ Legal : TODO!
+*/
+/* Topic : Description
+ This file contains configuration constants required to execute on different platforms
+*/
+#ifndef CORE_PORTME_H
+#define CORE_PORTME_H
+/************************/
+/* Data types and settings */
+/************************/
+/* Configuration : HAS_FLOAT
+ Define to 1 if the platform supports floating point.
+*/
+#ifndef HAS_FLOAT
+#define HAS_FLOAT 0
+#endif
+/* Configuration : HAS_TIME_H
+ Define to 1 if platform has the time.h header file,
+ and implementation of functions thereof.
+*/
+#ifndef HAS_TIME_H
+#define HAS_TIME_H 0
+#endif
+/* Configuration : USE_CLOCK
+ Define to 1 if platform has the time.h header file,
+ and implementation of functions thereof.
+*/
+#ifndef USE_CLOCK
+#define USE_CLOCK 0
+#endif
+/* Configuration : HAS_STDIO
+ Define to 1 if the platform has stdio.h.
+*/
+#ifndef HAS_STDIO
+#define HAS_STDIO 1
+#endif
+/* Configuration : HAS_PRINTF
+ Define to 1 if the platform has stdio.h and implements the printf function.
+*/
+#ifndef HAS_PRINTF
+#define HAS_PRINTF 0
+#endif
+
+#include "sc_print.h"
+#define ee_printf sc_printf
+
+/* static inline int ee_printf(const char *fmt, ...) {} */
+
+/* Configuration : CORE_TICKS
+ Define type of return from the timing functions.
+ */
+/* #include <time.h> */
+/* typedef clock_t CORE_TICKS; */
+#include <stdint.h>
+#include <stddef.h>
+#define CORETIMETYPE uint32_t
+typedef uint32_t CORE_TICKS;
+
+/* Definitions : COMPILER_VERSION, COMPILER_FLAGS, MEM_LOCATION
+ Initialize these strings per platform
+*/
+#ifndef COMPILER_VERSION
+ #ifdef __GNUC__
+ #define COMPILER_VERSION "GCC"__VERSION__
+ #else
+ #define COMPILER_VERSION "Please put compiler version here (e.g. gcc 4.1)"
+ #endif
+#endif
+#ifndef COMPILER_FLAGS
+ #define COMPILER_FLAGS FLAGS_STR /* "Please put compiler flags here (e.g. -o3)" */
+#endif
+#ifndef MEM_LOCATION
+ /* #define MEM_LOCATION "STACK" */
+ #define MEM_LOCATION "STATIC"
+#endif
+
+/* Data Types :
+ To avoid compiler issues, define the data types that need ot be used for 8b, 16b and 32b in <core_portme.h>.
+
+ *Imprtant* :
+ ee_ptr_int needs to be the data type used to hold pointers, otherwise coremark may fail!!!
+*/
+typedef int16_t ee_s16;
+typedef uint16_t ee_u16;
+typedef int32_t ee_s32;
+typedef float ee_f32;
+typedef uint8_t ee_u8;
+typedef uint32_t ee_u32;
+typedef uintptr_t ee_ptr_int;
+typedef size_t ee_size_t;
+/* align_mem :
+ This macro is used to align an offset to point to a 32b value. It is used in the Matrix algorithm to initialize the input memory blocks.
+*/
+#define align_mem(x) (void *)(4 + (((ee_ptr_int)(x) - 1) & ~3))
+
+/* Configuration : SEED_METHOD
+ Defines method to get seed values that cannot be computed at compile time.
+
+ Valid values :
+ SEED_ARG - from command line.
+ SEED_FUNC - from a system function.
+ SEED_VOLATILE - from volatile variables.
+*/
+#ifndef SEED_METHOD
+#define SEED_METHOD SEED_VOLATILE
+#endif
+
+/* Configuration : MEM_METHOD
+ Defines method to get a block of memry.
+
+ Valid values :
+ MEM_MALLOC - for platforms that implement malloc and have malloc.h.
+ MEM_STATIC - to use a static memory array.
+ MEM_STACK - to allocate the data block on the stack (NYI).
+*/
+#ifndef MEM_METHOD
+/* #define MEM_METHOD MEM_STACK */
+#define MEM_METHOD MEM_STATIC
+#endif
+
+/* Configuration : MULTITHREAD
+ Define for parallel execution
+
+ Valid values :
+ 1 - only one context (default).
+ N>1 - will execute N copies in parallel.
+
+ Note :
+ If this flag is defined to more then 1, an implementation for launching parallel contexts must be defined.
+
+ Two sample implementations are provided. Use <USE_PTHREAD> or <USE_FORK> to enable them.
+
+ It is valid to have a different implementation of <core_start_parallel> and <core_end_parallel> in <core_portme.c>,
+ to fit a particular architecture.
+*/
+#ifndef MULTITHREAD
+#define MULTITHREAD 1
+#define USE_PTHREAD 0
+#define USE_FORK 0
+#define USE_SOCKET 0
+#endif
+
+/* Configuration : MAIN_HAS_NOARGC
+ Needed if platform does not support getting arguments to main.
+
+ Valid values :
+ 0 - argc/argv to main is supported
+ 1 - argc/argv to main is not supported
+
+ Note :
+ This flag only matters if MULTITHREAD has been defined to a value greater then 1.
+*/
+#ifndef MAIN_HAS_NOARGC
+#define MAIN_HAS_NOARGC 1
+#endif
+
+/* Configuration : MAIN_HAS_NORETURN
+ Needed if platform does not support returning a value from main.
+
+ Valid values :
+ 0 - main returns an int, and return value will be 0.
+ 1 - platform does not support returning a value from main
+*/
+#ifndef MAIN_HAS_NORETURN
+#define MAIN_HAS_NORETURN 0
+#endif
+
+/* Variable : default_num_contexts
+ Not used for this simple port, must cintain the value 1.
+*/
+extern ee_u32 default_num_contexts;
+
+typedef struct CORE_PORTABLE_S {
+ ee_u8 portable_id;
+} core_portable;
+
+/* target specific init/fini */
+void portable_init(core_portable *p, int *argc, char *argv[]);
+void portable_fini(core_portable *p);
+
+#if !defined(PROFILE_RUN) && !defined(PERFORMANCE_RUN) && !defined(VALIDATION_RUN)
+#if (TOTAL_DATA_SIZE==1200)
+#define PROFILE_RUN 1
+#elif (TOTAL_DATA_SIZE==2000)
+#define PERFORMANCE_RUN 1
+#else
+#define VALIDATION_RUN 1
+#endif
+#endif
+
+typedef ee_s16 MATDAT;
+typedef ee_s32 MATRES;
+
+
+ee_u16 crcu8(ee_u8 data, ee_u16 crc ) __attribute__ ((hot));
+ee_u16 crcu16(ee_u16 newval, ee_u16 crc) __attribute__ ((hot));
+ee_u16 crcu32(ee_u32 newval, ee_u16 crc) __attribute__ ((hot));
+ee_u16 crc16(ee_s16 newval, ee_u16 crc) __attribute__ ((hot));
+ee_s16 matrix_sum(ee_u32 N, MATRES *C, MATDAT clipval) __attribute__ ((hot));
+void matrix_mul_const(ee_u32 N, MATRES *C, MATDAT *A, MATDAT val) __attribute__ ((hot));
+void matrix_mul_vect(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B) __attribute__ ((hot));
+void matrix_mul_matrix(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B) __attribute__ ((hot));
+void matrix_mul_matrix_bitextract(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B) __attribute__ ((hot));
+void matrix_add_const(ee_u32 N, MATDAT *A, MATDAT val) __attribute__ ((hot));
+
+#endif /* CORE_PORTME_H */
diff --git a/verilog/dv/riscv_regress/tests/benchmarks/dhrystone21/Makefile b/verilog/dv/riscv_regress/tests/benchmarks/dhrystone21/Makefile
new file mode 100644
index 0000000..7056489
--- /dev/null
+++ b/verilog/dv/riscv_regress/tests/benchmarks/dhrystone21/Makefile
@@ -0,0 +1,16 @@
+src_dir := $(dir $(lastword $(MAKEFILE_LIST)))
+
+ADD_FLAGS := -flto
+ADD_CFLAGS := -DSELF_TIMED=1 -DTIME=1
+
+c_src := sc_print.c dhry_1.c dhry_2.c
+
+include $(inc_dir)/common.mk
+
+default: log_requested_tgt $(bld_dir)/dhrystone21.elf $(bld_dir)/dhrystone21.hex $(bld_dir)/dhrystone21.dump
+
+log_requested_tgt:
+ @echo dhrystone21.hex>> $(bld_dir)/test_info
+
+clean:
+ $(RM) $(c_objs) $(asm_objs) $(bld_dir)/dhrystone21.elf $(bld_dir)/dhrystone21.hex $(bld_dir)/dhrystone21.dump
\ No newline at end of file
diff --git a/verilog/dv/riscv_regress/tests/benchmarks/dhrystone21/dhry.h b/verilog/dv/riscv_regress/tests/benchmarks/dhrystone21/dhry.h
new file mode 100644
index 0000000..cba0059
--- /dev/null
+++ b/verilog/dv/riscv_regress/tests/benchmarks/dhrystone21/dhry.h
@@ -0,0 +1,446 @@
+/*****************************************************************************
+ * The BYTE UNIX Benchmarks - Release 3
+ * Module: dhry.h SID: 3.4 5/15/91 19:30:21
+ *
+ *****************************************************************************
+ * Bug reports, patches, comments, suggestions should be sent to:
+ *
+ * Ben Smith, Rick Grehan or Tom Yager
+ * ben@bytepb.byte.com rick_g@bytepb.byte.com tyager@bytepb.byte.com
+ *
+ *****************************************************************************
+ * Modification Log:
+ * addapted from:
+ *
+ *
+ * "DHRYSTONE" Benchmark Program
+ * -----------------------------
+ *
+ * Version: C, Version 2.1
+ *
+ * File: dhry.h (part 1 of 3)
+ *
+ * Date: May 25, 1988
+ *
+ * Author: Reinhold P. Weicker
+ * Siemens AG, AUT E 51
+ * Postfach 3220
+ * 8520 Erlangen
+ * Germany (West)
+ * Phone: [+49]-9131-7-20330
+ * (8-17 Central European Time)
+ * Usenet: ..!mcvax!unido!estevax!weicker
+ *
+ * Original Version (in Ada) published in
+ * "Communications of the ACM" vol. 27., no. 10 (Oct. 1984),
+ * pp. 1013 - 1030, together with the statistics
+ * on which the distribution of statements etc. is based.
+ *
+ * In this C version, the following C library functions are used:
+ * - strcpy, strcmp (inside the measurement loop)
+ * - printf, scanf (outside the measurement loop)
+ * In addition, Berkeley UNIX system calls "times ()" or "time ()"
+ * are used for execution time measurement. For measurements
+ * on other systems, these calls have to be changed.
+ *
+ * Collection of Results:
+ * Reinhold Weicker (address see above) and
+ *
+ * Rick Richardson
+ * PC Research. Inc.
+ * 94 Apple Orchard Drive
+ * Tinton Falls, NJ 07724
+ * Phone: (201) 834-1378 (9-17 EST)
+ * Usenet: ...!seismo!uunet!pcrat!rick
+ *
+ * Please send results to Rick Richardson and/or Reinhold Weicker.
+ * Complete information should be given on hardware and software used.
+ * Hardware information includes: Machine type, CPU, type and size
+ * of caches; for microprocessors: clock frequency, memory speed
+ * (number of wait states).
+ * Software information includes: Compiler (and runtime library)
+ * manufacturer and version, compilation switches, OS version.
+ * The Operating System version may give an indication about the
+ * compiler; Dhrystone itself performs no OS calls in the measurement loop.
+ *
+ * The complete output generated by the program should be mailed
+ * such that at least some checks for correctness can be made.
+ *
+ ***************************************************************************
+ *
+ * History: This version C/2.1 has been made for two reasons:
+ *
+ * 1) There is an obvious need for a common C version of
+ * Dhrystone, since C is at present the most popular system
+ * programming language for the class of processors
+ * (microcomputers, minicomputers) where Dhrystone is used most.
+ * There should be, as far as possible, only one C version of
+ * Dhrystone such that results can be compared without
+ * restrictions. In the past, the C versions distributed
+ * by Rick Richardson (Version 1.1) and by Reinhold Weicker
+ * had small (though not significant) differences.
+ *
+ * 2) As far as it is possible without changes to the Dhrystone
+ * statistics, optimizing compilers should be prevented from
+ * removing significant statements.
+ *
+ * This C version has been developed in cooperation with
+ * Rick Richardson (Tinton Falls, NJ), it incorporates many
+ * ideas from the "Version 1.1" distributed previously by
+ * him over the UNIX network Usenet.
+ * I also thank Chaim Benedelac (National Semiconductor),
+ * David Ditzel (SUN), Earl Killian and John Mashey (MIPS),
+ * Alan Smith and Rafael Saavedra-Barrera (UC at Berkeley)
+ * for their help with comments on earlier versions of the
+ * benchmark.
+ *
+ * Changes: In the initialization part, this version follows mostly
+ * Rick Richardson's version distributed via Usenet, not the
+ * version distributed earlier via floppy disk by Reinhold Weicker.
+ * As a concession to older compilers, names have been made
+ * unique within the first 8 characters.
+ * Inside the measurement loop, this version follows the
+ * version previously distributed by Reinhold Weicker.
+ *
+ * At several places in the benchmark, code has been added,
+ * but within the measurement loop only in branches that
+ * are not executed. The intention is that optimizing compilers
+ * should be prevented from moving code out of the measurement
+ * loop, or from removing code altogether. Since the statements
+ * that are executed within the measurement loop have NOT been
+ * changed, the numbers defining the "Dhrystone distribution"
+ * (distribution of statements, operand types and locality)
+ * still hold. Except for sophisticated optimizing compilers,
+ * execution times for this version should be the same as
+ * for previous versions.
+ *
+ * Since it has proven difficult to subtract the time for the
+ * measurement loop overhead in a correct way, the loop check
+ * has been made a part of the benchmark. This does have
+ * an impact - though a very minor one - on the distribution
+ * statistics which have been updated for this version.
+ *
+ * All changes within the measurement loop are described
+ * and discussed in the companion paper "Rationale for
+ * Dhrystone version 2".
+ *
+ * Because of the self-imposed limitation that the order and
+ * distribution of the executed statements should not be
+ * changed, there are still cases where optimizing compilers
+ * may not generate code for some statements. To a certain
+ * degree, this is unavoidable for small synthetic benchmarks.
+ * Users of the benchmark are advised to check code listings
+ * whether code is generated for all statements of Dhrystone.
+ *
+ * Version 2.1 is identical to version 2.0 distributed via
+ * the UNIX network Usenet in March 1988 except that it corrects
+ * some minor deficiencies that were found by users of version 2.0.
+ * The only change within the measurement loop is that a
+ * non-executed "else" part was added to the "if" statement in
+ * Func_3, and a non-executed "else" part removed from Proc_3.
+ *
+ ***************************************************************************
+ *
+ * Defines: The following "Defines" are possible:
+ * -DREG=register (default: Not defined)
+ * As an approximation to what an average C programmer
+ * might do, the "register" storage class is applied
+ * (if enabled by -DREG=register)
+ * - for local variables, if they are used (dynamically)
+ * five or more times
+ * - for parameters if they are used (dynamically)
+ * six or more times
+ * Note that an optimal "register" strategy is
+ * compiler-dependent, and that "register" declarations
+ * do not necessarily lead to faster execution.
+ * -DNOSTRUCTASSIGN (default: Not defined)
+ * Define if the C compiler does not support
+ * assignment of structures.
+ * -DNOENUMS (default: Not defined)
+ * Define if the C compiler does not support
+ * enumeration types.
+ * -DTIMES (default)
+ * -DTIME
+ * The "times" function of UNIX (returning process times)
+ * or the "time" function (returning wallclock time)
+ * is used for measurement.
+ * For single user machines, "time ()" is adequate. For
+ * multi-user machines where you cannot get single-user
+ * access, use the "times ()" function. If you have
+ * neither, use a stopwatch in the dead of night.
+ * "printf"s are provided marking the points "Start Timer"
+ * and "Stop Timer". DO NOT use the UNIX "time(1)"
+ * command, as this will measure the total time to
+ * run this program, which will (erroneously) include
+ * the time to allocate storage (malloc) and to perform
+ * the initialization.
+ * -DHZ=nnn
+ * In Berkeley UNIX, the function "times" returns process
+ * time in 1/HZ seconds, with HZ = 60 for most systems.
+ * CHECK YOUR SYSTEM DESCRIPTION BEFORE YOU JUST APPLY
+ * A VALUE.
+ *
+ ***************************************************************************
+ *
+ * Compilation model and measurement (IMPORTANT):
+ *
+ * This C version of Dhrystone consists of three files:
+ * - dhry.h (this file, containing global definitions and comments)
+ * - dhry_1.c (containing the code corresponding to Ada package Pack_1)
+ * - dhry_2.c (containing the code corresponding to Ada package Pack_2)
+ *
+ * The following "ground rules" apply for measurements:
+ * - Separate compilation
+ * - No procedure merging
+ * - Otherwise, compiler optimizations are allowed but should be indicated
+ * - Default results are those without register declarations
+ * See the companion paper "Rationale for Dhrystone Version 2" for a more
+ * detailed discussion of these ground rules.
+ *
+ * For 16-Bit processors (e.g. 80186, 80286), times for all compilation
+ * models ("small", "medium", "large" etc.) should be given if possible,
+ * together with a definition of these models for the compiler system used.
+ *
+ **************************************************************************
+ *
+ * Dhrystone (C version) statistics:
+ *
+ * [Comment from the first distribution, updated for version 2.
+ * Note that because of language differences, the numbers are slightly
+ * different from the Ada version.]
+ *
+ * The following program contains statements of a high level programming
+ * language (here: C) in a distribution considered representative:
+ *
+ * assignments 52 (51.0 %)
+ * control statements 33 (32.4 %)
+ * procedure, function calls 17 (16.7 %)
+ *
+ * 103 statements are dynamically executed. The program is balanced with
+ * respect to the three aspects:
+ *
+ * - statement type
+ * - operand type
+ * - operand locality
+ * operand global, local, parameter, or constant.
+ *
+ * The combination of these three aspects is balanced only approximately.
+ *
+ * 1. Statement Type:
+ * ----------------- number
+ *
+ * V1 = V2 9
+ * (incl. V1 = F(..)
+ * V = Constant 12
+ * Assignment, 7
+ * with array element
+ * Assignment, 6
+ * with record component
+ * --
+ * 34 34
+ *
+ * X = Y +|-|"&&"|"|" Z 5
+ * X = Y +|-|"==" Constant 6
+ * X = X +|- 1 3
+ * X = Y *|/ Z 2
+ * X = Expression, 1
+ * two operators
+ * X = Expression, 1
+ * three operators
+ * --
+ * 18 18
+ *
+ * if .... 14
+ * with "else" 7
+ * without "else" 7
+ * executed 3
+ * not executed 4
+ * for ... 7 | counted every time
+ * while ... 4 | the loop condition
+ * do ... while 1 | is evaluated
+ * switch ... 1
+ * break 1
+ * declaration with 1
+ * initialization
+ * --
+ * 34 34
+ *
+ * P (...) procedure call 11
+ * user procedure 10
+ * library procedure 1
+ * X = F (...)
+ * function call 6
+ * user function 5
+ * library function 1
+ * --
+ * 17 17
+ * ---
+ * 103
+ *
+ * The average number of parameters in procedure or function calls
+ * is 1.82 (not counting the function values as implicit parameters).
+ *
+ *
+ * 2. Operators
+ * ------------
+ * number approximate
+ * percentage
+ *
+ * Arithmetic 32 50.8
+ *
+ * + 21 33.3
+ * - 7 11.1
+ * * 3 4.8
+ * / (int div) 1 1.6
+ *
+ * Comparison 27 42.8
+ *
+ * == 9 14.3
+ * /= 4 6.3
+ * > 1 1.6
+ * < 3 4.8
+ * >= 1 1.6
+ * <= 9 14.3
+ *
+ * Logic 4 6.3
+ *
+ * && (AND-THEN) 1 1.6
+ * | (OR) 1 1.6
+ * ! (NOT) 2 3.2
+ *
+ * -- -----
+ * 63 100.1
+ *
+ *
+ * 3. Operand Type (counted once per operand reference):
+ * ---------------
+ * number approximate
+ * percentage
+ *
+ * Integer 175 72.3 %
+ * Character 45 18.6 %
+ * Pointer 12 5.0 %
+ * String30 6 2.5 %
+ * Array 2 0.8 %
+ * Record 2 0.8 %
+ * --- -------
+ * 242 100.0 %
+ *
+ * When there is an access path leading to the final operand (e.g. a record
+ * component), only the final data type on the access path is counted.
+ *
+ *
+ * 4. Operand Locality:
+ * -------------------
+ * number approximate
+ * percentage
+ *
+ * local variable 114 47.1 %
+ * global variable 22 9.1 %
+ * parameter 45 18.6 %
+ * value 23 9.5 %
+ * reference 22 9.1 %
+ * function result 6 2.5 %
+ * constant 55 22.7 %
+ * --- -------
+ * 242 100.0 %
+ *
+ *
+ * The program does not compute anything meaningful, but it is syntactically
+ * and semantically correct. All variables have a value assigned to them
+ * before they are used as a source operand.
+ *
+ * There has been no explicit effort to account for the effects of a
+ * cache, or to balance the use of long or short displacements for code or
+ * data.
+ *
+ ***************************************************************************
+ */
+
+
+/* Compiler and system dependent definitions: */
+
+#ifndef TIME
+#define TIMES
+#endif
+ /* Use times(2) time function unless */
+ /* explicitly defined otherwise */
+
+#ifdef TIMES
+#include <sys/types.h>
+#include <sys/times.h>
+ /* for "times" */
+#endif
+
+#define Mic_secs_Per_Second 1000000
+ /* Berkeley UNIX C returns process times in seconds/HZ */
+
+#ifdef NOSTRUCTASSIGN
+#define structassign(d, s) memcpy(&(d), &(s), sizeof(d))
+#else
+#define structassign(d, s) d = s
+#endif
+
+#ifdef NOENUM
+#define Ident_1 0
+#define Ident_2 1
+#define Ident_3 2
+#define Ident_4 3
+#define Ident_5 4
+ typedef int Enumeration;
+#else
+ typedef enum {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5}
+ Enumeration;
+#endif
+ /* for boolean and enumeration types in Ada, Pascal */
+
+/* General definitions: */
+
+#include <stdio.h>
+#include <string.h>
+ /* for strcpy, strcmp */
+
+#define Null 0
+ /* Value of a Null pointer */
+#define true 1
+#define false 0
+
+typedef int One_Thirty;
+typedef int One_Fifty;
+typedef char Capital_Letter;
+typedef int Boolean;
+typedef char Str_30 [31];
+typedef int Arr_1_Dim [50];
+typedef int Arr_2_Dim [50] [50];
+
+typedef struct record
+ {
+ struct record *Ptr_Comp;
+ Enumeration Discr;
+ union {
+ struct {
+ Enumeration Enum_Comp;
+ int Int_Comp;
+ char Str_Comp [31];
+ } var_1;
+ struct {
+ Enumeration E_Comp_2;
+ char Str_2_Comp [31];
+ } var_2;
+ struct {
+ char Ch_1_Comp;
+ char Ch_2_Comp;
+ } var_3;
+ } variant;
+ } Rec_Type, *Rec_Pointer;
+
+#include "sc_print.h"
+#include "csr.h"
+
+# define printf sc_printf
+
+#define HZ 1000000
+static long time(long *x)
+{
+ return rdcycle();
+}
diff --git a/verilog/dv/riscv_regress/tests/benchmarks/dhrystone21/dhry_1.c b/verilog/dv/riscv_regress/tests/benchmarks/dhrystone21/dhry_1.c
new file mode 100644
index 0000000..d52acbb
--- /dev/null
+++ b/verilog/dv/riscv_regress/tests/benchmarks/dhrystone21/dhry_1.c
@@ -0,0 +1,461 @@
+/*****************************************************************************
+ * The BYTE UNIX Benchmarks - Release 3
+ * Module: dhry_1.c SID: 3.4 5/15/91 19:30:21
+ *
+ *****************************************************************************
+ * Bug reports, patches, comments, suggestions should be sent to:
+ *
+ * Ben Smith, Rick Grehan or Tom Yager
+ * ben@bytepb.byte.com rick_g@bytepb.byte.com tyager@bytepb.byte.com
+ *
+ *****************************************************************************
+ *
+ * *** WARNING **** With BYTE's modifications applied, results obtained with
+ * ******* this version of the Dhrystone program may not be applicable
+ * to other versions.
+ *
+ * Modification Log:
+ * 10/22/97 - code cleanup to remove ANSI C compiler warnings
+ * Andy Kahn <kahn@zk3.dec.com>
+ *
+ * Adapted from:
+ *
+ * "DHRYSTONE" Benchmark Program
+ * -----------------------------
+ *
+ * Version: C, Version 2.1
+ *
+ * File: dhry_1.c (part 2 of 3)
+ *
+ * Date: May 25, 1988
+ *
+ * Author: Reinhold P. Weicker
+ *
+ ***************************************************************************/
+char SCCSid[] = "@(#) @(#)dhry_1.c:3.4 -- 5/15/91 19:30:21";
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include "dhry.h"
+//#include "timeit.c"
+
+unsigned long Run_Index;
+/*
+void report()
+{
+ fprintf(stderr,"COUNT|%ld|1|lps\n", Run_Index);
+ exit(0);
+}
+*/
+/* Global Variables: */
+
+Rec_Pointer Ptr_Glob,
+ Next_Ptr_Glob;
+int Int_Glob;
+Boolean Bool_Glob;
+char Ch_1_Glob,
+ Ch_2_Glob;
+int Arr_1_Glob [50];
+int Arr_2_Glob [50] [50];
+
+Enumeration Func_1 ();
+ /* forward declaration necessary since Enumeration may not simply be int */
+
+#ifndef REG
+ Boolean Reg = false;
+#define REG
+ /* REG becomes defined as empty */
+ /* i.e. no register variables */
+#else
+ Boolean Reg = true;
+#endif
+
+/* variables for time measurement: */
+
+#ifdef TIMES
+struct tms time_info;
+/* extern int times (); */
+ /* see library function "times" */
+#define Too_Small_Time 120
+ /* Measurements should last at least about 2 seconds */
+#endif
+#ifdef TIME
+extern long time();
+ /* see library function "time" */
+#define Too_Small_Time 2
+ /* Measurements should last at least 2 seconds */
+#endif
+
+long Begin_Time,
+ End_Time,
+ User_Time;
+#if 0
+float Microseconds,
+ Dhrystones_Per_Second;
+#else
+long Microseconds,
+ Dhrystones_Per_Second;
+#endif
+
+/* end of variables for time measurement */
+
+void Proc_1 (REG Rec_Pointer Ptr_Val_Par);
+void Proc_2 (One_Fifty *Int_Par_Ref);
+void Proc_3 (Rec_Pointer *Ptr_Ref_Par);
+void Proc_4 (void);
+void Proc_5 (void);
+
+
+extern Boolean Func_2(Str_30, Str_30);
+extern void Proc_6(Enumeration, Enumeration *);
+extern void Proc_7(One_Fifty, One_Fifty, One_Fifty *);
+extern void Proc_8(Arr_1_Dim, Arr_2_Dim, int, int);
+
+int main (argc, argv)
+int argc;
+char *argv[];
+ /* main program, corresponds to procedures */
+ /* Main and Proc_0 in the Ada version */
+{
+#ifdef SELF_TIMED
+ int Number_Of_Runs;
+#else /* SELF_TIMED */
+ int duration;
+#endif /* SELF_TIMED */
+ One_Fifty Int_1_Loc;
+ REG One_Fifty Int_2_Loc;
+ One_Fifty Int_3_Loc;
+ REG char Ch_Index;
+ Enumeration Enum_Loc;
+ Str_30 Str_1_Loc;
+ Str_30 Str_2_Loc;
+
+ /* Initializations */
+#if 0
+ Next_Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type));
+ Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type));
+#else
+ static Rec_Type glob1, glob2;
+ Next_Ptr_Glob = &glob1;
+ Ptr_Glob = &glob2;
+#endif
+
+ Ptr_Glob->Ptr_Comp = Next_Ptr_Glob;
+ Ptr_Glob->Discr = Ident_1;
+ Ptr_Glob->variant.var_1.Enum_Comp = Ident_3;
+ Ptr_Glob->variant.var_1.Int_Comp = 40;
+ strcpy (Ptr_Glob->variant.var_1.Str_Comp,
+ "DHRYSTONE PROGRAM, SOME STRING");
+ strcpy (Str_1_Loc, "DHRYSTONE PROGRAM, 1'ST STRING");
+
+ Arr_2_Glob [8][7] = 10;
+ /* Was missing in published program. Without this statement, */
+ /* Arr_2_Glob [8][7] would have an undefined value. */
+ /* Warning: With 16-Bit processors and Number_Of_Runs > 32000, */
+ /* overflow may occur for this array element. */
+
+#ifdef SELF_TIMED
+ Number_Of_Runs = 500;//500000;
+ if (argc >= 2) {
+ Number_Of_Runs = atoi(argv[1]);
+ }
+ printf ("\n");
+ printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n");
+ printf ("\n");
+ if (Reg)
+ {
+ printf ("Program compiled with 'register' attribute\n");
+ printf ("\n");
+ }
+ else
+ {
+ printf ("Program compiled without 'register' attribute\n");
+ printf ("\n");
+ }
+#ifdef PRATTLE
+ printf ("Please give the number of runs through the benchmark: ");
+ {
+ int n;
+ scanf ("%d", &n);
+ Number_Of_Runs = n;
+ }
+ printf ("\n");
+#endif /* PRATTLE */
+
+ printf ("Execution starts, %d runs through Dhrystone\n", Number_Of_Runs);
+
+ Run_Index = 0;
+#else /* SELF_TIMED */
+ if (argc != 2) {
+ fprintf(stderr, "Usage: %s duration\n", argv[0]);
+ exit(1);
+ }
+
+ duration = atoi(argv[1]);
+ Run_Index = 0;
+ wake_me(duration, report);
+#endif /* SELF_TIMED */
+
+ /***************/
+ /* Start timer */
+ /***************/
+
+#ifdef SELF_TIMED
+#ifdef TIMES
+ times (&time_info);
+ Begin_Time = (long) time_info.tms_utime;
+#endif
+#ifdef TIME
+ Begin_Time = time ( (long *) 0);
+#endif
+#endif /* SELF_TIMED */
+
+#ifdef SELF_TIMED
+ for (Run_Index = 1; Run_Index <= Number_Of_Runs ; ++Run_Index)
+#else /* SELF_TIMED */
+ for (Run_Index = 1; ; ++Run_Index)
+#endif /* SELF_TIMED */
+ {
+
+ Proc_5();
+ Proc_4();
+ /* Ch_1_Glob == 'A', Ch_2_Glob == 'B', Bool_Glob == true */
+ Int_1_Loc = 2;
+ Int_2_Loc = 3;
+ strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING");
+ Enum_Loc = Ident_2;
+ Bool_Glob = ! Func_2 (Str_1_Loc, Str_2_Loc);
+ /* Bool_Glob == 1 */
+ while (Int_1_Loc < Int_2_Loc) /* loop body executed once */
+ {
+ Int_3_Loc = 5 * Int_1_Loc - Int_2_Loc;
+ /* Int_3_Loc == 7 */
+ Proc_7 (Int_1_Loc, Int_2_Loc, &Int_3_Loc);
+ /* Int_3_Loc == 7 */
+ Int_1_Loc += 1;
+ } /* while */
+ /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
+ Proc_8 (Arr_1_Glob, Arr_2_Glob, Int_1_Loc, Int_3_Loc);
+ /* Int_Glob == 5 */
+ Proc_1 (Ptr_Glob);
+ for (Ch_Index = 'A'; Ch_Index <= Ch_2_Glob; ++Ch_Index)
+ /* loop body executed twice */
+ {
+ if (Enum_Loc == Func_1 (Ch_Index, 'C'))
+ /* then, not executed */
+ {
+ Proc_6 (Ident_1, &Enum_Loc);
+ strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING");
+ Int_2_Loc = Run_Index;
+ Int_Glob = Run_Index;
+ }
+ }
+ /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
+ Int_2_Loc = Int_2_Loc * Int_1_Loc;
+ Int_1_Loc = Int_2_Loc / Int_3_Loc;
+ Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc;
+ /* Int_1_Loc == 1, Int_2_Loc == 13, Int_3_Loc == 7 */
+ Proc_2 (&Int_1_Loc);
+ /* Int_1_Loc == 5 */
+
+ } /* loop "for Run_Index" */
+
+ /**************/
+ /* Stop timer */
+ /**************/
+#ifdef SELF_TIMED
+#ifdef TIMES
+ times (&time_info);
+ End_Time = (long) time_info.tms_utime;
+#endif
+#ifdef TIME
+ End_Time = time ( (long *) 0);
+#endif
+#endif /* SELF_TIMED */
+
+ /* BYTE version never executes this stuff */
+#ifdef SELF_TIMED
+ printf ("Execution ends\n");
+ printf ("\n");
+ printf ("Final values of the variables used in the benchmark:\n");
+ printf ("\n");
+ printf ("Int_Glob: %d\n", Int_Glob);
+ printf (" should be: %d\n", 5);
+ printf ("Bool_Glob: %d\n", Bool_Glob);
+ printf (" should be: %d\n", 1);
+ printf ("Ch_1_Glob: %c\n", Ch_1_Glob);
+ printf (" should be: %c\n", 'A');
+ printf ("Ch_2_Glob: %c\n", Ch_2_Glob);
+ printf (" should be: %c\n", 'B');
+ printf ("Arr_1_Glob[8]: %d\n", Arr_1_Glob[8]);
+ printf (" should be: %d\n", 7);
+ printf ("Arr_2_Glob[8][7]: %d\n", Arr_2_Glob[8][7]);
+ printf (" should be: Number_Of_Runs + 10\n");
+ printf ("Ptr_Glob->\n");
+ printf (" Ptr_Comp: %d\n", (int) Ptr_Glob->Ptr_Comp);
+ printf (" should be: (implementation-dependent)\n");
+ printf (" Discr: %d\n", Ptr_Glob->Discr);
+ printf (" should be: %d\n", 0);
+ printf (" Enum_Comp: %d\n", Ptr_Glob->variant.var_1.Enum_Comp);
+ printf (" should be: %d\n", 2);
+ printf (" Int_Comp: %d\n", Ptr_Glob->variant.var_1.Int_Comp);
+ printf (" should be: %d\n", 17);
+ printf (" Str_Comp: %s\n", Ptr_Glob->variant.var_1.Str_Comp);
+ printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n");
+ printf ("Next_Ptr_Glob->\n");
+ printf (" Ptr_Comp: %d\n", (int) Next_Ptr_Glob->Ptr_Comp);
+ printf (" should be: (implementation-dependent), same as above\n");
+ printf (" Discr: %d\n", Next_Ptr_Glob->Discr);
+ printf (" should be: %d\n", 0);
+ printf (" Enum_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Enum_Comp);
+ printf (" should be: %d\n", 1);
+ printf (" Int_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Int_Comp);
+ printf (" should be: %d\n", 18);
+ printf (" Str_Comp: %s\n",
+ Next_Ptr_Glob->variant.var_1.Str_Comp);
+ printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n");
+ printf ("Int_1_Loc: %d\n", Int_1_Loc);
+ printf (" should be: %d\n", 5);
+ printf ("Int_2_Loc: %d\n", Int_2_Loc);
+ printf (" should be: %d\n", 13);
+ printf ("Int_3_Loc: %d\n", Int_3_Loc);
+ printf (" should be: %d\n", 7);
+ printf ("Enum_Loc: %d\n", Enum_Loc);
+ printf (" should be: %d\n", 1);
+ printf ("Str_1_Loc: %s\n", Str_1_Loc);
+ printf (" should be: DHRYSTONE PROGRAM, 1'ST STRING\n");
+ printf ("Str_2_Loc: %s\n", Str_2_Loc);
+ printf (" should be: DHRYSTONE PROGRAM, 2'ND STRING\n");
+ printf ("\n");
+
+ User_Time = End_Time - Begin_Time;
+
+ if (User_Time < Too_Small_Time)
+ {
+ printf ("Measured time too small to obtain meaningful results\n");
+ printf ("Please increase number of runs\n");
+ printf ("\n");
+ }
+ else
+ {
+#if 0
+#ifdef TIME
+ Microseconds = (float) User_Time * Mic_secs_Per_Second
+ / (float) Number_Of_Runs;
+ Dhrystones_Per_Second = (float) Number_Of_Runs / (float) User_Time;
+#else
+ Microseconds = (float) User_Time * Mic_secs_Per_Second
+ / ((float) HZ * ((float) Number_Of_Runs));
+ Dhrystones_Per_Second = ((float) HZ * (float) Number_Of_Runs)
+ / (float) User_Time;
+#endif
+#else
+ Microseconds = ((User_Time / Number_Of_Runs) * Mic_secs_Per_Second) / HZ;
+ Dhrystones_Per_Second = (HZ * Number_Of_Runs) / User_Time;
+
+ sc_printf("Number_Of_Runs= %ld, HZ= %ld\n", Number_Of_Runs, HZ);
+ sc_printf("Time: begin= %ld, end= %ld, diff= %ld\n", Begin_Time, End_Time, User_Time);
+ sc_printf("Microseconds for one run through Dhrystone: %ld\n", Microseconds);
+ sc_printf("Dhrystones per Second: %ld\n", Dhrystones_Per_Second);
+
+#endif
+ }
+#endif /* SELF_TIMED */
+}
+
+
+void Proc_1 (REG Rec_Pointer Ptr_Val_Par)
+ /* executed once */
+{
+ REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp;
+ /* == Ptr_Glob_Next */
+ /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp, */
+ /* corresponds to "rename" in Ada, "with" in Pascal */
+
+ structassign (*Ptr_Val_Par->Ptr_Comp, *Ptr_Glob);
+ Ptr_Val_Par->variant.var_1.Int_Comp = 5;
+ Next_Record->variant.var_1.Int_Comp
+ = Ptr_Val_Par->variant.var_1.Int_Comp;
+ Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp;
+ Proc_3 (&Next_Record->Ptr_Comp);
+ /* Ptr_Val_Par->Ptr_Comp->Ptr_Comp
+ == Ptr_Glob->Ptr_Comp */
+ if (Next_Record->Discr == Ident_1)
+ /* then, executed */
+ {
+ Next_Record->variant.var_1.Int_Comp = 6;
+ Proc_6 (Ptr_Val_Par->variant.var_1.Enum_Comp,
+ &Next_Record->variant.var_1.Enum_Comp);
+ Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp;
+ Proc_7 (Next_Record->variant.var_1.Int_Comp, 10,
+ &Next_Record->variant.var_1.Int_Comp);
+ }
+ else /* not executed */
+ structassign (*Ptr_Val_Par, *Ptr_Val_Par->Ptr_Comp);
+} /* Proc_1 */
+
+
+void Proc_2 (One_Fifty *Int_Par_Ref)
+ /* executed once */
+ /* *Int_Par_Ref == 1, becomes 4 */
+{
+ One_Fifty Int_Loc;
+ Enumeration Enum_Loc;
+
+ Enum_Loc = 0;
+
+ Int_Loc = *Int_Par_Ref + 10;
+ do /* executed once */
+ if (Ch_1_Glob == 'A')
+ /* then, executed */
+ {
+ Int_Loc -= 1;
+ *Int_Par_Ref = Int_Loc - Int_Glob;
+ Enum_Loc = Ident_1;
+ } /* if */
+ while (Enum_Loc != Ident_1); /* true */
+} /* Proc_2 */
+
+
+void Proc_3 (Rec_Pointer *Ptr_Ref_Par)
+ /* executed once */
+ /* Ptr_Ref_Par becomes Ptr_Glob */
+{
+ if (Ptr_Glob != Null)
+ /* then, executed */
+ *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp;
+ Proc_7 (10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp);
+} /* Proc_3 */
+
+
+void Proc_4 (void) /* without parameters */
+ /* executed once */
+{
+ Boolean Bool_Loc;
+
+ Bool_Loc = Ch_1_Glob == 'A';
+ Bool_Glob = Bool_Loc | Bool_Glob;
+ Ch_2_Glob = 'B';
+} /* Proc_4 */
+
+void Proc_5 (void) /* without parameters */
+/*******/
+ /* executed once */
+{
+ Ch_1_Glob = 'A';
+ Bool_Glob = false;
+} /* Proc_5 */
+
+
+ /* Procedure for the assignment of structures, */
+ /* if the C compiler doesn't support this feature */
+#ifdef NOSTRUCTASSIGN
+memcpy (d, s, l)
+register char *d;
+register char *s;
+register int l;
+{
+ while (l--) *d++ = *s++;
+}
+#endif
diff --git a/verilog/dv/riscv_regress/tests/benchmarks/dhrystone21/dhry_2.c b/verilog/dv/riscv_regress/tests/benchmarks/dhrystone21/dhry_2.c
new file mode 100644
index 0000000..140161f
--- /dev/null
+++ b/verilog/dv/riscv_regress/tests/benchmarks/dhrystone21/dhry_2.c
@@ -0,0 +1,209 @@
+/*****************************************************************************
+ * The BYTE UNIX Benchmarks - Release 3
+ * Module: dhry_2.c SID: 3.4 5/15/91 19:30:22
+ *
+ *****************************************************************************
+ * Bug reports, patches, comments, suggestions should be sent to:
+ *
+ * Ben Smith, Rick Grehan or Tom Yager
+ * ben@bytepb.byte.com rick_g@bytepb.byte.com tyager@bytepb.byte.com
+ *
+ *****************************************************************************
+ * Modification Log:
+ * 10/22/97 - code cleanup to remove ANSI C compiler warnings
+ * Andy Kahn <kahn@zk3.dec.com>
+ *
+ * Adapted from:
+ *
+ * "DHRYSTONE" Benchmark Program
+ * -----------------------------
+ *
+ * **** WARNING **** See warning in n.dhry_1.c
+ *
+ * Version: C, Version 2.1
+ *
+ * File: dhry_2.c (part 3 of 3)
+ *
+ * Date: May 25, 1988
+ *
+ * Author: Reinhold P. Weicker
+ *
+ ****************************************************************************/
+/* SCCSid is defined in dhry_1.c */
+
+#include <string.h>
+#include "dhry.h"
+
+#ifndef REG
+#define REG
+ /* REG becomes defined as empty */
+ /* i.e. no register variables */
+#endif
+
+extern int Int_Glob;
+extern char Ch_1_Glob;
+
+void Proc_6(Enumeration, Enumeration *);
+void Proc_7(One_Fifty, One_Fifty, One_Fifty *);
+void Proc_8(Arr_1_Dim, Arr_2_Dim, int, int);
+Enumeration Func_1(Capital_Letter, Capital_Letter);
+Boolean Func_2(Str_30, Str_30);
+Boolean Func_3(Enumeration);
+
+void Proc_6 (Enumeration Enum_Val_Par, Enumeration *Enum_Ref_Par)
+ /* executed once */
+ /* Enum_Val_Par == Ident_3, Enum_Ref_Par becomes Ident_2 */
+{
+ *Enum_Ref_Par = Enum_Val_Par;
+ if (! Func_3 (Enum_Val_Par))
+ /* then, not executed */
+ *Enum_Ref_Par = Ident_4;
+ switch (Enum_Val_Par)
+ {
+ case Ident_1:
+ *Enum_Ref_Par = Ident_1;
+ break;
+ case Ident_2:
+ if (Int_Glob > 100)
+ /* then */
+ *Enum_Ref_Par = Ident_1;
+ else *Enum_Ref_Par = Ident_4;
+ break;
+ case Ident_3: /* executed */
+ *Enum_Ref_Par = Ident_2;
+ break;
+ case Ident_4: break;
+ case Ident_5:
+ *Enum_Ref_Par = Ident_3;
+ break;
+ } /* switch */
+} /* Proc_6 */
+
+void Proc_7 (Int_1_Par_Val, Int_2_Par_Val, Int_Par_Ref)
+One_Fifty Int_1_Par_Val;
+One_Fifty Int_2_Par_Val;
+One_Fifty *Int_Par_Ref;
+/**********************************************/
+ /* executed three times */
+ /* first call: Int_1_Par_Val == 2, Int_2_Par_Val == 3, */
+ /* Int_Par_Ref becomes 7 */
+ /* second call: Int_1_Par_Val == 10, Int_2_Par_Val == 5, */
+ /* Int_Par_Ref becomes 17 */
+ /* third call: Int_1_Par_Val == 6, Int_2_Par_Val == 10, */
+ /* Int_Par_Ref becomes 18 */
+{
+ One_Fifty Int_Loc;
+
+ Int_Loc = Int_1_Par_Val + 2;
+ *Int_Par_Ref = Int_2_Par_Val + Int_Loc;
+} /* Proc_7 */
+
+
+void Proc_8 (Arr_1_Par_Ref, Arr_2_Par_Ref, Int_1_Par_Val, Int_2_Par_Val)
+/*********************************************************************/
+ /* executed once */
+ /* Int_Par_Val_1 == 3 */
+ /* Int_Par_Val_2 == 7 */
+Arr_1_Dim Arr_1_Par_Ref;
+Arr_2_Dim Arr_2_Par_Ref;
+int Int_1_Par_Val;
+int Int_2_Par_Val;
+{
+ REG One_Fifty Int_Index;
+ REG One_Fifty Int_Loc;
+
+ Int_Loc = Int_1_Par_Val + 5;
+ Arr_1_Par_Ref [Int_Loc] = Int_2_Par_Val;
+ Arr_1_Par_Ref [Int_Loc+1] = Arr_1_Par_Ref [Int_Loc];
+ Arr_1_Par_Ref [Int_Loc+30] = Int_Loc;
+ for (Int_Index = Int_Loc; Int_Index <= Int_Loc+1; ++Int_Index)
+ Arr_2_Par_Ref [Int_Loc] [Int_Index] = Int_Loc;
+ Arr_2_Par_Ref [Int_Loc] [Int_Loc-1] += 1;
+ Arr_2_Par_Ref [Int_Loc+20] [Int_Loc] = Arr_1_Par_Ref [Int_Loc];
+ Int_Glob = 5;
+} /* Proc_8 */
+
+
+Enumeration Func_1 (Capital_Letter Ch_1_Par_Val, Capital_Letter Ch_2_Par_Val)
+/*************************************************/
+ /* executed three times */
+ /* first call: Ch_1_Par_Val == 'H', Ch_2_Par_Val == 'R' */
+ /* second call: Ch_1_Par_Val == 'A', Ch_2_Par_Val == 'C' */
+ /* third call: Ch_1_Par_Val == 'B', Ch_2_Par_Val == 'C' */
+{
+ Capital_Letter Ch_1_Loc;
+ Capital_Letter Ch_2_Loc;
+
+ Ch_1_Loc = Ch_1_Par_Val;
+ Ch_2_Loc = Ch_1_Loc;
+ if (Ch_2_Loc != Ch_2_Par_Val)
+ /* then, executed */
+ return (Ident_1);
+ else /* not executed */
+ {
+ Ch_1_Glob = Ch_1_Loc;
+ return (Ident_2);
+ }
+} /* Func_1 */
+
+
+
+Boolean Func_2 (Str_1_Par_Ref, Str_2_Par_Ref)
+/*************************************************/
+ /* executed once */
+ /* Str_1_Par_Ref == "DHRYSTONE PROGRAM, 1'ST STRING" */
+ /* Str_2_Par_Ref == "DHRYSTONE PROGRAM, 2'ND STRING" */
+
+Str_30 Str_1_Par_Ref;
+Str_30 Str_2_Par_Ref;
+{
+ REG One_Thirty Int_Loc;
+ Capital_Letter Ch_Loc;
+
+ Ch_Loc = 'A';
+ Int_Loc = 2;
+ while (Int_Loc <= 2) /* loop body executed once */
+ if (Func_1 (Str_1_Par_Ref[Int_Loc],
+ Str_2_Par_Ref[Int_Loc+1]) == Ident_1)
+ /* then, executed */
+ {
+ Ch_Loc = 'A';
+ Int_Loc += 1;
+ } /* if, while */
+ if (Ch_Loc >= 'W' && Ch_Loc < 'Z')
+ /* then, not executed */
+ Int_Loc = 7;
+ if (Ch_Loc == 'R')
+ /* then, not executed */
+ return (true);
+ else /* executed */
+ {
+ if (strcmp (Str_1_Par_Ref, Str_2_Par_Ref) > 0)
+ /* then, not executed */
+ {
+ Int_Loc += 7;
+ Int_Glob = Int_Loc;
+ return (true);
+ }
+ else /* executed */
+ return (false);
+ } /* if Ch_Loc */
+} /* Func_2 */
+
+
+Boolean Func_3 (Enum_Par_Val)
+/***************************/
+ /* executed once */
+ /* Enum_Par_Val == Ident_3 */
+Enumeration Enum_Par_Val;
+{
+ Enumeration Enum_Loc;
+
+ Enum_Loc = Enum_Par_Val;
+ if (Enum_Loc == Ident_3)
+ /* then, executed */
+ return (true);
+ else /* not executed */
+ return (false);
+} /* Func_3 */
+
diff --git a/verilog/dv/riscv_regress/tests/hello/Makefile b/verilog/dv/riscv_regress/tests/hello/Makefile
new file mode 100644
index 0000000..0f55d60
--- /dev/null
+++ b/verilog/dv/riscv_regress/tests/hello/Makefile
@@ -0,0 +1,13 @@
+src_dir := $(dir $(lastword $(MAKEFILE_LIST)))
+
+c_src := sc_print.c hello.c
+
+include $(inc_dir)/common.mk
+
+default: log_requested_tgt $(bld_dir)/hello.elf $(bld_dir)/hello.hex $(bld_dir)/hello.dump
+
+log_requested_tgt:
+ echo hello.hex>> $(bld_dir)/test_info
+
+clean:
+ $(RM) $(c_objs) $(asm_objs) $(bld_dir)/hello.elf $(bld_dir)/hello.hex $(bld_dir)/hello.dump
\ No newline at end of file
diff --git a/verilog/dv/riscv_regress/tests/hello/hello.c b/verilog/dv/riscv_regress/tests/hello/hello.c
new file mode 100644
index 0000000..52cf1bc
--- /dev/null
+++ b/verilog/dv/riscv_regress/tests/hello/hello.c
@@ -0,0 +1,7 @@
+#include "sc_print.h"
+
+int main()
+{
+ sc_printf("Hello from SCR1!\n");
+ return 0;
+}
\ No newline at end of file
diff --git a/verilog/dv/riscv_regress/tests/isr_sample/Makefile b/verilog/dv/riscv_regress/tests/isr_sample/Makefile
new file mode 100644
index 0000000..1c95e74
--- /dev/null
+++ b/verilog/dv/riscv_regress/tests/isr_sample/Makefile
@@ -0,0 +1,26 @@
+src_dir := $(dir $(lastword $(MAKEFILE_LIST)))
+
+LDFLAGS := -nostartfiles -nostdlib -march=rv32$(ARCH) -mabi=$(ABI)
+ADD_ASM_MACRO := -DASM
+
+ifeq ($(IPIC) ,1)
+ ADD_ASM_MACRO += -DIPIC_ENABLED
+endif
+
+ifeq ($(VECT_IRQ) ,1)
+ ADD_ASM_MACRO += -DVECT_IRQ_ENABLED
+endif
+asm_src := isr_sample.S
+
+# override ld script
+ld_script := $(inc_dir)/link.ld
+
+include $(inc_dir)/common.mk
+
+default: log_requested_tgt $(bld_dir)/isr_sample.elf $(bld_dir)/isr_sample.hex $(bld_dir)/isr_sample.dump
+
+log_requested_tgt:
+ echo isr_sample.hex >> $(bld_dir)/test_info
+
+clean:
+ $(RM)$(asm_objs) $(bld_dir)/isr_sample.elf $(bld_dir)/isr_sample.hex $(bld_dir)/isr_sample.dump
\ No newline at end of file
diff --git a/verilog/dv/riscv_regress/tests/isr_sample/isr_sample.S b/verilog/dv/riscv_regress/tests/isr_sample/isr_sample.S
new file mode 100644
index 0000000..d7b3d63
--- /dev/null
+++ b/verilog/dv/riscv_regress/tests/isr_sample/isr_sample.S
@@ -0,0 +1,291 @@
+#include "riscv_macros.h"
+#include "sc_test.h"
+
+.altmacro
+// global interrupt bit
+#define MSIE (1 << IRQ_M_SOFT) //machine software interrupt enable
+#define MTIE (1 << IRQ_M_TIMER) //machine timer interrupt enable
+#define MEIE (1 << IRQ_M_EXT) //machine external interrupt enable
+#define MCAUSE_EXT_IRQ (1 << 31 | IRQ_M_EXT)
+#define MCAUSE_SOFT_IRQ (1 << 31 | IRQ_M_SOFT)
+#define MCAUSE_TMR_IRQ (1 << 31 | IRQ_M_TIMER)
+
+// IPIC
+#define IRQ_LINES_ADDR 0x10020018 // simulation
+#define TRIG_EXT_IRQ_ADDR 0x10020018 // external irq is triggered when tb memory is set to non-zero // Bit [15:0]
+#define TRIG_SW_IRQ_ADDR 0x10020018 // software irq is triggered when tb memory is set to non-zero // Bit [16]
+
+#define IPIC_EOI 0xBF4 // end of interrupt
+#define IPIC_SOI 0xBF5 // start of interrupt
+#define IPIC_IDX 0xBF6 // index register
+#define IPIC_ICSR 0xBF7 // interrupt control status register
+
+// IPIC Interrupt Constrol Status Register
+#define IPIC_ICSR_IP (1 << 0) // interrupt pending
+#define IPIC_ICSR_IE (1 << 1) // interrupt enable
+#define IPIC_ICSR_IM (1 << 2) // interrupt mode (0/1: level/edge)
+#define IPIC_ICSR_INV (1 << 3) // line inversion
+#define IPIC_ICSR_IS (1 << 4) // in service
+
+// Interrupt lines in use
+#define IPIC_IRQ_LINE9 9
+#define EXT_IRQ_LINE_COMMON 0
+
+#include "timer.h"
+#include "reloc.h"
+
+.macro jmp_sc_exit
+ la t0, sc_exit
+ jr t0
+.endm
+
+ .section .text.init
+ .option norvc
+ .globl _start
+// -----------------------------------------------------------------
+// Trap handlers
+// 0xXXXXXX00
+ .option norvc
+.org (64*3)
+
+//0xXXXXXXC0
+ .balign 64
+machine_trap_entry:
+vec_usr_soft:
+#ifdef VECT_IRQ_ENABLED
+ trap_entry:
+ j _trap_fail
+ vec_supervisor_soft:
+ j _trap_fail
+ vec_reserved1:
+ j _trap_fail
+ vec_machine_soft:
+ j vec_machine_soft_handler
+ vec_usr_tmr:
+ j _trap_fail
+ vec_supervisor_tmr:
+ j _trap_fail
+ vec_reserved2:
+ j _trap_fail
+ vec_machine_tmr:
+ j vec_machine_tmr_handler
+ vec_usr_ext:
+ j _trap_fail
+ vec_supervisor_ext:
+ j _trap_fail
+ vec_reserved3:
+ j _trap_fail
+ vec_machine_ext:
+ j vec_machine_ext_handler
+ vec_reserved4:
+ j _trap_fail
+ j _trap_fail
+ j _trap_fail
+ j _trap_fail
+#else
+ trap_entry:
+ j direct_irq_handler
+ vec_supervisor_soft:
+ j _trap_fail
+ vec_reserved1:
+ j _trap_fail
+ vec_machine_soft:
+ j _trap_fail
+ vec_usr_tmr:
+ j _trap_fail
+ vec_supervisor_tmr:
+ j _trap_fail
+ vec_reserved2:
+ j _trap_fail
+ vec_machine_tmr:
+ j _trap_fail
+ vec_usr_ext:
+ j _trap_fail
+ vec_supervisor_ext:
+ j _trap_fail
+ vec_reserved3:
+ j _trap_fail
+ vec_machine_ext:
+ j _trap_fail
+ vec_reserved4:
+ j _trap_fail
+ j _trap_fail
+ j _trap_fail
+ j _trap_fail
+
+#endif // ifdef VECT_IRQ_ENABLED
+
+
+ .balign 64
+_start:
+ la t0, machine_trap_entry
+ csrw mtvec, t0
+
+ la t0, test_start
+ jr (t0)
+
+// -----------------------------------------------------------------
+ .option norvc
+ .balign 64
+test_start:
+
+ la t0, trap_entry
+ csrw mtvec, t0 // set mtvec to trap_entry
+ #ifdef VECT_IRQ_ENABLED
+ csrsi mtvec, 1 // set vectored mode
+ #else
+ csrsi mtvec, 0 // set direct mode
+ #endif
+
+ /// configuring timer interrupt ///
+ _reset_mtimecmp; // reset timer
+ _run_timer; // run timer
+ csrs mstatus, MSTATUS_MIE // enable global interrupt
+ li a0, MTIE
+ csrs mie, a0 // enable timer interrupt
+ li t2, 0 // reset timer counter = 0 (updated in isr)
+ _read_mtime s1 // read timer value
+ addi s1, s1, 256
+ _write_mtimecmp_32 s1
+ wfi
+
+
+ /// configuring external interrupt ///
+ csrw mie, zero // disable all interrupts
+ li t0, IRQ_LINES_ADDR
+ sh zero, (t0) // set all exterinal interrupt lines low
+ #ifdef IPIC_ENABLED
+ li t0, IPIC_IRQ_LINE9
+ csrw IPIC_IDX, t0 // set IPIC to expect interupt on line 9...
+ li t0, (IPIC_ICSR_IE | IPIC_ICSR_IM)
+ csrw IPIC_ICSR, t0 // ....enable interrupt,set edge interrupt mode
+ #endif
+ li t0, MEIE
+ csrs mie, t0 // enable external interrupt
+ li t0, TRIG_EXT_IRQ_ADDR
+ #ifdef IPIC_ENABLED
+ li t1, (1 << IPIC_IRQ_LINE9)
+ #else
+ li t1, (1 << EXT_IRQ_LINE_COMMON)
+ #endif
+ sh t1, (t0) //send command to generate external interrupt on line 9 to testbench
+ nop
+ nop
+ nop
+ nop //wait for external interrupt
+
+
+ /// configuring software interrupt ///
+ csrw mie, zero // disable all interrupts
+ li t0, TRIG_SW_IRQ_ADDR
+ li t1, 0x00010000 // Soft ireq bit [16]
+ sw t1, (t0) //send command to generate software interrupt
+ li t0, MSIE
+ csrs mie, t0 // enable software interrupt
+ nop
+ nop
+ nop
+ nop //wait for software interrupt
+
+ li s1, 3
+ li a0, 0
+ beq t2, s1, 1f
+ li a0, -1
+1:
+ jmp_sc_exit
+
+
+#ifndef VECT_IRQ_ENABLED
+
+direct_irq_handler:
+ csrr a1, mcause
+ li a5, MCAUSE_TMR_IRQ //0x80000007 -- mcause = tmr.irq
+ beq a1, a5, vec_machine_tmr_handler
+ li a5, MCAUSE_SOFT_IRQ //0x80000003 -- mcause = soft.irq
+ beq a1, a5, vec_machine_soft_handler
+ li a5, MCAUSE_EXT_IRQ //0x8000000B -- mcause = ext.irq
+ beq a1, a5, vec_machine_ext_handler
+ mret
+#endif
+
+vec_machine_tmr_handler:
+ csrr a1, mcause
+ li a5, MCAUSE_TMR_IRQ //0x80000007 -- mcause = tmr.irq
+ li a0, -1
+ bne a1, a5, check_fail
+ csrr t1, mip
+ li t0, MIP_MTIP
+ and t0, t1, t0
+ beqz t0, check_fail
+#ifdef IPIC_ENABLED
+ csrw IPIC_SOI, zero
+ csrw IPIC_EOI, zero
+#endif
+ _reset_mtimecmp
+ csrr t1, mip
+ andi t1, t1, MIP_MTIP
+ bne t1, zero, check_fail
+ addi t2, t2, 1 // tmr irq counter update
+ mret
+
+vec_machine_ext_handler:
+
+ csrr a1, mcause
+ li a5, MCAUSE_EXT_IRQ //0x8000000B -- mcause = ext.irq
+ li a0, -1
+ bne a1, a5, check_fail
+ csrr t1, mip
+ li t0, MIP_MEIP
+ and t0, t1, t0
+ beqz t0, check_fail
+#ifdef IPIC_ENABLED
+ csrw IPIC_SOI, zero
+ csrw IPIC_EOI, zero
+#endif
+ li t0, MEIE
+ csrc mie, t0 // disable software interrupt
+
+ li t0, TRIG_EXT_IRQ_ADDR
+ li t1, EXT_IRQ_LINE_COMMON
+ sh t1, (t0) // send command to disable external interrupt
+
+ csrr t1, mip
+ li t0, MIP_MEIP
+ bne t1, zero, check_fail
+ addi t2, t2, 1 // ext irq counter update
+ mret
+
+vec_machine_soft_handler:
+ csrr a1, mcause
+ li a5, MCAUSE_SOFT_IRQ //0x80000003 -- mcause = soft.irq
+ li a0, -1
+ bne a1, a5, check_fail
+ csrr t1, mip
+ li t0, MIP_MSIP
+ and t0, t1, t0
+ beqz t0, check_fail
+ #ifdef IPIC_ENABLED
+ csrw IPIC_SOI, zero
+ csrw IPIC_EOI, zero
+ #endif
+ li t0, MSIE
+ csrc mie, t0 // disable software interrupt
+ li t0, TRIG_SW_IRQ_ADDR
+ li t1, 0x00000000
+ sw t1, (t0) // send command to stop generating software interrupt
+ li t0, MIP_MSIP
+ csrc mip, t0
+ csrr t1, mip
+ li t0, MIP_MSIP
+ and t1, t1, t0
+ bne t1, zero, check_fail
+ addi t2, t2, 1 // ext irq counter update
+ mret
+
+check_fail:
+ la t0, sc_exit
+ jr t0
+
+_trap_fail:
+ li a0, -1
+ j check_fail
diff --git a/verilog/dv/riscv_regress/tests/isr_sample/timer.h b/verilog/dv/riscv_regress/tests/isr_sample/timer.h
new file mode 100644
index 0000000..b81bcc8
--- /dev/null
+++ b/verilog/dv/riscv_regress/tests/isr_sample/timer.h
@@ -0,0 +1,97 @@
+#ifndef __TIMER__H
+#define __TIMER__H
+
+
+
+#define MEM_MTIME_MASK 0xF0000000
+#define MEM_MTIME_CTRL 0x00490000
+#define MEM_MTIME_DIV 0x00490004
+#define MEM_MTIME 0x00490008
+#define MEM_MTIMEH 0x0049000C
+#define MEM_MTIMECMP 0x00490010
+#define MEM_MTIMECMPH 0x00490014
+
+#define TMP t0
+#define TMP2 t1
+#define TMP3 t2
+
+// Reset
+.macro _reset_mtime
+ li TMP, MEM_MTIME
+ sw zero, 0(TMP)
+ sw zero, 4(TMP)
+.endm
+
+.macro _reset_mtimecmp
+ li TMP, MEM_MTIMECMP
+ not TMP2, zero
+ sw TMP2, 0(TMP)
+ sw TMP2, 4(TMP)
+.endm
+
+// Write
+.macro _write_mtime_ctrl reg
+ li TMP, MEM_MTIME_CTRL
+ sw \reg, 0(TMP)
+.endm
+
+.macro _write_mtime_div reg
+ li TMP, MEM_MTIME_DIV
+ sw \reg, 0(TMP)
+.endm
+
+.macro _write_mtimecmp_32 reg
+ li TMP, MEM_MTIMECMP
+ li TMP2, -1
+ sw TMP2, 0(TMP)
+ sw zero, 4(TMP)
+ sw \reg, 0(TMP)
+.endm
+
+.macro _write_mtime reg
+ li TMP, MEM_MTIME
+ sw \reg, 0(TMP)
+.endm
+
+.macro _read_mtime reg
+ li TMP, MEM_MTIME
+ lw \reg, 0(TMP)
+.endm
+
+// Read
+.macro _read_mtimecmp reg
+ li TMP, MEM_MTIMECMP
+ lw \reg, 0(TMP)
+.endm
+
+.macro _read_mtime_ctrl reg
+ li TMP, MEM_MTIME_CTRL
+ lw \reg, 0(TMP)
+.endm
+
+.macro _read_mtime_div reg
+ li TMP, MEM_MTIME_DIV
+ lw \reg, 0(TMP)
+.endm
+
+// Misc
+.macro _run_timer
+ li TMP, MEM_MTIME_CTRL
+ lw TMP2, 0(TMP)
+ li TMP3, (1 << SCR1_MTIME_CTRL_EN)
+ or TMP2, TMP2, TMP3
+ sw TMP2, 0(TMP)
+.endm
+
+.macro _stop_timer
+ li TMP, MEM_MTIME_CTRL
+ lw TMP2, 0(TMP)
+ li TMP3, (1 << SCR1_MTIME_CTRL_EN)
+ not TMP3, TMP3
+ and TMP2, TMP2, TMP3
+ sw TMP2, 0(TMP)
+.endm
+
+
+
+#endif // #ifndef __TIMER__H
diff --git a/verilog/dv/riscv_regress/tests/riscv_compliance/Makefile b/verilog/dv/riscv_regress/tests/riscv_compliance/Makefile
new file mode 100644
index 0000000..e04fc87
--- /dev/null
+++ b/verilog/dv/riscv_regress/tests/riscv_compliance/Makefile
@@ -0,0 +1,202 @@
+## @file
+## Syntacore SCR* tests
+##
+## @copyright 2015-2018 Syntacore. All rights reserved.
+## RISCV-Compliance
+##
+
+ARCH ?=im
+override ARCH:=rv32$(ARCH)
+
+src_dir := $(CURDIR)
+RISCV_COMPLIANCE_TESTS := $(src_dir)/../../dependencies/riscv-compliance/
+
+#I IM IMC IC
+#EM EMC EC
+
+ifeq (rv32e,$(findstring rv32e,$(ARCH)))
+ $(info >>> RV32E - no compliance tests)
+else ## ifdef SCR_BASE_RVE_EXT
+ #ifeq (rv32i,$(findstring rv32i,$(ARCH)))
+ ifeq ($(ARCH),$(filter $(ARCH),rv32i rv32im rv32imc rv32ic))
+ $(info >>> I32 TESTS)
+ included_i += $(filter %.S,\
+ $(wildcard $(RISCV_COMPLIANCE_TESTS)/riscv-test-suite/rv32i/src/*))
+ included_i += $(filter %.S,\
+ $(wildcard $(RISCV_COMPLIANCE_TESTS)/riscv-test-suite/rv32Zicsr/src/*))
+ included_i += $(filter %.S,\
+ $(wildcard $(RISCV_COMPLIANCE_TESTS)/riscv-test-suite/rv32Zifencei/src/*))
+ compliance_set += $(included_i)
+ endif
+
+ #$(if or ifeq(rv32im,$(findstring rv32im,$(ARCH))), (rv32imc,$(findstring rv32imc,$(ARCH))))
+ ifeq ($(ARCH),$(filter $(ARCH), rv32im rv32imc))
+ $(info >>> IM32 TESTS)
+ included_im += $(filter %.S,\
+ $(wildcard $(RISCV_COMPLIANCE_TESTS)/riscv-test-suite/rv32im/src/*))
+ compliance_set += $(included_im)
+ endif ##
+
+ ifeq (rv32imc,$(findstring rv32imc,$(ARCH)))
+ $(info >>> IMC32 TESTS)
+ included_imc += $(filter %.S,\
+ $(wildcard $(RISCV_COMPLIANCE_TESTS)/riscv-test-suite/rv32imc/src/*))
+ compliance_set += $(included_imc)
+ endif ## ifeq (rv32imc,$(findstring rv32imc,$(ARCH)))
+ ifeq (rv32ic,$(findstring rv32ic,$(ARCH)))
+ endif
+endif ##
+
+
+$(info >>>$(ARCH) set included)
+
+ifeq ($(compliance_set),)
+$(info >>> No compliance tests included)
+endif
+
+$(info >>>>> compliance set: $(compliance_set))
+
+dst_dir := $(bld_dir)
+test_name := riscv_compliance
+bld_dir := $(addprefix $(dst_dir)/, $(test_name))
+obj_dir := $(bld_dir)/riscv_compliance_objs
+
+#cut_list += scall csr shamt simple
+cut_list += I-MISALIGN_JMP-01 I-MISALIGN_LDST-01 I-EBREAK-01 I-ECALL-01
+reference_src += $(wildcard $(RISCV_COMPLIANCE_TESTS)/riscv-test-suite/rv32i*/*/*.reference_output)
+reference_src += $(wildcard $(RISCV_COMPLIANCE_TESTS)/riscv-test-suite/rv32Zi*/*/*.reference_output)
+testnames := $(basename $(notdir $(compliance_set)))
+filtered := $(filter-out $(cut_list),$(testnames))
+objs := $(addprefix $(bld_dir)/,$(filtered:%=%.o))
+test_elf := $(addprefix $(dst_dir)/compliance_,$(filtered:%=%.elf))
+test_hex := $(addprefix $(dst_dir)/compliance_,$(filtered:%=%.hex))
+test_dump := $(addprefix $(bld_dir)/compliance_,$(filtered:%=%.dump))
+
+compliance_macros_file := $(root_dir)/tests/riscv_compliance/compliance_io.h
+compliance_output ?= true
+
+testnames_i := $(basename $(notdir $(included_i)))
+testnames_im := $(basename $(notdir $(included_im)))
+testnames_imc := $(basename $(notdir $(included_imc)))
+filtered_i := $(filter-out $(cut_list),$(testnames_i))
+filtered_im := $(filter-out $(cut_list),$(testnames_im))
+filtered_imc := $(filter-out $(cut_list),$(testnames_imc))
+
+# ARCH_FLAGS := -Wa,-march=rv32im -march=rv32im
+# ARCH_FLAGS_C := -Wa,-march=rv32imc -march=rv32imc
+CFLAGS := -I$(inc_dir) -I$(src_dir) -DASM -mabi=ilp32 -D__riscv_xlen=32 -w
+LDFLAGS := -static -fvisibility=hidden -nostdlib -nostartfiles -T$(inc_dir)/link.ld -march=$(ARCH) -mabi=ilp32
+GCCVERSIONGT7 := $(shell expr `$(RISCV_GCC) -dumpfullversion | cut -f1 -d'.'` \> 7)
+ifeq "$(GCCVERSIONGT7)" "1"
+ LDFLAGS += -mno-relax
+endif
+VPATH += $(src_dir) $(bld_dir) $(obj_dir) $(asm_path) $(ref_path) $(RISCV_COMPLIANCE_TESTS)
+
+ifeq ($(compliance_output), true)
+CFLAGS += -D_COMPLIANCE_OUTPUT
+endif
+
+default: clean log_requested_tgt check_version cp_asm ref_data $(test_elf) $(test_hex) $(test_dump)
+
+define compile_template
+$(obj_dir)/$(1).o: $(obj_dir) cp_asm
+ $(RISCV_GCC) -c $$(bld_dir)/compliance_asm/$(1).S $$(CFLAGS) -Wa,$(2) $(2) -o $$@
+endef
+
+define preprocessing
+for test_asm in $(1); do \
+march_tmp=$$test_asm ; \
+march_tmp=$${march_tmp%/src*} ; \
+march_tmp=$$(basename $$march_tmp) ; \
+file_name="$$(basename $${test_asm})" ; \
+$(RISCV_GCC) $(CFLAGS) -Wa,$(2) $(2) -E $$test_asm \
+-o $(bld_dir)/compliance_asm/$$file_name ; \
+done
+endef
+
+$(foreach SRC,$(filtered_i),$(eval $(call compile_template,$(SRC),-march=rv32i)))
+$(foreach SRC,$(filtered_im),$(eval $(call compile_template,$(SRC),-march=rv32im)))
+$(foreach SRC,$(filtered_imc),$(eval $(call compile_template,$(SRC),-march=rv32imc)))
+
+
+log_requested_tgt: $(bld_dir)
+ $(foreach test_name, $(filtered), $(eval $(shell echo compliance_$(test_name).hex >> $(bld_dir)/../test_info)))
+
+$(bld_dir) :
+ mkdir -p $(bld_dir)
+
+$(obj_dir) : | ref_data
+ mkdir -p $(obj_dir)
+
+$(dst_dir)/compliance_%.elf: $(obj_dir)/%.o | $(dep_files)
+ $(RISCV_GCC) $^ $(LDFLAGS) -o $@ -g
+
+$(dst_dir)/compliance_%.hex: $(dst_dir)/compliance_%.elf
+ $(RISCV_ROM_OBJCOPY) $^ $@
+ $(RISCV_RAM_OBJCOPY) $^ $@.ram
+ #assign 0x0048_0xxx to 0x0000_0xxx to map to TCM Memory
+ sed -i 's/@00480/@00000/g' $@.ram
+
+$(bld_dir)/compliance_%.dump: $(dst_dir)/compliance_%.elf
+ $(RISCV_OBJDUMP) -D -w -x -S $^ > $@
+
+ref_data:
+ mkdir -p $(bld_dir)/ref_data
+ for files in $(reference_src) ; do \
+ sed_input=$$files ; \
+ sed_output=$$(basename $${files%.*}) ; \
+ sed "s/\r$$//; \
+ s/\(........\)/\1,/g; \
+ s/.$$//; s/\(.*\),\(.*\),\(.*\),\(.*\)/\4,\3,\2,\1/; \
+ s/\(.........\)/\10x/g; s/^/0x/; s/$$/,/; $$ s/.$$//" $$sed_input > $(bld_dir)/ref_data/$$sed_output; \
+ done
+
+cp_asm:
+ mkdir -p $(bld_dir)/compliance_asm
+ $(call preprocessing,$(included_i),-march=rv32i)
+ $(call preprocessing,$(included_im),-march=rv32im)
+ $(call preprocessing,$(included_imc),-march=rv32imc)
+
+
+riscv_compliance_tests_dir := $(if $(RISCV_COMPLIANCE_TESTS), $(RISCV_COMPLIANCE_TESTS), ./undefined)
+riscv_tests_commit := d51259b2a949be3af02e776c39e135402675ac9b
+## commit hash readed from local copy of https://github.com/riscv/riscv-compliance
+tmp_commit = $(shell cd $(riscv_compliance_tests_dir) 2>/dev/null && git log -1 | grep "commit" | cut -f2 -d ' ')
+is_commit_good = $(if $(subst $(riscv_tests_commit),,$(tmp_commit)),false,true)
+
+# Color
+RED=\033[0;31m
+NC=\033[0m
+
+check_version : $(riscv_compliance_tests_dir)
+ @if [ ! -d $(riscv_compliance_tests_dir) ]; then \
+ echo -e "$(RED)==========================================================================" &&\
+ echo " Error! Environment variable RISCV_COMPLIANCE_TESTS='$(riscv_compliance_tests_dir)' " &&\
+ echo " directory not exist!" && \
+ echo "==========================================================================$(NC)" ; \
+ fi
+ifneq ($(is_commit_good),true)
+ @echo -e "$(RED)=========================================================================="
+ @echo " Warning! Execution of test code is not guaranteed "
+ @echo " while using the current commit of repository located at : $(riscv_compliance_tests_dir) ."
+ @echo " "
+ @echo " riscv_compliance repository must point to commit $(riscv_tests_commit)!"
+ @echo -e "==========================================================================$(NC)"
+endif
+
+$(riscv_compliance_tests_dir) :.
+ifndef RISCV_COMPLIANCE_TESTS
+ @echo -e "$(RED)=========================================================================="
+ @echo " Error! Environment variable RISCV_COMPLIANCE_TESTS not set!"
+ @echo " You must set the environment variable RISCV_COMPLIANCE_TESTS"
+ @echo " The variable should point to the local copy of the"
+ @echo " repository https://github.com/riscv/riscv-compliance"
+ @echo " with the commit $(riscv_tests_commit)"
+ @echo -e "==========================================================================$(NC)"
+ exit 1
+endif
+
+clean:
+ $(RM) -R $(test_elf) $(test_hex) $(bld_dir)
+
+.PHONY: check_version clean ref_data cp_asm default
diff --git a/verilog/dv/riscv_regress/tests/riscv_compliance/aw_test_macros.h b/verilog/dv/riscv_regress/tests/riscv_compliance/aw_test_macros.h
new file mode 100644
index 0000000..3e052a1
--- /dev/null
+++ b/verilog/dv/riscv_regress/tests/riscv_compliance/aw_test_macros.h
@@ -0,0 +1,683 @@
+/*
+ COPY OF /riscv-compliance/riscv-test-env/aw_test_macros.h
+ */
+
+// See LICENSE for license details.
+
+#ifndef __TEST_MACROS_SCALAR_H
+#define __TEST_MACROS_SCALAR_H
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+
+#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1))
+
+#define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1: srli a0, a0, 31; la t0, begin_signature; sw a0, 0(t0)
+
+#define TESTNUM gp
+
+#define SWSIG( testnum, testreg ) \
+ la x28, test_res; \
+ sw testreg, (testnum<<2)(x28); \
+
+#
+# Address = base+(testnum<<2)
+# sw testreg, (testnum<<2)(basereg)
+#
+#define TEST_CASE( testnum, testreg, correctval, code... ) \
+test_ ## testnum: \
+ code; \
+ li x29, MASK_XLEN(correctval); \
+ li TESTNUM, testnum; \
+ SWSIG(testnum,testreg); \
+ bne testreg, x29, fail;
+
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+
+#define TEST_INSERT_NOPS_0
+#define TEST_INSERT_NOPS_1 nop; TEST_INSERT_NOPS_0
+#define TEST_INSERT_NOPS_2 nop; TEST_INSERT_NOPS_1
+#define TEST_INSERT_NOPS_3 nop; TEST_INSERT_NOPS_2
+#define TEST_INSERT_NOPS_4 nop; TEST_INSERT_NOPS_3
+#define TEST_INSERT_NOPS_5 nop; TEST_INSERT_NOPS_4
+#define TEST_INSERT_NOPS_6 nop; TEST_INSERT_NOPS_5
+#define TEST_INSERT_NOPS_7 nop; TEST_INSERT_NOPS_6
+#define TEST_INSERT_NOPS_8 nop; TEST_INSERT_NOPS_7
+#define TEST_INSERT_NOPS_9 nop; TEST_INSERT_NOPS_8
+#define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9
+
+
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+
+#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
+
+#define TEST_IMM_OP( testnum, inst, result, val1, imm ) \
+ TEST_CASE( testnum, x30, result, \
+ li x1, MASK_XLEN(val1); \
+ inst x30, x1, SEXT_IMM(imm); \
+ )
+
+#define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \
+ TEST_CASE( testnum, x1, result, \
+ li x1, MASK_XLEN(val1); \
+ inst x1, x1, SEXT_IMM(imm); \
+ )
+
+#define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
+ TEST_CASE( testnum, x6, result, \
+ li x4, 0; \
+1: li x1, MASK_XLEN(val1); \
+ inst x30, x1, SEXT_IMM(imm); \
+ TEST_INSERT_NOPS_ ## nop_cycles \
+ addi x6, x30, 0; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+ )
+
+#define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
+ TEST_CASE( testnum, x30, result, \
+ li x4, 0; \
+1: li x1, MASK_XLEN(val1); \
+ TEST_INSERT_NOPS_ ## nop_cycles \
+ inst x30, x1, SEXT_IMM(imm); \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+ )
+
+#define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \
+ TEST_CASE( testnum, x1, result, \
+ inst x1, x0, SEXT_IMM(imm); \
+ )
+
+#define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \
+ TEST_CASE( testnum, x0, 0, \
+ li x1, MASK_XLEN(val1); \
+ inst x0, x1, SEXT_IMM(imm); \
+ )
+
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+
+#define TEST_R_OP( testnum, inst, result, val1 ) \
+ TEST_CASE( testnum, x30, result, \
+ li x1, val1; \
+ inst x30, x1; \
+ )
+
+#define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \
+ TEST_CASE( testnum, x1, result, \
+ li x1, val1; \
+ inst x1, x1; \
+ )
+
+#define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \
+ TEST_CASE( testnum, x6, result, \
+ li x4, 0; \
+1: li x1, val1; \
+ inst x30, x1; \
+ TEST_INSERT_NOPS_ ## nop_cycles \
+ addi x6, x30, 0; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+ )
+
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+
+#define TEST_RR_OP( testnum, inst, result, val1, val2 ) \
+ TEST_CASE( testnum, x30, result, \
+ li x1, MASK_XLEN(val1); \
+ li x2, MASK_XLEN(val2); \
+ inst x30, x1, x2; \
+ )
+
+#define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \
+ TEST_CASE( testnum, x1, result, \
+ li x1, MASK_XLEN(val1); \
+ li x2, MASK_XLEN(val2); \
+ inst x1, x1, x2; \
+ )
+
+#define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \
+ TEST_CASE( testnum, x2, result, \
+ li x1, MASK_XLEN(val1); \
+ li x2, MASK_XLEN(val2); \
+ inst x2, x1, x2; \
+ )
+
+#define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \
+ TEST_CASE( testnum, x1, result, \
+ li x1, MASK_XLEN(val1); \
+ inst x1, x1, x1; \
+ )
+
+#define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \
+ TEST_CASE( testnum, x6, result, \
+ li x4, 0; \
+1: li x1, MASK_XLEN(val1); \
+ li x2, MASK_XLEN(val2); \
+ inst x30, x1, x2; \
+ TEST_INSERT_NOPS_ ## nop_cycles \
+ addi x6, x30, 0; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+ )
+
+#define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
+ TEST_CASE( testnum, x30, result, \
+ li x4, 0; \
+1: li x1, MASK_XLEN(val1); \
+ TEST_INSERT_NOPS_ ## src1_nops \
+ li x2, MASK_XLEN(val2); \
+ TEST_INSERT_NOPS_ ## src2_nops \
+ inst x30, x1, x2; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+ )
+
+#define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
+ TEST_CASE( testnum, x30, result, \
+ li x4, 0; \
+1: li x2, MASK_XLEN(val2); \
+ TEST_INSERT_NOPS_ ## src1_nops \
+ li x1, MASK_XLEN(val1); \
+ TEST_INSERT_NOPS_ ## src2_nops \
+ inst x30, x1, x2; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+ )
+
+#define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \
+ TEST_CASE( testnum, x2, result, \
+ li x1, MASK_XLEN(val); \
+ inst x2, x0, x1; \
+ )
+
+#define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \
+ TEST_CASE( testnum, x2, result, \
+ li x1, MASK_XLEN(val); \
+ inst x2, x1, x0; \
+ )
+
+#define TEST_RR_ZEROSRC12( testnum, inst, result ) \
+ TEST_CASE( testnum, x1, result, \
+ inst x1, x0, x0; \
+ )
+
+#define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \
+ TEST_CASE( testnum, x0, 0, \
+ li x1, MASK_XLEN(val1); \
+ li x2, MASK_XLEN(val2); \
+ inst x0, x1, x2; \
+ )
+
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+
+#define TEST_LD_OP( testnum, inst, result, offset, base ) \
+ TEST_CASE( testnum, x30, result, \
+ la x1, base; \
+ inst x30, offset(x1); \
+ )
+
+#define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \
+ TEST_CASE( testnum, x30, result, \
+ la x1, base; \
+ li x2, result; \
+ store_inst x2, offset(x1); \
+ load_inst x30, offset(x1); \
+ )
+
+#define TEST_LD_DEST_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ SWSIG (testnum, TESTNUM);\
+ li x4, 0; \
+1: la x1, base; \
+ inst x30, offset(x1); \
+ TEST_INSERT_NOPS_ ## nop_cycles \
+ addi x6, x30, 0; \
+ li x29, result; \
+ bne x6, x29, fail; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b; \
+
+#define TEST_LD_SRC1_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ SWSIG (testnum, TESTNUM);\
+ li x4, 0; \
+1: la x1, base; \
+ TEST_INSERT_NOPS_ ## nop_cycles \
+ inst x30, offset(x1); \
+ li x29, result; \
+ bne x30, x29, fail; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+
+#define TEST_ST_SRC12_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ SWSIG (testnum, TESTNUM);\
+ li x4, 0; \
+1: li x1, result; \
+ TEST_INSERT_NOPS_ ## src1_nops \
+ la x2, base; \
+ TEST_INSERT_NOPS_ ## src2_nops \
+ store_inst x1, offset(x2); \
+ load_inst x30, offset(x2); \
+ li x29, result; \
+ bne x30, x29, fail; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+
+#define TEST_ST_SRC21_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ SWSIG (testnum, TESTNUM);\
+ li x4, 0; \
+1: la x2, base; \
+ TEST_INSERT_NOPS_ ## src1_nops \
+ li x1, result; \
+ TEST_INSERT_NOPS_ ## src2_nops \
+ store_inst x1, offset(x2); \
+ load_inst x30, offset(x2); \
+ li x29, result; \
+ bne x30, x29, fail; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+
+#define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2 ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ SWSIG (testnum, TESTNUM);\
+ li x1, val1; \
+ li x2, val2; \
+ inst x1, x2, 2f; \
+ bne x0, TESTNUM, fail; \
+1: bne x0, TESTNUM, 3f; \
+2: inst x1, x2, 1b; \
+ bne x0, TESTNUM, fail; \
+3:
+
+#define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ SWSIG (testnum, TESTNUM);\
+ li x1, val1; \
+ li x2, val2; \
+ inst x1, x2, 1f; \
+ bne x0, TESTNUM, 2f; \
+1: bne x0, TESTNUM, fail; \
+2: inst x1, x2, 1b; \
+3:
+
+#define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ SWSIG (testnum, TESTNUM);\
+ li x4, 0; \
+1: li x1, val1; \
+ TEST_INSERT_NOPS_ ## src1_nops \
+ li x2, val2; \
+ TEST_INSERT_NOPS_ ## src2_nops \
+ inst x1, x2, fail; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+
+#define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ SWSIG (testnum, TESTNUM);\
+ li x4, 0; \
+1: li x2, val2; \
+ TEST_INSERT_NOPS_ ## src1_nops \
+ li x1, val1; \
+ TEST_INSERT_NOPS_ ## src2_nops \
+ inst x1, x2, fail; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+
+#define TEST_JR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ SWSIG (testnum, TESTNUM);\
+ li x4, 0; \
+1: la x6, 2f; \
+ TEST_INSERT_NOPS_ ## nop_cycles \
+ inst x6; \
+ bne x0, TESTNUM, fail; \
+2: addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+
+#define TEST_JALR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ SWSIG (testnum, TESTNUM);\
+ li x4, 0; \
+1: la x6, 2f; \
+ TEST_INSERT_NOPS_ ## nop_cycles \
+ inst x19, x6, 0; \
+ bne x0, TESTNUM, fail; \
+2: addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+
+
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+
+#define qNaNf 0f:7fc00000
+#define sNaNf 0f:7f800001
+#define qNaN 0d:7ff8000000000000
+#define sNaN 0d:7ff0000000000001
+
+#define TEST_FP_OP_S_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ SWSIG (testnum, TESTNUM);\
+ la a0, test_ ## testnum ## _data ;\
+ flw f0, 0(a0); \
+ flw f1, 4(a0); \
+ flw f2, 8(a0); \
+ lw a3, 12(a0); \
+ code; \
+ fsflags a1, x0; \
+ li a2, flags; \
+ bne a0, a3, fail; \
+ bne a1, a2, fail; \
+ .pushsection .data; \
+ .align 2; \
+ test_ ## testnum ## _data: \
+ .float val1; \
+ .float val2; \
+ .float val3; \
+ .result; \
+ .popsection
+
+#define TEST_FP_OP_D_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ SWSIG (testnum, TESTNUM);\
+ la a0, test_ ## testnum ## _data ;\
+ fld f0, 0(a0); \
+ fld f1, 8(a0); \
+ fld f2, 16(a0); \
+ ld a3, 24(a0); \
+ code; \
+ fsflags a1, x0; \
+ li a2, flags; \
+ bne a0, a3, fail; \
+ bne a1, a2, fail; \
+ .pushsection .data; \
+ .align 3; \
+ test_ ## testnum ## _data: \
+ .double val1; \
+ .double val2; \
+ .double val3; \
+ .result; \
+ .popsection
+
+// TODO: assign a separate mem location for the comparison address?
+#define TEST_FP_OP_D32_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ SWSIG (testnum, TESTNUM);\
+ la a0, test_ ## testnum ## _data ;\
+ fld f0, 0(a0); \
+ fld f1, 8(a0); \
+ fld f2, 16(a0); \
+ lw a3, 24(a0); \
+ lw t1, 28(a0); \
+ code; \
+ fsflags a1, x0; \
+ li a2, flags; \
+ bne a0, a3, fail; \
+ bne t1, t2, fail; \
+ bne a1, a2, fail; \
+ .pushsection .data; \
+ .align 3; \
+ test_ ## testnum ## _data: \
+ .double val1; \
+ .double val2; \
+ .double val3; \
+ .result; \
+ .popsection
+
+#define TEST_FCVT_S_D32( testnum, result, val1 ) \
+ TEST_FP_OP_D32_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \
+ fcvt.s.d f3, f0; fcvt.d.s f3, f3; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
+
+#define TEST_FCVT_S_D( testnum, result, val1 ) \
+ TEST_FP_OP_D_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \
+ fcvt.s.d f3, f0; fcvt.d.s f3, f3; fmv.x.d a0, f3)
+
+#define TEST_FCVT_D_S( testnum, result, val1 ) \
+ TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \
+ fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3)
+
+#define TEST_FP_OP1_S( testnum, inst, flags, result, val1 ) \
+ TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, 0.0, 0.0, \
+ inst f3, f0; fmv.x.s a0, f3)
+
+#define TEST_FP_OP1_D32( testnum, inst, flags, result, val1 ) \
+ TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \
+ inst f3, f0; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
+// ^: store computation result in address from a0, load high-word into t2
+
+#define TEST_FP_OP1_D( testnum, inst, flags, result, val1 ) \
+ TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \
+ inst f3, f0; fmv.x.d a0, f3)
+
+#define TEST_FP_OP1_S_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
+ TEST_FP_OP_S_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
+ inst f3, f0; fmv.x.s a0, f3)
+
+#define TEST_FP_OP1_D32_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
+ TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
+ inst f3, f0; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
+// ^: store computation result in address from a0, load high-word into t2
+
+#define TEST_FP_OP1_D_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
+ TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
+ inst f3, f0; fmv.x.d a0, f3)
+
+#define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \
+ TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, 0.0, \
+ inst f3, f0, f1; fmv.x.s a0, f3)
+
+#define TEST_FP_OP2_D32( testnum, inst, flags, result, val1, val2 ) \
+ TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \
+ inst f3, f0, f1; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
+// ^: store computation result in address from a0, load high-word into t2
+
+#define TEST_FP_OP2_D( testnum, inst, flags, result, val1, val2 ) \
+ TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \
+ inst f3, f0, f1; fmv.x.d a0, f3)
+
+#define TEST_FP_OP3_S( testnum, inst, flags, result, val1, val2, val3 ) \
+ TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, val3, \
+ inst f3, f0, f1, f2; fmv.x.s a0, f3)
+
+#define TEST_FP_OP3_D32( testnum, inst, flags, result, val1, val2, val3 ) \
+ TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, val3, \
+ inst f3, f0, f1, f2; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
+// ^: store computation result in address from a0, load high-word into t2
+
+#define TEST_FP_OP3_D( testnum, inst, flags, result, val1, val2, val3 ) \
+ TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, val3, \
+ inst f3, f0, f1, f2; fmv.x.d a0, f3)
+
+#define TEST_FP_INT_OP_S( testnum, inst, flags, result, val1, rm ) \
+ TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \
+ inst a0, f0, rm)
+
+#define TEST_FP_INT_OP_D32( testnum, inst, flags, result, val1, rm ) \
+ TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
+ inst a0, f0, f1; li t2, 0)
+
+#define TEST_FP_INT_OP_D( testnum, inst, flags, result, val1, rm ) \
+ TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
+ inst a0, f0, rm)
+
+#define TEST_FP_CMP_OP_S( testnum, inst, flags, result, val1, val2 ) \
+ TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, val2, 0.0, \
+ inst a0, f0, f1)
+
+#define TEST_FP_CMP_OP_D32( testnum, inst, flags, result, val1, val2 ) \
+ TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \
+ inst a0, f0, f1; li t2, 0)
+
+#define TEST_FP_CMP_OP_D( testnum, inst, flags, result, val1, val2 ) \
+ TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \
+ inst a0, f0, f1)
+
+#define TEST_FCLASS_S(testnum, correct, input) \
+ TEST_CASE(testnum, a0, correct, li a0, input; fmv.s.x fa0, a0; \
+ fclass.s a0, fa0)
+
+#define TEST_FCLASS_D32(testnum, correct, input) \
+ TEST_CASE(testnum, a0, correct, \
+ la a0, test_ ## testnum ## _data ;\
+ fld fa0, 0(a0); \
+ fclass.d a0, fa0) \
+ .pushsection .data; \
+ .align 3; \
+ test_ ## testnum ## _data: \
+ .dword input; \
+ .popsection
+
+#define TEST_FCLASS_D(testnum, correct, input) \
+ TEST_CASE(testnum, a0, correct, li a0, input; fmv.d.x fa0, a0; \
+ fclass.d a0, fa0)
+
+#define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ SWSIG (testnum, TESTNUM);\
+ la a0, test_ ## testnum ## _data ;\
+ lw a3, 0(a0); \
+ li a0, val1; \
+ inst f0, a0; \
+ fsflags x0; \
+ fmv.x.s a0, f0; \
+ bne a0, a3, fail; \
+ .pushsection .data; \
+ .align 2; \
+ test_ ## testnum ## _data: \
+ .float result; \
+ .popsection
+
+#define TEST_INT_FP_OP_D32( testnum, inst, result, val1 ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ SWSIG (testnum, TESTNUM);\
+ la a0, test_ ## testnum ## _data ;\
+ lw a3, 0(a0); \
+ lw a4, 4(a0); \
+ li a1, val1; \
+ inst f0, a1; \
+ \
+ fsd f0, 0(a0); \
+ lw a1, 4(a0); \
+ lw a0, 0(a0); \
+ \
+ fsflags x0; \
+ bne a0, a3, fail; \
+ bne a1, a4, fail; \
+ .pushsection .data; \
+ .align 3; \
+ test_ ## testnum ## _data: \
+ .double result; \
+ .popsection
+
+#define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ SWSIG (testnum, TESTNUM);\
+ la a0, test_ ## testnum ## _data ;\
+ ld a3, 0(a0); \
+ li a0, val1; \
+ inst f0, a0; \
+ fsflags x0; \
+ fmv.x.d a0, f0; \
+ bne a0, a3, fail; \
+ .pushsection .data; \
+ .align 3; \
+ test_ ## testnum ## _data: \
+ .double result; \
+ .popsection
+
+// We need some special handling here to allow 64-bit comparison in 32-bit arch
+// TODO: find a better name and clean up when intended for general usage?
+#define TEST_CASE_D32( testnum, testreg1, testreg2, correctval, code... ) \
+test_ ## testnum: \
+ code; \
+ la x31, test_ ## testnum ## _data ; \
+ lw x29, 0(x31); \
+ lw x31, 4(x31); \
+ li TESTNUM, testnum; \
+ SWSIG (testnum, TESTNUM);\
+ bne testreg1, x29, fail;\
+ bne testreg2, x31, fail;\
+ .pushsection .data; \
+ .align 3; \
+ test_ ## testnum ## _data: \
+ .dword correctval; \
+ .popsection
+
+// ^ x30 is used in some other macros, to avoid issues we use x31 for upper word
+
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in TESTNUM)
+#-----------------------------------------------------------------------
+
+#define TEST_PASSFAIL \
+ bne x0, TESTNUM, pass; \
+fail: \
+ RVTEST_FAIL; \
+pass: \
+ RVTEST_PASS \
+
+
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+
+#define TEST_DATA
+
+#endif
diff --git a/verilog/dv/riscv_regress/tests/riscv_compliance/compliance_io.h b/verilog/dv/riscv_regress/tests/riscv_compliance/compliance_io.h
new file mode 100644
index 0000000..5b7ca54
--- /dev/null
+++ b/verilog/dv/riscv_regress/tests/riscv_compliance/compliance_io.h
@@ -0,0 +1,70 @@
+// RISC-V Compliance IO Test Header File
+
+/*
+ * Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+ * either express or implied.
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef _COMPLIANCE_IO_H
+#define _COMPLIANCE_IO_H
+
+//-----------------------------------------------------------------------
+// RV IO Macros (Non functional)
+//-----------------------------------------------------------------------
+#ifdef _COMPLIANCE_OUTPUT
+
+#define RVTEST_IO_PUSH(_SP) \
+la _SP, begin_regstate; \
+sw x3, 0(_SP); \
+sw x4, 4(_SP); \
+sw x5, 8(_SP);
+
+#define RVTEST_IO_POP(_SP) \
+la _SP, begin_regstate; \
+lw x3, 0(_SP); \
+lw x4, 4(_SP); \
+lw x5, 8(_SP);
+
+#define RVTEST_IO_WRITE_STR(_SP, _STR) \
+ .section .data.string; \
+20001: \
+ .string _STR; \
+ .section .text; \
+ RVTEST_IO_PUSH(_SP) \
+ li x3, 0xF0000000; \
+ la x4, 20001b; \
+2: lb x5, 0(x4); \
+ sb x5, 0(x3); \
+ beq x5, zero, 1f; \
+ add x4, x4, 1; \
+ j 2b; \
+1: RVTEST_IO_POP(_SP)
+
+#else // #ifdef _COMPLIANCE_OUTPUT
+
+#define RVTEST_IO_WRITE_STR(_SP, _STR)
+
+#endif // #end #ifdef _COMPLIANCE_OUTPUT
+
+#define RVTEST_IO_INIT
+#define RVTEST_IO_CHECK()
+#define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I)
+#define RVTEST_IO_ASSERT_SFPR_EQ(_F, _R, _I)
+#define RVTEST_IO_ASSERT_DFPR_EQ(_D, _R, _I)
+#define RVTEST_IO_ASSERT_EQ(_R, _I)
+
+#endif // _COMPLIANCE_IO_H
diff --git a/verilog/dv/riscv_regress/tests/riscv_compliance/compliance_test.h b/verilog/dv/riscv_regress/tests/riscv_compliance/compliance_test.h
new file mode 100644
index 0000000..0c7e7f9
--- /dev/null
+++ b/verilog/dv/riscv_regress/tests/riscv_compliance/compliance_test.h
@@ -0,0 +1,31 @@
+// RISC-V Compliance Test Header File
+// Copyright (c) 2017, Codasip Ltd. All Rights Reserved.
+// See LICENSE for license details.
+//
+// Description: Common header file for RV32I tests
+
+#ifndef _COMPLIANCE_TEST_H
+#define _COMPLIANCE_TEST_H
+
+//-----------------------------------------------------------------------
+// RV Compliance Macros
+//-----------------------------------------------------------------------
+
+#define RV_COMPLIANCE_HALT \
+
+#define RV_COMPLIANCE_RV32M \
+ RVTEST_RV32M \
+
+#define RV_COMPLIANCE_CODE_BEGIN \
+ RVTEST_CODE_BEGIN \
+
+#define RV_COMPLIANCE_CODE_END \
+ RVTEST_CODE_END \
+
+#define RV_COMPLIANCE_DATA_BEGIN \
+ RVTEST_DATA_BEGIN \
+
+#define RV_COMPLIANCE_DATA_END \
+ RVTEST_DATA_END \
+
+#endif
\ No newline at end of file
diff --git a/verilog/dv/riscv_regress/tests/riscv_compliance/riscv_test.h b/verilog/dv/riscv_regress/tests/riscv_compliance/riscv_test.h
new file mode 100644
index 0000000..fdc6156
--- /dev/null
+++ b/verilog/dv/riscv_regress/tests/riscv_compliance/riscv_test.h
@@ -0,0 +1,7 @@
+
+#ifndef _RISCV_TEST_H
+#define _RISCV_TEST_H
+
+#include "test_macros.h"
+
+#endif
\ No newline at end of file
diff --git a/verilog/dv/riscv_regress/tests/riscv_compliance/riscv_test_macros.h b/verilog/dv/riscv_regress/tests/riscv_compliance/riscv_test_macros.h
new file mode 100644
index 0000000..6717bd4
--- /dev/null
+++ b/verilog/dv/riscv_regress/tests/riscv_compliance/riscv_test_macros.h
@@ -0,0 +1,463 @@
+// RISC-V Compliance IO Test Header File
+
+/*
+ * Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+ * either express or implied.
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#include "riscv_macros.h"
+
+//
+// In general the following registers are reserved
+// ra, a0, t0, t1
+// Additionally on an assertion violation, t1, t2 are overwritten
+// x1, x10, x5, x6, x7 respectively
+// Floating registers reserved
+// f5
+//
+
+#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1))
+
+#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
+
+// Base function for integer operations
+#define TEST_CASE(testreg, destreg, correctval, swreg, offset, code... ) \
+ code; \
+ sw destreg, offset(swreg); \
+ RVTEST_IO_ASSERT_GPR_EQ(testreg, destreg, correctval) \
+
+// Base functions for single precision floating point operations
+#define TEST_CASE_FP(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, code... ) \
+ la a0, test_ ## test_num ## _data; \
+ flw reg1, 0(a0); \
+ flw reg2, 4(a0); \
+ lw t1, 8(a0); \
+ code; \
+ fsw destreg, offset(swreg); \
+ RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \
+ .pushsection .data; \
+ .align 3; \
+ test_ ## test_num ## _data: \
+ .float val1; \
+ .float val2; \
+ .word correctval; \
+ .popsection
+
+#define TEST_CASE_FP_I(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
+ la a0, test_ ## test_num ## _data; \
+ lw t1, 0(a0); \
+ code; \
+ fsw destreg, offset(swreg); \
+ RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \
+ .pushsection .data; \
+ .align 1; \
+ test_ ## test_num ## _data: \
+ .word correctval; \
+ .popsection
+
+#define TEST_CASE_FP_I2(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
+ la a0, test_ ## test_num ## _data; \
+ flw reg, 0(a0); \
+ lw t1, 4(a0); \
+ code; \
+ sw destreg, offset(swreg); \
+ RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \
+ .pushsection .data; \
+ .align 2; \
+ test_ ## test_num ## _data: \
+ .float val; \
+ .word correctval; \
+ .popsection
+
+#define TEST_CASE_FP_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, code... ) \
+ la a0, test_ ## test_num ## _data; \
+ flw reg1, 0(a0); \
+ flw reg2, 4(a0); \
+ flw reg3, 8(a0); \
+ lw t1, 12(a0); \
+ code; \
+ fsw destreg, offset(swreg); \
+ RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \
+ .pushsection .data; \
+ .align 4; \
+ test_ ## test_num ## _data: \
+ .float val1; \
+ .float val2; \
+ .float val3; \
+ .word correctval; \
+ .popsection
+
+#define TEST_CASE_FP_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
+ la a0, test_ ## test_num ## _data; \
+ flw reg, 0(a0); \
+ code; \
+ sw destreg, offset(swreg); \
+ RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \
+ .pushsection .data; \
+ .align 1; \
+ test_ ## test_num ## _data: \
+ .float val; \
+ .popsection
+
+#define TEST_CASE_FP_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset, code...) \
+ la a0, test_ ## test_num ## _data; \
+ li reg, val; \
+ code; \
+ fsw destreg, offset(swreg); \
+ lw a1, 0(a0); \
+ RVTEST_IO_ASSERT_SFPR_EQ(destreg, a1, correctval) \
+ .pushsection .data; \
+ .align 1; \
+ test_ ## test_num ## _data: \
+ .word correctval; \
+ .popsection
+
+// Base functions for double precision floating point operations - rv32d
+#define TEST_CASE_FPD(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, code... ) \
+ la a0, test_ ## test_num ## _data; \
+ fld reg1, 0(a0); \
+ fld reg2, 8(a0); \
+ code; \
+ fsd destreg, offset(swreg); \
+ lw t1, 16(a0); \
+ lw t2, 20(a0); \
+ la a0, store_ ## test_num ## _data; \
+ fsd destreg, 0(a0); \
+ lw a1, 0(a0); \
+ lw a2, 4(a0); \
+ RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \
+ .pushsection .data; \
+ .align 3; \
+ test_ ## test_num ## _data: \
+ .double val1; \
+ .double val2; \
+ .dword correctval; \
+ .popsection; \
+ .pushsection .data; \
+ store_ ## test_num ## _data: \
+ .fill 1, 8, -1; \
+ .popsection
+
+#define TEST_CASE_FPD_I(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
+ la a0, test_ ## test_num ## _data; \
+ code; \
+ fsd destreg, offset(swreg); \
+ lw t1, 0(a0); \
+ lw t2, 4(a0); \
+ la a0, store_ ## test_num ## _data; \
+ fsd destreg, 0(a0); \
+ lw a1, 0(a0); \
+ lw a2, 4(a0); \
+ RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \
+ .pushsection .data; \
+ .align 1; \
+ test_ ## test_num ## _data: \
+ .dword correctval; \
+ .popsection; \
+ store_ ## test_num ## _data: \
+ .fill 1, 8, -1; \
+ .popsection
+
+#define TEST_CASE_FPD_I2(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
+ la a0, test_ ## test_num ## _data; \
+ fld reg, 0(a0); \
+ lw t1, 8(a0); \
+ code; \
+ sw destreg, offset(swreg); \
+ RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \
+ .pushsection .data; \
+ .align 2; \
+ test_ ## test_num ## _data: \
+ .double val; \
+ .word correctval; \
+ .popsection
+
+#define TEST_CASE_FPD_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, code... ) \
+ la a0, test_ ## test_num ## _data; \
+ fld reg1, 0(a0); \
+ fld reg2, 8(a0); \
+ fld reg3, 16(a0); \
+ code; \
+ fsd destreg, offset(swreg); \
+ lw t1, 24(a0); \
+ lw t2, 28(a0); \
+ la a0, store_ ## test_num ## _data; \
+ fsd destreg, 0(a0); \
+ lw a1, 0(a0); \
+ lw a2, 4(a0); \
+ RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \
+ .pushsection .data; \
+ .align 4; \
+ test_ ## test_num ## _data: \
+ .double val1; \
+ .double val2; \
+ .double val3; \
+ .dword correctval; \
+ .popsection; \
+ .pushsection .data; \
+ store_ ## test_num ## _data: \
+ .fill 1, 8, -1; \
+ .popsection
+
+//Tests for a instructions with register-register operand
+#define TEST_RR_OP(inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, testreg) \
+ TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+ li reg1, MASK_XLEN(val1); \
+ li reg2, MASK_XLEN(val2); \
+ inst destreg, reg1, reg2; \
+ )
+
+#define TEST_RR_SRC1( inst, destreg, reg, correctval, val1, val2, swreg, offset, testreg) \
+ TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+ li destreg, MASK_XLEN(val1); \
+ li reg, MASK_XLEN(val2); \
+ inst destreg, destreg, reg; \
+ )
+
+#define TEST_RR_SRC2( inst, destreg, reg, correctval, val1, val2, swreg, offset, testreg) \
+ TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+ li reg, MASK_XLEN(val1); \
+ li destreg, MASK_XLEN(val2); \
+ inst destreg, reg, destreg; \
+ )
+
+#define TEST_RR_SRC12( inst, destreg, correctval, val, swreg, offset, testreg) \
+ TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+ li destreg, MASK_XLEN(val1); \
+ inst destreg, destreg, destreg; \
+ )
+
+#define TEST_RR_ZERO1( inst, destreg, reg, correctval, val, swreg, offset, testreg) \
+ TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+ li reg, MASK_XLEN(val); \
+ inst destreg, x0, reg; \
+ )
+
+#define TEST_RR_ZERO2( inst, destreg, reg, correctval, val, swreg, offset, testreg) \
+ TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+ li reg, MASK_XLEN(val); \
+ inst destreg, reg, x0; \
+ )
+
+#define TEST_RR_ZERO12( inst, destreg, correctval, swreg, offset, testreg) \
+ TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+ inst destreg, x0, x0; \
+ )
+
+#define TEST_RR_ZERODEST( inst, reg1, reg2, val1, val2, swreg, offset, testreg) \
+ TEST_CASE(testreg, x0, 0, swreg, offset, \
+ li reg1, MASK_XLEN(val1); \
+ li reg2, MASK_XLEN(val2); \
+ inst x0, reg1, reg2; \
+ )
+
+//Tests for a instructions with register-immediate operand
+#define TEST_IMM_OP( inst, destreg, reg, correctval, val, imm, swreg, offset, testreg) \
+ TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+ li reg, MASK_XLEN(val); \
+ inst destreg, reg, SEXT_IMM(imm); \
+ )
+
+#define TEST_IMM_SRC( inst, destreg, correctval, val, imm, swreg, offset, testreg) \
+ TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+ li destreg, MASK_XLEN(val); \
+ inst destreg, destreg, SEXT_IMM(imm); \
+ )
+
+#define TEST_IMM_ZEROSRC( inst, destreg, correctval, imm, swreg, offset, testreg) \
+ TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+ inst destreg, x0, SEXT_IMM(imm); \
+ )
+
+#define TEST_IMM_ZERODEST( inst, reg, val, imm, swreg, offset, testreg) \
+ TEST_CASE(testreg, x0, 0, swreg, offset, \
+ li reg, MASK_XLEN(val); \
+ inst x0, reg, SEXT_IMM(imm); \
+ )
+
+#define TEST_IMM_ONEREG( inst, destreg, correctval, imm, swreg, offset, testreg) \
+ TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+ inst destreg, SEXT_IMM(imm); \
+ )
+
+#define TEST_AUIPC(inst, destreg, correctval, imm, swreg, offset, testreg) \
+ TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+ 1: \
+ inst destreg, imm; \
+ la swreg, 1b; \
+ sub destreg, destreg, swreg; \
+ )
+
+//Tests for a compressed instruction
+#define TEST_CR_OP( inst, destreg, reg, correctval, val1, val2, swreg, offset, testreg) \
+ TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+ li reg, MASK_XLEN(val1); \
+ li destreg, MASK_XLEN(val2); \
+ inst destreg, reg; \
+ )
+
+#define TEST_CI_OP( inst, destreg, correctval, val, imm, swreg, offset, testreg) \
+ TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+ li destreg, MASK_XLEN(val); \
+ inst destreg, imm; \
+ )
+
+#define TEST_CI_OP_NOREG(inst, correctval, imm, swreg, offset, testreg) \
+ TEST_CASE(testreg,x0, correctval, swreg, offset, \
+ inst imm; \
+ )
+
+//Tests for floating point instructions - single precision
+#define TEST_FP_OP(test_num, inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset) \
+ TEST_CASE_FP(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, \
+ inst destreg, reg1, reg2; \
+ )
+
+#define TEST_FP_ONEREG(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
+ TEST_CASE_FP(test_num, destreg, reg, reg, correctval, val, val, swreg, offset, \
+ inst destreg, reg; \
+ )
+
+#define TEST_FP_4REG(test_num, inst, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset) \
+ TEST_CASE_FP_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, \
+ inst destreg, reg1, reg2, reg3; \
+ )
+
+#define TEST_FP_I(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
+ TEST_CASE_FP_I(test_num, destreg, reg, correctval, val, swreg, offset, \
+ li reg, MASK_XLEN(val); \
+ inst destreg, reg; \
+ )
+
+#define TEST_FP_I2(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
+ TEST_CASE_FP_I2(test_num, destreg, reg, correctval, val, swreg, offset, \
+ inst destreg, reg; \
+ )
+
+//Tests for floating point instructions - double precision
+#define TEST_FPD_OP(test_num, inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset) \
+ TEST_CASE_FPD(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, \
+ inst destreg, reg1, reg2; \
+ )
+
+#define TEST_FPD_ONEREG(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
+ TEST_CASE_FPD(test_num, destreg, reg, reg, correctval, val, val, swreg, offset, \
+ inst destreg, reg; \
+ )
+
+#define TEST_FPD_4REG(test_num, inst, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset) \
+ TEST_CASE_FPD_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, \
+ inst destreg, reg1, reg2, reg3; \
+ )
+
+#define TEST_FPD_I(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
+ TEST_CASE_FPD_I(test_num, destreg, reg, correctval, val, swreg, offset, \
+ li reg, MASK_XLEN(val); \
+ inst destreg, reg; \
+ )
+
+#define TEST_FPD_I2(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
+ TEST_CASE_FPD_I2(test_num, destreg, reg, correctval, val, swreg, offset, \
+ inst destreg, reg; \
+ )
+
+#define TEST_CADDI16SP(correctval, imm, swreg, offset, testreg) \
+ TEST_CASE(testreg,x2, correctval, swreg, offset, \
+ c.addi16sp x2, imm; \
+ )
+
+#define TEST_CADDI4SPN(destreg, correctval, imm, swreg, offset, testreg) \
+ TEST_CASE(testreg,destreg, correctval, swreg, offset, \
+ c.addi4spn destreg, x2, SEXT_IMM(imm); \
+ )
+
+#define TEST_CJL(inst, reg, val, swreg, offset) \
+ li x10, val; \
+ la reg, 1f; \
+ inst reg; \
+ li x10, 0x123ab; \
+1: \
+ sw x10, offset(swreg); \
+ RVTEST_IO_ASSERT_GPR_EQ(x31, x10, val); \
+
+#define ABS(x) ((x >> 11) ^ x) - (x >> 11)
+
+#define TEST_CJ(inst, reg, val, swreg, offset) \
+ li reg, val; \
+ inst 1f; \
+ li reg, 0x123ab; \
+1: \
+ sw reg, offset(swreg); \
+ RVTEST_IO_ASSERT_GPR_EQ(x31, reg, val); \
+
+#define TEST_CL(inst, reg, imm, swreg, offset) \
+ la reg, test_data; \
+ inst reg, imm(reg); \
+ sw reg, offset(swreg); \
+
+// lw reg, imm(x2)
+// c.lwsp reg, imm(x2)
+#define TEST_CLWSP(reg, imm, swreg, offset) \
+ la x2, test_data; \
+ c.lwsp reg, imm(x2); \
+ sw reg, offset(swreg); \
+
+#define TEST_CSW(test_data, inst, reg1, reg2, val, imm, swreg, offset) \
+ li reg1, val; \
+ la reg2, test_data; \
+ inst reg1, imm(reg2); \
+ lw reg1, imm(reg2); \
+ sw reg1, offset(swreg); \
+ RVTEST_IO_ASSERT_GPR_EQ(x31, reg1, val); \
+
+#define TEST_CSWSP(test_data, reg, val, imm, swreg, offset) \
+ la x2, test_data; \
+ li reg, val; \
+ c.swsp reg, imm(x2); \
+ lw reg, imm(x2); \
+ sw reg, offset(swreg); \
+ RVTEST_IO_ASSERT_GPR_EQ(x31, reg, val); \
+
+#define TEST_CBEQZ(reg, val, swreg, offset) \
+ li reg, val; \
+ c.sub reg, reg; \
+ c.beqz reg, 3f; \
+ li reg, 0x123ab; \
+3: \
+ sw reg, offset(swreg); \
+ RVTEST_IO_ASSERT_GPR_EQ(x31, reg, 0x0); \
+
+#define TEST_CBNEZ(reg, val, swreg, offset) \
+ li reg, val; \
+ c.bnez reg, 4f; \
+ li reg, 0x0; \
+4: \
+ sw reg, offset(swreg); \
+ RVTEST_IO_ASSERT_GPR_EQ(x31, reg, val); \
+
+#define TEST_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset) \
+ TEST_CASE_FP_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset, \
+ fmv.x.s destreg, reg; \
+ )
+
+#define TEST_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset) \
+ TEST_CASE_FP_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset, \
+ fmv.s.x destreg, reg; \
+ )
+
+#define SWSIG(a,b)
+
diff --git a/verilog/dv/riscv_regress/tests/riscv_compliance/test_macros.h b/verilog/dv/riscv_regress/tests/riscv_compliance/test_macros.h
new file mode 100644
index 0000000..b2c610e
--- /dev/null
+++ b/verilog/dv/riscv_regress/tests/riscv_compliance/test_macros.h
@@ -0,0 +1,593 @@
+
+// RISC-V Compliance Test Header File
+// Copyright (c) 2017, Codasip Ltd. All Rights Reserved.
+// See LICENSE for license details.
+//
+// Description: Common header file for RV32I tests
+
+#ifndef _TEST_MACROS_H
+#define _TEST_MACROS_H
+
+#include "riscv_macros.h"
+
+// RISC-V Compliance IO Test Header File
+
+/*
+ * Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+ * either express or implied.
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+
+//
+// In general the following registers are reserved
+// ra, a0, t0, t1
+// Additionally on an assertion violation, t1, t2 are overwritten
+// x1, x10, x5, x6, x7 respectively
+// Floating registers reserved
+// f5
+//
+
+#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1))
+
+#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
+
+// Base function for integer operations
+#define TEST_CASE(destreg, correctval, swreg, offset, code... ) \
+ code; \
+ sw destreg, offset(swreg); \
+ RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \
+
+// Base functions for single precision floating point operations
+#define TEST_CASE_FP(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, code... ) \
+ la a0, test_ ## test_num ## _data; \
+ flw reg1, 0(a0); \
+ flw reg2, 4(a0); \
+ lw t1, 8(a0); \
+ code; \
+ fsw destreg, offset(swreg); \
+ RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \
+ .pushsection .data; \
+ .balign 8; \
+ test_ ## test_num ## _data: \
+ .float val1; \
+ .float val2; \
+ .word correctval; \
+ .popsection
+
+#define TEST_CASE_FP_I(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
+ la a0, test_ ## test_num ## _data; \
+ lw t1, 0(a0); \
+ code; \
+ fsw destreg, offset(swreg); \
+ RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \
+ .pushsection .data; \
+ .balign 2; \
+ test_ ## test_num ## _data: \
+ .word correctval; \
+ .popsection
+
+#define TEST_CASE_FP_I2(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
+ la a0, test_ ## test_num ## _data; \
+ flw reg, 0(a0); \
+ lw t1, 4(a0); \
+ code; \
+ sw destreg, offset(swreg); \
+ RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \
+ .pushsection .data; \
+ .balign 4; \
+ test_ ## test_num ## _data: \
+ .float val; \
+ .word correctval; \
+ .popsection
+
+#define TEST_CASE_FP_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, code... ) \
+ la a0, test_ ## test_num ## _data; \
+ flw reg1, 0(a0); \
+ flw reg2, 4(a0); \
+ flw reg3, 8(a0); \
+ lw t1, 12(a0); \
+ code; \
+ fsw destreg, offset(swreg); \
+ RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \
+ .pushsection .data; \
+ .balign 16; \
+ test_ ## test_num ## _data: \
+ .float val1; \
+ .float val2; \
+ .float val3; \
+ .word correctval; \
+ .popsection
+
+#define TEST_CASE_FP_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
+ la a0, test_ ## test_num ## _data; \
+ flw reg, 0(a0); \
+ code; \
+ sw destreg, offset(swreg); \
+ RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \
+ .pushsection .data; \
+ .balign 2; \
+ test_ ## test_num ## _data: \
+ .float val; \
+ .popsection
+
+#define TEST_CASE_FP_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset, code...) \
+ la a0, test_ ## test_num ## _data; \
+ li reg, val; \
+ code; \
+ fsw destreg, offset(swreg); \
+ lw a1, 0(a0); \
+ RVTEST_IO_ASSERT_SFPR_EQ(destreg, a1, correctval) \
+ .pushsection .data; \
+ .balign 2; \
+ test_ ## test_num ## _data: \
+ .word correctval; \
+ .popsection
+
+// Base functions for double precision floating point operations - rv32d
+#define TEST_CASE_FPD(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, code... ) \
+ la a0, test_ ## test_num ## _data; \
+ fld reg1, 0(a0); \
+ fld reg2, 8(a0); \
+ code; \
+ fsd destreg, offset(swreg); \
+ lw t1, 16(a0); \
+ lw t2, 20(a0); \
+ la a0, store_ ## test_num ## _data; \
+ fsd destreg, 0(a0); \
+ lw a1, 0(a0); \
+ lw a2, 4(a0); \
+ RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \
+ .pushsection .data; \
+ .balign 8; \
+ test_ ## test_num ## _data: \
+ .double val1; \
+ .double val2; \
+ .dword correctval; \
+ .popsection; \
+ .pushsection .data; \
+ store_ ## test_num ## _data: \
+ .fill 1, 8, -1; \
+ .popsection
+
+#define TEST_CASE_FPD_I(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
+ la a0, test_ ## test_num ## _data; \
+ code; \
+ fsd destreg, offset(swreg); \
+ lw t1, 0(a0); \
+ lw t2, 4(a0); \
+ la a0, store_ ## test_num ## _data; \
+ fsd destreg, 0(a0); \
+ lw a1, 0(a0); \
+ lw a2, 4(a0); \
+ RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \
+ .pushsection .data; \
+ .balign 2; \
+ test_ ## test_num ## _data: \
+ .dword correctval; \
+ .popsection; \
+ store_ ## test_num ## _data: \
+ .fill 1, 8, -1; \
+ .popsection
+
+#define TEST_CASE_FPD_I2(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
+ la a0, test_ ## test_num ## _data; \
+ fld reg, 0(a0); \
+ lw t1, 8(a0); \
+ code; \
+ sw destreg, offset(swreg); \
+ RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \
+ .pushsection .data; \
+ .balign 4; \
+ test_ ## test_num ## _data: \
+ .double val; \
+ .word correctval; \
+ .popsection
+
+#define TEST_CASE_FPD_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, code... ) \
+ la a0, test_ ## test_num ## _data; \
+ fld reg1, 0(a0); \
+ fld reg2, 8(a0); \
+ fld reg3, 16(a0); \
+ code; \
+ fsd destreg, offset(swreg); \
+ lw t1, 24(a0); \
+ lw t2, 28(a0); \
+ la a0, store_ ## test_num ## _data; \
+ fsd destreg, 0(a0); \
+ lw a1, 0(a0); \
+ lw a2, 4(a0); \
+ RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \
+ .pushsection .data; \
+ .balign 16; \
+ test_ ## test_num ## _data: \
+ .double val1; \
+ .double val2; \
+ .double val3; \
+ .dword correctval; \
+ .popsection; \
+ .pushsection .data; \
+ store_ ## test_num ## _data: \
+ .fill 1, 8, -1; \
+ .popsection
+
+//Tests for a instructions with register-register operand
+#define TEST_RR_OP(inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset) \
+ TEST_CASE( destreg, correctval, swreg, offset, \
+ li reg1, MASK_XLEN(val1); \
+ li reg2, MASK_XLEN(val2); \
+ inst destreg, reg1, reg2; \
+ )
+
+#define TEST_RR_SRC1( inst, destreg, reg, correctval, val1, val2, swreg, offset) \
+ TEST_CASE( destreg, correctval, swreg, offset, \
+ li destreg, MASK_XLEN(val1); \
+ li reg, MASK_XLEN(val2); \
+ inst destreg, destreg, reg; \
+ )
+
+#define TEST_RR_SRC2( inst, destreg, reg, correctval, val1, val2, swreg, offset) \
+ TEST_CASE( destreg, correctval, swreg, offset, \
+ li reg, MASK_XLEN(val1); \
+ li destreg, MASK_XLEN(val2); \
+ inst destreg, reg, destreg; \
+ )
+
+#define TEST_RR_SRC12( inst, destreg, correctval, val, swreg, offset) \
+ TEST_CASE( destreg, correctval, swreg, offset, \
+ li destreg, MASK_XLEN(val1); \
+ inst destreg, destreg, destreg; \
+ )
+
+#define TEST_RR_ZERO1( inst, destreg, reg, correctval, val, swreg, offset) \
+ TEST_CASE( destreg, correctval, swreg, offset, \
+ li reg, MASK_XLEN(val); \
+ inst destreg, x0, reg; \
+ )
+
+#define TEST_RR_ZERO2( inst, destreg, reg, correctval, val, swreg, offset) \
+ TEST_CASE( destreg, correctval, swreg, offset, \
+ li reg, MASK_XLEN(val); \
+ inst destreg, reg, x0; \
+ )
+
+#define TEST_RR_ZERO12( inst, destreg, correctval, swreg, offset) \
+ TEST_CASE( destreg, correctval, swreg, offset, \
+ inst destreg, x0, x0; \
+ )
+
+#define TEST_RR_ZERODEST( inst, reg1, reg2, val1, val2, swreg, offset) \
+ TEST_CASE( x0, 0, swreg, offset, \
+ li reg1, MASK_XLEN(val1); \
+ li reg2, MASK_XLEN(val2); \
+ inst x0, reg1, reg2; \
+ )
+
+//Tests for a instructions with register-immediate operand
+#define TEST_IMM_OP( inst, destreg, reg, correctval, val, imm, swreg, offset) \
+ TEST_CASE ( destreg, correctval, swreg, offset, \
+ li reg, MASK_XLEN(val); \
+ inst destreg, reg, SEXT_IMM(imm); \
+ )
+
+#define TEST_IMM_SRC( inst, destreg, correctval, val, imm, swreg, offset) \
+ TEST_CASE ( destreg, correctval, swreg, offset, \
+ li destreg, MASK_XLEN(val); \
+ inst destreg, destreg, SEXT_IMM(imm); \
+ )
+
+#define TEST_IMM_ZEROSRC( inst, destreg, correctval, imm, swreg, offset) \
+ TEST_CASE ( destreg, correctval, swreg, offset, \
+ inst destreg, x0, SEXT_IMM(imm); \
+ )
+
+#define TEST_IMM_ZERODEST( inst, reg, val, imm, swreg, offset) \
+ TEST_CASE ( x0, 0, swreg, offset, \
+ li reg, MASK_XLEN(val); \
+ inst x0, reg, SEXT_IMM(imm); \
+ )
+
+#define TEST_IMM_ONEREG( inst, destreg, correctval, imm, swreg, offset) \
+ TEST_CASE ( destreg, correctval, swreg, offset, \
+ inst destreg, SEXT_IMM(imm); \
+ )
+
+#define TEST_AUIPC(inst, destreg, correctval, imm, swreg, offset) \
+ TEST_CASE ( destreg, correctval, swreg, offset, \
+ 1: \
+ inst destreg, SEXT_IMM(imm); \
+ la swreg, 1b; \
+ sub destreg, destreg, swreg; \
+ )
+
+//Tests for a compressed instruction
+#define TEST_CR_OP( inst, destreg, reg, correctval, val1, val2, swreg, offset) \
+ TEST_CASE ( destreg, correctval, swreg, offset, \
+ li reg, MASK_XLEN(val1); \
+ li destreg, MASK_XLEN(val2); \
+ inst destreg, reg; \
+ )
+
+#define TEST_CI_OP( inst, destreg, correctval, val, imm, swreg, offset) \
+ TEST_CASE( destreg, correctval, swreg, offset, \
+ li destreg, MASK_XLEN(val); \
+ inst destreg, imm; \
+ )
+
+#define TEST_CI_OP_NOREG(inst, correctval, imm, swreg, offset) \
+ TEST_CASE (x0, correctval, swreg, offset, \
+ inst imm; \
+ )
+
+//Tests for floating point instructions - single precision
+#define TEST_FP_OP(test_num, inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset) \
+ TEST_CASE_FP(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, \
+ inst destreg, reg1, reg2; \
+ )
+
+#define TEST_FP_ONEREG(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
+ TEST_CASE_FP(test_num, destreg, reg, reg, correctval, val, val, swreg, offset, \
+ inst destreg, reg; \
+ )
+
+#define TEST_FP_4REG(test_num, inst, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset) \
+ TEST_CASE_FP_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, \
+ inst destreg, reg1, reg2, reg3; \
+ )
+
+#define TEST_FP_I(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
+ TEST_CASE_FP_I(test_num, destreg, reg, correctval, val, swreg, offset, \
+ li reg, MASK_XLEN(val); \
+ inst destreg, reg; \
+ )
+
+#define TEST_FP_I2(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
+ TEST_CASE_FP_I2(test_num, destreg, reg, correctval, val, swreg, offset, \
+ inst destreg, reg; \
+ )
+
+//Tests for floating point instructions - double precision
+#define TEST_FPD_OP(test_num, inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset) \
+ TEST_CASE_FPD(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, \
+ inst destreg, reg1, reg2; \
+ )
+
+#define TEST_FPD_ONEREG(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
+ TEST_CASE_FPD(test_num, destreg, reg, reg, correctval, val, val, swreg, offset, \
+ inst destreg, reg; \
+ )
+
+#define TEST_FPD_4REG(test_num, inst, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset) \
+ TEST_CASE_FPD_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, \
+ inst destreg, reg1, reg2, reg3; \
+ )
+
+#define TEST_FPD_I(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
+ TEST_CASE_FPD_I(test_num, destreg, reg, correctval, val, swreg, offset, \
+ li reg, MASK_XLEN(val); \
+ inst destreg, reg; \
+ )
+
+#define TEST_FPD_I2(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
+ TEST_CASE_FPD_I2(test_num, destreg, reg, correctval, val, swreg, offset, \
+ inst destreg, reg; \
+ )
+
+#define TEST_CADDI16SP(correctval, imm, swreg, offset) \
+ TEST_CASE(x2, correctval, swreg, offset, \
+ c.addi16sp x2, imm; \
+ )
+
+#define TEST_CADDI4SPN(destreg, correctval, imm, swreg, offset) \
+ TEST_CASE(destreg, correctval, swreg, offset, \
+ c.addi4spn destreg, x2, SEXT_IMM(imm); \
+ )
+
+#define TEST_CJL(inst, reg, val, swreg, offset) \
+ li x10, val; \
+ la reg, 1f; \
+ inst reg; \
+ li x10, 0x123ab; \
+1: \
+ sw x10, offset(swreg); \
+ RVTEST_IO_ASSERT_GPR_EQ(x31, x10, val); \
+
+#define ABS(x) ((x >> 11) ^ x) - (x >> 11)
+
+#define TEST_CJ(inst, reg, val, swreg, offset) \
+ li reg, val; \
+ inst 1f; \
+ li reg, 0x123ab; \
+1: \
+ sw reg, offset(swreg); \
+ RVTEST_IO_ASSERT_GPR_EQ(x31, reg, val); \
+
+#define TEST_CL(inst, reg, imm, swreg, offset) \
+ la reg, test_data; \
+ inst reg, imm(reg); \
+ sw reg, offset(swreg); \
+
+// lw reg, imm(x2)
+// c.lwsp reg, imm(x2)
+#define TEST_CLWSP(reg, imm, swreg, offset) \
+ la x2, test_data; \
+ c.lwsp reg, imm(x2); \
+ sw reg, offset(swreg); \
+
+#define TEST_CSW(test_data, inst, reg1, reg2, val, imm, swreg, offset) \
+ li reg1, val; \
+ la reg2, test_data; \
+ inst reg1, imm(reg2); \
+ lw reg1, imm(reg2); \
+ sw reg1, offset(swreg); \
+ RVTEST_IO_ASSERT_GPR_EQ(x31, reg1, val); \
+
+#define TEST_CSWSP(test_data, reg, val, imm, swreg, offset) \
+ la x2, test_data; \
+ li reg, val; \
+ c.swsp reg, imm(x2); \
+ lw reg, imm(x2); \
+ sw reg, offset(swreg); \
+ RVTEST_IO_ASSERT_GPR_EQ(x31, reg, val); \
+
+#define TEST_CBEQZ(reg, val, swreg, offset) \
+ li reg, val; \
+ c.sub reg, reg; \
+ c.beqz reg, 3f; \
+ li reg, 0x123ab; \
+3: \
+ sw reg, offset(swreg); \
+ RVTEST_IO_ASSERT_GPR_EQ(x31, reg, 0x0); \
+
+#define TEST_CBNEZ(reg, val, swreg, offset) \
+ li reg, val; \
+ c.bnez reg, 4f; \
+ li reg, 0x0; \
+4: \
+ sw reg, offset(swreg); \
+ RVTEST_IO_ASSERT_GPR_EQ(x31, reg, val); \
+
+#define TEST_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset) \
+ TEST_CASE_FP_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset, \
+ fmv.x.s destreg, reg; \
+ )
+
+#define TEST_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset) \
+ TEST_CASE_FP_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset, \
+ fmv.s.x destreg, reg; \
+ )
+
+#define SWSIG(a,b)
+
+
+#if __riscv_xlen == 64
+#define SATP_MODE SATP64_MODE
+#else
+#define SATP_MODE SATP32_MODE
+#endif
+
+#define SATP32_MODE 0x80000000
+#define SATP32_ASID 0x7FC00000
+#define SATP32_PPN 0x003FFFFF
+#define SATP64_MODE 0xF000000000000000
+#define SATP64_ASID 0x0FFFF00000000000
+#define SATP64_PPN 0x00000FFFFFFFFFFF
+
+#define SATP_MODE_OFF 0
+#define SATP_MODE_SV32 1
+#define SATP_MODE_SV39 8
+#define SATP_MODE_SV48 9
+#define SATP_MODE_SV57 10
+#define SATP_MODE_SV64 11
+
+#define TEST_FP_OP2_D32( testnum, inst, flags, result, val1, val2 ) \
+ TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \
+ inst f3, f0, f1; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
+
+#define TEST_CASE_D32( testnum, testreg1, testreg2, correctval, code... ) \
+test_ ## testnum: \
+ code; \
+ la x31, test_ ## testnum ## _data ; \
+ lw x29, 0(x31); \
+ lw x31, 4(x31); \
+ li TESTNUM, testnum; \
+ bne testreg1, x29, fail;\
+ bne testreg2, x31, fail;\
+ .pushsection .data; \
+ .balign 8; \
+ test_ ## testnum ## _data: \
+ .dword correctval; \
+ .popsection
+
+#define TEST_FP_OP_D32_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ la a0, test_ ## testnum ## _data ;\
+ fld f0, 0(a0); \
+ fld f1, 8(a0); \
+ fld f2, 16(a0); \
+ lw a3, 24(a0); \
+ lw t1, 28(a0); \
+ code; \
+ fsflags a1, x0; \
+ li a2, flags; \
+ bne a0, a3, fail; \
+ bne t1, t2, fail; \
+ bne a1, a2, fail; \
+ .pushsection .data; \
+ .balign 8; \
+ test_ ## testnum ## _data: \
+ .double val1; \
+ .double val2; \
+ .double val3; \
+ .result; \
+ .popsection
+
+#define TEST_FP_OP1_D32( testnum, inst, flags, result, val1 ) \
+ TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \
+ inst f3, f0; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
+
+#define TEST_FCLASS_D32(testnum, correct, input) \
+ TEST_CASE(testnum, a0, correct, \
+ la a0, test_ ## testnum ## _data ;\
+ fld fa0, 0(a0); \
+ fclass.d a0, fa0) \
+ .pushsection .data; \
+ .balign 8; \
+ test_ ## testnum ## _data: \
+ .dword input; \
+ .popsection
+
+#define TEST_FP_CMP_OP_D32( testnum, inst, flags, result, val1, val2 ) \
+ TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \
+ inst a0, f0, f1; li t2, 0)
+
+#define TEST_INT_FP_OP_D32( testnum, inst, result, val1 ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ la a0, test_ ## testnum ## _data ;\
+ lw a3, 0(a0); \
+ lw a4, 4(a0); \
+ li a1, val1; \
+ inst f0, a1; \
+ \
+ fsd f0, 0(a0); \
+ lw a1, 4(a0); \
+ lw a0, 0(a0); \
+ \
+ fsflags x0; \
+ bne a0, a3, fail; \
+ bne a1, a4, fail; \
+ .pushsection .data; \
+ .balign 8; \
+ test_ ## testnum ## _data: \
+ .double result; \
+ .popsection
+
+#define TEST_FCVT_S_D32( testnum, result, val1 ) \
+ TEST_FP_OP_D32_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \
+ fcvt.s.d f3, f0; fcvt.d.s f3, f3; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
+
+#define TEST_FP_OP3_D32( testnum, inst, flags, result, val1, val2, val3 ) \
+ TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, val3, \
+ inst f3, f0, f1, f2; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
+
+#define TEST_FP_OP1_D32_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
+ TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
+ inst f3, f0; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
+
+
+#endif
diff --git a/verilog/dv/riscv_regress/tests/riscv_isa/Makefile b/verilog/dv/riscv_regress/tests/riscv_isa/Makefile
new file mode 100644
index 0000000..a572172
--- /dev/null
+++ b/verilog/dv/riscv_regress/tests/riscv_isa/Makefile
@@ -0,0 +1,96 @@
+
+include rv32_tests.inc
+
+ARCH_tmp := imf
+
+ifneq (,$(findstring c,$(ARCH_lowercase)))
+ ARCH_tmp := $(ARCH_tmp)c
+endif
+
+override ARCH := $(ARCH_tmp)
+
+src_dir := $(CURDIR)
+obj_dir := $(bld_dir)/riscv_objs
+test_list := $(patsubst %.S, %, $(notdir $(rv32_isa_tests)))
+objs := $(addprefix $(obj_dir)/,$(test_list:%=%.o))
+test_elf := $(addprefix $(bld_dir)/,$(test_list:%=%.elf))
+test_hex := $(addprefix $(bld_dir)/,$(test_list:%=%.hex))
+test_dump := $(addprefix $(bld_dir)/,$(test_list:%=%.dump))
+
+CFLAGS := -I$(inc_dir) -I$(src_dir) -DASM -Wa,-march=rv32$(ARCH) -march=rv32$(ARCH) -mabi=ilp32f -D__riscv_xlen=32
+LDFLAGS := -static -fvisibility=hidden -nostdlib -nostartfiles -T$(inc_dir)/link.ld -march=rv32$(ARCH) -mabi=ilp32f
+RISCV_TESTS := $(src_dir)/../../dependencies/riscv-tests/
+
+VPATH += $(src_dir) $(bld_dir) $(obj_dir) $(RISCV_TESTS)
+
+default: log_requested_tgt check_riscv_tests $(test_elf) $(test_hex) $(test_dump)
+
+define compile_template
+$(obj_dir)/$$(basename $(notdir $(SRC))).o: $$(SRC) | $(obj_dir)
+ $(RISCV_GCC) -c $$< $(CFLAGS) -o $$@
+ endef
+
+$(foreach SRC,$(rv32_isa_tests), $(eval $(compile_template)))
+
+log_requested_tgt:
+ $(foreach test_name, $(test_list), $(eval $(shell echo $(test_name).hex >> $(bld_dir)/test_info)))
+
+$(obj_dir) :
+ mkdir -p $(obj_dir)
+
+$(bld_dir)/%.elf: $(obj_dir)/%.o | $(obj_dir)
+ $(RISCV_GCC) $^ $(LDFLAGS) -o $@
+
+$(bld_dir)/%.hex: $(bld_dir)/%.elf
+ $(RISCV_ROM_OBJCOPY) $^ $@
+ $(RISCV_RAM_OBJCOPY) $^ $@.ram
+ #assign 0x0048_0xxx to 0x0000_0xxx to map to TCM Memory
+ sed -i 's/@00480/@00000/g' $@.ram
+
+$(bld_dir)/%.dump: $(bld_dir)/%.elf
+ $(RISCV_OBJDUMP) $^ > $@
+
+clean:
+ $(RM) $(test_elf) $(test_hex) $(test_dump) $(objs)
+ $(RM) -R $(obj_dir)
+
+
+.PHONY: check_riscv_tests
+
+riscv_tests_dir := $(if $(RISCV_TESTS), $(RISCV_TESTS), ./undefined)
+riscv_tests_commit := 5f8a4918c6482e65c67a2b7decd5c2af3e3fe0e5
+## commit hash readed from local copy of https://github.com/riscv/riscv-tests
+tmp_commit = $(shell cd $(riscv_tests_dir) 2>/dev/null && git log -1 | grep "commit" | cut -f2 -d ' ')
+is_commit_good = $(if $(subst $(riscv_tests_commit),,$(tmp_commit)),false,true)
+
+# Color
+RED=\033[0;31m
+NC=\033[0m
+
+check_riscv_tests : $(riscv_tests_dir)
+ @if [ ! -d $(riscv_tests_dir) ]; then \
+ echo -e "$(RED)==========================================================================" &&\
+ echo " Error! Environment variable RISCV_TESTS='$(riscv_tests_dir)' " &&\
+ echo " directory not exist!" && \
+ echo "==========================================================================$(NC)" ; \
+ fi
+ifneq ($(is_commit_good),true)
+ @echo -e "$(RED)=========================================================================="
+ @echo " Warning! Execution of test code is not guaranteed "
+ @echo " while using the current commit of repositorylocated at : $(riscv_tests_dir) ."
+ @echo " "
+ @echo " Riscv-tests repository must point to commit $(riscv_tests_commit)!"
+ @echo -e "==========================================================================$(NC)"
+endif
+
+$(riscv_tests_dir) :.
+ifndef RISCV_TESTS
+ @echo -e "$(RED)=========================================================================="
+ @echo " Error! Environment variable RISCV_TESTS not set!"
+ @echo " You must set the environment variable RISCV_TESTS"
+ @echo " The variable should point to the local copy of the"
+ @echo " repository https://github.com/riscv/riscv-tests"
+ @echo " with the commit $(riscv_tests_commit)"
+ @echo -e "==========================================================================$(NC)"
+ exit 1
+endif
diff --git a/verilog/dv/riscv_regress/tests/riscv_isa/riscv_test.h b/verilog/dv/riscv_regress/tests/riscv_isa/riscv_test.h
new file mode 100644
index 0000000..2b9ce0d
--- /dev/null
+++ b/verilog/dv/riscv_regress/tests/riscv_isa/riscv_test.h
@@ -0,0 +1,6 @@
+#ifndef __RISCV__TEST__H
+#define __RISCV__TEST__H
+
+#include "riscv_macros.h"
+
+#endif // #ifndef __RISCV__TEST__H
diff --git a/verilog/dv/riscv_regress/tests/riscv_isa/rv32_tests.inc b/verilog/dv/riscv_regress/tests/riscv_isa/rv32_tests.inc
new file mode 100644
index 0000000..62e5012
--- /dev/null
+++ b/verilog/dv/riscv_regress/tests/riscv_isa/rv32_tests.inc
@@ -0,0 +1,66 @@
+
+ARCH_lowercase = $(shell echo $(ARCH) | tr A-Z a-z)
+
+
+rv32_isa_tests += isa/rv32ui/add.S \
+ isa/rv32ui/addi.S \
+ isa/rv32ui/and.S \
+ isa/rv32ui/andi.S \
+ isa/rv32ui/auipc.S \
+ isa/rv32ui/beq.S \
+ isa/rv32ui/bge.S \
+ isa/rv32ui/bgeu.S \
+ isa/rv32ui/blt.S \
+ isa/rv32ui/bltu.S \
+ isa/rv32ui/bne.S \
+ isa/rv32mi/csr.S \
+ isa/rv32ui/fence_i.S \
+ isa/rv32mi/illegal.S \
+ isa/rv32ui/jal.S \
+ isa/rv32ui/jalr.S \
+ isa/rv32ui/lb.S \
+ isa/rv32ui/lbu.S \
+ isa/rv32ui/lh.S \
+ isa/rv32ui/lhu.S \
+ isa/rv32ui/lui.S \
+ isa/rv32ui/lw.S \
+ isa/rv32mi/ma_addr.S \
+ isa/rv32mi/ma_fetch.S \
+ isa/rv32mi/mcsr.S \
+ isa/rv32ui/or.S \
+ isa/rv32ui/ori.S \
+ isa/rv32ui/sb.S \
+ isa/rv32mi/sbreak.S \
+ isa/rv32mi/scall.S \
+ isa/rv32ui/sh.S \
+ isa/rv32mi/shamt.S \
+ isa/rv32ui/simple.S \
+ isa/rv32ui/sll.S \
+ isa/rv32ui/slli.S \
+ isa/rv32ui/slt.S \
+ isa/rv32ui/slti.S \
+ isa/rv32ui/sltiu.S \
+ isa/rv32ui/sltu.S \
+ isa/rv32ui/sra.S \
+ isa/rv32ui/srai.S \
+ isa/rv32ui/srl.S \
+ isa/rv32ui/srli.S \
+ isa/rv32ui/sub.S \
+ isa/rv32ui/sw.S \
+ isa/rv32ui/xor.S \
+ isa/rv32ui/xori.S
+
+ifneq (,$(findstring m,$(ARCH_lowercase)))
+rv32_isa_tests += isa/rv32um/div.S \
+ isa/rv32um/divu.S \
+ isa/rv32um/mul.S \
+ isa/rv32um/mulh.S \
+ isa/rv32um/mulhsu.S \
+ isa/rv32um/mulhu.S \
+ isa/rv32um/rem.S \
+ isa/rv32um/remu.S
+endif ## ifeq (m,$(findstring m,$(ARCH_lowercase)))
+
+ifneq (,$(findstring c,$(ARCH_lowercase)))
+rv32_isa_tests += isa/rv32uc/rvc.S
+endif ## ifeq (m,$(findstring c,$(ARCH_lowercase)))
\ No newline at end of file
diff --git a/verilog/dv/riscv_regress/tests/riscv_isa/test_macros.h b/verilog/dv/riscv_regress/tests/riscv_isa/test_macros.h
new file mode 100644
index 0000000..743918d
--- /dev/null
+++ b/verilog/dv/riscv_regress/tests/riscv_isa/test_macros.h
@@ -0,0 +1,5 @@
+#ifndef __TEST__MACROS__H
+#define __TEST__MACROS__H
+
+
+#endif
diff --git a/verilog/dv/uart_master/Makefile b/verilog/dv/uart_master/Makefile
index fdaa47d..a207608 100644
--- a/verilog/dv/uart_master/Makefile
+++ b/verilog/dv/uart_master/Makefile
@@ -31,7 +31,7 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
diff --git a/verilog/dv/user_basic/Makefile b/verilog/dv/user_basic/Makefile
index 2c9b432..2c0b01f 100644
--- a/verilog/dv/user_basic/Makefile
+++ b/verilog/dv/user_basic/Makefile
@@ -29,14 +29,14 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include
-## SYNTACORE FIRMWARE
-SYNTACORE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/rtl/syntacore/scr1/sim/tests/common
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware
GCC64_PREFIX?=riscv64-unknown-elf
## RISCV GCC
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index 865e4f9..918149f 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -242,8 +242,8 @@
wb_user_core_write('h3080_0000,'h1);
wb_user_core_read_check(32'h30020058,read_data,32'h8273_8343);
- wb_user_core_read_check(32'h3002005C,read_data,32'h0601_2022);
- wb_user_core_read_check(32'h30020060,read_data,32'h0002_5000);
+ wb_user_core_read_check(32'h3002005C,read_data,32'h1401_2022);
+ wb_user_core_read_check(32'h30020060,read_data,32'h0003_0000);
end
diff --git a/verilog/dv/user_i2cm/Makefile b/verilog/dv/user_i2cm/Makefile
index 854e8cf..605c623 100644
--- a/verilog/dv/user_i2cm/Makefile
+++ b/verilog/dv/user_i2cm/Makefile
@@ -29,14 +29,14 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include
-## SYNTACORE FIRMWARE
-SYNTACORE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/rtl/syntacore/scr1/sim/tests/common
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware
GCC64_PREFIX?=riscv64-unknown-elf
## RISCV GCC
@@ -59,9 +59,9 @@
vvp: ${PATTERN:=.vvp}
%.vvp: %_tb.v
- ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common user_uart.c -o user_uart.o
- ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common/ ../../rtl/syntacore/scr1/sim/tests/common/crt_tcm.S -o crt_tcm.o
- ${GCC64_PREFIX}-gcc -o user_uart.elf -T ../../rtl/syntacore/scr1/sim/tests/common/link_tcm.ld user_uart.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32
+ ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_uart.c -o user_uart.o
+ ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt_tcm.S -o crt_tcm.o
+ ${GCC64_PREFIX}-gcc -o user_uart.elf -T $(YIFIVE_FIRMWARE_PATH)/link_tcm.ld user_uart.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32
${GCC64_PREFIX}-objcopy -O verilog user_uart.elf user_uart.hex
${GCC64_PREFIX}-objdump -D user_uart.elf > user_uart.dump
rm crt_tcm.o user_uart.o
diff --git a/verilog/dv/user_mbist_test1/Makefile b/verilog/dv/user_mbist_test1/Makefile
index d6d34c6..3263b33 100644
--- a/verilog/dv/user_mbist_test1/Makefile
+++ b/verilog/dv/user_mbist_test1/Makefile
@@ -29,14 +29,14 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include
-## SYNTACORE FIRMWARE
-SYNTACORE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/rtl/syntacore/scr1/sim/tests/common
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware
GCC64_PREFIX?=riscv64-unknown-elf
## RISCV GCC
diff --git a/verilog/dv/user_risc_boot/Makefile b/verilog/dv/user_risc_boot/Makefile
index d84401d..26104a8 100644
--- a/verilog/dv/user_risc_boot/Makefile
+++ b/verilog/dv/user_risc_boot/Makefile
@@ -29,19 +29,19 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include
-## SYNTACORE FIRMWARE
-SYNTACORE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/rtl/syntacore/scr1/sim/tests/common
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware
GCC64_PREFIX?=riscv64-unknown-elf
## RISCV GCC
GCC_PATH?=/ef/apps/bin
-GCC32_PREFIX?=riscv32-unknown-elf
+GCC_PREFIX?=riscv32-unknown-elf
PDK_PATH?=/ef/tech/SW/sky130A
## Simulation mode: RTL/GL
@@ -59,9 +59,9 @@
vvp: ${PATTERN:=.vvp}
%.vvp: %_tb.v
- ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common user_risc_boot.c -o user_risc_boot.o
- ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common/ ../../rtl/syntacore/scr1/sim/tests/common/crt_tcm.S -o crt_tcm.o
- ${GCC64_PREFIX}-gcc -o user_risc_boot.elf -T $(SYNTACORE_FIRMWARE_PATH)/link_tcm.ld user_risc_boot.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
+ ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_risc_boot.c -o user_risc_boot.o
+ ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt_tcm.S -o crt_tcm.o
+ ${GCC64_PREFIX}-gcc -o user_risc_boot.elf -T $(YIFIVE_FIRMWARE_PATH)/link_tcm.ld user_risc_boot.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
${GCC64_PREFIX}-objcopy -O verilog user_risc_boot.elf user_risc_boot.hex
${GCC64_PREFIX}-objdump -D user_risc_boot.elf > user_risc_boot.dump
rm crt_tcm.o user_risc_boot.o
diff --git a/verilog/dv/user_risc_soft_boot/Makefile b/verilog/dv/user_risc_soft_boot/Makefile
index 381b34a..3998666 100644
--- a/verilog/dv/user_risc_soft_boot/Makefile
+++ b/verilog/dv/user_risc_soft_boot/Makefile
@@ -29,14 +29,14 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include
-## SYNTACORE FIRMWARE
-SYNTACORE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/rtl/syntacore/scr1/sim/tests/common
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware
GCC64_PREFIX?=riscv64-unknown-elf
## RISCV GCC
@@ -59,9 +59,9 @@
vvp: ${PATTERN:=.vvp}
%.vvp: %_tb.v
- ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common user_risc_boot.c -o user_risc_boot.o
- ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common/ ../../rtl/syntacore/scr1/sim/tests/common/crt_tcm.S -o crt_tcm.o
- ${GCC64_PREFIX}-gcc -o user_risc_boot.elf -T ../../rtl/syntacore/scr1/sim/tests/common/link_tcm.ld user_risc_boot.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
+ ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_risc_boot.c -o user_risc_boot.o
+ ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt_tcm.S -o crt_tcm.o
+ ${GCC64_PREFIX}-gcc -o user_risc_boot.elf -T $(YIFIVE_FIRMWARE_PATH)/link_tcm.ld user_risc_boot.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
${GCC64_PREFIX}-objcopy -O verilog user_risc_boot.elf user_risc_boot.hex
${GCC64_PREFIX}-objdump -D user_risc_boot.elf > user_risc_boot.dump
rm crt_tcm.o user_risc_boot.o
diff --git a/verilog/dv/user_spi/Makefile b/verilog/dv/user_spi/Makefile
index 37f26fe..32bbfec 100644
--- a/verilog/dv/user_spi/Makefile
+++ b/verilog/dv/user_spi/Makefile
@@ -29,14 +29,14 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include
-## SYNTACORE FIRMWARE
-SYNTACORE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/rtl/syntacore/scr1/sim/tests/common
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware
GCC64_PREFIX?=riscv64-unknown-elf
## RISCV GCC
@@ -59,9 +59,9 @@
vvp: ${PATTERN:=.vvp}
%.vvp: %_tb.v
- ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common user_risc_boot.c -o user_risc_boot.o
- ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common/ ../../rtl/syntacore/scr1/sim/tests/common/crt_tcm.S -o crt_tcm.o
- ${GCC64_PREFIX}-gcc -o user_risc_boot.elf -T ../../rtl/syntacore/scr1/sim/tests/common/link_tcm.ld user_risc_boot.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
+ ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_risc_boot.c -o user_risc_boot.o
+ ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt_tcm.S -o crt_tcm.o
+ ${GCC64_PREFIX}-gcc -o user_risc_boot.elf -T $(YIFIVE_FIRMWARE_PATH)/link_tcm.ld user_risc_boot.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
${GCC64_PREFIX}-objcopy -O verilog user_risc_boot.elf user_risc_boot.hex
${GCC64_PREFIX}-objdump -D user_risc_boot.elf > user_risc_boot.dump
rm crt_tcm.o user_risc_boot.o
diff --git a/verilog/dv/user_uart/Makefile b/verilog/dv/user_uart/Makefile
index 401a399..95eba63 100644
--- a/verilog/dv/user_uart/Makefile
+++ b/verilog/dv/user_uart/Makefile
@@ -29,14 +29,14 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include
-## SYNTACORE FIRMWARE
-SYNTACORE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/rtl/syntacore/scr1/sim/tests/common
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware
GCC64_PREFIX?=riscv64-unknown-elf
## RISCV GCC
@@ -59,9 +59,9 @@
vvp: ${PATTERN:=.vvp}
%.vvp: %_tb.v
- ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common user_uart.c -o user_uart.o
- ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common/ ../../rtl/syntacore/scr1/sim/tests/common/crt_tcm.S -o crt_tcm.o
- ${GCC64_PREFIX}-gcc -o user_uart.elf -T ../../rtl/syntacore/scr1/sim/tests/common/link_tcm.ld user_uart.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
+ ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_uart.c -o user_uart.o
+ ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt_tcm.S -o crt_tcm.o
+ ${GCC64_PREFIX}-gcc -o user_uart.elf -T $(YIFIVE_FIRMWARE_PATH)/link_tcm.ld user_uart.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
${GCC64_PREFIX}-objcopy -O verilog user_uart.elf user_uart.hex
${GCC64_PREFIX}-objdump -D user_uart.elf > user_uart.dump
rm crt_tcm.o user_uart.o
diff --git a/verilog/dv/user_uart_master/Makefile b/verilog/dv/user_uart_master/Makefile
index cb31b0b..dbe1ce7 100644
--- a/verilog/dv/user_uart_master/Makefile
+++ b/verilog/dv/user_uart_master/Makefile
@@ -29,14 +29,14 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include
-## SYNTACORE FIRMWARE
-SYNTACORE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/rtl/syntacore/scr1/sim/tests/common
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware
## Simulation mode: RTL/GL
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile
index 6e144bf..d378ce7 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/wb_port/Makefile
@@ -30,7 +30,7 @@
UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv
index e3ae61b..12d5625 100755
--- a/verilog/rtl/pinmux/src/pinmux.sv
+++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -1,3 +1,41 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Pinmux ////
+//// ////
+//// This file is part of the riscduino cores project ////
+//// https://github.com/dineshannayya/riscduino.git ////
+//// ////
+//// Description ////
+//// PinMux Manages all the pin multiplexing ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 16th Feb 2021, Dinesh A ////
+//// initial version ////
+//////////////////////////////////////////////////////////////////////
+
module pinmux (
`ifdef USE_POWER_PINS
input logic vccd1,// User area 1 1.8V supply
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv
index 24c8ae6..549dc68 100644
--- a/verilog/rtl/pinmux/src/pinmux_reg.sv
+++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -1,4 +1,41 @@
-
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Pinmux Register ////
+//// ////
+//// This file is part of the riscduino cores project ////
+//// https://github.com/dineshannayya/riscduino.git ////
+//// ////
+//// Description ////
+//// Hold all the Global and PinMux Register ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 16th Feb 2021, Dinesh A ////
+//// initial version ////
+//////////////////////////////////////////////////////////////////////
+//
module pinmux_reg (
// System Signals
// Inputs
@@ -684,7 +721,7 @@
//-----------------------------------------
// Software Reg-2, Release date: <DAY><MONTH><YEAR>
// ----------------------------------------
-gen_32b_reg #(32'h0801_2022) u_reg_23 (
+gen_32b_reg #(32'h1401_2022) u_reg_23 (
//List of Inputs
.reset_n (h_reset_n ),
.clk (mclk ),
@@ -697,9 +734,9 @@
);
//-----------------------------------------
-// Software Reg-3: Poject Revison 2.6 = 0002600
+// Software Reg-3: Poject Revison 3.0 = 0003000
// ----------------------------------------
-gen_32b_reg #(32'h0002_6000) u_reg_24 (
+gen_32b_reg #(32'h0003_0000) u_reg_24 (
//List of Inputs
.reset_n (h_reset_n ),
.clk (mclk ),
diff --git a/verilog/rtl/syntacore/scr1/LICENSE b/verilog/rtl/syntacore/scr1/LICENSE
deleted file mode 100644
index 0d753ad..0000000
--- a/verilog/rtl/syntacore/scr1/LICENSE
+++ /dev/null
@@ -1,23 +0,0 @@
-# Solderpad Hardware Licence Version 2.0
-
-This licence (the “Licence”) operates as a wraparound licence to the Apache License Version 2.0 (the “Apache License”) and grants to You the rights, and imposes the obligations, set out in the Apache License (which can be found here: http://apache.org/licenses/LICENSE-2.0), with the following extensions. It must be read in conjunction with the Apache License. Section 1 below modifies definitions in the Apache License, and section 2 below replaces sections 2 of the Apache License. You may, at your option, choose to treat any Work released under this License as released under the Apache License (thus ignoring all sections written below entirely). Words in italics indicate changes rom the Apache License, but are indicative and not to be taken into account in interpretation.
-
-1. The definitions set out in the Apache License are modified as follows:
-
-Copyright any reference to ‘copyright’ (whether capitalised or not) includes ‘Rights’ (as defined below).
-
-Contribution also includes any design, as well as any work of authorship.
-
-Derivative Works shall not include works that remain reversibly separable from, or merely link (or bind by name) or physically connect to or interoperate with the interfaces of the Work and Derivative Works thereof.
-
-Object form shall mean any form resulting from mechanical transformation or translation of a Source form or the application of a Source form to physical material, including but not limited to compiled object code, generated documentation, the instantiation of a hardware design or physical object and conversions to other media types, including intermediate forms such as bytecodes, FPGA bitstreams, moulds, artwork and semiconductor topographies (mask works).
-
-Rights means copyright and any similar right including design right (whether registered or unregistered), semiconductor topography (mask) rights and database rights (but excluding Patents and Trademarks).
-
-Source form shall mean the preferred form for making modifications, including but not limited to source code, net lists, board layouts, CAD files, documentation source, and configuration files.
-
-Work also includes a design or work of authorship, whether in Source form or other Object form.
-
-2. Grant of Licence
-
-2.1 Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable license under the Rights to reproduce, prepare Derivative Works of, make, adapt, repair, publicly display, publicly perform, sublicense, and distribute the Work and such Derivative Works in Source or Object form and do anything in relation to the Work as if the Rights did not exist.
diff --git a/verilog/rtl/syntacore/scr1/Makefile b/verilog/rtl/syntacore/scr1/Makefile
deleted file mode 100644
index a2142c4..0000000
--- a/verilog/rtl/syntacore/scr1/Makefile
+++ /dev/null
@@ -1,310 +0,0 @@
-#//////////////////////////////////////////////////////////////////////////////
-#// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-#//
-#// Licensed under the Apache License, Version 2.0 (the "License");
-#// you may not use this file except in compliance with the License.
-#// You may obtain a copy of the License at
-#//
-#// http://www.apache.org/licenses/LICENSE-2.0
-#//
-#// Unless required by applicable law or agreed to in writing, software
-#// distributed under the License is distributed on an "AS IS" BASIS,
-#// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-#// See the License for the specific language governing permissions and
-#// limitations under the License.
-#// SPDX-License-Identifier: Apache-2.0
-#// SPDX-FileContributor: Syntacore LLC
-#// //////////////////////////////////////////////////////////////////////////
-#------------------------------------------------------------------------------
-# Makefile for SCR1
-#------------------------------------------------------------------------------
-
-# PARAMETERS
-
-# CFG = <MAX, BASE, MIN, CUSTOM>
-# BUS = <AHB, AXI>
-
-export CFG ?= MAX
-export BUS ?= AHB
-
-ifeq ($(CFG), MAX)
-# Predefined configuration SCR1_CFG_RV32IMC_MAX
- override ARCH := IMC
- override VECT_IRQ := 1
- override IPIC := 1
- override TCM := 1
- override SIM_CFG_DEF := SCR1_CFG_RV32IMC_MAX
-else
- ifeq ($(CFG), BASE)
- # Predefined configuration SCR1_CFG_RV32IC_BASE
- override ARCH := IC
- override VECT_IRQ := 1
- override IPIC := 1
- override TCM := 1
- override SIM_CFG_DEF := SCR1_CFG_RV32IC_BASE
- else
- ifeq ($(CFG), MIN)
- # Predefined configuration SCR1_CFG_RV32EC_MIN
- override ARCH := EC
- override VECT_IRQ := 0
- override IPIC := 0
- override TCM := 1
- override SIM_CFG_DEF := SCR1_CFG_RV32EC_MIN
- else
- # CUSTOM configuration. Parameters can be overwritten
- # These options are for compiling tests only. Set the corresponding RTL parameters manually in the file scr1_arch_description.svh.
- # ARCH = <IMC, IC, IM, I, EMC, EM, EC, E>
- # VECT_IRQ = <0, 1>
- # IPIC = <0, 1>
- # TCM = <0, 1>
- ARCH ?= IMC
- VECT_IRQ ?= 0
- IPIC ?= 0
- TCM ?= 0
- SIM_CFG_DEF = SCR1_CFG_$(CFG)
- endif
- endif
-endif
-
-# export all overrided variables
-export ARCH
-export VECT_IRQ
-export IPIC
-export TCM
-export SIM_CFG_DEF
-
-ARCH_lowercase = $(shell echo $(ARCH) | tr A-Z a-z)
-BUS_lowercase = $(shell echo $(BUS) | tr A-Z a-z)
-
-ifeq ($(ARCH_lowercase),)
- ARCH_tmp = imc
-else
- ifneq (,$(findstring e,$(ARCH_lowercase)))
- ARCH_tmp += e
- EXT_CFLAGS += -D__RVE_EXT
- else
- ARCH_tmp += i
- endif
- ifneq (,$(findstring m,$(ARCH_lowercase)))
- ARCH_tmp := $(ARCH_tmp)m
- endif
- ifneq (,$(findstring c,$(ARCH_lowercase)))
- ARCH_tmp := $(ARCH_tmp)c
- EXT_CFLAGS += -D__RVC_EXT
- endif
-endif
-
-override ARCH=$(ARCH_tmp)
-
-# Use this parameter to enable tracelog
-TRACE ?= 0
-
-ifeq ($(TRACE), 1)
- export SIM_TRACE_DEF = SCR1_TRACE_LOG_EN
-else
- export SIM_TRACE_DEF = SCR1_TRACE_LOG_DIS
-endif
-
-
-# Use this parameter to pass additional options for simulation build command
-SIM_BUILD_OPTS ?=
-
-# Use this parameter to set the list of tests to run
-# TARGETS = <riscv_isa, riscv_compliance, coremark, dhrystone21, hello, isr_sample>
-export TARGETS :=
-
-
-export ABI ?= ilp32
-# Testbench memory delay patterns\
- (FFFFFFFF - no delay, 00000000 - random delay, 00000001 - max delay)
-imem_pattern ?= FFFFFFFF
-dmem_pattern ?= FFFFFFFF
-
-VCS_OPTS ?=
-MODELSIM_OPTS ?=
-NCSIM_OPTS ?=
-VERILATOR_OPTS ?=
-
-current_goal := $(MAKECMDGOALS:run_%=%)
-ifeq ($(current_goal),)
- current_goal := verilator
-endif
-
-# Paths
-export root_dir := $(shell pwd)
-export tst_dir := $(root_dir)/sim/tests
-export inc_dir := $(tst_dir)/common
-export bld_dir := $(root_dir)/build/$(current_goal)_$(BUS)_$(CFG)_$(ARCH)_IPIC_$(IPIC)_TCM_$(TCM)_VIRQ_$(VECT_IRQ)_TRACE_$(TRACE)
-
-test_results := $(bld_dir)/test_results.txt
-test_info := $(bld_dir)/test_info
-sim_results := $(bld_dir)/sim_results.txt
-
-todo_list := $(bld_dir)/todo.txt
-# Environment
-export CROSS_PREFIX ?= riscv64-unknown-elf-
-export RISCV_GCC ?= $(CROSS_PREFIX)gcc
-export RISCV_OBJDUMP ?= $(CROSS_PREFIX)objdump -D
-export RISCV_OBJCOPY ?= $(CROSS_PREFIX)objcopy -O verilog
-export RISCV_READELF ?= $(CROSS_PREFIX)readelf -s
-#--
-ifneq (,$(findstring axi,$(BUS_lowercase)))
-export rtl_top_files := axi_top.files
-export rtl_tb_files := axi_tb.files
-export top_module := scr1_top_tb_axi
-else
-export rtl_top_files := ahb_top.files
-export rtl_tb_files := ahb_tb.files
-export top_module := scr1_top_tb_ahb
-endif
-
-ifneq (,$(findstring e,$(ARCH_lowercase)))
-# Tests can be compiled for RVE only if gcc version 8.0.0 or higher
- GCCVERSIONGT7 := $(shell expr `$(RISCV_GCC) -dumpfullversion | cut -f1 -d'.'` \> 7)
- ifeq "$(GCCVERSIONGT7)" "1"
- ABI := ilp32e
- endif
-endif
-
-#--
-ifeq (,$(findstring e,$(ARCH_lowercase)))
-# These tests cannot be compiled for RVE
-
- # Comment this target if you don't want to run the riscv_isa
- TARGETS += riscv_isa
-
- # Comment this target if you don't want to run the riscv_compliance
- TARGETS += riscv_compliance
-endif
-
-# Comment this target if you don't want to run the isr_sample
-TARGETS += isr_sample
-
-# Comment this target if you don't want to run the coremark
-TARGETS += coremark
-
-# Comment this target if you don't want to run the dhrystone
-TARGETS += dhrystone21
-
-# Comment this target if you don't want to run the hello test
-TARGETS += hello
-
-# Targets
-.PHONY: tests run_modelsim run_vcs run_ncsim run_verilator run_verilator_wf
-
-default: clean_test_list run_verilator
-
-clean_test_list:
- rm -f $(test_info)
-
-echo_out: tests
- @echo " Test | build | simulation " ;
- @echo "$$(cat $(test_results))"
-
-tests: $(TARGETS)
-
-$(test_info): clean_hex tests
- cd $(bld_dir)
-
-isr_sample: | $(bld_dir)
- $(MAKE) -C $(tst_dir)/isr_sample ARCH=$(ARCH) IPIC=$(IPIC) VECT_IRQ=$(VECT_IRQ)
-
-dhrystone21: | $(bld_dir)
- $(MAKE) -C $(tst_dir)/benchmarks/dhrystone21 EXT_CFLAGS="$(EXT_CFLAGS)" ARCH=$(ARCH)
-
-coremark: | $(bld_dir)
- -$(MAKE) -C $(tst_dir)/benchmarks/coremark EXT_CFLAGS="$(EXT_CFLAGS)" ARCH=$(ARCH)
-
-riscv_isa: | $(bld_dir)
- $(MAKE) -C $(tst_dir)/riscv_isa ARCH=$(ARCH)
-
-riscv_compliance: | $(bld_dir)
- $(MAKE) -C $(tst_dir)/riscv_compliance ARCH=$(ARCH)
-
-hello: | $(bld_dir)
- -$(MAKE) -C $(tst_dir)/hello EXT_CFLAGS="$(EXT_CFLAGS)" ARCH=$(ARCH)
-
-clean_hex: | $(bld_dir)
- $(RM) $(bld_dir)/*.hex
-
-$(bld_dir):
- mkdir -p $(bld_dir)
-
-run_vcs: $(test_info)
- $(MAKE) -C $(root_dir)/sim build_vcs SIM_CFG_DEF=$(SIM_CFG_DEF) SIM_TRACE_DEF=$(SIM_TRACE_DEF) SIM_BUILD_OPTS=$(SIM_BUILD_OPTS);
- printf "" > $(test_results);
- cd $(bld_dir); \
- $(bld_dir)/simv -V \
- +test_info=$(test_info) \
- +test_results=$(test_results) \
- +imem_pattern=$(imem_pattern) \
- +dmem_pattern=$(dmem_pattern) \
- $(VCS_OPTS) | tee $(sim_results) ;\
- printf " Test | build | simulation \n" ; \
- printf "$$(cat $(test_results)) \n"
-run_modelsim: $(test_info)
- $(MAKE) -C $(root_dir)/sim build_modelsim SIM_CFG_DEF=$(SIM_CFG_DEF) SIM_TRACE_DEF=$(SIM_TRACE_DEF) SIM_BUILD_OPTS=$(SIM_BUILD_OPTS); \
- printf "" > $(test_results); \
- cd $(bld_dir); \
- vsim -c -do "run -all" +nowarn3691 \
- +test_info=$(test_info) \
- +test_results=$(test_results) \
- +imem_pattern=$(imem_pattern) \
- +dmem_pattern=$(dmem_pattern) \
- work.$(top_module) \
- $(MODELSIM_OPTS) | tee $(sim_results) ;\
- printf "Simulation performed on $$(vsim -version) \n" ;\
- printf " Test | build | simulation \n" ; \
- printf "$$(cat $(test_results)) \n"
-
-run_ncsim: $(test_info)
- $(MAKE) -C $(root_dir)/sim build_ncsim SIM_CFG_DEF=$(SIM_CFG_DEF) SIM_TRACE_DEF=$(SIM_TRACE_DEF) SIM_BUILD_OPTS=$(SIM_BUILD_OPTS);
- printf "" > $(test_results);
- cd $(bld_dir); \
- irun \
- -R \
- -64bit \
- +test_info=$(test_info) \
- +test_results=$(test_results) \
- +imem_pattern=$(imem_pattern) \
- +dmem_pattern=$(dmem_pattern) \
- $(NCSIM_OPTS) | tee $(sim_results) ;\
- printf "Simulation performed on $$(irun -version) \n" ;\
- printf " Test | build | simulation \n" ; \
- printf "$$(cat $(test_results)) \n"
-
-run_verilator: $(test_info)
- $(MAKE) -C $(root_dir)/sim build_verilator SIM_CFG_DEF=$(SIM_CFG_DEF) SIM_TRACE_DEF=$(SIM_TRACE_DEF) SIM_BUILD_OPTS=$(SIM_BUILD_OPTS);
- printf "" > $(test_results);
- cd $(bld_dir); \
- echo $(top_module) | tee $(sim_results); \
- $(bld_dir)/verilator/V$(top_module) \
- +test_info=$(test_info) \
- +test_results=$(test_results) \
- +imem_pattern=$(imem_pattern) \
- +dmem_pattern=$(dmem_pattern) \
- $(VERILATOR_OPTS) | tee -a $(sim_results) ;\
- printf "Simulation performed on $$(verilator -version) \n" ;\
- printf " Test | build | simulation \n" ; \
- printf "$$(cat $(test_results)) \n"
-
-run_verilator_wf: $(test_info)
- $(MAKE) -C $(root_dir)/sim build_verilator_wf SIM_CFG_DEF=$(SIM_CFG_DEF) SIM_TRACE_DEF=$(SIM_TRACE_DEF) SIM_BUILD_OPTS=$(SIM_BUILD_OPTS);
- printf "" > $(test_results);
- cd $(bld_dir); \
- echo $(top_module) | tee $(sim_results); \
- $(bld_dir)/verilator/V$(top_module) \
- +test_info=$(test_info) \
- +test_results=$(test_results) \
- +imem_pattern=$(imem_pattern) \
- +dmem_pattern=$(dmem_pattern) \
- $(VERILATOR_OPTS) | tee -a $(sim_results) ;\
- printf "Simulation performed on $$(verilator -version) \n" ;\
- printf " Test | build | simulation \n" ; \
- printf "$$(cat $(test_results)) \n"
-clean:
- $(MAKE) -C $(tst_dir)/benchmarks/dhrystone21 clean
- $(MAKE) -C $(tst_dir)/riscv_isa clean
- $(MAKE) -C $(tst_dir)/riscv_compliance clean
- $(RM) -R $(root_dir)/build/*
- $(RM) $(test_info)
diff --git a/verilog/rtl/syntacore/scr1/README.md b/verilog/rtl/syntacore/scr1/README.md
deleted file mode 100644
index 0fb6648..0000000
--- a/verilog/rtl/syntacore/scr1/README.md
+++ /dev/null
@@ -1,197 +0,0 @@
-# SCR1 RISC-V Core
-
-SCR1 is an open-source and free to use RISC-V compatible MCU-class core, designed and maintained by Syntacore. It is industry-grade and silicon-proven (including full-wafer production), works out of the box in all major EDA flows and Verilator, and comes with extensive collateral and documentation.
-
-
-
-## Key features
-
-* Open sourced under SHL-license (see LICENSE file) - unrestricted commercial use allowed
-* RV32I or RV32E ISA base + optional RVM and RVC standard extensions
-* Machine privilege mode only
-* 2 to 4 stage pipeline
-* Optional Integrated Programmable Interrupt Controller with 16 IRQ lines
-* Optional RISC-V Debug subsystem with JTAG interface
-* Optional on-chip Tightly-Coupled Memory
-* 32-bit AXI4/AHB-Lite external interface
-* Written in SystemVerilog
-* Optimized for area and power
-* 3 predefined recommended configurations
-* A number of fine-tuning options for custom configuration
-* Verification suite provided
-* Extensive documentation
-
-For more information on core architecture, see [SCR1 External Architecture Specification](https://github.com/syntacore/scr1/blob/master/docs/scr1_eas.pdf).
-
-For more information on project usage, see [SCR1 User Manual](https://github.com/syntacore/scr1/blob/master/docs/scr1_um.pdf).
-
-## Repository contents
-
-|Folder | Description
-|------ | -----------
-|**dependencies** | **Dependent submodules**
-|├─ riscv-tests | Common source files for RISC-V ISA tests
-|├─ riscv-compliance | Common source files for RISC-V Compliance tests
-|└─ coremark | Common source files for EEMBC's CoreMark® benchmark
-|**docs** | **SCR1 documentation**
-|├─ scr1_eas.pdf | SCR1 External Architecture Specification
-|└─ scr1_um.pdf | SCR1 User Manual
-|**sim** | **Tests and scripts for simulation**
-|├─ tests/common | Common source files for tests
-|├─ tests/riscv_isa | RISC-V ISA tests platform specific source files
-|├─ tests/riscv_compliance | RISC-V Compliance platform specific source files
-|├─ tests/benchmarks/dhrystone21 | Dhrystone 2.1 benchmark source files
-|├─ tests/benchmarks/coremark | EEMBC's CoreMark® benchmark platform specific source files
-|├─ tests/isr_sample | Sample program "Interrupt Service Routine"
-|├─ tests/hello | Sample program "Hello"
-|└─ verilator_wrap | Wrappers for Verilator simulation
-|**src** | **SCR1 RTL source and testbench files**
-|├─ includes | Header files
-|├─ core | Core top source files
-|├─ top | Cluster source files
-|└─ tb | Testbench files
-
-## SCR1 source file lists
-
-SCR1 source file lists of SCR1 can be found in [./src](https://github.com/syntacore/scr1/tree/master/src):
-
-* **core.files** - all synthesized file sources of the SCR1 core
-* **ahb_top.files** - synthesized file sources of AHB cluster
-* **axi_top.files** - synthesized file sources of AXI cluster
-* **ahb_tb.files** - testbench file sources for AHB cluster (for simulation only)
-* **axi_tb.files** - testbench file sources for AXI cluster (for simulation only)
-
-Library with header files to include is [./src/includes/](https://github.com/syntacore/scr1/tree/master/src/includes)
-
-## Simulation quick start guide
-
-The project contains testbenches, test sources and scripts to quickly start the SCR1 simulation. Before starting the simulation, make sure you have:
-
-* installed RISC-V GCC toolchain,
-* installed one of the supported simulators,
-* initialized submodules with test sources.
-
-### Requirements
-
-#### Operating system
-
-GCC toolchain and make-scripts are supported by most popular Linux-like operating systems.
-
-To run from Windows you can use an additional compatibility layer, such as WSL or Cygwin.
-
-#### RISC-V GCC toolchain
-
-RISC-V GCC toolchain is required to compile the software. You can use pre-built binaries or build the toolchain from scratch.
-
-##### Using pre-built binary tools
-
-Pre-built RISC-V GCC toolchain with support for all SCR1 architectural configurations is available for download from http://syntacore.com/page/products/sw-tools.
-
-1. Download the archive for your platform.
-2. Extract the archive to preferred directory `<GCC_INSTALL_PATH>`.
-3. Add the `<GCC_INSTALL_PATH>/bin` folder to the $PATH environment variable:
-```
- export PATH=<GCC_INSTALL_PATH>/bin:$PATH
-```
-
-##### Building tools from source
-
-You can build the RISC-V GCC toolchain from sources, stored in official repo https://github.com/riscv/riscv-gnu-toolchain
-
-Instructions on how to prepare and build the toolchain can be found on https://github.com/riscv/riscv-gnu-toolchain/blob/master/README.md
-
-We recommend using the multilib compiler. Please note that RV32IC, RV32E, RV32EM, RV32EMC, RV32EC architectural configurations are not included in the compiler by default. If you plan to use them, you will need to include the appropriate libraries by yourself before building.
-
-After the building, be sure to add the `<GCC_INSTALL_PATH>/bin` folder to the $PATH environment variable
-
-
-#### HDL simulators
-
-Currently supported simulators:
-
-* Verilator (last verified version: v4.102)
-* Intel ModelSim (last verified version: INTEL FPGA STARTER EDITION vsim 2020.1_3)
-* Mentor Graphics ModelSim (last verified version: Modelsim PE Student Edition 10.4a)
-* Synopsys VCS (last verified version: vcs-mx_vL-2016.06)
-* Cadence NCSim
-
-Please note that RTL simulator executables should be in your $PATH variable.
-
-#### Tests preparation
-
-The simulation package includes the following tests:
-
-* **hello** - "Hello" sample program
-* **isr_sample** - "Interrupt Service Routine" sample program
-* **riscv_isa** - RISC-V ISA tests (submodule)
-* **riscv_compliance** - RISC-V Compliance tests (submodule)
-* **dhrystone21** - Dhrystone 2.1 benchmark
-* **coremark** - EEMBC's CoreMark® benchmark (submodule)
-
-After the main SCR1 repository has been cloned execute the following command:
-```
- git submodule update --init --recursive
-```
-
-This command will initialized submodules with test sources.
-
-### Running simulation
-
-To build RTL, compile and run tests from the repo root folder you have to call Makefile.
-By default, you may simply call Makefile without any parameters:
-``` sh
- make
-```
-
-In this case simulation will run on Verilator with following parameters: `CFG=MAX BUS=AHB TRACE=0 TARGETS="hello isr_sample riscv_isa riscv_compliance dhrystone21 coremark"`.
-
-Makefile supports:
-
-* choice of simulator - `run_<SIMULATOR> = <run_vcs, run_modelsim, run_ncsim, run_verilator, run_verilator_wf>`
-* selection of external interface - `BUS = <AHB, AXI>`,
-* configuration setup - `CFG = <MAX, BASE, MIN, CUSTOM>`,
-* parameters for CUSTOM configuration - `ARCH = <IMC, IC, IM, I, EMC, EM, EC, E>, VECT_IRQ = <0, 1>, IPIC = <0, 1>, TCM = <0, 1>`
-* tests subset to run - `TARGETS = <hello, isr_sample, riscv_isa, riscv_compliance, dhrystone21, coremark>`
-* enabling tracelog - `TRACE = <0, 1>`
-* and any additional options to pass to the simulator - `SIM_BUILD_OPTS`.
-
-Examples:
-``` sh
- make run_verilator_wf CFG=MAX BUS=AXI TARGETS="riscv_isa riscv_compliance" TRACE=1
- make run_vcs CFG=BASE BUS=AHB TARGETS="dhrystone21 coremark" SIM_BUILD_OPTS="-gui"
- make run_modelsim CFG=CUSTOM BUS=AXI ARCH=I VECT_IRQ=1 IPIC=1 TCM=0 TARGETS=isr_sample
-```
-
-Build and run parameters can be configured in the `./Makefile`.
-
-After all the tests have finished, the results can be found in `build/<SIM_CFG>/test_results.txt`.
-
-**IMPORTANT:** To ensure correct rebuild, please clean build directory between simulation runs:
-``` sh
- make clean
-```
-
-Please refer to the *"Simulation environment"* chapter of the [SCR1 User Manual](https://github.com/syntacore/scr1/blob/master/docs/scr1_um.pdf) for more information on setting up a simulation run.
-
-## SCR1 SDKs
-
-FPGA-based SDKs are available at the <https://github.com/syntacore/scr1-sdk>.
-
-Repo contains:
-
-* Pre-build images and open designs for several standard FPGAs boards:
- * Digilent Arty (Xilinx)
- * Digilent Nexys 4 DDR (Xilinx)
- * Arria V GX Starter (Intel)
- * Terasic DE10-Lite (Intel)
-* Software package:
- * Bootloader
- * Zephyr RTOS
- * Tests\SW samples
-* User Guides for SDKs and tools
-
-## Contacts
-
-Report an issue: <https://github.com/syntacore/scr1/issues>
-
-Ask a question: scr1@syntacore.com
diff --git a/verilog/rtl/syntacore/scr1/docs/img/scr1_cluster.svg b/verilog/rtl/syntacore/scr1/docs/img/scr1_cluster.svg
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diff --git a/verilog/rtl/syntacore/scr1/docs/scr1_eas.pdf b/verilog/rtl/syntacore/scr1/docs/scr1_eas.pdf
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index e436e1c..0000000
--- a/verilog/rtl/syntacore/scr1/docs/scr1_eas.pdf
+++ /dev/null
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diff --git a/verilog/rtl/syntacore/scr1/docs/scr1_um.pdf b/verilog/rtl/syntacore/scr1/docs/scr1_um.pdf
deleted file mode 100644
index 07a69d1..0000000
--- a/verilog/rtl/syntacore/scr1/docs/scr1_um.pdf
+++ /dev/null
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diff --git a/verilog/rtl/syntacore/scr1/src/core.files b/verilog/rtl/syntacore/scr1/src/core.files
deleted file mode 100644
index 5a40ec6..0000000
--- a/verilog/rtl/syntacore/scr1/src/core.files
+++ /dev/null
@@ -1,40 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: 2021, Dinesh Annayya
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
-// //////////////////////////////////////////////////////////////////////////
-core/pipeline/scr1_pipe_hdu.sv
-core/pipeline/scr1_pipe_tdu.sv
-core/pipeline/scr1_ipic.sv
-core/pipeline/scr1_pipe_csr.sv
-core/pipeline/scr1_pipe_exu.sv
-core/pipeline/scr1_pipe_ialu.sv
-core/pipeline/scr1_pipe_idu.sv
-core/pipeline/scr1_pipe_ifu.sv
-core/pipeline/scr1_pipe_lsu.sv
-core/pipeline/scr1_pipe_mprf.sv
-core/pipeline/scr1_pipe_mul.sv
-core/pipeline/scr1_pipe_div.sv
-core/pipeline/scr1_pipe_top.sv
-core/primitives/scr1_reset_cells.sv
-core/primitives/scr1_cg.sv
-core/scr1_clk_ctrl.sv
-core/scr1_tapc_shift_reg.sv
-core/scr1_tapc.sv
-core/scr1_tapc_synchronizer.sv
-core/scr1_core_top.sv
-core/scr1_dm.sv
-core/scr1_dmi.sv
-core/scr1_scu.sv
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_ipic.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_ipic.sv
deleted file mode 100644
index 4afaae5..0000000
--- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_ipic.sv
+++ /dev/null
@@ -1,673 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_ipic.sv>
-/// @brief Integrated Programmable Interrupt Controller (IPIC)
-///
-
-//------------------------------------------------------------------------------
- //
- // Functionality:
- // - Synchronizes IRQ lines (optional)
- // - Detects level and edge (with optional lines inversion) of IRQ lines
- // - Setups interrupts handling (mode, inversion, enable)
- // - Provides information about pending interrupts and interrupts currently in
- // service
- // - Generates interrupt request to CSR
- //
- // Structure:
- // - IRQ lines handling (synchronization, level and edge detection) logic
- // - IPIC registers:
- // - CISV
- // - CICSR
- // - EOI
- // - SOI
- // - IDX
- // - IPR
- // - ISVR
- // - IER
- // - IMR
- // - IINVR
- // - ICSR
- // - Priority interrupt generation logic
- //
-//------------------------------------------------------------------------------
-
-`include "scr1_arch_description.svh"
-
-`ifdef SCR1_IPIC_EN
-
-`include "scr1_ipic.svh"
-
-module scr1_ipic
-(
- // Common
- input logic rst_n, // IPIC reset
- input logic clk, // IPIC clock
-
- // External Interrupt lines
- input logic [SCR1_IRQ_LINES_NUM-1:0] soc2ipic_irq_lines_i, // External IRQ lines
-
- // CSR <-> IPIC interface
- input logic csr2ipic_r_req_i, // IPIC read request
- input logic csr2ipic_w_req_i, // IPIC write request
- input logic [2:0] csr2ipic_addr_i, // IPIC address
- input logic [`SCR1_XLEN-1:0] csr2ipic_wdata_i, // IPIC write data
- output logic [`SCR1_XLEN-1:0] ipic2csr_rdata_o, // IPIC read data
- output logic ipic2csr_irq_m_req_o // IRQ request from IPIC
-);
-
-//-------------------------------------------------------------------------------
-// Local types declaration
-//-------------------------------------------------------------------------------
-typedef struct packed { // cp.6
- logic vd;
- logic idx;
-} type_scr1_search_one_2_s;
-
-typedef struct packed { // cp.6
- logic vd;
- logic [SCR1_IRQ_VECT_WIDTH-1:0] idx;
-} type_scr1_search_one_16_s;
-
-typedef struct packed {
- logic ip;
- logic ie;
- logic im;
- logic inv;
- logic is;
- logic [SCR1_IRQ_LINES_WIDTH-1:0] line;
-} type_scr1_icsr_m_s;
-
-typedef struct packed {
- logic ip;
- logic ie;
-} type_scr1_cicsr_s;
-
-//-------------------------------------------------------------------------------
-// Local functions declaration
-//-------------------------------------------------------------------------------
-
-function automatic type_scr1_search_one_2_s scr1_search_one_2(
- input logic [1:0] din
-);
- type_scr1_search_one_2_s tmp;
-begin
- tmp.vd = |din;
- tmp.idx = ~din[0];
- scr1_search_one_2 = tmp;
-end
-endfunction
-
-function automatic type_scr1_search_one_16_s scr1_search_one_16(
- input logic [15:0] din
-);
- logic [7:0] stage1_vd;
- logic [3:0] stage2_vd;
- logic [1:0] stage3_vd;
-
- logic stage1_idx [7:0];
- logic [1:0] stage2_idx [3:0];
- logic [2:0] stage3_idx [1:0];
- type_scr1_search_one_16_s result;
- type_scr1_search_one_2_s tmp;
- integer i; // cp.17
-begin
- // Stage 1
- for (i=0; i<8; i=i+1) begin
- tmp = scr1_search_one_2(din[(i+1)*2-1-:2]);
- stage1_vd[i] = tmp.vd;
- stage1_idx[i] = tmp.idx;
- end
-
- // Stage 2
- for (i=0; i<4; i=i+1) begin
- tmp = scr1_search_one_2(stage1_vd[(i+1)*2-1-:2]);
- stage2_vd[i] = tmp.vd;
- stage2_idx[i] = (~tmp.idx) ? {tmp.idx, stage1_idx[2*i]} : {tmp.idx, stage1_idx[2*i+1]};
- end
-
- // Stage 3
- for (i=0; i<2; i=i+1) begin
- tmp = scr1_search_one_2(stage2_vd[(i+1)*2-1-:2]);
- stage3_vd[i] = tmp.vd;
- stage3_idx[i] = (~tmp.idx) ? {tmp.idx, stage2_idx[2*i]} : {tmp.idx, stage2_idx[2*i+1]};
- end
-
- // Stage 4
- result.vd = |stage3_vd;
- result.idx = (stage3_vd[0]) ? {1'b0, stage3_idx[0]} : {1'b1, stage3_idx[1]};
-
- scr1_search_one_16 = result;
-end
-endfunction
-
-//------------------------------------------------------------------------------
-// Local signals declaration
-//------------------------------------------------------------------------------
-
-// IRQ lines handling signals
-//------------------------------------------------------------------------------
-
-logic [SCR1_IRQ_VECT_NUM-1:0] irq_lines; // Internal IRQ lines
-`ifdef SCR1_IPIC_SYNC_EN
-logic [SCR1_IRQ_VECT_NUM-1:0] irq_lines_sync;
-`endif // SCR1_IPIC_SYNC_EN
-logic [SCR1_IRQ_VECT_NUM-1:0] irq_lines_dly; // Internal IRQ lines delayed for 1 cycle
-logic [SCR1_IRQ_VECT_NUM-1:0] irq_edge_detected; // IRQ lines edge detected flags
-logic [SCR1_IRQ_VECT_NUM-1:0] irq_lvl; // IRQ lines level
-
-// IPIC registers
-//------------------------------------------------------------------------------
-
-// CISV register
-logic ipic_cisv_upd; // Current Interrupt Vecotr in Service register update
-logic [SCR1_IRQ_VECT_WIDTH-1:0] ipic_cisv_ff; // Current Interrupt Vector in Service register
-logic [SCR1_IRQ_VECT_WIDTH-1:0] ipic_cisv_next; // Current Interrupt Vector in Service register next value
-
-// CICS register (CICSR)
-logic cicsr_wr_req; // Write request to Current Interrupt Control Status register
-type_scr1_cicsr_s ipic_cicsr; // Current Interrupt Control Status register
-
-// EOI register
-logic eoi_wr_req; // Write request to End of Interrupt register
-logic ipic_eoi_req; // Request to end the interrupt that is currently in service
-
-// SOI register
-logic soi_wr_req; // Write request to Start of Interrupt register
-logic ipic_soi_req; // Request to start the interrupt
-
-// IDX register (IDXR)
-logic idxr_wr_req; // Write request to Index register
-logic [SCR1_IRQ_IDX_WIDTH-1:0] ipic_idxr_ff; // Index register
-
-// IP register (IPR)
-logic ipic_ipr_upd; // Interrupt pending register update
-logic [SCR1_IRQ_VECT_NUM-1:0] ipic_ipr_ff; // Interrupt pending register
-logic [SCR1_IRQ_VECT_NUM-1:0] ipic_ipr_next; // Interrupt pending register next value
-logic [SCR1_IRQ_VECT_NUM-1:0] ipic_ipr_clr_cond; // Interrupt pending clear condition
-logic [SCR1_IRQ_VECT_NUM-1:0] ipic_ipr_clr_req; // Interrupt pending clear request
-logic [SCR1_IRQ_VECT_NUM-1:0] ipic_ipr_clr; // Interrupt pending clear operation
-
-// ISV register (ISVR)
-logic ipic_isvr_upd; // Interrupt Serviced register update
-logic [SCR1_IRQ_VECT_NUM-1:0] ipic_isvr_ff; // Interrupt Serviced register
-logic [SCR1_IRQ_VECT_NUM-1:0] ipic_isvr_next; // Interrupt Serviced register next value
-
-// IE register (IER)
-logic ipic_ier_upd; // Interrupt enable register update
-logic [SCR1_IRQ_VECT_NUM-1:0] ipic_ier_ff; // Interrupt enable register
-logic [SCR1_IRQ_VECT_NUM-1:0] ipic_ier_next; // Interrupt enable register next value
-
-// IM register (IMR)
-logic [SCR1_IRQ_VECT_NUM-1:0] ipic_imr_ff; // Interrupt mode register
-logic [SCR1_IRQ_VECT_NUM-1:0] ipic_imr_next; // Interrupt mode register next value
-
-// IINV register (IINVR)
-logic [SCR1_IRQ_VECT_NUM-1:0] ipic_iinvr_ff; // Interrupt Inversion register
-logic [SCR1_IRQ_VECT_NUM-1:0] ipic_iinvr_next; // Interrupt Inversion register next value
-
-// ICS register (ICSR)
-logic icsr_wr_req; // Write request to Interrupt Control Status register
-type_scr1_icsr_m_s ipic_icsr; // Interrupt Control Status register
-
-// Priority interrupt generation signals
-//------------------------------------------------------------------------------
-
-// Serviced interrupt signals
-logic irq_serv_vd; // There is an interrupt in service
-logic [SCR1_IRQ_VECT_WIDTH-1:0] irq_serv_idx; // Index of an interrupt that is currently in service
-
-// Requested interrupt signals
-logic irq_req_vd; // There is a requested interrupt
-logic [SCR1_IRQ_VECT_WIDTH-1:0] irq_req_idx; // Index of a requested interrupt
-
-// Interrupt requested on "end of the previous interrupt" signals
-logic irq_eoi_req_vd; // There is a requested interrupt when the previous one has ended
-logic [SCR1_IRQ_VECT_WIDTH-1:0] irq_eoi_req_idx; // Index of an interrupt requested when the previous one has ended
-
-logic [SCR1_IRQ_VECT_NUM-1:0] irq_req_v; // Vector of interrupts that are pending and enabled
-
-logic irq_start_vd; // Request to start an interrupt is valid
-logic irq_hi_prior_pnd; // There is a pending IRQ with a priority higher than of the interrupt that is currently in service
-
-type_scr1_search_one_16_s irr_priority; // Structure for vd and idx of the requested interrupt
-type_scr1_search_one_16_s isvr_priority_eoi; // Structure for vd and idx of the interrupt requested when the previous interrupt has ended
-logic [SCR1_IRQ_VECT_NUM-1:0] ipic_isvr_eoi; // Interrupt Serviced register when the previous interrupt has ended
-
-//------------------------------------------------------------------------------
-// IRQ lines handling
-//------------------------------------------------------------------------------
-
-`ifdef SCR1_IPIC_SYNC_EN
-// IRQ lines synchronization
-//------------------------------------------------------------------------------
-
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- irq_lines_sync <= '0;
- irq_lines <= '0;
- end else begin
- irq_lines_sync <= soc2ipic_irq_lines_i;
- irq_lines <= irq_lines_sync;
- end
-end
-`else // SCR1_IPIC_SYNC_EN
-assign irq_lines = soc2ipic_irq_lines_i;
-`endif // SCR1_IPIC_SYNC_EN
-
-// IRQ lines level detection
-//------------------------------------------------------------------------------
-
-assign irq_lvl = irq_lines ^ ipic_iinvr_next;
-
-// IRQ lines edge detection
-//------------------------------------------------------------------------------
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- irq_lines_dly <= '0;
- end else begin
- irq_lines_dly <= irq_lines;
- end
-end
-
-assign irq_edge_detected = (irq_lines_dly ^ irq_lines) & irq_lvl;
-
-//------------------------------------------------------------------------------
-// IPIC registers read/write interface
-//------------------------------------------------------------------------------
-
-// Read Logic
-//------------------------------------------------------------------------------
-
-// Read data multiplexer
-always_comb begin
- ipic2csr_rdata_o = '0;
-
- if (csr2ipic_r_req_i) begin
- case (csr2ipic_addr_i)
- SCR1_IPIC_CISV : begin
- ipic2csr_rdata_o[SCR1_IRQ_VECT_WIDTH-1:0] = irq_serv_vd
- ? ipic_cisv_ff
- : SCR1_IRQ_VOID_VECT_NUM;
- end
- SCR1_IPIC_CICSR : begin
- ipic2csr_rdata_o[SCR1_IPIC_ICSR_IP] = ipic_cicsr.ip;
- ipic2csr_rdata_o[SCR1_IPIC_ICSR_IE] = ipic_cicsr.ie;
- end
- SCR1_IPIC_IPR : begin
- ipic2csr_rdata_o = `SCR1_XLEN'(ipic_ipr_ff);
- end
- SCR1_IPIC_ISVR : begin
- ipic2csr_rdata_o = `SCR1_XLEN'(ipic_isvr_ff);
- end
- SCR1_IPIC_EOI,
- SCR1_IPIC_SOI : begin
- ipic2csr_rdata_o = '0;
- end
- SCR1_IPIC_IDX : begin
- ipic2csr_rdata_o = `SCR1_XLEN'(ipic_idxr_ff);
- end
- SCR1_IPIC_ICSR : begin
- ipic2csr_rdata_o[SCR1_IPIC_ICSR_IP] = ipic_icsr.ip;
- ipic2csr_rdata_o[SCR1_IPIC_ICSR_IE] = ipic_icsr.ie;
- ipic2csr_rdata_o[SCR1_IPIC_ICSR_IM] = ipic_icsr.im;
- ipic2csr_rdata_o[SCR1_IPIC_ICSR_INV] = ipic_icsr.inv;
- ipic2csr_rdata_o[SCR1_IPIC_ICSR_PRV_MSB:
- SCR1_IPIC_ICSR_PRV_LSB] = SCR1_IPIC_PRV_M;
- ipic2csr_rdata_o[SCR1_IPIC_ICSR_IS] = ipic_icsr.is;
- ipic2csr_rdata_o[SCR1_IPIC_ICSR_LN_MSB-1:
- SCR1_IPIC_ICSR_LN_LSB] = ipic_icsr.line;
- end
- default : begin
- ipic2csr_rdata_o = 'x;
- end
- endcase
- end
-end
-
-// Write logic
-//------------------------------------------------------------------------------
-
-// Register selection
-always_comb begin
- cicsr_wr_req = 1'b0;
- eoi_wr_req = 1'b0;
- soi_wr_req = 1'b0;
- idxr_wr_req = 1'b0;
- icsr_wr_req = 1'b0;
- if (csr2ipic_w_req_i) begin
- case (csr2ipic_addr_i)
- SCR1_IPIC_CISV : begin end // Quiet Read-Only
- SCR1_IPIC_CICSR: cicsr_wr_req = 1'b1;
- SCR1_IPIC_IPR : begin end
- SCR1_IPIC_ISVR : begin end // Quiet Read-Only
- SCR1_IPIC_EOI : eoi_wr_req = 1'b1;
- SCR1_IPIC_SOI : soi_wr_req = 1'b1;
- SCR1_IPIC_IDX : idxr_wr_req = 1'b1;
- SCR1_IPIC_ICSR : icsr_wr_req = 1'b1;
- default : begin // Illegal IPIC register address
- cicsr_wr_req = 'x;
- eoi_wr_req = 'x;
- soi_wr_req = 'x;
- idxr_wr_req = 'x;
- icsr_wr_req = 'x;
- end
- endcase
- end
-end
-
-//------------------------------------------------------------------------------
-// IPIC registers
-//------------------------------------------------------------------------------
-//
- // Registers:
- // - Current Interrupt Vector in Service (CISV) register
- // - Current Interrupt Control Status (CICSR) register
- // - End of Interrupt (EOI) register
- // - Start of Interrupt (SOI) register
- // - Index (IDX) register
- // - Interrupt Pending Register (IPR)
- // - Interrupt Serviced Register (ISVR)
- // - Interrupt Enable Register (IER)
- // - Interrupt Mode Register (IMR)
- // - Interrupt Inversion Register (IINVR)
- // - Interrupt Control Status Register (ICSR)
-//
-
-// CISV register
-//------------------------------------------------------------------------------
-// Contains number of the interrupt vector currently in service. When no
-// interrupts are in service, contains number of the void interrupt vector (0x10).
-// The register cannot contain all 0's
-
-assign ipic_cisv_upd = irq_start_vd | ipic_eoi_req;
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- ipic_cisv_ff <= SCR1_IRQ_VOID_VECT_NUM;
- end else if (ipic_cisv_upd) begin
- ipic_cisv_ff <= ipic_cisv_next;
- end
-end
-
-assign ipic_cisv_next = irq_start_vd ? irq_req_idx
- : ipic_eoi_req ? irq_eoi_req_vd ? irq_eoi_req_idx
- : SCR1_IRQ_VOID_VECT_NUM
- : 1'b0;
-
-assign irq_serv_idx = ipic_cisv_ff[SCR1_IRQ_VECT_WIDTH-2:0];
-assign irq_serv_vd = ~ipic_cisv_ff[SCR1_IRQ_VECT_WIDTH-1];
-
-// CICSR register
-//------------------------------------------------------------------------------
-// Shows whether the interrupt currently in service is pending and enabled
-
-assign ipic_cicsr.ip = ipic_ipr_ff[irq_serv_idx] & irq_serv_vd;
-assign ipic_cicsr.ie = ipic_ier_ff[irq_serv_idx] & irq_serv_vd;
-
-// EOI register
-//------------------------------------------------------------------------------
-// Writing any value to EOI register ends the interrupt which is currently in service
-
-assign ipic_eoi_req = eoi_wr_req & irq_serv_vd;
-
-// SOI register
-//------------------------------------------------------------------------------
-// Writing any value to SOI activates start of interrupt if one of the following
-// conditions is true:
-// - There is at least one pending interrupt with IE and ISR is zero
-// - There is at least one pending interrupt with IE and higher priority than the
-// interrupts currently in service
-
-assign ipic_soi_req = soi_wr_req & irq_req_vd;
-
-// IDX register
-//------------------------------------------------------------------------------
-// Defines the number of interrupt vector which is accessed through the IPIC_ICSR
-// register
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- ipic_idxr_ff <= '0;
- end else if (idxr_wr_req) begin
- ipic_idxr_ff <= csr2ipic_wdata_i[SCR1_IRQ_IDX_WIDTH-1:0];
- end
-end
-
-// IPR
-//------------------------------------------------------------------------------
-// For every IRQ line shows whether there is a pending interrupt
-
-assign ipic_ipr_upd = (ipic_ipr_next != ipic_ipr_ff);
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- ipic_ipr_ff <= '0;
- end else if (ipic_ipr_upd) begin
- ipic_ipr_ff <= ipic_ipr_next;
- end
-end
-
-always_comb begin
- ipic_ipr_clr_req = '0;
- if (csr2ipic_w_req_i) begin
- case (csr2ipic_addr_i)
- SCR1_IPIC_CICSR: ipic_ipr_clr_req[irq_serv_idx] = csr2ipic_wdata_i[SCR1_IPIC_ICSR_IP]
- & irq_serv_vd;
- SCR1_IPIC_IPR : ipic_ipr_clr_req = csr2ipic_wdata_i[SCR1_IRQ_VECT_NUM-1:0];
- SCR1_IPIC_SOI : ipic_ipr_clr_req[irq_req_idx] = irq_req_vd;
- SCR1_IPIC_ICSR : ipic_ipr_clr_req[ipic_idxr_ff] = csr2ipic_wdata_i[SCR1_IPIC_ICSR_IP];
- default : begin end
- endcase
- end
-end
-
-assign ipic_ipr_clr_cond = ~irq_lvl | ipic_imr_next;
-assign ipic_ipr_clr = ipic_ipr_clr_req & ipic_ipr_clr_cond;
-integer i;
-always_comb begin
- ipic_ipr_next = '0;
- for (i=0; i<SCR1_IRQ_VECT_NUM; i=i+1) begin
- ipic_ipr_next[i] = ipic_ipr_clr[i] ? 1'b0
- : ~ipic_imr_ff[i] ? irq_lvl[i]
- : ipic_ipr_ff[i] | irq_edge_detected[i];
- end
-end
-
-// ISVR
-//------------------------------------------------------------------------------
-// For every IRQ line shows whether the interrupt is in service or not
-
-assign ipic_isvr_upd = irq_start_vd | ipic_eoi_req;
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- ipic_isvr_ff <= '0;
- end else if (ipic_isvr_upd) begin
- ipic_isvr_ff <= ipic_isvr_next;
- end
-end
-
-always_comb begin
- ipic_isvr_eoi = ipic_isvr_ff;
- if (irq_serv_vd) begin
- ipic_isvr_eoi[irq_serv_idx] = 1'b0;
- end
-end
-
-always_comb begin
- ipic_isvr_next = ipic_isvr_ff;
- if (irq_start_vd) begin
- ipic_isvr_next[irq_req_idx] = 1'b1;
- end else if (ipic_eoi_req) begin
- ipic_isvr_next = ipic_isvr_eoi;
- end
-end
-
-// IER
-//------------------------------------------------------------------------------
-// Enables/disables interrupt for every IRQ line
-
-assign ipic_ier_upd = cicsr_wr_req | icsr_wr_req;
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- ipic_ier_ff <= '0;
- end else if (ipic_ier_upd) begin
- ipic_ier_ff <= ipic_ier_next;
- end
-end
-
-always_comb begin
- ipic_ier_next = ipic_ier_ff;
- if (cicsr_wr_req) begin
- ipic_ier_next[irq_serv_idx] = irq_serv_vd
- ? csr2ipic_wdata_i[SCR1_IPIC_ICSR_IE]
- : ipic_ier_ff[irq_serv_idx];
- end else if (icsr_wr_req) begin
- ipic_ier_next[ipic_idxr_ff] = csr2ipic_wdata_i[SCR1_IPIC_ICSR_IE];
- end
-end
-
-// IMR
-//------------------------------------------------------------------------------
-// For every IRQ line sets either Level (0) or Edge (1) detection
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- ipic_imr_ff <= '0;
- end else if (icsr_wr_req) begin
- ipic_imr_ff <= ipic_imr_next;
- end
-end
-
-always_comb begin
- ipic_imr_next = ipic_imr_ff;
- if (icsr_wr_req) begin
- ipic_imr_next[ipic_idxr_ff] = csr2ipic_wdata_i[SCR1_IPIC_ICSR_IM];
- end
-end
-
-// IINVR
-//------------------------------------------------------------------------------
-// For every IRQ line defines whether it should be inverted or not
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- ipic_iinvr_ff <= '0;
- end else if (icsr_wr_req) begin
- ipic_iinvr_ff <= ipic_iinvr_next;
- end
-end
-
-always_comb begin
- ipic_iinvr_next = ipic_iinvr_ff;
- if (icsr_wr_req) begin
- ipic_iinvr_next[ipic_idxr_ff] = csr2ipic_wdata_i[SCR1_IPIC_ICSR_INV];
- end
-end
-
-// ICSR
-//------------------------------------------------------------------------------
-// Holds control and status information about the interrupt defined by Index Register
-
-assign ipic_icsr.ip = ipic_ipr_ff [ipic_idxr_ff];
-assign ipic_icsr.ie = ipic_ier_ff [ipic_idxr_ff];
-assign ipic_icsr.im = ipic_imr_ff [ipic_idxr_ff];
-assign ipic_icsr.inv = ipic_iinvr_ff[ipic_idxr_ff];
-assign ipic_icsr.is = ipic_isvr_ff [ipic_idxr_ff];
-assign ipic_icsr.line = SCR1_IRQ_LINES_WIDTH'(ipic_idxr_ff);
-
-//------------------------------------------------------------------------------
-// Priority IRQ generation logic
-//------------------------------------------------------------------------------
-
-assign irq_req_v = ipic_ipr_ff & ipic_ier_ff;
-
-/*** Modified for Yosys handing typedef in function - dinesha
-assign irr_priority = scr1_search_one_16(irq_req_v);
-assign irq_req_vd = irr_priority.vd;
-assign irq_req_idx = irr_priority.idx;
-****/
-
-always_comb
-begin
- casex(irq_req_v)
- 16'bxxxx_xxxx_xxxx_xxx1 : irq_req_idx = 0;
- 16'bxxxx_xxxx_xxxx_xx10 : irq_req_idx = 1;
- 16'bxxxx_xxxx_xxxx_x100 : irq_req_idx = 2;
- 16'bxxxx_xxxx_xxxx_1000 : irq_req_idx = 3;
- 16'bxxxx_xxxx_xxx1_0000 : irq_req_idx = 4;
- 16'bxxxx_xxxx_xx10_0000 : irq_req_idx = 5;
- 16'bxxxx_xxxx_x100_0000 : irq_req_idx = 6;
- 16'bxxxx_xxxx_1000_0000 : irq_req_idx = 7;
- 16'bxxxx_xxx1_0000_0000 : irq_req_idx = 8;
- 16'bxxxx_xx10_0000_0000 : irq_req_idx = 9;
- 16'bxxxx_x100_0000_0000 : irq_req_idx = 10;
- 16'bxxxx_1000_0000_0000 : irq_req_idx = 11;
- 16'bxxx1_0000_0000_0000 : irq_req_idx = 12;
- 16'bxx10_0000_0000_0000 : irq_req_idx = 13;
- 16'bx100_0000_0000_0000 : irq_req_idx = 14;
- 16'b1000_0000_0000_0000 : irq_req_idx = 15;
- 16'b0000_0000_0000_0000 : irq_req_idx = 16;
- default : irq_req_idx = 16;
- endcase
- irq_req_vd = |irq_req_v;
-end
-
-/*** Modified for Yosys handing typedef in function - dinesha
-assign isvr_priority_eoi = scr1_search_one_16(ipic_isvr_eoi);
-assign irq_eoi_req_vd = isvr_priority_eoi.vd;
-assign irq_eoi_req_idx = isvr_priority_eoi.idx;
-*************************************************/
-
-always_comb
-begin
- casex(ipic_isvr_eoi)
- 16'bxxxx_xxxx_xxxx_xxx1 : irq_eoi_req_idx = 0;
- 16'bxxxx_xxxx_xxxx_xx10 : irq_eoi_req_idx = 1;
- 16'bxxxx_xxxx_xxxx_x100 : irq_eoi_req_idx = 2;
- 16'bxxxx_xxxx_xxxx_1000 : irq_eoi_req_idx = 3;
- 16'bxxxx_xxxx_xxx1_0000 : irq_eoi_req_idx = 4;
- 16'bxxxx_xxxx_xx10_0000 : irq_eoi_req_idx = 5;
- 16'bxxxx_xxxx_x100_0000 : irq_eoi_req_idx = 6;
- 16'bxxxx_xxxx_1000_0000 : irq_eoi_req_idx = 7;
- 16'bxxxx_xxx1_0000_0000 : irq_eoi_req_idx = 8;
- 16'bxxxx_xx10_0000_0000 : irq_eoi_req_idx = 9;
- 16'bxxxx_x100_0000_0000 : irq_eoi_req_idx = 10;
- 16'bxxxx_1000_0000_0000 : irq_eoi_req_idx = 11;
- 16'bxxx1_0000_0000_0000 : irq_eoi_req_idx = 12;
- 16'bxx10_0000_0000_0000 : irq_eoi_req_idx = 13;
- 16'bx100_0000_0000_0000 : irq_eoi_req_idx = 14;
- 16'b1000_0000_0000_0000 : irq_eoi_req_idx = 15;
- 16'b0000_0000_0000_0000 : irq_eoi_req_idx = 16;
- default : irq_eoi_req_idx = 16;
- endcase
- irq_eoi_req_vd = |ipic_isvr_eoi;
-end
-
-assign irq_hi_prior_pnd = irq_req_idx < irq_serv_idx;
-
-assign ipic2csr_irq_m_req_o = irq_req_vd & (~irq_serv_vd | irq_hi_prior_pnd);
-
-assign irq_start_vd = ipic2csr_irq_m_req_o & ipic_soi_req;
-
-endmodule : scr1_ipic
-
-`endif // SCR1_IPIC_EN
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv
deleted file mode 100644
index 05b820c..0000000
--- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv
+++ /dev/null
@@ -1,1186 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_pipe_csr.sv>
-/// @brief Control Status Registers (CSR)
-///
-
-//------------------------------------------------------------------------------
- //
- // Functionality:
- // - Provides access to RISC-V CSR Machine registers
- // - Handles events (EXC, IRQ and MRET):
- // - Setups handling configuration
- // - Displays events statuses and information
- // - Generates new PC
- // - Provides information about the number of executed instructions and elapsed
- // cycles
- // - Provides interfaces for IPIC, HDU and TDU registers access
- //
- // Structure:
- // - Events (EXC, IRQ, MRET) logic
- // - CSR read/write interface
- // - CSR registers:
- // - Machine Trap Setup registers
- // - Machine Trap Handling registers
- // - Machine Counters/Timers registers
- // - Non-standard CSRs (MCOUNTEN)
- // - CSR <-> EXU i/f
- // - CSR <-> IPIC i/f
- // - CSR <-> HDU i/f
- // - CSR <-> TDU i/f
- //
-//------------------------------------------------------------------------------
-
-`include "scr1_arch_description.svh"
-`include "scr1_csr.svh"
-`include "scr1_arch_types.svh"
-`include "scr1_riscv_isa_decoding.svh"
-`ifdef SCR1_IPIC_EN
-`include "scr1_ipic.svh"
-`endif // SCR1_IPIC_EN
-`ifdef SCR1_DBG_EN
-`include "scr1_hdu.svh"
-`endif // SCR1_DBG_EN
-`ifdef SCR1_TDU_EN
-`include "scr1_tdu.svh"
-`endif // SCR1_TDU_EN
-
-module scr1_pipe_csr (
- // Common
- input logic rst_n, // CSR reset
- input logic clk, // Gated CSR clock
-`ifdef SCR1_CLKCTRL_EN
- input logic clk_alw_on, // Not-gated CSR clock
-`endif // SCR1_CLKCTRL_EN
-
- // SOC signals
- // IRQ
- input logic soc2csr_irq_ext_i, // External interrupt request
- input logic soc2csr_irq_soft_i, // Software interrupt request
- input logic soc2csr_irq_mtimer_i, // External timer interrupt request
-
- // Memory-mapped external timer
- input logic [63:0] soc2csr_mtimer_val_i, // External timer value
-
- // MHARTID fuse
- input logic [`SCR1_XLEN-1:0] soc2csr_fuse_mhartid_i, // MHARTID fuse
-
- // CSR <-> EXU read/write interface
- input logic exu2csr_r_req_i, // CSR read/write address
- input logic [SCR1_CSR_ADDR_WIDTH-1:0] exu2csr_rw_addr_i, // CSR read request
- output logic [`SCR1_XLEN-1:0] csr2exu_r_data_o, // CSR read data
- input logic exu2csr_w_req_i, // CSR write request
- input type_scr1_csr_cmd_sel_e exu2csr_w_cmd_i, // CSR write command
- input logic [`SCR1_XLEN-1:0] exu2csr_w_data_i, // CSR write data
- output logic csr2exu_rw_exc_o, // CSR read/write access exception
-
- // CSR <-> EXU event interface
- input logic exu2csr_take_irq_i, // Take IRQ trap
- input logic exu2csr_take_exc_i, // Take exception trap
- input logic exu2csr_mret_update_i, // MRET update CSR
- input logic exu2csr_mret_instr_i, // MRET instruction
- input logic [SCR1_EXC_CODE_WIDTH_E-1:0] exu2csr_exc_code_i, // Exception code (see scr1_arch_types.svh) - cp.7
- input logic [`SCR1_XLEN-1:0] exu2csr_trap_val_i, // Trap value
- output logic csr2exu_irq_o, // IRQ request
- output logic csr2exu_ip_ie_o, // Some IRQ pending and locally enabled
- output logic csr2exu_mstatus_mie_up_o, // MSTATUS or MIE update in the current cycle
-
-`ifdef SCR1_IPIC_EN
- // CSR <-> IPIC interface
- output logic csr2ipic_r_req_o, // IPIC read request
- output logic csr2ipic_w_req_o, // IPIC write request
- output logic [2:0] csr2ipic_addr_o, // IPIC address
- output logic [`SCR1_XLEN-1:0] csr2ipic_wdata_o, // IPIC write data
- input logic [`SCR1_XLEN-1:0] ipic2csr_rdata_i, // IPIC read data
-`endif // SCR1_IPIC_EN
-
-`ifdef SCR1_DBG_EN
- // CSR <-> HDU interface
- output logic csr2hdu_req_o, // Request to HDU
- output type_scr1_csr_cmd_sel_e csr2hdu_cmd_o, // HDU command
- output logic [SCR1_HDU_DEBUGCSR_ADDR_WIDTH-1:0] csr2hdu_addr_o, // HDU address
- output logic [`SCR1_XLEN-1:0] csr2hdu_wdata_o, // HDU write data
- input logic [`SCR1_XLEN-1:0] hdu2csr_rdata_i, // HDU read data
- input type_scr1_csr_resp_e hdu2csr_resp_i, // HDU response
- input logic hdu2csr_no_commit_i, // Forbid instruction commitment
-`endif // SCR1_DBG_EN
-
-`ifdef SCR1_TDU_EN
- // CSR <-> TDU interface
- output logic csr2tdu_req_o, // Request to TDU
- output type_scr1_csr_cmd_sel_e csr2tdu_cmd_o, // TDU command
- output logic [SCR1_CSR_ADDR_TDU_OFFS_W-1:0] csr2tdu_addr_o, // TDU address
- output logic [`SCR1_XLEN-1:0] csr2tdu_wdata_o, // TDU write data
- input logic [`SCR1_XLEN-1:0] tdu2csr_rdata_i, // TDU read data
- input type_scr1_csr_resp_e tdu2csr_resp_i, // TDU response
-`endif // SCR1_TDU_EN
-
- // CSR <-> EXU PC interface
-`ifndef SCR1_CSR_REDUCED_CNT
- input logic exu2csr_instret_no_exc_i, // Instruction retired (without exception)
-`endif // SCR1_CSR_REDUCED_CNT
- input logic [`SCR1_XLEN-1:0] exu2csr_pc_curr_i, // Current PC
- input logic [`SCR1_XLEN-1:0] exu2csr_pc_next_i, // Next PC
- output logic [`SCR1_XLEN-1:0] csr2exu_new_pc_o // Exception/IRQ/MRET new PC
-);
-
-//------------------------------------------------------------------------------
-// Local parameters
-//------------------------------------------------------------------------------
-
-`ifdef SCR1_RVC_EXT
- localparam PC_LSB = 1;
-`else
- localparam PC_LSB = 2;
-`endif
-
-//------------------------------------------------------------------------------
-// Local signals declaration
-//------------------------------------------------------------------------------
-
-// Machine Trap Setup registers
-//------------------------------------------------------------------------------
-
-// MSTATUS register
-logic csr_mstatus_upd; // MSTATUS update enable
-logic [`SCR1_XLEN-1:0] csr_mstatus; // Aggregated MSTATUS
-logic csr_mstatus_mie_ff; // MSTATUS: Global interrupt enable
-logic csr_mstatus_mie_next; // MSTATUS: Global interrupt enable next value
-logic csr_mstatus_mpie_ff; // MSTATUS: Global interrupt enable prior to the trap
-logic csr_mstatus_mpie_next; // MSTATUS: Global interrupt enable prior to the trap next value
-
-// MIE register
-logic csr_mie_upd; // MIE update enable
-logic [`SCR1_XLEN-1:0] csr_mie; // Aggregated MIE
-logic csr_mie_mtie_ff; // MIE: Machine timer interrupt enable
-logic csr_mie_meie_ff; // MIE: Machine external interrupt enable
-logic csr_mie_msie_ff; // MIE: Machine software interrupt enable
-
-// MTVEC register
-logic csr_mtvec_upd; // MTVEC update enable
-logic [`SCR1_XLEN-1:SCR1_CSR_MTVEC_BASE_ZERO_BITS] csr_mtvec_base; // MTVEC: Base (upper 26 bits)
-logic csr_mtvec_mode; // MTVEC: Mode (0-direct, 1-vectored) (wired)
-`ifdef SCR1_MTVEC_MODE_EN
-logic csr_mtvec_mode_ff; // MTVEC: Mode (0-direct, 1-vectored) (registered)
-logic csr_mtvec_mode_vect;
-`endif
-
-// Machine Trap Handling registers
-//------------------------------------------------------------------------------
-
-// MSCRATCH register
-logic csr_mscratch_upd; // MSCRATCH update enable
-logic [`SCR1_XLEN-1:0] csr_mscratch_ff; // MSCRATCH
-
-// MEPC register
-logic csr_mepc_upd; // MEPC update enable
-logic [`SCR1_XLEN-1:PC_LSB] csr_mepc_ff; // MEPC registered value
-logic [`SCR1_XLEN-1:PC_LSB] csr_mepc_next; // MEPC next value
-logic [`SCR1_XLEN-1:0] csr_mepc; // MEPC registered value extended to XLEN
-
-// MCAUSE register
-logic csr_mcause_upd; // MCAUSE update enable
-logic csr_mcause_i_ff; // MCAUSE: Interrupt
-logic csr_mcause_i_next; // MCAUSE: Interrupt next value
-logic [SCR1_EXC_CODE_WIDTH_E-1:0] csr_mcause_ec_ff; // MCAUSE: Exception code - cp.7
-logic [SCR1_EXC_CODE_WIDTH_E-1:0] csr_mcause_ec_next; // MCAUSE: Exception code next value - cp.7
-logic [SCR1_EXC_CODE_WIDTH_E-1:0] csr_mcause_ec_new; // MCAUSE: Exception code new value (IRQs) - cp.7
-
-// MTVAL register
-logic csr_mtval_upd; // MTVAL update enable
-logic [`SCR1_XLEN-1:0] csr_mtval_ff; // MTVAL registered value
-logic [`SCR1_XLEN-1:0] csr_mtval_next; // MTVAL next value
-
-// MIP register
-logic [`SCR1_XLEN-1:0] csr_mip; // Aggregated MIP
-logic csr_mip_mtip; // MIP: Machine timer interrupt pending
-logic csr_mip_meip; // MIP: Machine external interrupt pending
-logic csr_mip_msip; // MIP: Machine software interrupt pending
-
-// Machine Counters/Timers registers
-//------------------------------------------------------------------------------
-
-`ifndef SCR1_CSR_REDUCED_CNT
-// MINSTRET register
-logic [1:0] csr_minstret_upd;
-logic [SCR1_CSR_COUNTERS_WIDTH-1:0] csr_minstret;
-logic csr_minstret_lo_inc;
-logic csr_minstret_lo_upd;
-logic [7:0] csr_minstret_lo_ff;
-logic [7:0] csr_minstret_lo_next;
-logic csr_minstret_hi_inc;
-logic csr_minstret_hi_upd;
-logic [SCR1_CSR_COUNTERS_WIDTH-1:8] csr_minstret_hi_ff;
-logic [SCR1_CSR_COUNTERS_WIDTH-1:8] csr_minstret_hi_next;
-logic [SCR1_CSR_COUNTERS_WIDTH-1:8] csr_minstret_hi_new;
-
-// MCYCLE register
-logic [1:0] csr_mcycle_upd;
-logic [SCR1_CSR_COUNTERS_WIDTH-1:0] csr_mcycle;
-logic csr_mcycle_lo_inc;
-logic csr_mcycle_lo_upd;
-logic [7:0] csr_mcycle_lo_ff;
-logic [7:0] csr_mcycle_lo_next;
-logic csr_mcycle_hi_inc;
-logic csr_mcycle_hi_upd;
-logic [SCR1_CSR_COUNTERS_WIDTH-1:8] csr_mcycle_hi_ff;
-logic [SCR1_CSR_COUNTERS_WIDTH-1:8] csr_mcycle_hi_next;
-logic [SCR1_CSR_COUNTERS_WIDTH-1:8] csr_mcycle_hi_new;
-`endif // ~SCR1_CSR_REDUCED_CNT
-
-// Non-standard CSRs
-//------------------------------------------------------------------------------
-
-// MCOUNTEN register
-`ifdef SCR1_MCOUNTEN_EN
-logic csr_mcounten_upd; // MCOUNTEN update enable
-logic [`SCR1_XLEN-1:0] csr_mcounten; // Aggregated MCOUNTEN
-logic csr_mcounten_cy_ff; // Cycle count enable
-logic csr_mcounten_ir_ff; // Instret count enable
-`endif // SCR1_MCOUNTEN_EN
-
-// CSR read/write i/f
-//------------------------------------------------------------------------------
-
-logic [`SCR1_XLEN-1:0] csr_r_data;
-logic [`SCR1_XLEN-1:0] csr_w_data;
-
-// Events (exceptions, interrupts, mret) signals
-//------------------------------------------------------------------------------
-
-// Event flags
-logic e_exc; // Successful exception trap
-logic e_irq; // Successful IRQ trap
-logic e_mret; // MRET instruction
-logic e_irq_nmret; // IRQ trap without MRET instruction
-
-// Interrupt pending & enable signals
-logic csr_eirq_pnd_en; // External IRQ pending and locally enabled
-logic csr_sirq_pnd_en; // Software IRQ pending and locally enabled
-logic csr_tirq_pnd_en; // Timer IRQ pending and locally enabled
-
-// Exception flags
-logic csr_w_exc;
-logic csr_r_exc;
-logic exu_req_no_exc;
-
-// Requests to other modules
-logic csr_ipic_req;
-`ifdef SCR1_DBG_EN
-logic csr_hdu_req;
-`endif // SCR1_DBG_EN
-`ifdef SCR1_TDU_EN
-logic csr_brkm_req;
-`endif // SCR1_TDU_EN
-
-//------------------------------------------------------------------------------
-// Events (IRQ, EXC, MRET)
-//------------------------------------------------------------------------------
-
-// Events priority
-assign e_exc = exu2csr_take_exc_i
-`ifdef SCR1_DBG_EN
- & ~hdu2csr_no_commit_i
-`endif // SCR1_DBG_EN
- ;
-assign e_irq = exu2csr_take_irq_i & ~exu2csr_take_exc_i
-`ifdef SCR1_DBG_EN
- & ~hdu2csr_no_commit_i
-`endif // SCR1_DBG_EN
- ;
-assign e_mret = exu2csr_mret_update_i
-`ifdef SCR1_DBG_EN
- & ~hdu2csr_no_commit_i
-`endif // SCR1_DBG_EN
- ;
-assign e_irq_nmret = e_irq & ~exu2csr_mret_instr_i;
-
-// IRQ pending & enable signals
-assign csr_eirq_pnd_en = csr_mip_meip & csr_mie_meie_ff;
-assign csr_sirq_pnd_en = csr_mip_msip & csr_mie_msie_ff;
-assign csr_tirq_pnd_en = csr_mip_mtip & csr_mie_mtie_ff;
-
-// IRQ exception codes priority
-always_comb begin
- case (1'b1)
- csr_eirq_pnd_en: csr_mcause_ec_new = SCR1_EXC_CODE_IRQ_M_EXTERNAL; // cp.7
- csr_sirq_pnd_en: csr_mcause_ec_new = SCR1_EXC_CODE_IRQ_M_SOFTWARE; // cp.7
- csr_tirq_pnd_en: csr_mcause_ec_new = SCR1_EXC_CODE_IRQ_M_TIMER; // cp.7
- default : csr_mcause_ec_new = SCR1_EXC_CODE_IRQ_M_EXTERNAL; // cp.7
- endcase
-end
-
-assign exu_req_no_exc = ((exu2csr_r_req_i & ~csr_r_exc)
- | (exu2csr_w_req_i & ~csr_w_exc));
-
-//------------------------------------------------------------------------------
-// CSR read/write interface
-//------------------------------------------------------------------------------
-
-// CSR read logic
-//------------------------------------------------------------------------------
-
-always_comb begin
- csr_r_data = '0;
- csr_r_exc = 1'b0;
-`ifdef SCR1_DBG_EN
- csr_hdu_req = 1'b0;
-`endif // SCR1_DBG_EN
-`ifdef SCR1_TDU_EN
- csr_brkm_req = 1'b0;
-`endif // SCR1_TDU_EN
-`ifdef SCR1_IPIC_EN
- csr2ipic_r_req_o = 1'b0;
-`endif // SCR1_IPIC_EN
-
- casez (exu2csr_rw_addr_i)
- // Machine Information Registers (read-only)
- SCR1_CSR_ADDR_MVENDORID : csr_r_data = SCR1_CSR_MVENDORID;
- SCR1_CSR_ADDR_MARCHID : csr_r_data = SCR1_CSR_MARCHID;
- SCR1_CSR_ADDR_MIMPID : csr_r_data = SCR1_CSR_MIMPID;
- SCR1_CSR_ADDR_MHARTID : csr_r_data = soc2csr_fuse_mhartid_i;
-
- // Machine Trap Setup (read-write)
- SCR1_CSR_ADDR_MSTATUS : csr_r_data = csr_mstatus;
- SCR1_CSR_ADDR_MISA : csr_r_data = SCR1_CSR_MISA;
- SCR1_CSR_ADDR_MIE : csr_r_data = csr_mie;
- SCR1_CSR_ADDR_MTVEC : csr_r_data = {csr_mtvec_base, 4'd0, 2'(csr_mtvec_mode)};
-
- // Machine Trap Handling (read-write)
- SCR1_CSR_ADDR_MSCRATCH : csr_r_data = csr_mscratch_ff;
- SCR1_CSR_ADDR_MEPC : csr_r_data = csr_mepc;
- SCR1_CSR_ADDR_MCAUSE : csr_r_data = {csr_mcause_i_ff, (`SCR1_XLEN-1)'(csr_mcause_ec_ff)};
- SCR1_CSR_ADDR_MTVAL : csr_r_data = csr_mtval_ff;
- SCR1_CSR_ADDR_MIP : csr_r_data = csr_mip;
-
- // User Counters/Timers (read-only)
- {SCR1_CSR_ADDR_HPMCOUNTER_MASK, 5'b?????} : begin
- case (exu2csr_rw_addr_i[4:0])
- 5'd1 : csr_r_data = soc2csr_mtimer_val_i[31:0];
-`ifndef SCR1_CSR_REDUCED_CNT
- 5'd0 : csr_r_data = csr_mcycle[31:0];
- 5'd2 : csr_r_data = csr_minstret[31:0];
-`endif // SCR1_CSR_REDUCED_CNT
- default : begin
- // return 0
- end
- endcase
- end
-
- {SCR1_CSR_ADDR_HPMCOUNTERH_MASK, 5'b?????} : begin
- case (exu2csr_rw_addr_i[4:0])
- 5'd1 : csr_r_data = soc2csr_mtimer_val_i[63:32];
-`ifndef SCR1_CSR_REDUCED_CNT
- 5'd0 : csr_r_data = csr_mcycle[63:32];
- 5'd2 : csr_r_data = csr_minstret[63:32];
-`endif // SCR1_CSR_REDUCED_CNT
- default : begin
- // return 0
- end
- endcase
- end
-
- // Machine Counters/Timers (read-write)
- {SCR1_CSR_ADDR_MHPMCOUNTER_MASK, 5'b?????} : begin
- case (exu2csr_rw_addr_i[4:0])
- 5'd1 : csr_r_exc = exu2csr_r_req_i;
-`ifndef SCR1_CSR_REDUCED_CNT
- 5'd0 : csr_r_data = csr_mcycle[31:0];
- 5'd2 : csr_r_data = csr_minstret[31:0];
-`endif // SCR1_CSR_REDUCED_CNT
- default : begin
- // return 0
- end
- endcase
- end
-
- {SCR1_CSR_ADDR_MHPMCOUNTERH_MASK, 5'b?????} : begin
- case (exu2csr_rw_addr_i[4:0])
- 5'd1 : csr_r_exc = exu2csr_r_req_i;
-`ifndef SCR1_CSR_REDUCED_CNT
- 5'd0 : csr_r_data = csr_mcycle[63:32];
- 5'd2 : csr_r_data = csr_minstret[63:32];
-`endif // SCR1_CSR_REDUCED_CNT
- default : begin
- // return 0
- end
- endcase
- end
-
- {SCR1_CSR_ADDR_MHPMEVENT_MASK, 5'b?????} : begin
- case (exu2csr_rw_addr_i[4:0])
- 5'd0,
- 5'd1,
- 5'd2 : csr_r_exc = exu2csr_r_req_i;
- default : begin
- // return 0
- end
- endcase
- end
-
-`ifdef SCR1_MCOUNTEN_EN
- SCR1_CSR_ADDR_MCOUNTEN : csr_r_data = csr_mcounten;
-`endif // SCR1_MCOUNTEN_EN
-
-`ifdef SCR1_IPIC_EN
- // IPIC registers
- SCR1_CSR_ADDR_IPIC_CISV,
- SCR1_CSR_ADDR_IPIC_CICSR,
- SCR1_CSR_ADDR_IPIC_IPR,
- SCR1_CSR_ADDR_IPIC_ISVR,
- SCR1_CSR_ADDR_IPIC_EOI,
- SCR1_CSR_ADDR_IPIC_SOI,
- SCR1_CSR_ADDR_IPIC_IDX,
- SCR1_CSR_ADDR_IPIC_ICSR : begin
- csr_r_data = ipic2csr_rdata_i;
- csr2ipic_r_req_o = exu2csr_r_req_i;
- end
-`endif // SCR1_IPIC_EN
-
-`ifdef SCR1_DBG_EN
- // HDU registers
- SCR1_HDU_DBGCSR_ADDR_DCSR,
- SCR1_HDU_DBGCSR_ADDR_DPC,
- SCR1_HDU_DBGCSR_ADDR_DSCRATCH0,
- SCR1_HDU_DBGCSR_ADDR_DSCRATCH1 : begin
- csr_hdu_req = 1'b1;
- csr_r_data = hdu2csr_rdata_i;
- end
-`endif // SCR1_DBG_EN
-
-`ifdef SCR1_TDU_EN
- // TDU registers
- SCR1_CSR_ADDR_TDU_TSELECT,
- SCR1_CSR_ADDR_TDU_TDATA1,
- SCR1_CSR_ADDR_TDU_TDATA2,
- SCR1_CSR_ADDR_TDU_TINFO: begin
- csr_brkm_req = 1'b1;
- csr_r_data = tdu2csr_rdata_i;
- end
-`endif // SCR1_TDU_EN
-
- default : begin
- csr_r_exc = exu2csr_r_req_i;
- end
- endcase // exu2csr_rw_addr_i
-end
-
-assign csr2exu_r_data_o = csr_r_data;
-
-// CSR write logic
-//------------------------------------------------------------------------------
-
-always_comb begin
- case (exu2csr_w_cmd_i)
- SCR1_CSR_CMD_WRITE : csr_w_data = exu2csr_w_data_i;
- SCR1_CSR_CMD_SET : csr_w_data = exu2csr_w_data_i | csr_r_data;
- SCR1_CSR_CMD_CLEAR : csr_w_data = ~exu2csr_w_data_i & csr_r_data;
- default : csr_w_data = '0;
- endcase
-end
-
-always_comb begin
- csr_mstatus_upd = 1'b0;
- csr_mie_upd = 1'b0;
- csr_mscratch_upd = 1'b0;
- csr_mepc_upd = 1'b0;
- csr_mcause_upd = 1'b0;
- csr_mtval_upd = 1'b0;
- csr_mtvec_upd = 1'b0;
-
-`ifndef SCR1_CSR_REDUCED_CNT
- csr_mcycle_upd = 2'b00;
- csr_minstret_upd = 2'b00;
-`endif // SCR1_CSR_REDUCED_CNT
-
-`ifdef SCR1_MCOUNTEN_EN
- csr_mcounten_upd = 1'b0;
-`endif // SCR1_MCOUNTEN_EN
- csr_w_exc = 1'b0;
-`ifdef SCR1_IPIC_EN
- csr2ipic_w_req_o = 1'b0;
-`endif // SCR1_IPIC_EN
-
- if (exu2csr_w_req_i) begin
- casez (exu2csr_rw_addr_i)
- // Machine Trap Setup (read-write)
- SCR1_CSR_ADDR_MSTATUS : csr_mstatus_upd = 1'b1;
- SCR1_CSR_ADDR_MISA : begin end
- SCR1_CSR_ADDR_MIE : csr_mie_upd = 1'b1;
- SCR1_CSR_ADDR_MTVEC : csr_mtvec_upd = 1'b1;
-
- // Machine Trap Handling (read-write)
- SCR1_CSR_ADDR_MSCRATCH : csr_mscratch_upd = 1'b1;
- SCR1_CSR_ADDR_MEPC : csr_mepc_upd = 1'b1;
- SCR1_CSR_ADDR_MCAUSE : csr_mcause_upd = 1'b1;
- SCR1_CSR_ADDR_MTVAL : csr_mtval_upd = 1'b1;
- SCR1_CSR_ADDR_MIP : begin end
-
- // Machine Counters/Timers (read-write)
- {SCR1_CSR_ADDR_MHPMCOUNTER_MASK, 5'b?????} : begin
- case (exu2csr_rw_addr_i[4:0])
- 5'd1 : csr_w_exc = 1'b1;
-`ifndef SCR1_CSR_REDUCED_CNT
- 5'd0 : csr_mcycle_upd[0] = 1'b1;
- 5'd2 : csr_minstret_upd[0] = 1'b1;
-`endif // SCR1_CSR_REDUCED_CNT
- default : begin
- // no exception
- end
- endcase
- end
-
- {SCR1_CSR_ADDR_MHPMCOUNTERH_MASK, 5'b?????} : begin
- case (exu2csr_rw_addr_i[4:0])
- 5'd1 : csr_w_exc = 1'b1;
-`ifndef SCR1_CSR_REDUCED_CNT
- 5'd0 : csr_mcycle_upd[1] = 1'b1;
- 5'd2 : csr_minstret_upd[1] = 1'b1;
-`endif // SCR1_CSR_REDUCED_CNT
- default : begin
- // no exception
- end
- endcase
- end
-
- {SCR1_CSR_ADDR_MHPMEVENT_MASK, 5'b?????} : begin
- case (exu2csr_rw_addr_i[4:0])
- 5'd0,
- 5'd1,
- 5'd2 : csr_w_exc = 1'b1;
- default : begin
- // no exception
- end
- endcase
- end
-
-`ifdef SCR1_MCOUNTEN_EN
- SCR1_CSR_ADDR_MCOUNTEN : csr_mcounten_upd = 1'b1;
-`endif // SCR1_MCOUNTEN_EN
-
-`ifdef SCR1_IPIC_EN
- // IPIC registers
- SCR1_CSR_ADDR_IPIC_CICSR,
- SCR1_CSR_ADDR_IPIC_IPR,
- SCR1_CSR_ADDR_IPIC_EOI,
- SCR1_CSR_ADDR_IPIC_SOI,
- SCR1_CSR_ADDR_IPIC_IDX,
- SCR1_CSR_ADDR_IPIC_ICSR : begin
- csr2ipic_w_req_o = 1'b1;
- end
- SCR1_CSR_ADDR_IPIC_CISV,
- SCR1_CSR_ADDR_IPIC_ISVR : begin
- // no exception on write
- end
-`endif // SCR1_IPIC_EN
-
-`ifdef SCR1_DBG_EN
- SCR1_HDU_DBGCSR_ADDR_DCSR,
- SCR1_HDU_DBGCSR_ADDR_DPC,
- SCR1_HDU_DBGCSR_ADDR_DSCRATCH0,
- SCR1_HDU_DBGCSR_ADDR_DSCRATCH1 : begin
- end
-`endif // SCR1_DBG_EN
-
-`ifdef SCR1_TDU_EN
- // TDU registers
- SCR1_CSR_ADDR_TDU_TSELECT,
- SCR1_CSR_ADDR_TDU_TDATA1,
- SCR1_CSR_ADDR_TDU_TDATA2,
- SCR1_CSR_ADDR_TDU_TINFO: begin
- end
-`endif // SCR1_TDU_EN
-
- default : begin
- csr_w_exc = 1'b1;
- end
- endcase
- end
-end
-
-//------------------------------------------------------------------------------
-// Machine Trap Setup registers
-//------------------------------------------------------------------------------
-//
- // Registers:
- // - MSTATUS
- // - MIE
- // - MTVEC
-//
-
-// MSTATUS register
-//------------------------------------------------------------------------------
-// Consists of 2 bits - current and previous (before trap) global interrupt
-// enable bits (MIE & MPIE)
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- csr_mstatus_mie_ff <= SCR1_CSR_MSTATUS_MIE_RST_VAL;
- csr_mstatus_mpie_ff <= SCR1_CSR_MSTATUS_MPIE_RST_VAL;
- end else begin
- csr_mstatus_mie_ff <= csr_mstatus_mie_next;
- csr_mstatus_mpie_ff <= csr_mstatus_mpie_next;
- end
-end
-
-always_comb begin
- case (1'b1)
- e_exc, e_irq : begin
- csr_mstatus_mie_next = 1'b0;
- csr_mstatus_mpie_next = csr_mstatus_mie_ff;
- end
- e_mret : begin
- csr_mstatus_mie_next = csr_mstatus_mpie_ff;
- csr_mstatus_mpie_next = 1'b1;
- end
- csr_mstatus_upd: begin
- csr_mstatus_mie_next = csr_w_data[SCR1_CSR_MSTATUS_MIE_OFFSET];
- csr_mstatus_mpie_next = csr_w_data[SCR1_CSR_MSTATUS_MPIE_OFFSET];
- end
- default : begin
- csr_mstatus_mie_next = csr_mstatus_mie_ff;
- csr_mstatus_mpie_next = csr_mstatus_mpie_ff;
- end
- endcase
-end
-
-always_comb begin
- csr_mstatus = '0;
- csr_mstatus[SCR1_CSR_MSTATUS_MIE_OFFSET] = csr_mstatus_mie_ff;
- csr_mstatus[SCR1_CSR_MSTATUS_MPIE_OFFSET] = csr_mstatus_mpie_ff;
- csr_mstatus[SCR1_CSR_MSTATUS_MPP_OFFSET+1:SCR1_CSR_MSTATUS_MPP_OFFSET] = SCR1_CSR_MSTATUS_MPP;
-end
-
-// MIE register
-//------------------------------------------------------------------------------
-// Contains interrupt enable bits (external, software, timer IRQs)
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- csr_mie_mtie_ff <= SCR1_CSR_MIE_MTIE_RST_VAL;
- csr_mie_meie_ff <= SCR1_CSR_MIE_MEIE_RST_VAL;
- csr_mie_msie_ff <= SCR1_CSR_MIE_MSIE_RST_VAL;
- end else if (csr_mie_upd) begin
- csr_mie_mtie_ff <= csr_w_data[SCR1_CSR_MIE_MTIE_OFFSET];
- csr_mie_meie_ff <= csr_w_data[SCR1_CSR_MIE_MEIE_OFFSET];
- csr_mie_msie_ff <= csr_w_data[SCR1_CSR_MIE_MSIE_OFFSET];
- end
-end
-
-always_comb begin
- csr_mie = '0;
- csr_mie[SCR1_CSR_MIE_MSIE_OFFSET] = csr_mie_msie_ff;
- csr_mie[SCR1_CSR_MIE_MTIE_OFFSET] = csr_mie_mtie_ff;
- csr_mie[SCR1_CSR_MIE_MEIE_OFFSET] = csr_mie_meie_ff;
-end
-
-// MTVEC register
-//------------------------------------------------------------------------------
-// Holds trap vector configuation. Consists of base and mode parts
-
-// MTVEC BASE part
-//------------------------------------------------------------------------------
-// Holds trap vector base address
-generate
- // All bits of MTVEC base are Read-Only and hardwired to 0's
- if (SCR1_MTVEC_BASE_WR_BITS == 0) begin : mtvec_base_ro
-
- assign csr_mtvec_base = SCR1_CSR_MTVEC_BASE_RST_VAL;
-
- // All bits of MTVEC base are RW
- end else if (SCR1_MTVEC_BASE_WR_BITS == SCR1_CSR_MTVEC_BASE_VAL_BITS) begin : mtvec_base_rw
-
- always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- csr_mtvec_base <= SCR1_CSR_MTVEC_BASE_RST_VAL;
- end else if (csr_mtvec_upd) begin
- csr_mtvec_base <= csr_w_data[`SCR1_XLEN-1:SCR1_CSR_MTVEC_BASE_ZERO_BITS];
- end
- end
-
- // Lower bits of MTVEC base are RO, higher - RW
- end else begin : mtvec_base_ro_rw
-
- logic [(`SCR1_XLEN-1):(`SCR1_XLEN-SCR1_MTVEC_BASE_WR_BITS)] csr_mtvec_base_reg;
-
- always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- csr_mtvec_base_reg <= SCR1_CSR_MTVEC_BASE_RST_VAL[(`SCR1_XLEN-1)-:SCR1_MTVEC_BASE_WR_BITS] ;
- end else if (csr_mtvec_upd) begin
- csr_mtvec_base_reg <= csr_w_data[(`SCR1_XLEN-1)-:SCR1_MTVEC_BASE_WR_BITS];
- end
- end
-
- assign csr_mtvec_base = {csr_mtvec_base_reg, SCR1_CSR_MTVEC_BASE_RST_VAL[SCR1_CSR_MTVEC_BASE_ZERO_BITS+:SCR1_CSR_MTVEC_BASE_RO_BITS]};
- end
-endgenerate
-
-// MTVEC MODE part
-//------------------------------------------------------------------------------
-// Chooses between direct (all exceptions set PC to BASE) or vectored
-// (asynchronous interrupts set PC to BASE+4xcause) interrupt modes
-
-`ifdef SCR1_MTVEC_MODE_EN
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- csr_mtvec_mode_ff <= SCR1_CSR_MTVEC_MODE_DIRECT;
- end else if (csr_mtvec_upd) begin
- csr_mtvec_mode_ff <= csr_w_data[0];
- end
-end
-
-assign csr_mtvec_mode = csr_mtvec_mode_ff;
-assign csr_mtvec_mode_vect = (csr_mtvec_mode_ff == SCR1_CSR_MTVEC_MODE_VECTORED);
-`else // SCR1_MTVEC_MODE_EN
-assign csr_mtvec_mode = SCR1_CSR_MTVEC_MODE_DIRECT;
-`endif // SCR1_MTVEC_MODE_EN
-
-//------------------------------------------------------------------------------
-// Machine Trap Handling registers
-//------------------------------------------------------------------------------
-//
- // Registers:
- // - MSCRATCH
- // - MEPC
- // - MCAUSE
- // - MTVAL
- // - MIP
-//
-
-// MSCRATCH register
-//------------------------------------------------------------------------------
-// Holds a pointer to a machine-mode hart-local context space
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- csr_mscratch_ff <= '0;
- end else if (csr_mscratch_upd) begin
- csr_mscratch_ff <= csr_w_data;
- end
-end
-
-// MEPC register
-//------------------------------------------------------------------------------
-// When a trap is taken into M-mode saves the virtual address of instruction that
-// was interrupted or that encountered the exception
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- csr_mepc_ff <= '0;
- end else begin
- csr_mepc_ff <= csr_mepc_next;
- end
-end
-
-always_comb begin
- case (1'b1)
- e_exc : csr_mepc_next = exu2csr_pc_curr_i[`SCR1_XLEN-1:PC_LSB];
- e_irq_nmret : csr_mepc_next = exu2csr_pc_next_i[`SCR1_XLEN-1:PC_LSB];
- csr_mepc_upd: csr_mepc_next = csr_w_data[`SCR1_XLEN-1:PC_LSB];
- default : csr_mepc_next = csr_mepc_ff;
- endcase
-end
-
-`ifdef SCR1_RVC_EXT
- assign csr_mepc = {csr_mepc_ff, 1'b0};
-`else
- assign csr_mepc = {csr_mepc_ff, 2'b00};
-`endif
-
-// MCAUSE register
-//------------------------------------------------------------------------------
-// When a trap is taken into M-mode saves a code indicating the event that caused
-// the trap
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- csr_mcause_i_ff <= 1'b0;
- csr_mcause_ec_ff <= SCR1_EXC_CODE_RESET; // cp.7
- end else begin
- csr_mcause_i_ff <= csr_mcause_i_next;
- csr_mcause_ec_ff <= csr_mcause_ec_next;
- end
-end
-
-always_comb begin
- case (1'b1)
- e_exc : begin
- csr_mcause_i_next = 1'b0;
- csr_mcause_ec_next = exu2csr_exc_code_i;
- end
- e_irq : begin
- csr_mcause_i_next = 1'b1;
- csr_mcause_ec_next = csr_mcause_ec_new;
- end
- csr_mcause_upd: begin
- csr_mcause_i_next = csr_w_data[`SCR1_XLEN-1];
- csr_mcause_ec_next = csr_w_data[SCR1_EXC_CODE_WIDTH_E-1:0]; // cp.7
- end
- default : begin
- csr_mcause_i_next = csr_mcause_i_ff;
- csr_mcause_ec_next = csr_mcause_ec_ff;
- end
- endcase
-end
-
-// MTVAL register
-//------------------------------------------------------------------------------
-// When a trap is taken into M-mode is either set to zero or written with exception-
-// specific information
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- csr_mtval_ff <= '0;
- end else begin
- csr_mtval_ff <= csr_mtval_next;
- end
-end
-
-always_comb begin
- case (1'b1)
- e_exc : csr_mtval_next = exu2csr_trap_val_i;
- e_irq : csr_mtval_next = '0;
- csr_mtval_upd: csr_mtval_next = csr_w_data;
- default : csr_mtval_next = csr_mtval_ff;
- endcase
-end
-
-// MIP register
-//------------------------------------------------------------------------------
-// Contains information on pending interrupts (external, software, timer IRQs)
-
-assign csr_mip_mtip = soc2csr_irq_mtimer_i;
-assign csr_mip_meip = soc2csr_irq_ext_i;
-assign csr_mip_msip = soc2csr_irq_soft_i;
-
-always_comb begin
- csr_mip = '0;
- csr_mip[SCR1_CSR_MIE_MSIE_OFFSET] = csr_mip_msip;
- csr_mip[SCR1_CSR_MIE_MTIE_OFFSET] = csr_mip_mtip;
- csr_mip[SCR1_CSR_MIE_MEIE_OFFSET] = csr_mip_meip;
-end
-
-//------------------------------------------------------------------------------
-// Machine Counters/Timers registers
-//------------------------------------------------------------------------------
-//
- // Registers:
- // - MCYCLE
- // - MINSTRET
-//
-
-`ifndef SCR1_CSR_REDUCED_CNT
-// MCYCLE register
-//------------------------------------------------------------------------------
-// Holds the number of clock cycles since some arbitrary point of time in the
-// past at which MCYCLE was zero
-
-assign csr_mcycle_lo_inc = 1'b1
- `ifdef SCR1_MCOUNTEN_EN
- & csr_mcounten_cy_ff
- `endif // SCR1_MCOUNTEN_EN
- ;
-assign csr_mcycle_hi_inc = csr_mcycle_lo_inc & (&csr_mcycle_lo_ff);
-
-assign csr_mcycle_lo_upd = csr_mcycle_lo_inc | csr_mcycle_upd[0];
-assign csr_mcycle_hi_upd = csr_mcycle_hi_inc | (|csr_mcycle_upd);
-
- `ifndef SCR1_CLKCTRL_EN
-always_ff @(negedge rst_n, posedge clk) begin
- `else // SCR1_CLKCTRL_EN
-always_ff @(negedge rst_n, posedge clk_alw_on) begin
- `endif // SCR1_CLKCTRL_EN
- if (~rst_n) begin
- csr_mcycle_lo_ff <= '0;
- csr_mcycle_hi_ff <= '0;
- end else begin
- if (csr_mcycle_lo_upd) csr_mcycle_lo_ff <= csr_mcycle_lo_next;
- if (csr_mcycle_hi_upd) csr_mcycle_hi_ff <= csr_mcycle_hi_next;
- end
-end
-
-assign csr_mcycle_hi_new = csr_mcycle_hi_ff + 1'b1;
-
-assign csr_mcycle_lo_next = csr_mcycle_upd[0] ? csr_w_data[7:0]
- : csr_mcycle_lo_inc ? csr_mcycle_lo_ff + 1'b1
- : csr_mcycle_lo_ff;
-assign csr_mcycle_hi_next = csr_mcycle_upd[0] ? {csr_mcycle_hi_new[63:32], csr_w_data[31:8]}
- : csr_mcycle_upd[1] ? {csr_w_data, csr_mcycle_hi_new[31:8]}
- : csr_mcycle_hi_inc ? csr_mcycle_hi_new
- : csr_mcycle_hi_ff;
-
-assign csr_mcycle = {csr_mcycle_hi_ff, csr_mcycle_lo_ff};
-
-// MINSTRET register
-//------------------------------------------------------------------------------
-// Holds the number of instructions executed by the core from some arbitrary time
-// in the past at which MINSTRET was equal to zero
-
-assign csr_minstret_lo_inc = exu2csr_instret_no_exc_i
- `ifdef SCR1_MCOUNTEN_EN
- & csr_mcounten_ir_ff
- `endif // SCR1_MCOUNTEN_EN
- ;
-assign csr_minstret_hi_inc = csr_minstret_lo_inc & (&csr_minstret_lo_ff);
-
-assign csr_minstret_lo_upd = csr_minstret_lo_inc | csr_minstret_upd[0];
-assign csr_minstret_hi_upd = csr_minstret_hi_inc | (|csr_minstret_upd);
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- csr_minstret_lo_ff <= '0;
- csr_minstret_hi_ff <= '0;
- end else begin
- if (csr_minstret_lo_upd) csr_minstret_lo_ff <= csr_minstret_lo_next;
- if (csr_minstret_hi_upd) csr_minstret_hi_ff <= csr_minstret_hi_next;
- end
-end
-
-assign csr_minstret_hi_new = csr_minstret_hi_ff + 1'b1;
-
-assign csr_minstret_lo_next = csr_minstret_upd[0] ? csr_w_data[7:0]
- : csr_minstret_lo_inc ? csr_minstret_lo_ff + 1'b1
- : csr_minstret_lo_ff;
-assign csr_minstret_hi_next = csr_minstret_upd[0] ? {csr_minstret_hi_new[63:32], csr_w_data[31:8]}
- : csr_minstret_upd[1] ? {csr_w_data, csr_minstret_hi_new[31:8]}
- : csr_minstret_hi_inc ? csr_minstret_hi_new
- : csr_minstret_hi_ff;
-
-assign csr_minstret = {csr_minstret_hi_ff, csr_minstret_lo_ff};
-`endif // SCR1_CSR_REDUCED_CNT
-
-//------------------------------------------------------------------------------
-// Non-standard CSR
-//------------------------------------------------------------------------------
-
-`ifdef SCR1_MCOUNTEN_EN
-// MCOUNTEN register
-//------------------------------------------------------------------------------
-// Holds Counters enable bits (CY - MCYCLE counter; IR - MINSTRET counter)
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- csr_mcounten_cy_ff <= 1'b1;
- csr_mcounten_ir_ff <= 1'b1;
- end else if (csr_mcounten_upd) begin
- csr_mcounten_cy_ff <= csr_w_data[SCR1_CSR_MCOUNTEN_CY_OFFSET];
- csr_mcounten_ir_ff <= csr_w_data[SCR1_CSR_MCOUNTEN_IR_OFFSET];
- end
-end
-
-always_comb begin
- csr_mcounten = '0;
- csr_mcounten[SCR1_CSR_MCOUNTEN_CY_OFFSET] = csr_mcounten_cy_ff;
- csr_mcounten[SCR1_CSR_MCOUNTEN_IR_OFFSET] = csr_mcounten_ir_ff;
-end
-`endif // SCR1_MCOUNTEN_EN
-
-//------------------------------------------------------------------------------
-// CSR <-> EXU interface
-//------------------------------------------------------------------------------
-
-// CSR exception
-assign csr2exu_rw_exc_o = csr_r_exc | csr_w_exc
-`ifdef SCR1_DBG_EN
- | (csr2hdu_req_o & (hdu2csr_resp_i != SCR1_CSR_RESP_OK))
-`endif // SCR1_DBG_EN
-`ifdef SCR1_TDU_EN
- | (csr2tdu_req_o & (tdu2csr_resp_i != SCR1_CSR_RESP_OK))
-`endif // SCR1_TDU_EN
- ;
-assign csr2exu_ip_ie_o = csr_eirq_pnd_en | csr_sirq_pnd_en | csr_tirq_pnd_en;
-assign csr2exu_irq_o = csr2exu_ip_ie_o & csr_mstatus_mie_ff;
-
-assign csr2exu_mstatus_mie_up_o = csr_mstatus_upd | csr_mie_upd | e_mret;
-
-// New PC multiplexer
-`ifndef SCR1_MTVEC_MODE_EN
-assign csr2exu_new_pc_o = (exu2csr_mret_instr_i & ~exu2csr_take_irq_i)
- ? csr_mepc
- : {csr_mtvec_base, SCR1_CSR_MTVEC_BASE_ZERO_BITS'(0)};
-`else // SCR1_MTVEC_MODE_EN
-always_comb begin
- if (exu2csr_mret_instr_i & ~exu2csr_take_irq_i) begin
- csr2exu_new_pc_o = csr_mepc;
- end else begin
- if (csr_mtvec_mode_vect) begin
- case (1'b1)
- exu2csr_take_exc_i: csr2exu_new_pc_o = {csr_mtvec_base, SCR1_CSR_MTVEC_BASE_ZERO_BITS'(0)};
- csr_eirq_pnd_en : csr2exu_new_pc_o = {csr_mtvec_base, SCR1_EXC_CODE_IRQ_M_EXTERNAL, 2'd0};
- csr_sirq_pnd_en : csr2exu_new_pc_o = {csr_mtvec_base, SCR1_EXC_CODE_IRQ_M_SOFTWARE, 2'd0};
- csr_tirq_pnd_en : csr2exu_new_pc_o = {csr_mtvec_base, SCR1_EXC_CODE_IRQ_M_TIMER, 2'd0};
- default : csr2exu_new_pc_o = {csr_mtvec_base, SCR1_CSR_MTVEC_BASE_ZERO_BITS'(0)};
- endcase
- end else begin // direct mode
- csr2exu_new_pc_o = {csr_mtvec_base, SCR1_CSR_MTVEC_BASE_ZERO_BITS'(0)};
- end
- end
-end
-`endif // SCR1_MTVEC_MODE_EN
-
-`ifdef SCR1_IPIC_EN
-//------------------------------------------------------------------------------
-// CSR <-> IPIC interface
-//------------------------------------------------------------------------------
-
-assign csr_ipic_req = csr2ipic_r_req_o | csr2ipic_w_req_o;
-assign csr2ipic_addr_o = csr_ipic_req ? exu2csr_rw_addr_i[2:0] : '0;
-assign csr2ipic_wdata_o = csr2ipic_w_req_o ? exu2csr_w_data_i : '0;
-`endif // SCR1_IPIC_EN
-
-`ifdef SCR1_DBG_EN
-//------------------------------------------------------------------------------
-// CSR <-> HDU interface
-//------------------------------------------------------------------------------
-
-assign csr2hdu_req_o = csr_hdu_req & exu_req_no_exc;
-assign csr2hdu_cmd_o = exu2csr_w_cmd_i;
-assign csr2hdu_addr_o = exu2csr_rw_addr_i[SCR1_HDU_DEBUGCSR_ADDR_WIDTH-1:0];
-assign csr2hdu_wdata_o = exu2csr_w_data_i;
-`endif // SCR1_DBG_EN
-
-`ifdef SCR1_TDU_EN
-//------------------------------------------------------------------------------
-// CSR <-> TDU interface
-//------------------------------------------------------------------------------
-
-assign csr2tdu_req_o = csr_brkm_req & exu_req_no_exc;
-assign csr2tdu_cmd_o = exu2csr_w_cmd_i;
-assign csr2tdu_addr_o = exu2csr_rw_addr_i[SCR1_CSR_ADDR_TDU_OFFS_W-1:0];
-assign csr2tdu_wdata_o = exu2csr_w_data_i;
-`endif // SCR1_TDU_EN
-
-`ifdef SCR1_TRGT_SIMULATION
-//------------------------------------------------------------------------------
-// Assertions
-//------------------------------------------------------------------------------
-
-// X checks
-
-SCR1_SVA_CSR_XCHECK_CTRL : assert property (
- @(negedge clk) disable iff (~rst_n)
- !$isunknown({exu2csr_r_req_i, exu2csr_w_req_i, exu2csr_take_irq_i, exu2csr_take_exc_i, exu2csr_mret_update_i
-`ifndef SCR1_CSR_REDUCED_CNT
- , exu2csr_instret_no_exc_i
-`endif // SCR1_CSR_REDUCED_CNT
- })
- ) else $error("CSR Error: unknown control values");
-
-SCR1_SVA_CSR_XCHECK_READ : assert property (
- @(negedge clk) disable iff (~rst_n)
- exu2csr_r_req_i |-> !$isunknown({exu2csr_rw_addr_i, csr2exu_r_data_o, csr2exu_rw_exc_o})
- ) else $error("CSR Error: unknown control values");
-
-SCR1_SVA_CSR_XCHECK_WRITE : assert property (
- @(negedge clk) disable iff (~rst_n)
- exu2csr_w_req_i |-> !$isunknown({exu2csr_rw_addr_i, exu2csr_w_cmd_i, exu2csr_w_data_i, csr2exu_rw_exc_o})
- ) else $error("CSR Error: unknown control values");
-
-`ifdef SCR1_IPIC_EN
-SCR1_SVA_CSR_XCHECK_READ_IPIC : assert property (
- @(negedge clk) disable iff (~rst_n)
- csr2ipic_r_req_o |-> !$isunknown({csr2ipic_addr_o, ipic2csr_rdata_i})
- ) else $error("CSR Error: unknown control values");
-
-SCR1_SVA_CSR_XCHECK_WRITE_IPIC : assert property (
- @(negedge clk) disable iff (~rst_n)
- csr2ipic_w_req_o |-> !$isunknown({csr2ipic_addr_o, csr2ipic_wdata_o})
- ) else $error("CSR Error: unknown control values");
-`endif // SCR1_IPIC_EN
-
-// Behavior checks
-
-`ifndef VERILATOR
-SCR1_SVA_CSR_MRET : assert property (
- @(negedge clk) disable iff (~rst_n)
- e_mret |=> ($stable(csr_mepc_ff) & $stable(csr_mtval_ff))
- ) else $error("CSR Error: MRET wrong behavior");
-
-SCR1_SVA_CSR_MRET_IRQ : assert property (
- @(negedge clk) disable iff (~rst_n)
- (exu2csr_mret_instr_i & e_irq)
- |=> ($stable(csr_mepc_ff) & (exu2csr_pc_curr_i != csr_mepc))
- ) else $error("CSR Error: MRET+IRQ wrong behavior");
-
-SCR1_SVA_CSR_EXC_IRQ : assert property (
- @(negedge clk) disable iff (~rst_n)
- (exu2csr_take_exc_i & exu2csr_take_irq_i
-`ifdef SCR1_DBG_EN
- & ~hdu2csr_no_commit_i
-`endif
- ) |=>
- (~csr_mstatus_mie_ff & (~csr_mcause_i_ff)
- & (exu2csr_pc_curr_i=={csr_mtvec_base, SCR1_CSR_MTVEC_BASE_ZERO_BITS'(0)}))
- ) else $error("CSR Error: wrong EXC+IRQ");
-`endif // VERILATOR
-SCR1_SVA_CSR_EVENTS : assert property (
- @(negedge clk) disable iff (~rst_n)
- $onehot0({e_irq, e_exc, e_mret})
- ) else $error("CSR Error: more than one event at a time");
-
-SCR1_SVA_CSR_RW_EXC : assert property (
- @(negedge clk) disable iff (~rst_n)
- csr2exu_rw_exc_o |-> (exu2csr_w_req_i | exu2csr_r_req_i)
- ) else $error("CSR Error: impossible exception");
-
-`ifndef VERILATOR
-SCR1_SVA_CSR_MSTATUS_MIE_UP : assert property (
- @(negedge clk) disable iff (~rst_n)
- csr2exu_mstatus_mie_up_o |=> ~csr2exu_mstatus_mie_up_o
- ) else $error("CSR Error: csr2exu_mstatus_mie_up_o can only be high for one mcycle");
-`endif // VERILATOR
-
-`ifndef SCR1_CSR_REDUCED_CNT
-
-`ifndef VERILATOR
-SCR1_SVA_CSR_CYCLE_INC : assert property (
- @(
-`ifndef SCR1_CLKCTRL_EN
-negedge clk
-`else // SCR1_CLKCTRL_EN
-negedge clk_alw_on
-`endif // SCR1_CLKCTRL_EN
- ) disable iff (~rst_n)
- (~|csr_mcycle_upd) |=>
-`ifdef SCR1_MCOUNTEN_EN
- ($past(csr_mcounten_cy_ff) ? (csr_mcycle == $past(csr_mcycle + 1'b1)) : $stable(csr_mcycle))
-`else //SCR1_MCOUNTEN_EN
- (csr_mcycle == $past(csr_mcycle + 1'b1))
-`endif // SCR1_MCOUNTEN_EN
- ) else $error("CSR Error: CYCLE increment wrong behavior");
-
-SCR1_SVA_CSR_INSTRET_INC : assert property (
- @(negedge clk) disable iff (~rst_n)
- (exu2csr_instret_no_exc_i & ~|csr_minstret_upd) |=>
-`ifdef SCR1_MCOUNTEN_EN
- ($past(csr_mcounten_ir_ff) ? (csr_minstret == $past(csr_minstret + 1'b1)) : $stable(csr_minstret))
-`else //SCR1_MCOUNTEN_EN
- (csr_minstret == $past(csr_minstret + 1'b1))
-`endif // SCR1_MCOUNTEN_EN
- ) else $error("CSR Error: INSTRET increment wrong behavior");
-`endif
-SCR1_SVA_CSR_CYCLE_INSTRET_UP : assert property (
- @(negedge clk) disable iff (~rst_n)
- ~(&csr_minstret_upd | &csr_mcycle_upd)
- ) else $error("CSR Error: INSTRET/CYCLE up illegal value");
-
-`endif // SCR1_CSR_REDUCED_CNT
-
-`endif // SCR1_TRGT_SIMULATION
-
-endmodule : scr1_pipe_csr
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_div.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_div.sv
deleted file mode 100755
index a911d41..0000000
--- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_div.sv
+++ /dev/null
@@ -1,215 +0,0 @@
-/////////////////////////////////////////////////////////////////////////////
-//// SPDX-FileCopyrightText: 2021, Dinesh Annayya
-////
-//// Licensed under the Apache License, Version 2.0 (the "License");
-//// you may not use this file except in compliance with the License.
-//// You may obtain a copy of the License at
-////
-//// http://www.apache.org/licenses/LICENSE-2.0
-////
-//// Unless required by applicable law or agreed to in writing, software
-//// distributed under the License is distributed on an "AS IS" BASIS,
-//// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-//// See the License for the specific language governing permissions and
-//// limitations under the License.
-//// SPDX-License-Identifier: Apache-2.0
-//// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
-/////////////////////////////////////////////////////////////////////////////
-/////////////////////////////////////////////////////////////////////////////
-//// ////
-//// 32 / 32 Divider with 16 stage pipe line , Support Signed Division ////
-//// ////
-//// This file is part of the yifive cores project ////
-//// https://github.com/dineshannayya/yifive_r0.git ////
-//// http://www.opencores.org/cores/yifive/ ////
-//// ////
-//// Description: ////
-//// 32 Div By 32 with 16 stage pipe line for timing reason ////
-//// Note: 2 Bit are computed at a time ////
-//// bit[32] =1 indicate negative number ////
-//// ////
-//// Example: 4'b1011 Div 4'b0011 ////
-//// ////
-//// ////
-//// """"""""| ////
-//// 1011 | <- qr reg ////
-//// -0011000 | <- Shuft Divider by 3 ////
-//// """"""""| <- 0011000 > 1011 , ignore sub, Quo: 0 ////
-//// 1011 | ////
-//// -001100 | <- Shift Divider by 2 ////
-//// """"""""| <- 001100 > 1011 , ignore sub, Quo:00 ////
-//// 1011 | ////
-//// -00110 | <- Shift Divider by 1 ////
-//// """"""""| <- 00110 < 1011, Rem: 0101 and Quo:001 ////
-//// 0101 | ////
-//// -0011 | <- Shift Divider by 0 ////
-//// """"""""| <- 0011 < 0101 , Rem: 10 and Quo: 0011 ////
-//// 10 | ////
-//// ////
-//// Quotient, 3 (0011); remainder 2 (10). ////
-//// ////
-//// To Do: ////
-//// nothing ////
-//// ////
-//// Author(s): ////
-//// - Dinesh Annayya, dinesha@opencores.org ////
-//// ////
-//// Revision : ////
-//// ////
-/////////////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-/////////////////////////////////////////////////////////////////////////////
-
-module scr1_pipe_div(
- input logic clk,
- input logic rstn,
- input logic data_valid, // input valid
- input logic [32:0] Din1, // dividend
- input logic [32:0] Din2, // divider
- output logic [31:0] quotient, // quotient
- output logic [31:0] remainder, // remainder
- output logic div_rdy_o, // Div result ready
- input logic data_done // Result processing complete indication
- );
-
-parameter WAIT_CMD = 2'b00; // Accept command and Do Signed to unsigned
-parameter WAIT_COMP = 2'b01; // Wait for COMPUTATION
-parameter WAIT_DONE = 2'b10; // Do Signed to Unsigned conversion
-parameter WAIT_EXIT = 2'b11; // Wait for Data Completion
-
-logic [31:0] src1, src2;
-
-// wires
-logic div0, div1;
-logic [31:0] rem0, rem1, rem2;
-logic [32:0] sub0, sub1;
-logic [63:0] cmp0, cmp1;
-logic [31:0] div_out, rem_out;
-logic [1:0] state, next_state;
-logic div_rdy_i;
-logic [31:0] quotient_next; // quotient
-logic [31:0] remainder_next; // remainder
-
-// real registers
-logic [3:0] cycle,next_cycle;
-
-// The main logic
-assign cmp1 = src2 << ({4'b1111 - cycle, 1'b0} + 'h1);
-assign cmp0 = src2 << ({4'b1111 - cycle, 1'b0} + 'h0);
-
-assign rem2 = cycle != 0 ? remainder : src1;
-
-assign sub1 = {1'b0, rem2} - {1'b0, cmp1[31:0]};
-assign div1 = |cmp1[63:32] ? 1'b0 : !sub1[32];
-assign rem1 = div1 ? sub1[31:0] : rem2[31:0];
-
-assign sub0 = {1'b0, rem1} - {1'b0, cmp0[31:0]};
-assign div0 = |cmp0[63:32] ? 1'b0 : !sub0[32];
-assign rem0 = div0 ? sub0[31:0] : rem1[31:0];
-
-//
-// in clock cycle 0 we first calculate two MSB bits, ...
-// till finally in clock cycle 3 we calculate two LSB bits
-assign div_out = {quotient[29:0], div1, div0};
-assign rem_out = rem0;
-
-//
-// divider works in four clock cycles -- 0, 1, 2 and 3
-always_ff @(posedge clk or negedge rstn)
-begin
- if (!rstn) begin
- state <= WAIT_CMD;
- cycle <= 4'b0;
- div_rdy_o <= 1'b0;
- quotient <= 32'h0;
- remainder <= 32'h0;
- src1 <= 32'h0;
- src2 <= 32'h0;
- end else begin
- cycle <= next_cycle;
- state <= next_state;
- div_rdy_o <= div_rdy_i;
- if(data_valid && state== WAIT_CMD ) begin
- src1 <= (Din1[32] == 1'b1) ? (32'hFFFF_FFFF ^ Din1[31:0])+1 : Din1[31:0];
- src2 <= (Din2[32] == 1'b1) ? (32'hFFFF_FFFF ^ Din2[31:0])+1 : Din2[31:0];
- end
- quotient <= quotient_next;
- remainder <= remainder_next;
- end
-end
-
-
-always_comb
-begin
- div_rdy_i = 0;
- next_cycle = cycle;
- next_state = state;
- quotient_next = quotient;
- remainder_next = remainder;
- case(state)
- WAIT_CMD: if(data_valid) begin
- next_cycle = 0;
- if(Din2[31:0] == 0) begin // Div by 0 case
- next_state = WAIT_DONE;
- end else begin
- next_state = WAIT_COMP;
- end
- end
- // WAIT for Computation
- WAIT_COMP:
- begin
- quotient_next = div_out;
- remainder_next = rem_out;
- next_cycle = cycle +1;
- if(cycle == 15) begin
- next_state = WAIT_DONE;
- end else begin
- next_cycle = cycle +1;
- end
- end
- WAIT_DONE:
- begin
- if(Din2[31:0] == 0) begin // Handling div by 0 case
- quotient_next = 32'hFFFF_FFFF;
- remainder_next = Din1[31:0];
- end else begin
- if(Din1[32] ^ Din2[32]) begin
- quotient_next = (32'hFFFF_FFFF ^ quotient[31:0]) + 1;
- end
- if(Din1[32]) begin
- remainder_next = (32'hFFFF_FFFF ^ remainder[31:0]) + 1;
- end
- end
- div_rdy_i = 1'b1;
- next_state = WAIT_EXIT;
- end
- WAIT_EXIT: begin
- if(data_done) // Wait for data completion command
- next_state = WAIT_CMD;
- end
- endcase
-end
-endmodule
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv
deleted file mode 100644
index 27ae857..0000000
--- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv
+++ /dev/null
@@ -1,1092 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_pipe_exu.sv>
-/// @brief Execution Unit (EXU)
-///
-
-//------------------------------------------------------------------------------
- //
- // Functionality:
- // - Performs instructions execution:
- // - Prevents instructions from execution if the HART is in WFI or Debug Halted
- // state
- // - Fetches operands for IALU
- // - Calculates operation results via IALU
- // - Stores IALU results in MPRF
- // - Performs LOAD/STORE operations via LSU
- // - Handles exceptions:
- // - Generates exception request
- // - Encodes exception code
- // - Calculates exception trap value
- // - Controls WFI instruction execution
- // - Calculates PC value:
- // - Initializes PC on reset
- // - Stores the current PC value
- // - Calculates a New PC value and generates a New PC request to IFU
- //
- // Structure:
- // - Instruction queue
- // - Integer Arithmetic Logic Unit (IALU)
- // - Exceptions logic
- // - WFI logic
- // - Program Counter logic
- // - Load-Store Unit (LSU)
- // - EXU status logic
- // - EXU <-> MPRF i/f
- // - EXU <-> CSR i/f
- // - EXU <-> TDU i/f
- //
-//------------------------------------------------------------------------------
-
-`include "scr1_arch_description.svh"
-`include "scr1_arch_types.svh"
-`include "scr1_memif.svh"
-`include "scr1_riscv_isa_decoding.svh"
-`include "scr1_csr.svh"
-
-`ifdef SCR1_DBG_EN
- `include "scr1_hdu.svh"
-`endif // SCR1_DBG_EN
-
-`ifdef SCR1_TDU_EN
- `include "scr1_tdu.svh"
-`endif // SCR1_TDU_EN
-
-module scr1_pipe_exu (
- // Common
- input logic rst_n, // EXU reset
- input logic clk, // Gated EXU clock
-`ifdef SCR1_CLKCTRL_EN
- input logic clk_alw_on, // Not-gated EXU clock
- input logic clk_pipe_en, // EXU clock enabled flag
-`endif // SCR1_CLKCTRL_EN
-
- // EXU <-> IDU interface
- input logic idu2exu_req_i, // Request form IDU to EXU
- output logic exu2idu_rdy_o, // EXU ready for new data from IDU
- input type_scr1_exu_cmd_s idu2exu_cmd_i, // EXU command
- input logic idu2exu_use_rs1_i, // Clock gating on rs1_addr field
- input logic idu2exu_use_rs2_i, // Clock gating on rs2_addr field
-`ifndef SCR1_NO_EXE_STAGE
- input logic idu2exu_use_rd_i, // Clock gating on rd_addr field
- input logic idu2exu_use_imm_i, // Clock gating on imm field
-`endif // SCR1_NO_EXE_STAGE
-
- // EXU <-> MPRF interface
- output logic [`SCR1_MPRF_AWIDTH-1:0] exu2mprf_rs1_addr_o, // MPRF rs1 read address
- input logic [`SCR1_XLEN-1:0] mprf2exu_rs1_data_i, // MPRF rs1 read data
- output logic [`SCR1_MPRF_AWIDTH-1:0] exu2mprf_rs2_addr_o, // MPRF rs2 read address
- input logic [`SCR1_XLEN-1:0] mprf2exu_rs2_data_i, // MPRF rs2 read data
- output logic exu2mprf_w_req_o, // MPRF write request
- output logic [`SCR1_MPRF_AWIDTH-1:0] exu2mprf_rd_addr_o, // MPRF rd write address
- output logic [`SCR1_XLEN-1:0] exu2mprf_rd_data_o, // MPRF rd write data
-
- // EXU <-> CSR read/write interface
- output logic [SCR1_CSR_ADDR_WIDTH-1:0] exu2csr_rw_addr_o, // CSR read/write address
- output logic exu2csr_r_req_o, // CSR read request
- input logic [`SCR1_XLEN-1:0] csr2exu_r_data_i, // CSR read data
- output logic exu2csr_w_req_o, // CSR write request
- output type_scr1_csr_cmd_sel_e exu2csr_w_cmd_o, // CSR write command
- output logic [`SCR1_XLEN-1:0] exu2csr_w_data_o, // CSR write data
- input logic csr2exu_rw_exc_i, // CSR read/write access exception
-
- // EXU <-> CSR events interface
- output logic exu2csr_take_irq_o, // Take IRQ trap
- output logic exu2csr_take_exc_o, // Take exception trap
- output logic exu2csr_mret_update_o, // MRET update CSR
- output logic exu2csr_mret_instr_o, // MRET instruction
- output logic [SCR1_EXC_CODE_WIDTH_E-1:0] exu2csr_exc_code_o, // Exception code (see scr1_arch_types.svh) - cp.7
- output logic [`SCR1_XLEN-1:0] exu2csr_trap_val_o, // Trap value
- input logic [`SCR1_XLEN-1:0] csr2exu_new_pc_i, // Exception/IRQ/MRET new PC
- input logic csr2exu_irq_i, // IRQ request
- input logic csr2exu_ip_ie_i, // Some IRQ pending and locally enabled
- input logic csr2exu_mstatus_mie_up_i, // MSTATUS or MIE update in the current cycle
-
- // EXU <-> DMEM interface
- output logic exu2dmem_req_o, // Data memory request
- output logic exu2dmem_cmd_o, // Data memory command - cp.7
- output logic [1:0] exu2dmem_width_o, // Data memory width
- output logic [`SCR1_DMEM_AWIDTH-1:0] exu2dmem_addr_o, // Data memory address
- output logic [`SCR1_DMEM_DWIDTH-1:0] exu2dmem_wdata_o, // Data memory write data
- input logic dmem2exu_req_ack_i, // Data memory request acknowledge
- input logic [`SCR1_DMEM_DWIDTH-1:0] dmem2exu_rdata_i, // Data memory read data
- input logic [1:0] dmem2exu_resp_i, // Data memory response - cp.7
-
- // EXU control
- output logic exu2pipe_exc_req_o, // Exception on last instruction
- output logic exu2pipe_brkpt_o, // Software Breakpoint (EBREAK)
- output logic exu2pipe_init_pc_o, // Reset exit
- output logic exu2pipe_wfi_run2halt_o, // Transition to WFI halted state
- output logic exu2pipe_instret_o, // Instruction retired (with or without exception)
- output logic exu2csr_instret_no_exc_o, // Instruction retired (without exception)
- output logic exu2pipe_exu_busy_o, // EXU busy
-
-`ifdef SCR1_DBG_EN
- // EXU <-> HDU interface
- input logic hdu2exu_no_commit_i, // Forbid instruction commitment
- input logic hdu2exu_irq_dsbl_i, // Disable IRQ
- input logic hdu2exu_pc_advmt_dsbl_i, // Forbid PC advancement
- input logic hdu2exu_dmode_sstep_en_i, // Enable single-step
- input logic hdu2exu_pbuf_fetch_i, // Take instructions from Program Buffer
- input logic hdu2exu_dbg_halted_i, // Debug halted state
- input logic hdu2exu_dbg_run2halt_i, // Transition to debug halted state
- input logic hdu2exu_dbg_halt2run_i, // Transition to run state
- input logic hdu2exu_dbg_run_start_i, // First cycle of run state
- input logic [`SCR1_XLEN-1:0] hdu2exu_dbg_new_pc_i, // New PC as starting point for HART Resume
-`endif // SCR1_DBG_EN
-
-`ifdef SCR1_TDU_EN
- // EXU <-> TDU interface
- output type_scr1_brkm_instr_mon_s exu2tdu_imon_o, // Instruction monitor
- input logic [SCR1_TDU_ALLTRIG_NUM-1:0] tdu2exu_ibrkpt_match_i, // Instruction breakpoint(s) match
- input logic tdu2exu_ibrkpt_exc_req_i, // Instruction breakpoint exception
- output type_scr1_brkm_lsu_mon_s lsu2tdu_dmon_o, // Data monitor
- input logic tdu2lsu_ibrkpt_exc_req_i, // Instruction breakpoint exception
- input logic [SCR1_TDU_MTRIG_NUM-1:0] tdu2lsu_dbrkpt_match_i, // Data breakpoint(s) match
- input logic tdu2lsu_dbrkpt_exc_req_i, // Data breakpoint exception
- output logic [SCR1_TDU_ALLTRIG_NUM-1:0] exu2tdu_ibrkpt_ret_o, // Instruction with breakpoint flag retire
- output logic exu2hdu_ibrkpt_hw_o, // Hardware breakpoint on current instruction
-`endif // SCR1_TDU_EN
-
- // PC interface
-`ifdef SCR1_CLKCTRL_EN
- output logic exu2pipe_wfi_halted_o, // WFI halted state
-`endif // SCR1_CLKCTRL_EN
- output logic [`SCR1_XLEN-1:0] exu2pipe_pc_curr_o, // Current PC
- output logic [`SCR1_XLEN-1:0] exu2csr_pc_next_o, // Next PC
- output logic exu2ifu_pc_new_req_o, // New PC request
- output logic [`SCR1_XLEN-1:0] exu2ifu_pc_new_o // New PC data
-);
-
-//------------------------------------------------------------------------------
-// Local parameters declaration
-//------------------------------------------------------------------------------
-
-localparam SCR1_JUMP_MASK = `SCR1_XLEN'hFFFF_FFFE;
-
-//------------------------------------------------------------------------------
-// Local types declaration
-//------------------------------------------------------------------------------
-
-//typedef enum logic {
-parameter SCR1_CSR_INIT = 1'b0;
-parameter SCR1_CSR_RDY = 1'b1;
-//} scr1_csr_access_e;
-
-//------------------------------------------------------------------------------
-// Local signals declaration
-//------------------------------------------------------------------------------
-
-// Instruction queue signals
-//------------------------------------------------------------------------------
-logic exu_queue_vd;
-type_scr1_exu_cmd_s exu_queue;
-logic exu_queue_barrier;
-
-`ifdef SCR1_DBG_EN
-logic dbg_run_start_npbuf;
-`endif // SCR1_DBG_EN
-logic exu_queue_en;
-logic [`SCR1_XLEN-1:0] exu_illegal_instr;
-
-`ifndef SCR1_NO_EXE_STAGE
-logic idu2exu_use_rs1_ff;
-logic idu2exu_use_rs2_ff;
-
-// EXU queue valid flag register signals
-logic exu_queue_vd_upd;
-logic exu_queue_vd_ff;
-logic exu_queue_vd_next;
-`endif // SCR1_NO_EXE_STAGE
-
-// IALU signals
-//------------------------------------------------------------------------------
-`ifdef SCR1_RVM_EXT
-logic ialu_rdy;
-logic ialu_vd;
-`endif // SCR1_RVM_EXT
-logic [`SCR1_XLEN-1:0] ialu_main_op1;
-logic [`SCR1_XLEN-1:0] ialu_main_op2;
-logic [`SCR1_XLEN-1:0] ialu_main_res;
-logic [`SCR1_XLEN-1:0] ialu_addr_op1;
-logic [`SCR1_XLEN-1:0] ialu_addr_op2;
-logic [`SCR1_XLEN-1:0] ialu_addr_res;
-logic ialu_cmp;
-
-// Exceptions signals
-//------------------------------------------------------------------------------
-logic exu_exc_req;
-`ifdef SCR1_DBG_EN
-logic exu_exc_req_ff;
-logic exu_exc_req_next;
-`endif // SCR1_DBG_EN
-logic [SCR1_EXC_CODE_WIDTH_E-1:0] exc_code; // cp.7
-logic [`SCR1_XLEN-1:0] exc_trap_val;
-logic instr_fault_rvi_hi;
-
-// WFI signals
-//------------------------------------------------------------------------------
-// WFI control signals
-logic wfi_halt_cond;
-logic wfi_run_req;
-logic wfi_halt_req;
-
-// WFI Run Start register
-logic wfi_run_start_ff;
-logic wfi_run_start_next;
-
-// WFI halted register
-logic wfi_halted_upd;
-logic wfi_halted_ff;
-logic wfi_halted_next;
-
-// PC signals
-//------------------------------------------------------------------------------
-logic [3:0] init_pc_v;
-logic init_pc;
-logic [`SCR1_XLEN-1:0] inc_pc;
-
-logic branch_taken;
-logic jb_taken;
-logic [`SCR1_XLEN-1:0] jb_new_pc;
-`ifndef SCR1_RVC_EXT
-logic jb_misalign;
-`endif
-
-// Current PC register
-logic pc_curr_upd;
-logic [`SCR1_XLEN-1:0] pc_curr_ff;
-logic [`SCR1_XLEN-1:0] pc_curr_next;
-
-// LSU signals
-//------------------------------------------------------------------------------
-logic lsu_req;
-logic lsu_rdy;
-logic [`SCR1_XLEN-1:0] lsu_l_data;
-logic lsu_exc_req;
-logic [SCR1_EXC_CODE_WIDTH_E-1:0] lsu_exc_code; // cp.7
-
-// EXU status signals
-//------------------------------------------------------------------------------
-logic exu_rdy;
-
-// MPRF signals
-//------------------------------------------------------------------------------
-logic mprf_rs1_req;
-logic mprf_rs2_req;
-
-logic [`SCR1_MPRF_AWIDTH-1:0] mprf_rs1_addr;
-logic [`SCR1_MPRF_AWIDTH-1:0] mprf_rs2_addr;
-
-// CSR signals
-//------------------------------------------------------------------------------
-// CSR access register
-logic csr_access_ff;
-logic csr_access_next;
-logic csr_access_init;
-
-//------------------------------------------------------------------------------
-// Instruction execution queue
-//------------------------------------------------------------------------------
-//
- // Instruction execution queue consists of the following functional units:
- // - EXU queue control logic
- // - EXU queue valid flag register
- // - EXU queue register
- // - EXU queue status logic
-//
-
-`ifdef SCR1_DBG_EN
-assign dbg_run_start_npbuf = hdu2exu_dbg_run_start_i & ~hdu2exu_pbuf_fetch_i;
-`endif // SCR1_DBG_EN
-
-`ifndef SCR1_NO_EXE_STAGE
-
-// EXU queue control logic
-//------------------------------------------------------------------------------
-
-assign exu_queue_barrier = wfi_halted_ff | wfi_halt_req | wfi_run_start_ff
-`ifdef SCR1_DBG_EN
- | hdu2exu_dbg_halted_i | hdu2exu_dbg_run2halt_i
- | dbg_run_start_npbuf
-`endif // SCR1_DBG_EN
-;
-
-assign exu_queue_en = exu2idu_rdy_o & idu2exu_req_i;
-
-// EXU queue valid flag register
-//------------------------------------------------------------------------------
-
-assign exu_queue_vd_upd = exu_queue_barrier | exu_rdy;
-
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- exu_queue_vd_ff <= 1'b0;
- end else if (exu_queue_vd_upd) begin
- exu_queue_vd_ff <= exu_queue_vd_next;
- end
-end
-
-assign exu_queue_vd_next = ~exu_queue_barrier & idu2exu_req_i & ~exu2ifu_pc_new_req_o;
-assign exu_queue_vd = exu_queue_vd_ff;
-
-// EXU queue register
-//------------------------------------------------------------------------------
-
-always_ff @(posedge clk) begin
- if (exu_queue_en) begin
- exu_queue.instr_rvc <= idu2exu_cmd_i.instr_rvc;
- exu_queue.ialu_op <= idu2exu_cmd_i.ialu_op;
- exu_queue.ialu_cmd <= idu2exu_cmd_i.ialu_cmd;
- exu_queue.sum2_op <= idu2exu_cmd_i.sum2_op;
- exu_queue.lsu_cmd <= idu2exu_cmd_i.lsu_cmd;
- exu_queue.csr_op <= idu2exu_cmd_i.csr_op;
- exu_queue.csr_cmd <= idu2exu_cmd_i.csr_cmd;
- exu_queue.rd_wb_sel <= idu2exu_cmd_i.rd_wb_sel;
- exu_queue.jump_req <= idu2exu_cmd_i.jump_req;
- exu_queue.branch_req <= idu2exu_cmd_i.branch_req;
- exu_queue.mret_req <= idu2exu_cmd_i.mret_req;
- exu_queue.fencei_req <= idu2exu_cmd_i.fencei_req;
- exu_queue.wfi_req <= idu2exu_cmd_i.wfi_req;
- exu_queue.exc_req <= idu2exu_cmd_i.exc_req;
- exu_queue.exc_code <= idu2exu_cmd_i.exc_code;
- idu2exu_use_rs1_ff <= idu2exu_use_rs1_i;
- idu2exu_use_rs2_ff <= idu2exu_use_rs2_i;
- if (idu2exu_use_rs1_i) begin
- exu_queue.rs1_addr <= idu2exu_cmd_i.rs1_addr;
- end
- if (idu2exu_use_rs2_i) begin
- exu_queue.rs2_addr <= idu2exu_cmd_i.rs2_addr;
- end
- if (idu2exu_use_rd_i) begin
- exu_queue.rd_addr <= idu2exu_cmd_i.rd_addr;
- end
- if (idu2exu_use_imm_i) begin
- exu_queue.imm <= idu2exu_cmd_i.imm;
- end
- end
-end
-
-`else // ~SCR1_NO_EXE_STAGE
-
-assign exu_queue_barrier = wfi_halted_ff | wfi_run_start_ff
-`ifdef SCR1_DBG_EN
- | hdu2exu_dbg_halted_i | dbg_run_start_npbuf
-`endif // SCR1_DBG_EN
-;
-assign exu_queue_vd = idu2exu_req_i & ~exu_queue_barrier;
-assign exu_queue = idu2exu_cmd_i;
-
-`endif // ~SCR1_NO_EXE_STAGE
-
-//------------------------------------------------------------------------------
-// Integer Arithmetic Logic Unit (IALU)
-//------------------------------------------------------------------------------
- //
- // Functionality:
- // - Performs addition/subtraction and arithmetic and branch comparisons
- // - Performs logical operations (AND(I), OR(I), XOR(I))
- // - Performs address calculation for branch, jump, DMEM load and store and AUIPC
- // instructions
- // - Performs shift operations
- // - Performs MUL/DIV operations
- //
-//------------------------------------------------------------------------------
-
-// IALU main operands fetch
-//------------------------------------------------------------------------------
-
-`ifdef SCR1_RVM_EXT
-assign ialu_vd = exu_queue_vd & (exu_queue.ialu_cmd != SCR1_IALU_CMD_NONE)
-`ifdef SCR1_TDU_EN
- & ~tdu2exu_ibrkpt_exc_req_i
-`endif // SCR1_TDU_EN
- ;
-`endif // SCR1_RVM_EXT
-
-always_comb begin
-`ifdef SCR1_RVM_EXT
- if (~ialu_vd) begin
- ialu_main_op1 = '0;
- ialu_main_op2 = '0;
- end else begin
-`endif // SCR1_RVM_EXT
- if (exu_queue.ialu_op == SCR1_IALU_OP_REG_REG) begin
- ialu_main_op1 = mprf2exu_rs1_data_i;
- ialu_main_op2 = mprf2exu_rs2_data_i;
- end else begin
- ialu_main_op1 = mprf2exu_rs1_data_i;
- ialu_main_op2 = exu_queue.imm;
- end
-`ifdef SCR1_RVM_EXT
- end
-`endif // SCR1_RVM_EXT
-end
-
-// IALU address operands fetch
-//------------------------------------------------------------------------------
-
-always_comb begin
- if (exu_queue.sum2_op == SCR1_SUM2_OP_REG_IMM) begin
- ialu_addr_op1 = mprf2exu_rs1_data_i;
- ialu_addr_op2 = exu_queue.imm;
- end else begin
- ialu_addr_op1 = pc_curr_ff;
- ialu_addr_op2 = exu_queue.imm;
- end
-end
-
-// IALU module instantiation
-//------------------------------------------------------------------------------
-
-scr1_pipe_ialu i_ialu(
-`ifdef SCR1_RVM_EXT
- // Common
- .clk (clk ),
- .rst_n (rst_n ),
- .exu2ialu_rvm_cmd_vd_i (ialu_vd ),
- .ialu2exu_rvm_res_rdy_o (ialu_rdy ),
-`endif // SCR1_RVM_EXT
-
- // IALU
- .exu2ialu_main_op1_i (ialu_main_op1 ),
- .exu2ialu_main_op2_i (ialu_main_op2 ),
- .exu2ialu_cmd_i (exu_queue.ialu_cmd),
- .ialu2exu_main_res_o (ialu_main_res ),
- .ialu2exu_cmp_res_o (ialu_cmp ),
-
- // Address adder signals
- .exu2ialu_addr_op1_i (ialu_addr_op1 ),
- .exu2ialu_addr_op2_i (ialu_addr_op2 ),
- .ialu2exu_addr_res_o (ialu_addr_res )
-);
-
-//------------------------------------------------------------------------------
-// Exceptions logic
-//------------------------------------------------------------------------------
-//
- // Exceptions logic consists of the following functional units:
- // - Exception request logic
- // - Exception code encoder
- // - Exception trap value multiplexer
- //
-//
-
-`ifndef SCR1_RVC_EXT
-assign jb_misalign = exu_queue_vd & jb_taken & |jb_new_pc[1:0];
-`endif // ~SCR1_RVC_EXT
-
-// Exception request
-assign exu_exc_req = exu_queue_vd & (exu_queue.exc_req | lsu_exc_req
- | csr2exu_rw_exc_i
-`ifndef SCR1_RVC_EXT
- | jb_misalign
-`endif // ~SCR1_RVC_EXT
-`ifdef SCR1_TDU_EN
- | exu2hdu_ibrkpt_hw_o
-`endif // SCR1_TDU_EN
- );
-
-// EXU exception request register
-//------------------------------------------------------------------------------
-
-`ifdef SCR1_DBG_EN
-
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- exu_exc_req_ff <= 1'b0;
- end else begin
- exu_exc_req_ff <= exu_exc_req_next;
- end
-end
-
-assign exu_exc_req_next = hdu2exu_dbg_halt2run_i ? 1'b0 : exu_exc_req;
-`endif // SCR1_DBG_EN
-
-// Exception code encoder
-//------------------------------------------------------------------------------
-
-always_comb begin
- case (1'b1)
-`ifdef SCR1_TDU_EN
- exu2hdu_ibrkpt_hw_o: exc_code = SCR1_EXC_CODE_BREAKPOINT;
-`endif // SCR1_TDU_EN
- exu_queue.exc_req : exc_code = exu_queue.exc_code;
- lsu_exc_req : exc_code = lsu_exc_code;
- csr2exu_rw_exc_i : exc_code = SCR1_EXC_CODE_ILLEGAL_INSTR;
-`ifndef SCR1_RVC_EXT
- jb_misalign : exc_code = SCR1_EXC_CODE_INSTR_MISALIGN;
-`endif // ~SCR1_RVC_EXT
- default : exc_code = SCR1_EXC_CODE_ECALL_M;
- endcase // 1'b1
-end
-
-// Exception trap value multiplexer
-//------------------------------------------------------------------------------
-
-assign instr_fault_rvi_hi = exu_queue.instr_rvc;
-assign exu_illegal_instr = {exu2csr_rw_addr_o, // CSR address
- 5'(exu_queue.rs1_addr), // rs1 / zimm
- exu_queue.imm[14:12], // funct3
- 5'(exu_queue.rd_addr), // rd
- SCR1_OPCODE_SYSTEM,
- SCR1_INSTR_RVI
- };
-
-// If Instruction Access Fault occurred on high part of RVI instruction trap
-// value is set to point on the high part of the instruction (inc_pc=pc+2)
-always_comb begin
- case (exc_code)
-`ifndef SCR1_RVC_EXT
- SCR1_EXC_CODE_INSTR_MISALIGN : exc_trap_val = jb_new_pc;
-`endif // SCR1_RVC_EXT
- SCR1_EXC_CODE_INSTR_ACCESS_FAULT: exc_trap_val = instr_fault_rvi_hi
- ? inc_pc
- : pc_curr_ff;
-`ifdef SCR1_MTVAL_ILLEGAL_INSTR_EN
- SCR1_EXC_CODE_ILLEGAL_INSTR : exc_trap_val = exu_queue.exc_req
- ? exu_queue.imm
- : exu_illegal_instr;
-`else // SCR1_MTVAL_ILLEGAL_INSTR_EN
- SCR1_EXC_CODE_ILLEGAL_INSTR : exc_trap_val = '0;
-`endif // SCR1_MTVAL_ILLEGAL_INSTR_EN
-`ifdef SCR1_TDU_EN
- SCR1_EXC_CODE_BREAKPOINT: begin
- case (1'b1)
- tdu2exu_ibrkpt_exc_req_i: exc_trap_val = pc_curr_ff;
- tdu2lsu_dbrkpt_exc_req_i: exc_trap_val = ialu_addr_res;
- default : exc_trap_val = '0;
- endcase
- end
-`endif // SCR1_TDU_EN
- SCR1_EXC_CODE_LD_ADDR_MISALIGN,
- SCR1_EXC_CODE_LD_ACCESS_FAULT,
- SCR1_EXC_CODE_ST_ADDR_MISALIGN,
- SCR1_EXC_CODE_ST_ACCESS_FAULT : exc_trap_val = ialu_addr_res;
- default : exc_trap_val = '0;
- endcase // exc_code
-end
-
-//------------------------------------------------------------------------------
-// WFI logic
-//------------------------------------------------------------------------------
-//
- // Wait for interrupt (WFI) logic consists of the following functional units:
- // - WFI control logic
- // - WFI Run Start register
- // - WFI Halted flag register
- // - WFI status signals
-//
-
-// WFI control logic
-//------------------------------------------------------------------------------
-
-assign wfi_halt_cond = ~csr2exu_ip_ie_i
- & ((exu_queue_vd & exu_queue.wfi_req) | wfi_run_start_ff)
-`ifdef SCR1_DBG_EN
- & ~hdu2exu_no_commit_i & ~hdu2exu_dmode_sstep_en_i & ~hdu2exu_dbg_run2halt_i
-`endif // SCR1_DBG_EN
- ;
-assign wfi_halt_req = ~wfi_halted_ff & wfi_halt_cond;
-
-// HART will exit WFI halted state if the event that causes the HART to resume
-// execution occurs even if it doesn't cause an interrupt to be taken
-assign wfi_run_req = wfi_halted_ff & (csr2exu_ip_ie_i
-`ifdef SCR1_DBG_EN
- | hdu2exu_dbg_halt2run_i
-`endif // SCR1_DBG_EN
- );
-
-// WFI Run Start register
-//------------------------------------------------------------------------------
-
-`ifndef SCR1_CLKCTRL_EN
-always_ff @(negedge rst_n, posedge clk) begin
-`else // SCR1_CLKCTRL_EN
-always_ff @(negedge rst_n, posedge clk_alw_on) begin
-`endif // SCR1_CLKCTRL_EN
- if (~rst_n) begin
- wfi_run_start_ff <= 1'b0;
- end else begin
- wfi_run_start_ff <= wfi_run_start_next;
- end
-end
-
-assign wfi_run_start_next = wfi_halted_ff & csr2exu_ip_ie_i & ~exu2csr_take_irq_o;
-
-// WFI halted flag register
-//------------------------------------------------------------------------------
-
-assign wfi_halted_upd = wfi_halt_req | wfi_run_req;
-
-`ifndef SCR1_CLKCTRL_EN
-always_ff @(negedge rst_n, posedge clk) begin
-`else // SCR1_CLKCTRL_EN
-always_ff @(negedge rst_n, posedge clk_alw_on) begin
-`endif // SCR1_CLKCTRL_EN
- if (~rst_n) begin
- wfi_halted_ff <= 1'b0;
- end else if (wfi_halted_upd) begin
- wfi_halted_ff <= wfi_halted_next;
- end
-end
-
-assign wfi_halted_next = wfi_halt_req | ~wfi_run_req;
-
-// WFI status signals
-//------------------------------------------------------------------------------
-
-assign exu2pipe_wfi_run2halt_o = wfi_halt_req;
-`ifdef SCR1_CLKCTRL_EN
-assign exu2pipe_wfi_halted_o = wfi_halted_ff;
-`endif // SCR1_CLKCTRL_EN
-
-//------------------------------------------------------------------------------
-// Program Counter logic
-//------------------------------------------------------------------------------
-//
- // PC logic consists of the following functional units:
- // - PC initialization logic
- // - Current PC register
- // - New PC multiplexer
-
-// PC initialization logic
-//------------------------------------------------------------------------------
-// Generates a New PC request to set PC to reset value
-
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- init_pc_v <= '0;
- end else begin
- if (~&init_pc_v) begin
- init_pc_v <= {init_pc_v[2:0], 1'b1};
- end
- end
-end
-
-assign init_pc = ~init_pc_v[3] & init_pc_v[2];
-
-// Current PC register
-//------------------------------------------------------------------------------
-
-assign pc_curr_upd = ((exu2pipe_instret_o | exu2csr_take_irq_o
-`ifdef SCR1_DBG_EN
- | dbg_run_start_npbuf) & ( ~hdu2exu_pc_advmt_dsbl_i
- & ~hdu2exu_no_commit_i
-`endif // SCR1_DBG_EN
- ));
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- pc_curr_ff <= SCR1_RST_VECTOR;
- end else if (pc_curr_upd) begin
- pc_curr_ff <= pc_curr_next;
- end
-end
-
-`ifdef SCR1_RVC_EXT
-assign inc_pc = pc_curr_ff + (exu_queue.instr_rvc ? `SCR1_XLEN'd2 : `SCR1_XLEN'd4);
-`else // ~SCR1_RVC_EXT
-assign inc_pc = pc_curr_ff + `SCR1_XLEN'd4;
-`endif // ~SCR1_RVC_EXT
-
-assign pc_curr_next = exu2ifu_pc_new_req_o ? exu2ifu_pc_new_o
- : (inc_pc[6] ^ pc_curr_ff[6]) ? inc_pc
- : {pc_curr_ff[`SCR1_XLEN-1:6], inc_pc[5:0]};
-
-// New PC multiplexer
-//------------------------------------------------------------------------------
-
-always_comb begin
- case (1'b1)
- init_pc : exu2ifu_pc_new_o = SCR1_RST_VECTOR;
- exu2csr_take_exc_o,
- exu2csr_take_irq_o,
- exu2csr_mret_instr_o: exu2ifu_pc_new_o = csr2exu_new_pc_i;
-`ifdef SCR1_DBG_EN
- dbg_run_start_npbuf : exu2ifu_pc_new_o = hdu2exu_dbg_new_pc_i;
-`endif // SCR1_DBG_EN
- wfi_run_start_ff : exu2ifu_pc_new_o = pc_curr_ff;
- exu_queue.fencei_req: exu2ifu_pc_new_o = inc_pc;
- default : exu2ifu_pc_new_o = ialu_addr_res & SCR1_JUMP_MASK;
- endcase
-end
-
-assign exu2ifu_pc_new_req_o = init_pc // reset
- | exu2csr_take_irq_o
- | exu2csr_take_exc_o
- | (exu2csr_mret_instr_o & ~csr2exu_mstatus_mie_up_i)
- | (exu_queue_vd & exu_queue.fencei_req)
- | (wfi_run_start_ff
-`ifdef SCR1_CLKCTRL_EN
- & clk_pipe_en
-`endif // SCR1_CLKCTRL_EN
- )
-`ifdef SCR1_DBG_EN
- | dbg_run_start_npbuf
-`endif // SCR1_DBG_EN
- | (exu_queue_vd & jb_taken);
-
-// Jump/branch signals
-assign branch_taken = exu_queue.branch_req & ialu_cmp & ialu_rdy;
-assign jb_taken = exu_queue.jump_req | branch_taken;
-assign jb_new_pc = ialu_addr_res & SCR1_JUMP_MASK;
-
-// PC to be loaded on MRET from interrupt trap
-assign exu2csr_pc_next_o = ~exu_queue_vd ? pc_curr_ff
- : jb_taken ? jb_new_pc
- : inc_pc;
-assign exu2pipe_pc_curr_o = pc_curr_ff;
-
-//------------------------------------------------------------------------------
-// Load/Store Unit (LSU)
-//------------------------------------------------------------------------------
- //
- // Functionality:
- // - Performs load and store operations in Data Memory
- // - Generates DMEM address misalign and access fault exceptions
- // - Passes DMEM operations information to TDU and generates LSU breakpoint exception
- //
-//------------------------------------------------------------------------------
-
-assign lsu_req = ((exu_queue.lsu_cmd != SCR1_LSU_CMD_NONE) & exu_queue_vd);
-
-scr1_pipe_lsu i_lsu(
- .rst_n (rst_n ),
- .clk (clk ),
-
- // EXU <-> LSU interface
- .exu2lsu_req_i (lsu_req ), // Request to LSU
- .exu2lsu_cmd_i (exu_queue.lsu_cmd ), // LSU command
- .exu2lsu_addr_i (ialu_addr_res ), // DMEM address
- .exu2lsu_sdata_i (mprf2exu_rs2_data_i ), // Data for store to DMEM
- .lsu2exu_rdy_o (lsu_rdy ), // LSU ready
- .lsu2exu_ldata_o (lsu_l_data ), // Loaded data form DMEM
- .lsu2exu_exc_o (lsu_exc_req ), // LSU exception
- .lsu2exu_exc_code_o (lsu_exc_code ), // LSU exception code
-
-`ifdef SCR1_TDU_EN
- // TDU <-> LSU interface
- .lsu2tdu_dmon_o (lsu2tdu_dmon_o ),
- .tdu2lsu_ibrkpt_exc_req_i (tdu2lsu_ibrkpt_exc_req_i),
- .tdu2lsu_dbrkpt_exc_req_i (tdu2lsu_dbrkpt_exc_req_i),
-`endif // SCR1_TDU_EN
-
- // Data memory interface
- .lsu2dmem_req_o (exu2dmem_req_o ), // DMEM request
- .lsu2dmem_cmd_o (exu2dmem_cmd_o ), // DMEM command
- .lsu2dmem_width_o (exu2dmem_width_o ), // DMEM width
- .lsu2dmem_addr_o (exu2dmem_addr_o ), // DMEM address
- .lsu2dmem_wdata_o (exu2dmem_wdata_o ), // DMEM write data
- .dmem2lsu_req_ack_i (dmem2exu_req_ack_i ), // DMEM request acknowledge
- .dmem2lsu_rdata_i (dmem2exu_rdata_i ), // DMEM read data
- .dmem2lsu_resp_i (dmem2exu_resp_i ) // DMEM response
-);
-
-//------------------------------------------------------------------------------
-// EXU status logic
-//------------------------------------------------------------------------------
-
-// EXU ready flag
-always_comb begin
- case (1'b1)
- lsu_req : exu_rdy = lsu_rdy | lsu_exc_req;
-`ifdef SCR1_RVM_EXT
- ialu_vd : exu_rdy = ialu_rdy;
-`endif // SCR1_RVM_EXT
- csr2exu_mstatus_mie_up_i: exu_rdy = 1'b0;
- default : exu_rdy = 1'b1;
- endcase
-end
-
-assign exu2pipe_init_pc_o = init_pc;
-assign exu2idu_rdy_o = exu_rdy & ~exu_queue_barrier;
-assign exu2pipe_exu_busy_o = exu_queue_vd & ~exu_rdy;
-assign exu2pipe_instret_o = exu_queue_vd & exu_rdy;
-assign exu2csr_instret_no_exc_o = exu2pipe_instret_o & ~exu_exc_req;
-
-// Exceptions
-`ifdef SCR1_DBG_EN
-assign exu2pipe_exc_req_o = exu_queue_vd ? exu_exc_req : exu_exc_req_ff;
-`else // SCR1_DBG_EN
-assign exu2pipe_exc_req_o = exu_exc_req;
-`endif // SCR1_DBG_EN
-
-// Breakpoints
-assign exu2pipe_brkpt_o = exu_queue_vd & (exu_queue.exc_code == SCR1_EXC_CODE_BREAKPOINT);
-`ifdef SCR1_TDU_EN
-assign exu2hdu_ibrkpt_hw_o = tdu2exu_ibrkpt_exc_req_i | tdu2lsu_dbrkpt_exc_req_i;
-`endif // SCR1_TDU_EN
-
-//------------------------------------------------------------------------------
-// EXU <-> MPRF interface
-//------------------------------------------------------------------------------
-
-// Operands fetching stage
-//------------------------------------------------------------------------------
-
-`ifdef SCR1_NO_EXE_STAGE
-assign mprf_rs1_req = exu_queue_vd & idu2exu_use_rs1_i;
-assign mprf_rs2_req = exu_queue_vd & idu2exu_use_rs2_i;
-`else // SCR1_NO_EXE_STAGE
- `ifdef SCR1_MPRF_RAM
- assign mprf_rs1_req = exu_queue_en
- ? (exu_queue_vd_next & idu2exu_use_rs1_i)
- : (exu_queue_vd & idu2exu_use_rs1_ff);
- assign mprf_rs2_req = exu_queue_en
- ? (exu_queue_vd_next & idu2exu_use_rs2_i)
- : (exu_queue_vd & idu2exu_use_rs2_ff);
- `else // SCR1_MPRF_RAM
- `ifdef SCRC1_MPRF_STAGE // ADD FF Stage at MRPF
- assign mprf_rs1_req = exu_queue_en
- ? (exu_queue_vd_next & idu2exu_use_rs1_i)
- : (exu_queue_vd & idu2exu_use_rs1_ff);
- assign mprf_rs2_req = exu_queue_en
- ? (exu_queue_vd_next & idu2exu_use_rs2_i)
- : (exu_queue_vd & idu2exu_use_rs2_ff);
-
- `else
- assign mprf_rs1_req = exu_queue_vd & idu2exu_use_rs1_ff;
- assign mprf_rs2_req = exu_queue_vd & idu2exu_use_rs2_ff;
- `endif // SCR1_MPRF_RAM
- `endif
-`endif // SCR1_NO_EXE_STAGE
-
-// If exu_queue isn't enabled we need previous addresses and usage flags because
-// RAM blocks read operation is SYNCHRONOUS
-`ifdef SCR1_MPRF_RAM
- assign mprf_rs1_addr = exu_queue_en ? idu2exu_cmd_i.rs1_addr : exu_queue.rs1_addr;
- assign mprf_rs2_addr = exu_queue_en ? idu2exu_cmd_i.rs2_addr : exu_queue.rs2_addr;
-`else // SCR1_MPRF_RAM
- `ifdef SCRC1_MPRF_STAGE
- assign mprf_rs1_addr = exu_queue_en ? idu2exu_cmd_i.rs1_addr : exu_queue.rs1_addr;
- assign mprf_rs2_addr = exu_queue_en ? idu2exu_cmd_i.rs2_addr : exu_queue.rs2_addr;
- `else
- assign mprf_rs1_addr = exu_queue.rs1_addr;
- assign mprf_rs2_addr = exu_queue.rs2_addr;
- `endif
-`endif // SCR1_MPRF_RAM
-
-assign exu2mprf_rs1_addr_o = mprf_rs1_req ? `SCR1_MPRF_AWIDTH'(mprf_rs1_addr) : '0;
-assign exu2mprf_rs2_addr_o = mprf_rs2_req ? `SCR1_MPRF_AWIDTH'(mprf_rs2_addr) : '0;
-
-// Write back stage
-//------------------------------------------------------------------------------
-
-assign exu2mprf_w_req_o = (exu_queue.rd_wb_sel != SCR1_RD_WB_NONE) & exu_queue_vd & ~exu_exc_req
-`ifdef SCR1_DBG_EN
- & ~hdu2exu_no_commit_i
-`endif // SCR1_DBG_EN
- & ((exu_queue.rd_wb_sel == SCR1_RD_WB_CSR) ? csr_access_init : exu_rdy);
-
-assign exu2mprf_rd_addr_o = `SCR1_MPRF_AWIDTH'(exu_queue.rd_addr);
-
-// MRPF RD data multiplexer
-always_comb begin
- case (exu_queue.rd_wb_sel)
- SCR1_RD_WB_SUM2 : exu2mprf_rd_data_o = ialu_addr_res;
- SCR1_RD_WB_IMM : exu2mprf_rd_data_o = exu_queue.imm;
- SCR1_RD_WB_INC_PC: exu2mprf_rd_data_o = inc_pc;
- SCR1_RD_WB_LSU : exu2mprf_rd_data_o = lsu_l_data;
- SCR1_RD_WB_CSR : exu2mprf_rd_data_o = csr2exu_r_data_i;
- default : exu2mprf_rd_data_o = ialu_main_res;
- endcase
-end
-
-//------------------------------------------------------------------------------
-// EXU <-> CSR interface
-//------------------------------------------------------------------------------
-//
- // EXU <-> CSR interface consists of the following functional units:
- // - CSR write/read interface
- // - CSR access FSM
- // - CSR events interface:
- // - Exceptions signals
- // - Interrupts signals
- // - MRET signals
-//
-
-// CSRs write/read interface
-//------------------------------------------------------------------------------
-
-// CSR write/read request signals calculation
-always_comb begin
- if (~exu_queue_vd
-`ifdef SCR1_TDU_EN
- | tdu2exu_ibrkpt_exc_req_i
-`endif // SCR1_TDU_EN
- ) begin
- exu2csr_r_req_o = 1'b0;
- exu2csr_w_req_o = 1'b0;
- end else begin
- case (exu_queue.csr_cmd)
- SCR1_CSR_CMD_WRITE : begin
- exu2csr_r_req_o = |exu_queue.rd_addr;
- exu2csr_w_req_o = csr_access_init;
- end
- SCR1_CSR_CMD_SET,
- SCR1_CSR_CMD_CLEAR : begin
- exu2csr_r_req_o = 1'b1;
- exu2csr_w_req_o = |exu_queue.rs1_addr & csr_access_init;
- end
- default : begin
- exu2csr_r_req_o = 1'b0;
- exu2csr_w_req_o = 1'b0;
- end
- endcase
- end
-end
-
-assign exu2csr_w_cmd_o = exu_queue.csr_cmd;
-assign exu2csr_rw_addr_o = exu_queue.imm[SCR1_CSR_ADDR_WIDTH-1:0];
-assign exu2csr_w_data_o = (exu_queue.csr_op == SCR1_CSR_OP_REG)
- ? mprf2exu_rs1_data_i
- : {'0, exu_queue.rs1_addr}; // zimm
-
-
-// CSR access FSM
-//------------------------------------------------------------------------------
-
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- csr_access_ff <= SCR1_CSR_INIT;
- end else begin
- csr_access_ff <= csr_access_next;
- end
-end
-
-assign csr_access_next = (csr_access_init & csr2exu_mstatus_mie_up_i)
- ? SCR1_CSR_RDY
- : SCR1_CSR_INIT;
-
-assign csr_access_init = (csr_access_ff == SCR1_CSR_INIT);
-
-// CSR events interface
-//------------------------------------------------------------------------------
-
-// Exceptions signals
-assign exu2csr_take_exc_o = exu_exc_req
-`ifdef SCR1_DBG_EN
- & ~hdu2exu_dbg_halted_i
-`endif // SCR1_DBG_EN
- ;
-assign exu2csr_exc_code_o = exc_code;
-assign exu2csr_trap_val_o = exc_trap_val;
-
-// Interrupts signals
-assign exu2csr_take_irq_o = csr2exu_irq_i & ~exu2pipe_exu_busy_o
-`ifdef SCR1_DBG_EN
- & ~hdu2exu_irq_dsbl_i
- & ~hdu2exu_dbg_halted_i
-`endif // SCR1_DBG_EN
-`ifdef SCR1_CLKCTRL_EN
- & clk_pipe_en
-`endif // SCR1_CLKCTRL_EN
- ;
-
-// MRET signals
-// MRET instruction flag
-assign exu2csr_mret_instr_o = exu_queue_vd & exu_queue.mret_req
-`ifdef SCR1_TDU_EN
- & ~tdu2exu_ibrkpt_exc_req_i
-`endif // SCR1_TDU_EN
-`ifdef SCR1_DBG_EN
- & ~hdu2exu_dbg_halted_i
-`endif // SCR1_DBG_EN
- ;
-assign exu2csr_mret_update_o = exu2csr_mret_instr_o & csr_access_init;
-
-`ifdef SCR1_TDU_EN
-//------------------------------------------------------------------------------
-// EXU <-> TDU interface
-//------------------------------------------------------------------------------
-
-// Instruction monitor
-assign exu2tdu_imon_o.vd = exu_queue_vd;
-assign exu2tdu_imon_o.req = exu2pipe_instret_o;
-assign exu2tdu_imon_o.addr = pc_curr_ff;
-
-always_comb begin
- exu2tdu_ibrkpt_ret_o = '0;
- if (exu_queue_vd) begin
- exu2tdu_ibrkpt_ret_o = tdu2exu_ibrkpt_match_i;
- if (lsu_req) begin
- exu2tdu_ibrkpt_ret_o[SCR1_TDU_MTRIG_NUM-1:0] |= tdu2lsu_dbrkpt_match_i;
- end
- end
-end
-`endif // SCR1_TDU_EN
-
-
-`ifdef SCR1_TRGT_SIMULATION
-//------------------------------------------------------------------------------
-// Tracelog signals
-//------------------------------------------------------------------------------
-
-logic [`SCR1_XLEN-1:0] update_pc;
-logic update_pc_en;
-
-assign update_pc_en = (init_pc | exu2pipe_instret_o | exu2csr_take_irq_o)
-`ifdef SCR1_DBG_EN
- & ~hdu2exu_pc_advmt_dsbl_i & ~hdu2exu_no_commit_i
-`endif // SCR1_DBG_EN
- ;
-assign update_pc = exu2ifu_pc_new_req_o ? exu2ifu_pc_new_o : inc_pc;
-
-
-//------------------------------------------------------------------------------
-// Assertion
-//------------------------------------------------------------------------------
-
-// X checks
-
-SCR1_SVA_EXU_XCHECK_CTRL : assert property (
- @(negedge clk) disable iff (~rst_n)
- !$isunknown({idu2exu_req_i, csr2exu_irq_i, csr2exu_ip_ie_i, lsu_req, lsu_rdy, exu_exc_req})
- ) else $error("EXU Error: unknown control values");
-
-SCR1_SVA_EXU_XCHECK_QUEUE : assert property (
- @(negedge clk) disable iff (~rst_n)
- idu2exu_req_i |-> !$isunknown(idu2exu_cmd_i)
- ) else $error("EXU Error: unknown values in queue");
-
-SCR1_SVA_EXU_XCHECK_CSR_RDATA : assert property (
- @(negedge clk) disable iff (~rst_n)
- exu2csr_r_req_o |-> !$isunknown({csr2exu_r_data_i, csr2exu_rw_exc_i})
- ) else $error("EXU Error: unknown values from CSR");
-
-// Behavior checks
-
-SCR1_SVA_EXU_ONEHOT : assert property (
- @(negedge clk) disable iff (~rst_n)
- $onehot0({exu_queue.jump_req, exu_queue.branch_req, lsu_req})
- ) else $error("EXU Error: illegal combination of control signals");
-
-SCR1_SVA_EXU_ONEHOT_EXC : assert property (
- @(negedge clk) disable iff (~rst_n)
- exu_queue_vd |->
- $onehot0({exu_queue.exc_req, lsu_exc_req, csr2exu_rw_exc_i
-`ifndef SCR1_RVC_EXT
- , jb_misalign
-`endif
- })
- ) else $error("EXU Error: exceptions $onehot0 failed");
-
-`endif // SCR1_TRGT_SIMULATION
-
-endmodule : scr1_pipe_exu
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv
deleted file mode 100644
index e23e54b..0000000
--- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv
+++ /dev/null
@@ -1,920 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_pipe_hdu.sv>
-/// @brief HART Debug Unit (HDU)
-///
-
-//------------------------------------------------------------------------------
- //
- //
- // Functionality:
- // - Controls HART state (RUN, Debug RUN, Debug HALTED)
- // - Setups Debug Mode execution
- // - Provides status information about Debug Mode execution
- // - Provides Program Buffer functionality (a few instructions execution while
- // in Debug Mode)
- // - Provides access to Debug CSRs
- //
- // Structure:
- // - Debug state FSM
- // - HART Control logic
- // - HART Status logic
- // - Program Buffer
- // - Debug CSRs
- // - HDU <-> DM interface
- // - HDU <-> EXU interface
- // - HDU <-> IFU interface
- // - HDU <-> CSR interface
- // - HDU <-> TDU interface
- //
-//------------------------------------------------------------------------------
-
-`include "scr1_arch_description.svh"
-
-`ifdef SCR1_DBG_EN
-`include "scr1_arch_types.svh"
-`include "scr1_riscv_isa_decoding.svh"
-`include "scr1_hdu.svh"
-
-module scr1_pipe_hdu #(parameter HART_PBUF_INSTR_REGOUT_EN = 1'b1) (
- // Common signals
- input logic rst_n, // HDU reset
- input logic clk, // HDU clock
- input logic clk_en, // HDU clock enable
-`ifdef SCR1_CLKCTRL_EN
- input logic clk_pipe_en, // Pipeline clock enable
-`endif // SCR1_CLKCTRL_EN
- input logic pipe2hdu_rdc_qlfy_i, // Pipeline RDC qualifier
-
- // HDU <-> CSR i/f
- input logic csr2hdu_req_i, // CSR i/f request
- input type_scr1_csr_cmd_sel_e csr2hdu_cmd_i, // CSR i/f command
- input logic [SCR1_HDU_DEBUGCSR_ADDR_WIDTH-1:0] csr2hdu_addr_i, // CSR i/f address
- input logic [`SCR1_XLEN-1:0] csr2hdu_wdata_i, // CSR i/f write data
- output type_scr1_csr_resp_e hdu2csr_resp_o, // CSR i/f response
- output logic [`SCR1_XLEN-1:0] hdu2csr_rdata_o, // CSR i/f read data
-
- // HDU <-> DM i/f
- // HART Run Control i/f
- input logic dm2hdu_cmd_req_i, // DM-HART Command request
- input type_scr1_hdu_dbgstates_e dm2hdu_cmd_i, // DM-HART Command
- output logic hdu2dm_cmd_resp_o, // DM-HART Command response
- output logic hdu2dm_cmd_rcode_o, // DM-HART Command return code: 0 - Ok; 1 - Error
- output logic hdu2dm_hart_event_o, // DM-HART Event: 1 if HART debug state changed
- output type_scr1_hdu_hartstatus_s hdu2dm_hart_status_o, // DM-HART Status
-
- // Program Buffer i/f
- output logic [SCR1_HDU_PBUF_ADDR_WIDTH-1:0] hdu2dm_pbuf_addr_o, // Program Buffer address - so far request only for 1 instruction
- input logic [SCR1_HDU_CORE_INSTR_WIDTH-1:0] dm2hdu_pbuf_instr_i, // Program Buffer instruction
-
- // HART Abstract Data regs i/f
- output logic hdu2dm_dreg_req_o, // Abstract Data Register request
- output logic hdu2dm_dreg_wr_o, // Abstract Data Register write
- output logic [`SCR1_XLEN-1:0] hdu2dm_dreg_wdata_o, // Abstract Data Register write data
- input logic dm2hdu_dreg_resp_i, // Abstract Data Register response
- input logic dm2hdu_dreg_fail_i, // Abstract Data Register fail
- input logic [`SCR1_XLEN-1:0] dm2hdu_dreg_rdata_i, // Abstract Data Register read data
-
-`ifdef SCR1_TDU_EN
- // HDU <-> TDU interface
- output logic hdu2tdu_hwbrk_dsbl_o, // Disables BRKM
- input logic tdu2hdu_dmode_req_i, // Trigger Module requests transition to debug mode
- input logic exu2hdu_ibrkpt_hw_i, // Hardware breakpoint on current instruction
-`endif // SCR1_TDU_EN
-
- // HART Run Status
- input logic pipe2hdu_exu_busy_i, // EXU busy
- input logic pipe2hdu_instret_i, // Instruction retired (with or without exception)
- input logic pipe2hdu_init_pc_i, // Reset exit
-
- // HART Halt Status
- input logic pipe2hdu_exu_exc_req_i, // Exception request
- input logic pipe2hdu_brkpt_i, // Software Breakpoint (EBREAK)
-
- // HDU <-> EXU i/f
- // HART Run Control
- output logic hdu2exu_pbuf_fetch_o, // Fetch instruction from Program Buffer
- output logic hdu2exu_no_commit_o, // Forbid instruction commitment
- output logic hdu2exu_irq_dsbl_o, // Disable IRQ
- output logic hdu2exu_pc_advmt_dsbl_o, // Forbid PC advancement
- output logic hdu2exu_dmode_sstep_en_o, // Enable single-step
-
- // HART state
- output logic hdu2exu_dbg_halted_o, // Debug halted state
- output logic hdu2exu_dbg_run2halt_o, // Transition to debug halted state
- output logic hdu2exu_dbg_halt2run_o, // Transition to run state
- output logic hdu2exu_dbg_run_start_o, // First cycle of run state
-
- // PC interface
- input logic [`SCR1_XLEN-1:0] pipe2hdu_pc_curr_i, // Current PC
- output logic [`SCR1_XLEN-1:0] hdu2exu_dbg_new_pc_o, // New PC for resume
-
- // HDU <-> IFU i/f
- // Program Buffer Instruction interface
- input logic ifu2hdu_pbuf_instr_rdy_i, // Program Buffer Instruction i/f ready
- output logic hdu2ifu_pbuf_instr_vd_o, // Program Buffer Instruction valid
- output logic hdu2ifu_pbuf_instr_err_o, // Program Buffer Instruction i/f error
- output logic [SCR1_HDU_CORE_INSTR_WIDTH-1:0] hdu2ifu_pbuf_instr_o // Program Buffer Instruction itself
-);
-
-//------------------------------------------------------------------------------
-// Local Parameters
-//------------------------------------------------------------------------------
-
-localparam int unsigned SCR1_HDU_TIMEOUT = 64; // must be power of 2
-localparam int unsigned SCR1_HDU_TIMEOUT_WIDTH = $clog2(SCR1_HDU_TIMEOUT);
-
-//------------------------------------------------------------------------------
-// Local Signals
-//------------------------------------------------------------------------------
-
-// Debug FSM
-//------------------------------------------------------------------------------
-
-// FSM control signals
-logic dm_dhalt_req;
-logic dm_run_req;
-
-logic dm_cmd_run;
-logic dm_cmd_dhalted;
-logic dm_cmd_drun;
-
-// Debug state FSM signals
-type_scr1_hdu_dbgstates_e dbg_state;
-type_scr1_hdu_dbgstates_e dbg_state_next;
-logic dbg_state_dhalted;
-logic dbg_state_drun;
-logic dbg_state_run;
-logic dbg_state_reset;
-
-// FSM transition, update and event registers
-logic dfsm_trans;
-logic dfsm_trans_next;
-logic dfsm_update;
-logic dfsm_update_next;
-logic dfsm_event;
-logic dfsm_event_next;
-
-// HART Control signals
-//------------------------------------------------------------------------------
-
-logic hart_resume_req;
-logic hart_halt_req;
-logic hart_cmd_req;
-
-// HART Run Control register
-logic hart_runctrl_upd;
-logic hart_runctrl_clr;
-type_scr1_hdu_runctrl_s hart_runctrl;
-
-// HART halt request timeout counter signals
-logic [SCR1_HDU_TIMEOUT_WIDTH-1:0] halt_req_timeout_cnt;
-logic [SCR1_HDU_TIMEOUT_WIDTH-1:0] halt_req_timeout_cnt_next;
-logic halt_req_timeout_cnt_en;
-logic halt_req_timeout_flag;
-
-// HART Status signals
-//------------------------------------------------------------------------------
-
-type_scr1_hdu_haltstatus_s hart_haltstatus;
-type_scr1_hdu_haltcause_e hart_haltcause;
-
-logic hart_halt_pnd;
-logic hart_halt_ack;
-
-// Debug mode cause decoder signals
-logic dmode_cause_sstep;
-logic dmode_cause_except;
-logic dmode_cause_ebreak;
-logic dmode_cause_any;
-`ifdef SCR1_TDU_EN
-logic dmode_cause_tmreq;
-`endif // SCR1_TDU_EN
-
-// Program Buffer FSM
-//------------------------------------------------------------------------------
-
-// PBUF FSM control signals
-logic ifu_handshake_done;
-logic pbuf_exc_inj_req;
-logic pbuf_exc_inj_end;
-logic pbuf_start_fetch;
-
-// PBUF FSM signals
-type_scr1_hdu_pbufstates_e pbuf_fsm_curr;
-type_scr1_hdu_pbufstates_e pbuf_fsm_next;
-logic pbuf_fsm_idle;
-logic pbuf_fsm_fetch;
-logic pbuf_fsm_excinj;
-
-// PBUF address signals
-logic [SCR1_HDU_PBUF_ADDR_WIDTH-1:0] pbuf_addr_ff;
-logic [SCR1_HDU_PBUF_ADDR_WIDTH-1:0] pbuf_addr_next;
-logic pbuf_addr_end;
-logic pbuf_addr_next_vd;
-
-logic pbuf_instr_wait_latching;
-
-// Debugs CSRs
-//------------------------------------------------------------------------------
-
-// CSRs write/read interface signals
-logic csr_upd_on_halt;
-logic csr_wr;
-logic [`SCR1_XLEN-1:0] csr_wr_data;
-logic [`SCR1_XLEN-1:0] csr_rd_data;
-
-// Debug Control and Status register (DCSR)
-logic csr_dcsr_sel;
-logic csr_dcsr_wr;
-type_scr1_hdu_dcsr_s csr_dcsr_in;
-type_scr1_hdu_dcsr_s csr_dcsr_out;
-logic csr_dcsr_ebreakm;
-logic csr_dcsr_stepie;
-logic csr_dcsr_step;
-logic [SCR1_HDU_DCSR_CAUSE_BIT_L-
- SCR1_HDU_DCSR_CAUSE_BIT_R:0] csr_dcsr_cause;
-
-// Debug Program Counter register (DPC)
-logic csr_dpc_sel;
-logic csr_dpc_wr;
-logic [`SCR1_XLEN-1:0] csr_dpc_ff;
-logic [`SCR1_XLEN-1:0] csr_dpc_next;
-logic [`SCR1_XLEN-1:0] csr_dpc_out;
-
-// Debug Scratch register 0 (DSCRATCH0)
-logic csr_addr_dscratch0;
-logic csr_dscratch0_sel;
-logic csr_dscratch0_wr;
-logic [`SCR1_XLEN-1:0] csr_dscratch0_out;
-type_scr1_csr_resp_e csr_dscratch0_resp;
-
-//------------------------------------------------------------------------------
-// Debug state FSM logic
-//------------------------------------------------------------------------------
-//
- // Debug state FSM logic consists of the following functional units:
- // - FSM control logic
- // - Debug state FSM
- // - FSM transition, update and event registers
-//
-
-// FSM control logic
-//------------------------------------------------------------------------------
-
-assign dm_cmd_dhalted = (dm2hdu_cmd_i == SCR1_HDU_DBGSTATE_DHALTED);
-assign dm_cmd_run = (dm2hdu_cmd_i == SCR1_HDU_DBGSTATE_RUN);
-assign dm_cmd_drun = (dm2hdu_cmd_i == SCR1_HDU_DBGSTATE_DRUN);
-
-assign dm_dhalt_req = dm2hdu_cmd_req_i & dm_cmd_dhalted;
-assign dm_run_req = dm2hdu_cmd_req_i & (dm_cmd_run | dm_cmd_drun);
-
-// Debug state FSM
-//------------------------------------------------------------------------------
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- dbg_state <= SCR1_HDU_DBGSTATE_RESET;
- end else begin
- dbg_state <= dbg_state_next;
- end
-end
-
-always_comb begin
- if (~pipe2hdu_rdc_qlfy_i) begin
- dbg_state_next = SCR1_HDU_DBGSTATE_RESET;
- end else begin
- case (dbg_state)
- SCR1_HDU_DBGSTATE_RESET: begin
- dbg_state_next = ~pipe2hdu_init_pc_i ? SCR1_HDU_DBGSTATE_RESET
- : dm_dhalt_req ? SCR1_HDU_DBGSTATE_DHALTED
- : SCR1_HDU_DBGSTATE_RUN;
- end
- SCR1_HDU_DBGSTATE_RUN: begin
- dbg_state_next = dfsm_update ? SCR1_HDU_DBGSTATE_DHALTED
- : SCR1_HDU_DBGSTATE_RUN;
- end
- SCR1_HDU_DBGSTATE_DHALTED: begin
- dbg_state_next = ~dfsm_update ? SCR1_HDU_DBGSTATE_DHALTED
- : dm_cmd_drun ? SCR1_HDU_DBGSTATE_DRUN
- : SCR1_HDU_DBGSTATE_RUN;
- end
- SCR1_HDU_DBGSTATE_DRUN: begin
- dbg_state_next = dfsm_update ? SCR1_HDU_DBGSTATE_DHALTED
- : SCR1_HDU_DBGSTATE_DRUN;
- end
- default: begin
-`ifdef SCR1_XPROP_EN
- dbg_state_next = SCR1_HDU_DBGSTATE_XXX;
-`else // SCR1_XPROP_EN
- dbg_state_next = dbg_state;
-`endif // SCR1_XPROP_EN
- end
- endcase
- end
-end
-
-assign dbg_state_dhalted = (dbg_state == SCR1_HDU_DBGSTATE_DHALTED);
-assign dbg_state_drun = (dbg_state == SCR1_HDU_DBGSTATE_DRUN);
-assign dbg_state_run = (dbg_state == SCR1_HDU_DBGSTATE_RUN);
-assign dbg_state_reset = (dbg_state == SCR1_HDU_DBGSTATE_RESET);
-
-// FSM transition, update and event registers
-//------------------------------------------------------------------------------
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- dfsm_trans <= 1'b0;
- dfsm_update <= 1'b0;
- dfsm_event <= 1'b0;
- end else begin
- dfsm_trans <= dfsm_trans_next;
- dfsm_update <= dfsm_update_next;
- dfsm_event <= dfsm_event_next;
- end
-end
-
-always_comb begin
- dfsm_trans_next = 1'b0;
- dfsm_update_next = 1'b0;
- dfsm_event_next = 1'b0;
-
- if (~pipe2hdu_rdc_qlfy_i) begin
- dfsm_trans_next = 1'b0;
- dfsm_update_next = 1'b0;
- dfsm_event_next = 1'b1;
- end else begin
- case (dbg_state)
- SCR1_HDU_DBGSTATE_RESET: begin
- dfsm_trans_next = 1'b0;
- dfsm_update_next = 1'b0;
- dfsm_event_next = pipe2hdu_init_pc_i & ~dm2hdu_cmd_req_i;
- end
-
- SCR1_HDU_DBGSTATE_RUN,
- SCR1_HDU_DBGSTATE_DRUN: begin
- dfsm_trans_next = ~dfsm_update ? hart_halt_pnd : dfsm_trans;
- dfsm_update_next = ~dfsm_update & hart_halt_ack;
- dfsm_event_next = dfsm_update;
- end
-
- SCR1_HDU_DBGSTATE_DHALTED: begin
- dfsm_trans_next = ~dfsm_update ? ~dfsm_trans & dm_run_req
- : dfsm_trans;
- dfsm_update_next = ~dfsm_update & dfsm_trans;
- dfsm_event_next = dfsm_update;
- end
-
- default : begin
- dfsm_trans_next = 'X;
- dfsm_update_next = 'X;
- dfsm_event_next = 'X;
- end
- endcase
- end
-end
-
-//------------------------------------------------------------------------------
-// HART Control logic
-//------------------------------------------------------------------------------
-//
- // HART Control logic consists of the following functional units:
- // - Control signals
- // - HART Run Control register
- // - HART Halt Request Time-Out counter
-//
-
-// Control logic
-always_comb begin
- hart_cmd_req = 1'b0;
-
- if (~pipe2hdu_rdc_qlfy_i) begin
- hart_cmd_req = 1'b0;
- end else begin
- case (dbg_state)
- SCR1_HDU_DBGSTATE_RESET : hart_cmd_req = dm2hdu_cmd_req_i;
- SCR1_HDU_DBGSTATE_DHALTED: hart_cmd_req = (dfsm_update | dfsm_trans);
- SCR1_HDU_DBGSTATE_RUN,
- SCR1_HDU_DBGSTATE_DRUN : hart_cmd_req = ~dfsm_update & dfsm_trans;
- default : hart_cmd_req = 'X;
- endcase
- end
-end
-
-assign hart_halt_req = dm_cmd_dhalted & hart_cmd_req;
-assign hart_resume_req = (dm_cmd_run | dm_cmd_drun) & hart_cmd_req;
-
-// HART Run Control register
-//------------------------------------------------------------------------------
-
-assign hart_runctrl_clr = (dbg_state_run | dbg_state_drun)
- & (dbg_state_next == SCR1_HDU_DBGSTATE_DHALTED);
-assign hart_runctrl_upd = dbg_state_dhalted & dfsm_trans_next;
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- hart_runctrl.irq_dsbl <= 1'b0;
- hart_runctrl.fetch_src <= SCR1_HDU_FETCH_SRC_NORMAL;
- hart_runctrl.pc_advmt_dsbl <= 1'b0;
- hart_runctrl.hwbrkpt_dsbl <= 1'b0;
- hart_runctrl.redirect <= '0;
- end else if(clk_en) begin
- if (hart_runctrl_clr) begin
- hart_runctrl <= '0;
- end else begin
- if (hart_runctrl_upd) begin
- if (~dm_cmd_drun) begin
- // Case : resume to RUN state
- hart_runctrl.irq_dsbl <= csr_dcsr_step ? ~csr_dcsr_stepie : 1'b0;
- hart_runctrl.fetch_src <= SCR1_HDU_FETCH_SRC_NORMAL;
- hart_runctrl.pc_advmt_dsbl <= 1'b0;
- hart_runctrl.hwbrkpt_dsbl <= 1'b0;
- hart_runctrl.redirect.sstep <= csr_dcsr_step;
- hart_runctrl.redirect.ebreak <= csr_dcsr_ebreakm;
- end else begin
- // Case : resume to DRUN state
- hart_runctrl.irq_dsbl <= 1'b1;
- hart_runctrl.fetch_src <= SCR1_HDU_FETCH_SRC_PBUF;
- hart_runctrl.pc_advmt_dsbl <= 1'b1;
- hart_runctrl.hwbrkpt_dsbl <= 1'b1;
- hart_runctrl.redirect.sstep <= 1'b0;
- hart_runctrl.redirect.ebreak <= 1'b1;
- end
- end
- end
- end
-end
-
-// HART Halt Request Time-Out counter
-//------------------------------------------------------------------------------
-// HART goes into halt state only if the halt request is present for timeout period
-// of time
-
-assign halt_req_timeout_cnt_en = hdu2exu_dbg_halt2run_o
- | (hart_halt_req & ~hdu2exu_dbg_run2halt_o);
-
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- halt_req_timeout_cnt <= '1;
- end else if (halt_req_timeout_cnt_en) begin
- halt_req_timeout_cnt <= halt_req_timeout_cnt_next;
- end
-end
-
-assign halt_req_timeout_cnt_next = hdu2exu_dbg_halt2run_o ? '1
- : (hart_halt_req & ~hdu2exu_dbg_run2halt_o) ? halt_req_timeout_cnt - 1'b1
- : halt_req_timeout_cnt;
-
-assign halt_req_timeout_flag = ~|halt_req_timeout_cnt;
-
-//------------------------------------------------------------------------------
-// HART Status logic
-//------------------------------------------------------------------------------
-//
- // HART Status logic consists of the following functional units:
- // - Debug mode cause decoder
- // - Hart halt status cause encoder
- // - Hart halt status register
-//
-
-// Debug mode cause decoder
-//------------------------------------------------------------------------------
-
-assign dmode_cause_sstep = hart_runctrl.redirect.sstep & pipe2hdu_instret_i;
-assign dmode_cause_except = dbg_state_drun & pipe2hdu_exu_exc_req_i
- & ~pipe2hdu_brkpt_i
-`ifdef SCR1_TDU_EN
- & ~exu2hdu_ibrkpt_hw_i
-`endif // SCR1_TDU_EN
- ;
-assign dmode_cause_ebreak = hart_runctrl.redirect.ebreak & pipe2hdu_brkpt_i;
-`ifdef SCR1_TDU_EN
-assign dmode_cause_tmreq = tdu2hdu_dmode_req_i & exu2hdu_ibrkpt_hw_i;
-`endif // SCR1_TDU_EN
-
-assign dmode_cause_any = dmode_cause_sstep | dmode_cause_ebreak | dmode_cause_except
- | hart_halt_req
-`ifdef SCR1_TDU_EN
- | dmode_cause_tmreq
-`endif // SCR1_TDU_EN
- ;
-
-// HART halt cause encoder
-//------------------------------------------------------------------------------
-
-always_comb begin
- case (1'b1)
-`ifdef SCR1_TDU_EN
- dmode_cause_tmreq : hart_haltcause = SCR1_HDU_HALTCAUSE_TMREQ;
-`endif // SCR1_TDU_EN
- dmode_cause_ebreak : hart_haltcause = SCR1_HDU_HALTCAUSE_EBREAK;
- hart_halt_req : hart_haltcause = SCR1_HDU_HALTCAUSE_DMREQ;
- dmode_cause_sstep : hart_haltcause = SCR1_HDU_HALTCAUSE_SSTEP;
- default : hart_haltcause = SCR1_HDU_HALTCAUSE_NONE;
- endcase
-end
-
-// HART halt status register
-//------------------------------------------------------------------------------
-
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- hart_haltstatus <= '0;
- end else if (hart_halt_ack) begin
- hart_haltstatus.except <= dmode_cause_except;
- hart_haltstatus.cause <= hart_haltcause;
- end
-end
-
-assign hart_halt_pnd = (dfsm_trans | dm_dhalt_req) & ~hart_halt_ack;
-assign hart_halt_ack = ~hdu2exu_dbg_halted_o
- & (halt_req_timeout_flag | (~pipe2hdu_exu_busy_i & dmode_cause_any));
-
-//------------------------------------------------------------------------------
-// Program Buffer (PBUF) logic
-//------------------------------------------------------------------------------
-//
- // Program Buffer allows to execute small programs in debug mode
-//
-
-// To terminate Program Buffer execution exception should be raised. There are 2
-// cases:
-// - One of PBUF instructions raise an exception
-// - No PBUF instruction raise an exception before the last PBUF instruction has
-// been issued. In this case FSM goes into EXCINJECT state and an "Instruction
-// fetch access fault" exception is injected
-
-// PBUF FSM
-//------------------------------------------------------------------------------
-
-assign ifu_handshake_done = hdu2ifu_pbuf_instr_vd_o & ifu2hdu_pbuf_instr_rdy_i;
-assign pbuf_addr_end = (pbuf_addr_ff == (SCR1_HDU_PBUF_ADDR_SPAN-1));
-
-assign pbuf_start_fetch = dbg_state_dhalted & (dbg_state_next == SCR1_HDU_DBGSTATE_DRUN);
-assign pbuf_exc_inj_req = ifu_handshake_done & pbuf_addr_end;
-assign pbuf_exc_inj_end = pipe2hdu_exu_exc_req_i | ifu_handshake_done;
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- pbuf_fsm_curr <= SCR1_HDU_PBUFSTATE_IDLE;
- end else if(clk_en) begin
- pbuf_fsm_curr <= pbuf_fsm_next;
- end
-end
-
-always_comb begin
- case (pbuf_fsm_curr)
- SCR1_HDU_PBUFSTATE_IDLE: begin
- pbuf_fsm_next = pbuf_start_fetch ? SCR1_HDU_PBUFSTATE_FETCH
- : SCR1_HDU_PBUFSTATE_IDLE;
- end
- SCR1_HDU_PBUFSTATE_FETCH: begin
- pbuf_fsm_next = pipe2hdu_exu_exc_req_i ? SCR1_HDU_PBUFSTATE_WAIT4END
- : pbuf_exc_inj_req ? SCR1_HDU_PBUFSTATE_EXCINJECT
- : SCR1_HDU_PBUFSTATE_FETCH;
- end
- SCR1_HDU_PBUFSTATE_EXCINJECT: begin
- pbuf_fsm_next = pbuf_exc_inj_end ? SCR1_HDU_PBUFSTATE_WAIT4END
- : SCR1_HDU_PBUFSTATE_EXCINJECT;
- end
- SCR1_HDU_PBUFSTATE_WAIT4END: begin
- pbuf_fsm_next = hdu2exu_dbg_halted_o ? SCR1_HDU_PBUFSTATE_IDLE
- : SCR1_HDU_PBUFSTATE_WAIT4END;
- end
- endcase
-end
-
-assign pbuf_fsm_idle = (pbuf_fsm_curr == SCR1_HDU_PBUFSTATE_IDLE);
-assign pbuf_fsm_fetch = (pbuf_fsm_curr == SCR1_HDU_PBUFSTATE_FETCH);
-assign pbuf_fsm_excinj = (pbuf_fsm_curr == SCR1_HDU_PBUFSTATE_EXCINJECT);
-
-// Program Buffer address register
-//------------------------------------------------------------------------------
-
-assign pbuf_addr_next_vd = pbuf_fsm_fetch & ifu_handshake_done
- & ~pipe2hdu_exu_exc_req_i & ~pbuf_addr_end;
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- pbuf_addr_ff <= '0;
- end else if(clk_en) begin
- pbuf_addr_ff <= pbuf_addr_next;
- end
-end
-
-assign pbuf_addr_next = pbuf_fsm_idle ? '0
- : pbuf_addr_next_vd ? pbuf_addr_ff + 1'b1
- : pbuf_addr_ff;
-
-// Pass instruction from debug program buffer to cpu pipeline with two options:
-// - through register, better for frequency
-// - through wires, better for area
-generate if (HART_PBUF_INSTR_REGOUT_EN) begin
- always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- pbuf_instr_wait_latching <= 1'b0;
- end else begin
- pbuf_instr_wait_latching <= ifu_handshake_done;
- end
- end
-end else begin
- assign pbuf_instr_wait_latching = 1'b0;
-end endgenerate
-
-//------------------------------------------------------------------------------
-// Debug CSRs
-//------------------------------------------------------------------------------
-
-assign csr_upd_on_halt = (dbg_state_reset | dbg_state_run)
- & (dbg_state_next == SCR1_HDU_DBGSTATE_DHALTED);
-
-// CSRs select logic
-//------------------------------------------------------------------------------
-
-always_comb begin : csr_if_regsel
- csr_dcsr_sel = 1'b0;
- csr_dpc_sel = 1'b0;
- csr_dscratch0_sel = 1'b0;
- //csr_dscratch1_sel = 1'b0;
-
- if (csr2hdu_req_i) begin
- case (csr2hdu_addr_i)
- SCR1_HDU_DBGCSR_OFFS_DCSR : csr_dcsr_sel = 1'b1;
- SCR1_HDU_DBGCSR_OFFS_DPC : csr_dpc_sel = 1'b1;
- SCR1_HDU_DBGCSR_OFFS_DSCRATCH0: csr_dscratch0_sel = 1'b1;
- default : begin
- csr_dcsr_sel = 1'bX;
- csr_dpc_sel = 1'bX;
- csr_dscratch0_sel = 1'bX;
- end
- endcase
- end
-end : csr_if_regsel
-
-// CSRs read interface
-//------------------------------------------------------------------------------
-
-assign csr_rd_data = csr_dcsr_out | csr_dpc_out | csr_dscratch0_out;
-
-// CSRs write interface
-//------------------------------------------------------------------------------
-
-assign csr_wr = csr2hdu_req_i;
-
-always_comb begin : csr_if_write
- csr_wr_data = '0;
-
- if (csr2hdu_req_i) begin
- case (csr2hdu_cmd_i)
- SCR1_CSR_CMD_WRITE : csr_wr_data = csr2hdu_wdata_i;
- SCR1_CSR_CMD_SET : csr_wr_data = csr_rd_data | csr2hdu_wdata_i;
- SCR1_CSR_CMD_CLEAR : csr_wr_data = csr_rd_data & (~csr2hdu_wdata_i);
- default : csr_wr_data = 'X;
- endcase
- end
-end : csr_if_write
-
-// Debug Control and Status register
-//------------------------------------------------------------------------------
-// Setups the HART behaviour in Debug Mode and holds Debug status information
-
-always_comb begin
- csr_dcsr_in = csr_wr_data;
- csr_dcsr_wr = csr_wr & csr_dcsr_sel;
-
- csr_dcsr_out = '0;
- if (csr_dcsr_sel) begin
- csr_dcsr_out.xdebugver = SCR1_HDU_DEBUGCSR_DCSR_XDEBUGVER;
- csr_dcsr_out.ebreakm = csr_dcsr_ebreakm;
- csr_dcsr_out.stepie = csr_dcsr_stepie;
- csr_dcsr_out.step = csr_dcsr_step;
- csr_dcsr_out.prv = 2'b11;
- csr_dcsr_out.cause = csr_dcsr_cause;
- end
-end
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- csr_dcsr_ebreakm <= 1'b0;
- csr_dcsr_stepie <= 1'b0;
- csr_dcsr_step <= 1'b0;
- end else if(clk_en) begin
- if (csr_dcsr_wr) begin
- csr_dcsr_ebreakm <= csr_dcsr_in.ebreakm;
- csr_dcsr_stepie <= csr_dcsr_in.stepie;
- csr_dcsr_step <= csr_dcsr_in.step;
- end
- end
-end
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- csr_dcsr_cause <= 1'b0;
- end else if(clk_en) begin
- if(csr_upd_on_halt) begin
- csr_dcsr_cause <= hart_haltstatus.cause;
- end
- end
-end
-
-// Debug PC register
-//------------------------------------------------------------------------------
-// Saves the virtual address of the next instruction to be executed when Debug
-// Mode is entered. Could be changed by debugger
-
-assign csr_dpc_wr = csr_wr & csr_dpc_sel;
-
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- csr_dpc_ff <= '0;
- end else if(clk_en) begin
- csr_dpc_ff <= csr_dpc_next;
- end
-end
-
-assign csr_dpc_next = csr_upd_on_halt ? pipe2hdu_pc_curr_i
- : csr_dpc_wr ? csr_wr_data
- : csr_dpc_ff;
-assign csr_dpc_out = csr_dpc_sel ? csr_dpc_ff : '0;
-
-// Debug Scratch 0 register
-//------------------------------------------------------------------------------
-
-assign csr_dscratch0_resp = (~dm2hdu_dreg_resp_i | dm2hdu_dreg_fail_i)
- ? SCR1_CSR_RESP_ER
- : SCR1_CSR_RESP_OK;
-assign csr_dscratch0_out = csr_dscratch0_sel ? dm2hdu_dreg_rdata_i : '0;
-
-//------------------------------------------------------------------------------
-// HDU <-> DM interface
-//------------------------------------------------------------------------------
-
-assign hdu2dm_hart_event_o = dfsm_event;
-
-// HART status
-always_comb begin
- hdu2dm_hart_status_o = '0;
- hdu2dm_hart_status_o.dbg_state = dbg_state;
- hdu2dm_hart_status_o.except = dbg_state_dhalted & hart_haltstatus.except;
- hdu2dm_hart_status_o.ebreak = dbg_state_dhalted & (hart_haltstatus.cause == SCR1_HDU_HALTCAUSE_EBREAK);
-end
-
-assign hdu2dm_cmd_rcode_o = dbg_state_reset
- ? ~pipe2hdu_rdc_qlfy_i | ~pipe2hdu_init_pc_i | ~dm2hdu_cmd_req_i
- : ~pipe2hdu_rdc_qlfy_i | ~dfsm_update;
-
-always_comb begin
- hdu2dm_cmd_resp_o = 1'b0;
-
- case (dbg_state)
- SCR1_HDU_DBGSTATE_RESET: begin
- hdu2dm_cmd_resp_o = pipe2hdu_rdc_qlfy_i & pipe2hdu_init_pc_i & dm2hdu_cmd_req_i;
- end
-
- SCR1_HDU_DBGSTATE_RUN: begin
- hdu2dm_cmd_resp_o = pipe2hdu_rdc_qlfy_i & dfsm_update & dm2hdu_cmd_req_i;
- end
-
- SCR1_HDU_DBGSTATE_DHALTED: begin
- hdu2dm_cmd_resp_o = pipe2hdu_rdc_qlfy_i ? dfsm_update : dm2hdu_cmd_req_i;
- end
-
- SCR1_HDU_DBGSTATE_DRUN: begin
- hdu2dm_cmd_resp_o = (~pipe2hdu_rdc_qlfy_i | dfsm_update) & dm2hdu_cmd_req_i;
- end
-
- default: begin
- hdu2dm_cmd_resp_o = 'X;
- end
- endcase
-end
-
-assign hdu2dm_pbuf_addr_o = pbuf_addr_ff;
-assign hdu2dm_dreg_req_o = csr_dscratch0_sel;
-assign hdu2dm_dreg_wr_o = csr_wr & csr_dscratch0_sel;
-assign hdu2dm_dreg_wdata_o = csr_wr_data;
-
-//------------------------------------------------------------------------------
-// HDU <-> EXU interface
-//------------------------------------------------------------------------------
-
-assign hdu2exu_dbg_halted_o = (dbg_state_next == SCR1_HDU_DBGSTATE_DHALTED)
- | (~pipe2hdu_rdc_qlfy_i & ~dbg_state_run);
-assign hdu2exu_dbg_run_start_o = dbg_state_dhalted & pipe2hdu_rdc_qlfy_i & dfsm_update;
-assign hdu2exu_dbg_halt2run_o = hdu2exu_dbg_halted_o & hart_resume_req
-`ifdef SCR1_CLKCTRL_EN
- & clk_pipe_en
-`endif // SCR1_CLKCTRL_EN
- ;
-assign hdu2exu_dbg_run2halt_o = hart_halt_ack;
-
-assign hdu2exu_pbuf_fetch_o = hart_runctrl.fetch_src;
-assign hdu2exu_irq_dsbl_o = hart_runctrl.irq_dsbl;
-assign hdu2exu_pc_advmt_dsbl_o = hart_runctrl.pc_advmt_dsbl;
-// No change in arch. state if dmode caused by breakpoint
-assign hdu2exu_no_commit_o = dmode_cause_ebreak
-`ifdef SCR1_TDU_EN
- | dmode_cause_tmreq
-`endif // SCR1_TDU_EN
- ;
-assign hdu2exu_dmode_sstep_en_o = hart_runctrl.redirect.sstep;
-assign hdu2exu_dbg_new_pc_o = csr_dpc_ff;
-
-//------------------------------------------------------------------------------
-// HDU <-> IFU interface
-//------------------------------------------------------------------------------
-
-assign hdu2ifu_pbuf_instr_vd_o = (pbuf_fsm_fetch | pbuf_fsm_excinj)
- & ~pbuf_instr_wait_latching;
-assign hdu2ifu_pbuf_instr_err_o = pbuf_fsm_excinj;
-
-generate if (HART_PBUF_INSTR_REGOUT_EN) begin
- always_ff @(posedge clk) begin
- hdu2ifu_pbuf_instr_o <= dm2hdu_pbuf_instr_i;
- end
-end else begin
- assign hdu2ifu_pbuf_instr_o = dm2hdu_pbuf_instr_i;
-end endgenerate
-
-//------------------------------------------------------------------------------
-// HDU <-> CSR interface
-//------------------------------------------------------------------------------
-
-assign csr_addr_dscratch0 = (csr2hdu_addr_i == SCR1_HDU_DBGCSR_OFFS_DSCRATCH0);
-
-assign hdu2csr_resp_o = ~dbg_state_drun ? SCR1_CSR_RESP_ER
- : csr_addr_dscratch0 ? csr_dscratch0_resp
- : csr2hdu_req_i ? SCR1_CSR_RESP_OK
- : SCR1_CSR_RESP_ER;
-assign hdu2csr_rdata_o = csr_rd_data;
-
-`ifdef SCR1_TDU_EN
-//------------------------------------------------------------------------------
-// HDU <-> TDU interface
-//------------------------------------------------------------------------------
-
-assign hdu2tdu_hwbrk_dsbl_o = hart_runctrl.hwbrkpt_dsbl;
-`endif // SCR1_TDU_EN
-
-`ifdef SCR1_TRGT_SIMULATION
-//-------------------------------------------------------------------------------
-// Assertion
-//-------------------------------------------------------------------------------
-
-SVA_HDU_XCHECK_COMMON :
- assert property (
- @(negedge clk) disable iff (~rst_n)
- !$isunknown( {rst_n,clk,clk_en,csr2hdu_req_i,pipe2hdu_rdc_qlfy_i} )
- )
- else $error("HDU Error: common signals are in X state");
-
-SVA_HDU_XCHECK_CSR_INTF :
- assert property (
- @(negedge clk) disable iff (~rst_n)
- csr2hdu_req_i |-> !$isunknown( {csr2hdu_cmd_i,csr2hdu_addr_i,csr2hdu_wdata_i} )
- )
- else $error("HDU Error: CSR i/f is in X state");
-
-SVA_HDU_XCHECK_DM_INTF :
- assert property (
- @(negedge clk) disable iff (~rst_n)
- !$isunknown( {dm2hdu_cmd_req_i,dm2hdu_cmd_i,dm2hdu_dreg_resp_i,
- dm2hdu_dreg_fail_i} )
- )
- else $error("HDU Error: DM i/f is in X state");
-
-SVA_HDU_XCHECK_TDU_INTF :
- assert property (
- @(negedge clk) disable iff (~rst_n)
- !$isunknown( {tdu2hdu_dmode_req_i,exu2hdu_ibrkpt_hw_i} )
- )
- else $error("HDU Error: TDU i/f is in X state");
-
-SVA_HDU_XCHECK_HART_INTF :
- assert property (
- @(negedge clk) disable iff (~rst_n)
- !$isunknown( {pipe2hdu_exu_busy_i,pipe2hdu_instret_i,pipe2hdu_init_pc_i,pipe2hdu_exu_exc_req_i,pipe2hdu_brkpt_i,
- pipe2hdu_pc_curr_i,ifu2hdu_pbuf_instr_rdy_i} )
- )
- else $error("HDU Error: HART i/f is in X state");
-
-`endif // SCR1_TRGT_SIMULATION
-
-endmodule : scr1_pipe_hdu
-
-`endif // SCR1_DBG_EN
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv
deleted file mode 100644
index d42adf4..0000000
--- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv
+++ /dev/null
@@ -1,548 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_pipe_ialu.sv>
-/// @brief Integer Arithmetic Logic Unit (IALU)
-//// Ver 0.1 - 18th July 2021, Dinesh A, project: yifive
-//// A. For Timing Reason, Input and Output are registered
-//// Added SCR1_GOLDEN define to preserve the Previous Logic
-////////////////////////////////////////////////////////////////////////////
-
-//-------------------------------------------------------------------------------
- //
- // Functionality:
- // - Performs addition/subtraction and arithmetic and branch comparisons
- // - Performs logical operations (AND(I), OR(I), XOR(I))
- // - Performs address calculation for branch, jump, DMEM load and store and AUIPC
- // instructions
- // - Performs shift operations
- // - Performs MUL/DIV operations
- //
- // Structure:
- // - Main adder
- // - Address adder
- // - Shift logic
- // - MUL/DIV logic
- // - Output result multiplexer
- //
-//-------------------------------------------------------------------------------
-
-`include "scr1_arch_description.svh"
-`include "scr1_riscv_isa_decoding.svh"
-`include "scr1_search_ms1.svh"
-
-
-module scr1_pipe_ialu (
-`ifdef SCR1_RVM_EXT
- // Common
- input logic clk, // IALU clock
- input logic rst_n, // IALU reset
- input logic exu2ialu_rvm_cmd_vd_i, // MUL/DIV command valid
- output logic ialu2exu_rvm_res_rdy_o, // MUL/DIV result ready
-`endif // SCR1_RVM_EXT
-
- // Main adder
- input logic [`SCR1_XLEN-1:0] exu2ialu_main_op1_i, // main ALU 1st operand
- input logic [`SCR1_XLEN-1:0] exu2ialu_main_op2_i, // main ALU 2nd operand
- input type_scr1_ialu_cmd_sel_e exu2ialu_cmd_i, // IALU command
- output logic [`SCR1_XLEN-1:0] ialu2exu_main_res_o, // main ALU result
- output logic ialu2exu_cmp_res_o, // IALU comparison result
-
- // Address adder
- input logic [`SCR1_XLEN-1:0] exu2ialu_addr_op1_i, // Address adder 1st operand
- input logic [`SCR1_XLEN-1:0] exu2ialu_addr_op2_i, // Address adder 2nd operand
- output logic [`SCR1_XLEN-1:0] ialu2exu_addr_res_o // Address adder result
-);
-
-//-------------------------------------------------------------------------------
-// Local parameters declaration
-//-------------------------------------------------------------------------------
-
-`ifdef SCR1_RVM_EXT
-localparam SCR1_MUL_WIDTH = `SCR1_XLEN;
-localparam SCR1_MUL_RES_WIDTH = 2 * `SCR1_XLEN;
-localparam SCR1_MDU_SUM_WIDTH = `SCR1_XLEN + 1;
-
-localparam SCR1_DIV_WIDTH = 1;
-localparam SCR1_DIV_CNT_INIT = 32'b1 << (`SCR1_XLEN/SCR1_DIV_WIDTH - 2);
-`endif // SCR1_RVM_EXT
-
-//-------------------------------------------------------------------------------
-// Local types declaration
-//-------------------------------------------------------------------------------
-
-typedef struct packed {
- logic z; // Zero
- logic s; // Sign
- logic o; // Overflow
- logic c; // Carry
-} type_scr1_ialu_flags_s;
-
- `ifdef SCR1_RVM_EXT
-//typedef enum logic [1:0] {
-parameter SCR1_IALU_MDU_FSM_IDLE = 2'b00;
-parameter SCR1_IALU_MDU_FSM_ITER = 2'b01;
-parameter SCR1_IALU_MDU_FSM_CORR = 2'b10;
-//} type_scr1_ialu_fsm_state;
-
-//typedef enum logic [1:0] {
-parameter SCR1_IALU_MDU_NONE = 2'b00;
-parameter SCR1_IALU_MDU_MUL = 2'b01;
-parameter SCR1_IALU_MDU_DIV = 2'b10;
-//} type_scr1_ialu_mdu_cmd;
- `endif // SCR1_RVM_EXT
-
-//-------------------------------------------------------------------------------
-// Local signals declaration
-//-------------------------------------------------------------------------------
-
-// Main adder signals
-logic [`SCR1_XLEN:0] main_sum_res; // Main adder result
-type_scr1_ialu_flags_s main_sum_flags; // Main adder flags
-logic main_sum_pos_ovflw; // Main adder positive overflow
-logic main_sum_neg_ovflw; // Main adder negative overflow
-logic main_ops_diff_sgn; // Main adder operands have different signs
-logic main_ops_non_zero; // Both main adder operands are NOT 0
-
-// Shifter signals
-logic ialu_cmd_shft; // IALU command is shift
-logic signed [`SCR1_XLEN-1:0] shft_op1; // SHIFT operand 1
-logic [4:0] shft_op2; // SHIFT operand 2
-logic [1:0] shft_cmd; // SHIFT command: 00 - logical left, 10 - logical right, 11 - arithmetical right
-logic [`SCR1_XLEN-1:0] shft_res; // SHIFT result
-
-// MUL/DIV signals
-`ifdef SCR1_RVM_EXT
-
-// MDU command signals
-logic mdu_cmd_mul; // MDU command is MUL(HSU)
-logic mdu_cmd_div; // MDU command is DIV(U)/REM(U)
-logic [1:0] mul_cmd; // MUL command: 00 - MUL, 01 - MULH, 10 - MULHSU, 11 - MULHU
-logic mul_cmd_hi; // High part of MUL result is requested
-logic [1:0] div_cmd; // DIV command: 00 - DIV, 01 - DIVU, 10 - REM, 11 - REMU
-logic div_cmd_rem; // DIV command is REM(U)
-
-// Multiplier signals
-logic mul_op1_is_sgn; // First MUL operand is signed
-logic mul_op2_is_sgn; // Second MUL operand is signed
-logic mul_op1_sgn; // First MUL operand is negative
-logic mul_op2_sgn; // Second MUL operand is negative
-logic signed [`SCR1_XLEN:0] mul_op1; // MUL operand 1
-logic signed [SCR1_MUL_WIDTH:0] mul_op2; // MUL operand 1
-logic signed [SCR1_MUL_RES_WIDTH-1:0] mul_res; // MUL result
-
-// Divisor signals
-logic signed [`SCR1_XLEN:0] div_op1; // DIV operand 1
-logic signed [SCR1_MUL_WIDTH:0] div_op2; // DIV operand 2
-logic div_ops_are_sgn;
-logic div_op1_is_neg;
-logic div_op2_is_neg;
-logic [`SCR1_XLEN-1:0] div_res_rem;
-logic [`SCR1_XLEN-1:0] div_res_quo;
-
-
-`endif // SCR1_RVM_EXT
-
-
-//-------------------------------------------------------
-// Adding Input Register to break Timing Path
-// ------------------------------------------------------
-logic [`SCR1_XLEN-1:0] exu2ialu_main_op1_ff; // main ALU 1st operand
-logic [`SCR1_XLEN-1:0] exu2ialu_main_op2_ff; // main ALU 2nd operand
-type_scr1_ialu_cmd_sel_e exu2ialu_cmd_ff; // IALU command
-logic exu2ialu_rvm_cmd_vd_ff; // MUL/DIV command valid
-logic [`SCR1_XLEN-1:0] ialu2exu_main_res_i; // main ALU result
-logic ialu2exu_cmp_res_i; // IALU comparison result
-logic ialu2exu_rvm_res_rdy_i; // MUL/DIV result ready
-logic ialu_rdy ; // ialu ready
-logic ialu_data_pdone ; // ialu data process done
-
-
-`ifdef SCR1_GOLDEN
-assign exu2ialu_main_op1_ff = exu2ialu_main_op1_i;
-assign exu2ialu_main_op2_ff = exu2ialu_main_op2_i;
-assign exu2ialu_cmd_ff = exu2ialu_cmd_i;
-assign exu2ialu_rvm_cmd_vd_ff = exu2ialu_rvm_cmd_vd_i;
-
-assign ialu2exu_main_res_o = ialu2exu_main_res_i;
-assign ialu2exu_cmp_res_o = ialu2exu_cmp_res_i;
-assign ialu2exu_rvm_res_rdy_o = ialu2exu_rvm_res_rdy_i;
-assign ialu_rdy = 1;
-
-`else
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- exu2ialu_main_op1_ff <= '0;
- exu2ialu_main_op2_ff <= '0;
- exu2ialu_cmd_ff <= SCR1_IALU_CMD_NONE;
- exu2ialu_rvm_cmd_vd_ff <= '0;
- end else begin
- exu2ialu_main_op1_ff <= exu2ialu_main_op1_i;
- exu2ialu_main_op2_ff <= exu2ialu_main_op2_i;
- exu2ialu_cmd_ff <= exu2ialu_cmd_i;
- exu2ialu_rvm_cmd_vd_ff <= exu2ialu_rvm_cmd_vd_i;
- end
-end
-
-//-------------------------------------------------------
-// Adding Output Register to break Timing Path
-// ------------------------------------------------------
-
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- ialu2exu_main_res_o <= '0;
- ialu2exu_cmp_res_o <= '0;
- ialu2exu_rvm_res_rdy_o <= '0;
- ialu_data_pdone <= '0;
- end else begin
- ialu_data_pdone <= ialu2exu_rvm_res_rdy_o; // generate one cycle delayed process done
- ialu2exu_main_res_o <= ialu2exu_main_res_i;
- ialu2exu_cmp_res_o <= ialu2exu_cmp_res_i;
- ialu2exu_rvm_res_rdy_o <= ialu2exu_rvm_res_rdy_i;
- end
-end
-
-//-------------------------------------------------------
-// Creating Two cycle Latency to break timing path
-// One Cycle for Register Input + One Cycle Registered Output
-// -----------------------------------------------------
-logic cmd_vd_d;
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- cmd_vd_d <= '0;
- ialu_rdy <= '0;
- end else begin
- cmd_vd_d <= exu2ialu_rvm_cmd_vd_i & (ialu_rdy ==0);
- ialu_rdy <= cmd_vd_d & exu2ialu_rvm_cmd_vd_i & (ialu_rdy ==0) ;
- end
-end
-
-`endif
-
-//-------------------------------------------------------------------------------
-// Main adder
-//-------------------------------------------------------------------------------
-//
- // Main adder is used for the following types of operations:
- // - Addition/subtraction (ADD/ADDI/SUB)
- // - Branch comparisons (BEQ/BNE/BLT(U)/BGE(U))
- // - Arithmetic comparisons (SLT(U)/SLTI(U))
-//
-
-// Carry out (MSB of main_sum_res) is evaluated correctly because the result
-// width equals to the maximum width of both the right-hand and left-hand side variables
-always_comb begin
- main_sum_res = (exu2ialu_cmd_ff != SCR1_IALU_CMD_ADD)
- ? (exu2ialu_main_op1_ff - exu2ialu_main_op2_ff) // Subtraction and comparison
- : (exu2ialu_main_op1_ff + exu2ialu_main_op2_ff); // Addition
-
- main_sum_pos_ovflw = ~exu2ialu_main_op1_ff[`SCR1_XLEN-1]
- & exu2ialu_main_op2_ff[`SCR1_XLEN-1]
- & main_sum_res[`SCR1_XLEN-1];
- main_sum_neg_ovflw = exu2ialu_main_op1_ff[`SCR1_XLEN-1]
- & ~exu2ialu_main_op2_ff[`SCR1_XLEN-1]
- & ~main_sum_res[`SCR1_XLEN-1];
-
- // FLAGS1 - flags for comparison (result of subtraction)
- main_sum_flags.c = main_sum_res[`SCR1_XLEN];
- main_sum_flags.z = ~|main_sum_res[`SCR1_XLEN-1:0];
- main_sum_flags.s = main_sum_res[`SCR1_XLEN-1];
- main_sum_flags.o = main_sum_pos_ovflw | main_sum_neg_ovflw;
-end
-
-//-------------------------------------------------------------------------------
-// Address adder
-//-------------------------------------------------------------------------------
-//
- // Additional adder is used for the following types of operations:
- // - PC-based address calculation (AUIPC)
- // - IMEM branch address calculation (BEQ/BNE/BLT(U)/BGE(U))
- // - IMEM jump address calculation (JAL/JALR)
- // - DMEM load address calculation (LB(U)/LH(U)/LW)
- // - DMEM store address calculation (SB/SH/SW)
-//
-
-assign ialu2exu_addr_res_o = exu2ialu_addr_op1_i + exu2ialu_addr_op2_i;
-
-//-------------------------------------------------------------------------------
-// Shift logic
-//-------------------------------------------------------------------------------
- //
- // Shift logic supports the following types of shift operations:
- // - Logical left shift (SLLI/SLL)
- // - Logical right shift (SRLI/SRL)
- // - Arithmetic right shift (SRAI/SRA)
-//
-
-assign ialu_cmd_shft = (exu2ialu_cmd_ff == SCR1_IALU_CMD_SLL)
- | (exu2ialu_cmd_ff == SCR1_IALU_CMD_SRL)
- | (exu2ialu_cmd_ff == SCR1_IALU_CMD_SRA);
-assign shft_cmd = ialu_cmd_shft
- ? {(exu2ialu_cmd_ff != SCR1_IALU_CMD_SLL),
- (exu2ialu_cmd_ff == SCR1_IALU_CMD_SRA)}
- : 2'b00;
-
-always_comb begin
- shft_op1 = exu2ialu_main_op1_ff;
- shft_op2 = exu2ialu_main_op2_ff[4:0];
- case (shft_cmd)
- 2'b10 : shft_res = shft_op1 >> shft_op2;
- 2'b11 : shft_res = shft_op1 >>> shft_op2;
- default : shft_res = shft_op1 << shft_op2;
- endcase
-end
-
-`ifdef SCR1_RVM_EXT
-//-------------------------------------------------------------------------------
-// MUL/DIV logic
-//-------------------------------------------------------------------------------
-//
- // MUL/DIV instructions use the following functional units:
- // - MUL/DIV FSM control logic, including iteration number counter
- // - MUL/DIV FSM
- // - MUL logic
- // - DIV logic
- // - MDU adder to produce an intermediate result
- // - 2 registers to save the intermediate result (shared between MUL and DIV
- // operations)
-//
-
-//-------------------------------------------------------------------------------
-// MUL/DIV FSM Control logic
-//-------------------------------------------------------------------------------
-
-assign mdu_cmd_div = ((exu2ialu_cmd_ff == SCR1_IALU_CMD_DIV)
- | (exu2ialu_cmd_ff == SCR1_IALU_CMD_DIVU)
- | (exu2ialu_cmd_ff == SCR1_IALU_CMD_REM)
- | (exu2ialu_cmd_ff == SCR1_IALU_CMD_REMU)) & exu2ialu_rvm_cmd_vd_ff;
-assign mdu_cmd_mul = ((exu2ialu_cmd_ff == SCR1_IALU_CMD_MUL)
- | (exu2ialu_cmd_ff == SCR1_IALU_CMD_MULH)
- | (exu2ialu_cmd_ff == SCR1_IALU_CMD_MULHU)
- | (exu2ialu_cmd_ff == SCR1_IALU_CMD_MULHSU)) & exu2ialu_rvm_cmd_vd_ff;
-
-
-assign main_ops_non_zero = |exu2ialu_main_op1_ff & |exu2ialu_main_op2_ff;
-assign main_ops_diff_sgn = exu2ialu_main_op1_ff[`SCR1_XLEN-1]
- ^ exu2ialu_main_op2_ff[`SCR1_XLEN-1];
-
-
-
-assign div_cmd_rem = div_cmd[1];
-
-
-
-//-------------------------------------------------------------------------------
-// Multiplier logic
-//-------------------------------------------------------------------------------
-//
- // Multiplication has 2 options: fast (1 cycle) and Radix-2 (8 cycles) multiplication.
- //
- // 1. Fast multiplication uses the straightforward approach when 2 operands are
- // multiplied in one cycle
- //
- // 2. Radix-2 multiplication does 4bit multication at time
- //
- //
-//
-
-assign mul_cmd = {((exu2ialu_cmd_ff == SCR1_IALU_CMD_MULHU) | (exu2ialu_cmd_ff == SCR1_IALU_CMD_MULHSU)),
- ((exu2ialu_cmd_ff == SCR1_IALU_CMD_MULHU) | (exu2ialu_cmd_ff == SCR1_IALU_CMD_MULH))};
-
-assign mul_cmd_hi = |mul_cmd;
-assign mul_op1_is_sgn = ~&mul_cmd;
-assign mul_op2_is_sgn = ~mul_cmd[1];
-assign mul_op1_sgn = mul_op1_is_sgn & exu2ialu_main_op1_ff[`SCR1_XLEN-1];
-assign mul_op2_sgn = mul_op2_is_sgn & exu2ialu_main_op2_ff[`SCR1_XLEN-1];
-
-`ifdef SCR1_FAST_MUL
-assign mul_op1 = mdu_cmd_mul ? $signed({mul_op1_sgn, exu2ialu_main_op1_ff}) : '0;
-assign mul_op2 = mdu_cmd_mul ? $signed({mul_op2_sgn, exu2ialu_main_op2_ff}) : '0;
-assign mul_res = mdu_cmd_mul ? mul_op1 * mul_op2 : 'sb0;
-`else // ~SCR1_FAST_MUL
-
-assign mul_op1 = mdu_cmd_mul ? $signed({mul_op1_sgn, exu2ialu_main_op1_ff}) : '0;
-assign mul_op2 = mdu_cmd_mul ? $signed({mul_op2_sgn, exu2ialu_main_op2_ff}) : '0;
-
-logic mul_rdy;
-
-scr1_pipe_mul u_mul(
- .clk (clk),
- .rstn (rst_n),
- .data_valid (mdu_cmd_mul), // input valid
- .Din1 (mul_op1), // first operand
- .Din2 (mul_op2), // second operand
- .des_hig (mul_res[SCR1_MUL_RES_WIDTH-1:`SCR1_XLEN]), // first result
- .des_low (mul_res[`SCR1_XLEN-1:0]), // second result
- .mul_rdy_o (mul_rdy), // Multiply result ready
- .data_done (ialu_data_pdone) // data_process_done
- );
-
-
-`endif // ~SCR1_FAST_MUL
-
-
-
-//-------------------------------------------------------------------------------
-// Divider logic
-//-------------------------------------------------------------------------------
-
-assign div_cmd = {((exu2ialu_cmd_ff == SCR1_IALU_CMD_REM) | (exu2ialu_cmd_ff == SCR1_IALU_CMD_REMU)),
- ((exu2ialu_cmd_ff == SCR1_IALU_CMD_REMU) | (exu2ialu_cmd_ff == SCR1_IALU_CMD_DIVU))};
-
-assign div_ops_are_sgn = ~div_cmd[0];
-assign div_op1_is_neg = div_ops_are_sgn & exu2ialu_main_op1_ff[`SCR1_XLEN-1];
-assign div_op2_is_neg = div_ops_are_sgn & exu2ialu_main_op2_ff[`SCR1_XLEN-1];
-
-assign div_op1 = mdu_cmd_div ? $signed({div_op1_is_neg, exu2ialu_main_op1_ff}) : '0;
-assign div_op2 = mdu_cmd_div ? $signed({div_op2_is_neg, exu2ialu_main_op2_ff}) : '0;
-
-logic div_rdy;
-
-scr1_pipe_div u_div(
- .clk (clk),
- .rstn (rst_n),
- .data_valid (mdu_cmd_div), // input valid
- .Din1 (div_op1), // first operand
- .Din2 (div_op2), // second operand
- .quotient (div_res_quo), // Remainder
- .remainder (div_res_rem), // Quotient
- .div_rdy_o (div_rdy), // Divide result ready
- .data_done (ialu_data_pdone) // data_process_done
- );
-
-
-`endif // SCR1_RVM_EXT
-
-//-------------------------------------------------------------------------------
-// Operation result forming
-//-------------------------------------------------------------------------------
-
-always_comb begin
- ialu2exu_main_res_i = '0;
- ialu2exu_cmp_res_i = 1'b0;
- ialu2exu_rvm_res_rdy_i = 1'b0;
-
- case (exu2ialu_cmd_ff)
- SCR1_IALU_CMD_AND : begin
- ialu2exu_rvm_res_rdy_i = ialu_rdy;
- ialu2exu_main_res_i = exu2ialu_main_op1_ff & exu2ialu_main_op2_ff;
- end
- SCR1_IALU_CMD_OR : begin
- ialu2exu_rvm_res_rdy_i = ialu_rdy;
- ialu2exu_main_res_i = exu2ialu_main_op1_ff | exu2ialu_main_op2_ff;
- end
- SCR1_IALU_CMD_XOR : begin
- ialu2exu_rvm_res_rdy_i = ialu_rdy;
- ialu2exu_main_res_i = exu2ialu_main_op1_ff ^ exu2ialu_main_op2_ff;
- end
- SCR1_IALU_CMD_ADD : begin
- ialu2exu_rvm_res_rdy_i = ialu_rdy;
- ialu2exu_main_res_i = main_sum_res[`SCR1_XLEN-1:0];
- end
- SCR1_IALU_CMD_SUB : begin
- ialu2exu_rvm_res_rdy_i = ialu_rdy;
- ialu2exu_main_res_i = main_sum_res[`SCR1_XLEN-1:0];
- end
- SCR1_IALU_CMD_SUB_LT : begin
- ialu2exu_rvm_res_rdy_i = ialu_rdy;
- ialu2exu_main_res_i = `SCR1_XLEN'(main_sum_flags.s ^ main_sum_flags.o);
- ialu2exu_cmp_res_i = main_sum_flags.s ^ main_sum_flags.o;
- end
- SCR1_IALU_CMD_SUB_LTU : begin
- ialu2exu_rvm_res_rdy_i = ialu_rdy;
- ialu2exu_main_res_i = `SCR1_XLEN'(main_sum_flags.c);
- ialu2exu_cmp_res_i = main_sum_flags.c;
- end
- SCR1_IALU_CMD_SUB_EQ : begin
- ialu2exu_rvm_res_rdy_i = ialu_rdy;
- ialu2exu_main_res_i = `SCR1_XLEN'(main_sum_flags.z);
- ialu2exu_cmp_res_i = main_sum_flags.z;
- end
- SCR1_IALU_CMD_SUB_NE : begin
- ialu2exu_rvm_res_rdy_i = ialu_rdy;
- ialu2exu_main_res_i = `SCR1_XLEN'(~main_sum_flags.z);
- ialu2exu_cmp_res_i = ~main_sum_flags.z;
- end
- SCR1_IALU_CMD_SUB_GE : begin
- ialu2exu_rvm_res_rdy_i = ialu_rdy;
- ialu2exu_main_res_i = `SCR1_XLEN'(~(main_sum_flags.s ^ main_sum_flags.o));
- ialu2exu_cmp_res_i = ~(main_sum_flags.s ^ main_sum_flags.o);
- end
- SCR1_IALU_CMD_SUB_GEU : begin
- ialu2exu_rvm_res_rdy_i = ialu_rdy;
- ialu2exu_main_res_i = `SCR1_XLEN'(~main_sum_flags.c);
- ialu2exu_cmp_res_i = ~main_sum_flags.c;
- end
- SCR1_IALU_CMD_SLL,
- SCR1_IALU_CMD_SRL,
- SCR1_IALU_CMD_SRA: begin
- ialu2exu_rvm_res_rdy_i = ialu_rdy;
- ialu2exu_main_res_i = shft_res;
- end
-`ifdef SCR1_RVM_EXT
- SCR1_IALU_CMD_MUL,
- SCR1_IALU_CMD_MULHU,
- SCR1_IALU_CMD_MULHSU,
- SCR1_IALU_CMD_MULH : begin
- `ifdef SCR1_FAST_MUL
- ialu2exu_rvm_res_rdy_i = ialu_rdy;
- ialu2exu_main_res_i = mul_cmd_hi
- ? mul_res[SCR1_MUL_RES_WIDTH-1:`SCR1_XLEN]
- : mul_res[`SCR1_XLEN-1:0];
- `else // ~SCR1_FAST_MUL
- ialu2exu_rvm_res_rdy_i = mul_rdy;
- ialu2exu_main_res_i = mul_cmd_hi
- ? mul_res[SCR1_MUL_RES_WIDTH-1:`SCR1_XLEN]
- : mul_res[`SCR1_XLEN-1:0];
- `endif // ~SCR1_FAST_MUL
- end
- SCR1_IALU_CMD_DIV,
- SCR1_IALU_CMD_DIVU,
- SCR1_IALU_CMD_REM,
- SCR1_IALU_CMD_REMU : begin
- ialu2exu_main_res_i = div_cmd_rem ? div_res_rem : div_res_quo;
- ialu2exu_rvm_res_rdy_i = div_rdy;
- end
-`endif // SCR1_RVM_EXT
- default : begin end
- endcase
-end
-
-
-`ifdef SCR1_TRGT_SIMULATION
-//-------------------------------------------------------------------------------
-// Assertion
-//-------------------------------------------------------------------------------
-
-`ifdef SCR1_RVM_EXT
-
-// X checks
-
-SCR1_SVA_IALU_XCHECK_QUEUE : assert property (
- @(negedge clk) disable iff (~rst_n)
- exu2ialu_rvm_cmd_vd_ff |->
- !$isunknown({exu2ialu_main_op1_ff, exu2ialu_main_op2_ff, exu2ialu_cmd_ff})
- ) else $error("IALU Error: unknown values in queue");
-
-// Behavior checks
-
-
-`endif // SCR1_RVM_EXT
-
-`endif // SCR1_TRGT_SIMULATION
-
-endmodule : scr1_pipe_ialu
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv
deleted file mode 100644
index fec4b9d..0000000
--- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv
+++ /dev/null
@@ -1,892 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_pipe_idu.sv>
-/// @brief Instruction Decoder Unit (IDU)
-///
-
-//------------------------------------------------------------------------------
- //
- // Functionality:
- // - Decodes the instruction and creates the appropriate control signals for EXU
- //
- // Structure:
- // - Instruction decoder
- // - IDU <-> IFU i/f
- // - IDU <-> EXU i/f
- //
-//------------------------------------------------------------------------------
-
-`include "scr1_memif.svh"
-`include "scr1_arch_types.svh"
-`include "scr1_riscv_isa_decoding.svh"
-`include "scr1_arch_description.svh"
-
-module scr1_pipe_idu
-(
-`ifdef SCR1_TRGT_SIMULATION
- input logic rst_n, // IDU reset
- input logic clk, // IDU clock
-`endif // SCR1_TRGT_SIMULATION
-
- // IFU <-> IDU interface
- output logic idu2ifu_rdy_o, // IDU ready for new data
- input logic [`SCR1_IMEM_DWIDTH-1:0] ifu2idu_instr_i, // IFU instruction
- input logic ifu2idu_imem_err_i, // Instruction access fault exception
- input logic ifu2idu_err_rvi_hi_i, // 1 - imem fault when trying to fetch second half of an unaligned RVI instruction
- input logic ifu2idu_vd_i, // IFU request
-
- // IDU <-> EXU interface
- output logic idu2exu_req_o, // IDU request
- output type_scr1_exu_cmd_s idu2exu_cmd_o, // IDU command
- output logic idu2exu_use_rs1_o, // Instruction uses rs1
- output logic idu2exu_use_rs2_o, // Instruction uses rs2
- output logic idu2exu_use_rd_o, // Instruction uses rd
- output logic idu2exu_use_imm_o, // Instruction uses immediate
- input logic exu2idu_rdy_i // EXU ready for new data
-);
-
-//-------------------------------------------------------------------------------
-// Local parameters declaration
-//-------------------------------------------------------------------------------
-
-localparam [SCR1_GPR_FIELD_WIDTH-1:0] SCR1_MPRF_ZERO_ADDR = 5'd0;
-localparam [SCR1_GPR_FIELD_WIDTH-1:0] SCR1_MPRF_RA_ADDR = 5'd1;
-localparam [SCR1_GPR_FIELD_WIDTH-1:0] SCR1_MPRF_SP_ADDR = 5'd2;
-
-//-------------------------------------------------------------------------------
-// Local signals declaration
-//-------------------------------------------------------------------------------
-
-logic [`SCR1_IMEM_DWIDTH-1:0] instr;
-logic [1:0] instr_type;
-logic [6:2] rvi_opcode;
-logic rvi_illegal;
-logic [2:0] funct3;
-logic [6:0] funct7;
-logic [11:0] funct12;
-logic [4:0] shamt;
-`ifdef SCR1_RVC_EXT
-logic rvc_illegal;
-`endif // SCR1_RVC_EXT
-`ifdef SCR1_RVE_EXT
-logic rve_illegal;
-`endif // SCR1_RVE_EXT
-
-//-------------------------------------------------------------------------------
-// Instruction decoding
-//-------------------------------------------------------------------------------
-
-assign idu2ifu_rdy_o = exu2idu_rdy_i;
-assign idu2exu_req_o = ifu2idu_vd_i;
-assign instr = ifu2idu_instr_i;
-
-// RVI / RVC
-assign instr_type = instr[1:0];
-
-// RVI / RVC fields
-assign rvi_opcode = instr[6:2]; // RVI
-assign funct3 = (instr_type == SCR1_INSTR_RVI) ? instr[14:12] : instr[15:13]; // RVI / RVC
-assign funct7 = instr[31:25]; // RVI
-assign funct12 = instr[31:20]; // RVI (SYSTEM)
-assign shamt = instr[24:20]; // RVI
-
-// RV32I(MC) decode
-always_comb begin
- // Defaults
- idu2exu_cmd_o.instr_rvc = 1'b0;
- idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_REG;
- idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_NONE;
- idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_PC_IMM;
- idu2exu_cmd_o.lsu_cmd = SCR1_LSU_CMD_NONE;
- idu2exu_cmd_o.csr_op = SCR1_CSR_OP_REG;
- idu2exu_cmd_o.csr_cmd = SCR1_CSR_CMD_NONE;
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_NONE;
- idu2exu_cmd_o.jump_req = 1'b0;
- idu2exu_cmd_o.branch_req = 1'b0;
- idu2exu_cmd_o.mret_req = 1'b0;
- idu2exu_cmd_o.fencei_req = 1'b0;
- idu2exu_cmd_o.wfi_req = 1'b0;
- idu2exu_cmd_o.rs1_addr = '0;
- idu2exu_cmd_o.rs2_addr = '0;
- idu2exu_cmd_o.rd_addr = '0;
- idu2exu_cmd_o.imm = '0;
- idu2exu_cmd_o.exc_req = 1'b0;
- idu2exu_cmd_o.exc_code = SCR1_EXC_CODE_INSTR_MISALIGN;
-
- // Clock gating
- idu2exu_use_rs1_o = 1'b0;
- idu2exu_use_rs2_o = 1'b0;
- idu2exu_use_rd_o = 1'b0;
- idu2exu_use_imm_o = 1'b0;
-
- rvi_illegal = 1'b0;
-`ifdef SCR1_RVE_EXT
- rve_illegal = 1'b0;
-`endif // SCR1_RVE_EXT
-`ifdef SCR1_RVC_EXT
- rvc_illegal = 1'b0;
-`endif // SCR1_RVC_EXT
-
- // Check for IMEM access fault
- if (ifu2idu_imem_err_i) begin
- idu2exu_cmd_o.exc_req = 1'b1;
- idu2exu_cmd_o.exc_code = SCR1_EXC_CODE_INSTR_ACCESS_FAULT;
- idu2exu_cmd_o.instr_rvc = ifu2idu_err_rvi_hi_i;
- end else begin // no imem fault
- case (instr_type)
- SCR1_INSTR_RVI : begin
- idu2exu_cmd_o.rs1_addr = instr[19:15];
- idu2exu_cmd_o.rs2_addr = instr[24:20];
- idu2exu_cmd_o.rd_addr = instr[11:7];
- case (rvi_opcode)
- SCR1_OPCODE_AUIPC : begin
- idu2exu_use_rd_o = 1'b1;
- idu2exu_use_imm_o = 1'b1;
- idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_PC_IMM;
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_SUM2;
- idu2exu_cmd_o.imm = {instr[31:12], 12'b0};
-`ifdef SCR1_RVE_EXT
- if (instr[11]) rve_illegal = 1'b1;
-`endif // SCR1_RVE_EXT
- end // SCR1_OPCODE_AUIPC
-
- SCR1_OPCODE_LUI : begin
- idu2exu_use_rd_o = 1'b1;
- idu2exu_use_imm_o = 1'b1;
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IMM;
- idu2exu_cmd_o.imm = {instr[31:12], 12'b0};
-`ifdef SCR1_RVE_EXT
- if (instr[11]) rve_illegal = 1'b1;
-`endif // SCR1_RVE_EXT
- end // SCR1_OPCODE_LUI
-
- SCR1_OPCODE_JAL : begin
- idu2exu_use_rd_o = 1'b1;
- idu2exu_use_imm_o = 1'b1;
- idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_PC_IMM;
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_INC_PC;
- idu2exu_cmd_o.jump_req = 1'b1;
- idu2exu_cmd_o.imm = {{12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0};
-`ifdef SCR1_RVE_EXT
- if (instr[11]) rve_illegal = 1'b1;
-`endif // SCR1_RVE_EXT
- end // SCR1_OPCODE_JAL
-
- SCR1_OPCODE_LOAD : begin
- idu2exu_use_rs1_o = 1'b1;
- idu2exu_use_rd_o = 1'b1;
- idu2exu_use_imm_o = 1'b1;
- idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_REG_IMM;
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_LSU;
- idu2exu_cmd_o.imm = {{21{instr[31]}}, instr[30:20]};
- case (funct3)
- 3'b000 : idu2exu_cmd_o.lsu_cmd = SCR1_LSU_CMD_LB;
- 3'b001 : idu2exu_cmd_o.lsu_cmd = SCR1_LSU_CMD_LH;
- 3'b010 : idu2exu_cmd_o.lsu_cmd = SCR1_LSU_CMD_LW;
- 3'b100 : idu2exu_cmd_o.lsu_cmd = SCR1_LSU_CMD_LBU;
- 3'b101 : idu2exu_cmd_o.lsu_cmd = SCR1_LSU_CMD_LHU;
- default : rvi_illegal = 1'b1;
- endcase // funct3
-`ifdef SCR1_RVE_EXT
- if (instr[11] | instr[19]) rve_illegal = 1'b1;
-`endif // SCR1_RVE_EXT
- end // SCR1_OPCODE_LOAD
-
- SCR1_OPCODE_STORE : begin
- idu2exu_use_rs1_o = 1'b1;
- idu2exu_use_rs2_o = 1'b1;
- idu2exu_use_imm_o = 1'b1;
- idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_REG_IMM;
- idu2exu_cmd_o.imm = {{21{instr[31]}}, instr[30:25], instr[11:7]};
- case (funct3)
- 3'b000 : idu2exu_cmd_o.lsu_cmd = SCR1_LSU_CMD_SB;
- 3'b001 : idu2exu_cmd_o.lsu_cmd = SCR1_LSU_CMD_SH;
- 3'b010 : idu2exu_cmd_o.lsu_cmd = SCR1_LSU_CMD_SW;
- default : rvi_illegal = 1'b1;
- endcase // funct3
-`ifdef SCR1_RVE_EXT
- if (instr[19] | instr[24]) rve_illegal = 1'b1;
-`endif // SCR1_RVE_EXT
- end // SCR1_OPCODE_STORE
-
- SCR1_OPCODE_OP : begin
- idu2exu_use_rs1_o = 1'b1;
- idu2exu_use_rs2_o = 1'b1;
- idu2exu_use_rd_o = 1'b1;
- idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_REG;
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IALU;
- case (funct7)
- 7'b0000000 : begin
- case (funct3)
- 3'b000 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_ADD;
- 3'b001 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SLL;
- 3'b010 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SUB_LT;
- 3'b011 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SUB_LTU;
- 3'b100 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_XOR;
- 3'b101 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SRL;
- 3'b110 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_OR;
- 3'b111 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_AND;
- endcase // funct3
- end // 7'b0000000
-
- 7'b0100000 : begin
- case (funct3)
- 3'b000 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SUB;
- 3'b101 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SRA;
- default : rvi_illegal = 1'b1;
- endcase // funct3
- end // 7'b0100000
-`ifdef SCR1_RVM_EXT
- 7'b0000001 : begin
- case (funct3)
- 3'b000 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_MUL;
- 3'b001 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_MULH;
- 3'b010 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_MULHSU;
- 3'b011 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_MULHU;
- 3'b100 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_DIV;
- 3'b101 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_DIVU;
- 3'b110 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_REM;
- 3'b111 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_REMU;
- endcase // funct3
- end // 7'b0000001
-`endif // SCR1_RVM_EXT
- default : rvi_illegal = 1'b1;
- endcase // funct7
-`ifdef SCR1_RVE_EXT
- if (instr[11] | instr[19] | instr[24]) rve_illegal = 1'b1;
-`endif // SCR1_RVE_EXT
- end // SCR1_OPCODE_OP
-
- SCR1_OPCODE_OP_IMM : begin
- idu2exu_use_rs1_o = 1'b1;
- idu2exu_use_rd_o = 1'b1;
- idu2exu_use_imm_o = 1'b1;
- idu2exu_cmd_o.imm = {{21{instr[31]}}, instr[30:20]};
- idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_IMM;
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IALU;
- case (funct3)
- 3'b000 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_ADD; // ADDI
- 3'b010 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SUB_LT; // SLTI
- 3'b011 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SUB_LTU; // SLTIU
- 3'b100 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_XOR; // XORI
- 3'b110 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_OR; // ORI
- 3'b111 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_AND; // ANDI
- 3'b001 : begin
- case (funct7)
- 7'b0000000 : begin
- // SLLI
- idu2exu_cmd_o.imm = `SCR1_XLEN'(shamt); // zero-extend
- idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SLL;
- end
- default : rvi_illegal = 1'b1;
- endcase // funct7
- end
- 3'b101 : begin
- case (funct7)
- 7'b0000000 : begin
- // SRLI
- idu2exu_cmd_o.imm = `SCR1_XLEN'(shamt); // zero-extend
- idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SRL;
- end
- 7'b0100000 : begin
- // SRAI
- idu2exu_cmd_o.imm = `SCR1_XLEN'(shamt); // zero-extend
- idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SRA;
- end
- default : rvi_illegal = 1'b1;
- endcase // funct7
- end
- endcase // funct3
-`ifdef SCR1_RVE_EXT
- if (instr[11] | instr[19]) rve_illegal = 1'b1;
-`endif // SCR1_RVE_EXT
- end // SCR1_OPCODE_OP_IMM
-
- SCR1_OPCODE_MISC_MEM : begin
- case (funct3)
- 3'b000 : begin
- if (~|{instr[31:28], instr[19:15], instr[11:7]}) begin
- // FENCE = NOP
- end
- else rvi_illegal = 1'b1;
- end
- 3'b001 : begin
- if (~|{instr[31:15], instr[11:7]}) begin
- // FENCE.I
- idu2exu_cmd_o.fencei_req = 1'b1;
- end
- else rvi_illegal = 1'b1;
- end
- default : rvi_illegal = 1'b1;
- endcase // funct3
- end // SCR1_OPCODE_MISC_MEM
-
- SCR1_OPCODE_BRANCH : begin
- idu2exu_use_rs1_o = 1'b1;
- idu2exu_use_rs2_o = 1'b1;
- idu2exu_use_imm_o = 1'b1;
- idu2exu_cmd_o.imm = {{20{instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0};
- idu2exu_cmd_o.branch_req = 1'b1;
- idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_PC_IMM;
- idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_REG;
- case (funct3)
- 3'b000 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SUB_EQ;
- 3'b001 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SUB_NE;
- 3'b100 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SUB_LT;
- 3'b101 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SUB_GE;
- 3'b110 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SUB_LTU;
- 3'b111 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SUB_GEU;
- default : rvi_illegal = 1'b1;
- endcase // funct3
-`ifdef SCR1_RVE_EXT
- if (instr[19] | instr[24]) rve_illegal = 1'b1;
-`endif // SCR1_RVE_EXT
- end // SCR1_OPCODE_BRANCH
-
- SCR1_OPCODE_JALR : begin
- idu2exu_use_rs1_o = 1'b1;
- idu2exu_use_rd_o = 1'b1;
- idu2exu_use_imm_o = 1'b1;
- case (funct3)
- 3'b000 : begin
- // JALR
- idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_REG_IMM;
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_INC_PC;
- idu2exu_cmd_o.jump_req = 1'b1;
- idu2exu_cmd_o.imm = {{21{instr[31]}}, instr[30:20]};
- end
- default : rvi_illegal = 1'b1;
- endcase
-`ifdef SCR1_RVE_EXT
- if (instr[11] | instr[19]) rve_illegal = 1'b1;
-`endif // SCR1_RVE_EXT
- end // SCR1_OPCODE_JALR
-
- SCR1_OPCODE_SYSTEM : begin
- idu2exu_use_rd_o = 1'b1;
- idu2exu_use_imm_o = 1'b1;
- idu2exu_cmd_o.imm = `SCR1_XLEN'({funct3, instr[31:20]}); // {funct3, CSR address}
- case (funct3)
- 3'b000 : begin
- idu2exu_use_rd_o = 1'b0;
- idu2exu_use_imm_o = 1'b0;
- case ({instr[19:15], instr[11:7]})
- 10'd0 : begin
- case (funct12)
- 12'h000 : begin
- // ECALL
- idu2exu_cmd_o.exc_req = 1'b1;
- idu2exu_cmd_o.exc_code = SCR1_EXC_CODE_ECALL_M;
- end
- 12'h001 : begin
- // EBREAK
- idu2exu_cmd_o.exc_req = 1'b1;
- idu2exu_cmd_o.exc_code = SCR1_EXC_CODE_BREAKPOINT;
- end
- 12'h302 : begin
- // MRET
- idu2exu_cmd_o.mret_req = 1'b1;
- end
- 12'h105 : begin
- // WFI
- idu2exu_cmd_o.wfi_req = 1'b1;
- end
- default : rvi_illegal = 1'b1;
- endcase // funct12
- end
- default : rvi_illegal = 1'b1;
- endcase // {instr[19:15], instr[11:7]}
- end
- 3'b001 : begin
- // CSRRW
- idu2exu_use_rs1_o = 1'b1;
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_CSR;
- idu2exu_cmd_o.csr_cmd = SCR1_CSR_CMD_WRITE;
- idu2exu_cmd_o.csr_op = SCR1_CSR_OP_REG;
-`ifdef SCR1_RVE_EXT
- if (instr[11] | instr[19]) rve_illegal = 1'b1;
-`endif // SCR1_RVE_EXT
- end
- 3'b010 : begin
- // CSRRS
- idu2exu_use_rs1_o = 1'b1;
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_CSR;
- idu2exu_cmd_o.csr_cmd = SCR1_CSR_CMD_SET;
- idu2exu_cmd_o.csr_op = SCR1_CSR_OP_REG;
-`ifdef SCR1_RVE_EXT
- if (instr[11] | instr[19]) rve_illegal = 1'b1;
-`endif // SCR1_RVE_EXT
- end
- 3'b011 : begin
- // CSRRC
- idu2exu_use_rs1_o = 1'b1;
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_CSR;
- idu2exu_cmd_o.csr_cmd = SCR1_CSR_CMD_CLEAR;
- idu2exu_cmd_o.csr_op = SCR1_CSR_OP_REG;
-`ifdef SCR1_RVE_EXT
- if (instr[11] | instr[19]) rve_illegal = 1'b1;
-`endif // SCR1_RVE_EXT
- end
- 3'b101 : begin
- // CSRRWI
- idu2exu_use_rs1_o = 1'b1; // zimm
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_CSR;
- idu2exu_cmd_o.csr_cmd = SCR1_CSR_CMD_WRITE;
- idu2exu_cmd_o.csr_op = SCR1_CSR_OP_IMM;
-`ifdef SCR1_RVE_EXT
- if (instr[11]) rve_illegal = 1'b1;
-`endif // SCR1_RVE_EXT
- end
- 3'b110 : begin
- // CSRRSI
- idu2exu_use_rs1_o = 1'b1; // zimm
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_CSR;
- idu2exu_cmd_o.csr_cmd = SCR1_CSR_CMD_SET;
- idu2exu_cmd_o.csr_op = SCR1_CSR_OP_IMM;
-`ifdef SCR1_RVE_EXT
- if (instr[11]) rve_illegal = 1'b1;
-`endif // SCR1_RVE_EXT
- end
- 3'b111 : begin
- // CSRRCI
- idu2exu_use_rs1_o = 1'b1; // zimm
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_CSR;
- idu2exu_cmd_o.csr_cmd = SCR1_CSR_CMD_CLEAR;
- idu2exu_cmd_o.csr_op = SCR1_CSR_OP_IMM;
-`ifdef SCR1_RVE_EXT
- if (instr[11]) rve_illegal = 1'b1;
-`endif // SCR1_RVE_EXT
- end
- default : rvi_illegal = 1'b1;
- endcase // funct3
- end // SCR1_OPCODE_SYSTEM
-
- default : begin
- rvi_illegal = 1'b1;
- end
- endcase // rvi_opcode
- end // SCR1_INSTR_RVI
-
-`ifdef SCR1_RVC_EXT
-
- // Quadrant 0
- SCR1_INSTR_RVC0 : begin
- idu2exu_cmd_o.instr_rvc = 1'b1;
- idu2exu_use_rs1_o = 1'b1;
- idu2exu_use_imm_o = 1'b1;
- case (funct3)
- 3'b000 : begin
- if (~|instr[12:5]) rvc_illegal = 1'b1;
- // C.ADDI4SPN
- idu2exu_use_rd_o = 1'b1;
- idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_ADD;
- idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_IMM;
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IALU;
- idu2exu_cmd_o.rs1_addr = SCR1_MPRF_SP_ADDR;
- idu2exu_cmd_o.rd_addr = {2'b01, instr[4:2]};
- idu2exu_cmd_o.imm = {22'd0, instr[10:7], instr[12:11], instr[5], instr[6], 2'b00};
- end
- 3'b010 : begin
- // C.LW
- idu2exu_use_rd_o = 1'b1;
- idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_REG_IMM;
- idu2exu_cmd_o.lsu_cmd = SCR1_LSU_CMD_LW;
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_LSU;
- idu2exu_cmd_o.rs1_addr = {2'b01, instr[9:7]};
- idu2exu_cmd_o.rd_addr = {2'b01, instr[4:2]};
- idu2exu_cmd_o.imm = {25'd0, instr[5], instr[12:10], instr[6], 2'b00};
- end
- 3'b110 : begin
- // C.SW
- idu2exu_use_rs2_o = 1'b1;
- idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_REG_IMM;
- idu2exu_cmd_o.lsu_cmd = SCR1_LSU_CMD_SW;
- idu2exu_cmd_o.rs1_addr = {2'b01, instr[9:7]};
- idu2exu_cmd_o.rs2_addr = {2'b01, instr[4:2]};
- idu2exu_cmd_o.imm = {25'd0, instr[5], instr[12:10], instr[6], 2'b00};
- end
- default : begin
- rvc_illegal = 1'b1;
- end
- endcase // funct3
- end // Quadrant 0
-
- // Quadrant 1
- SCR1_INSTR_RVC1 : begin
- idu2exu_cmd_o.instr_rvc = 1'b1;
- idu2exu_use_rd_o = 1'b1;
- idu2exu_use_imm_o = 1'b1;
- case (funct3)
- 3'b000 : begin
- // C.ADDI / C.NOP
- idu2exu_use_rs1_o = 1'b1;
- idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_ADD;
- idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_IMM;
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IALU;
- idu2exu_cmd_o.rs1_addr = instr[11:7];
- idu2exu_cmd_o.rd_addr = instr[11:7];
- idu2exu_cmd_o.imm = {{27{instr[12]}}, instr[6:2]};
-`ifdef SCR1_RVE_EXT
- if (instr[11]) rve_illegal = 1'b1;
-`endif // SCR1_RVE_EXT
- end
- 3'b001 : begin
- // C.JAL
- idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_PC_IMM;
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_INC_PC;
- idu2exu_cmd_o.jump_req = 1'b1;
- idu2exu_cmd_o.rd_addr = SCR1_MPRF_RA_ADDR;
- idu2exu_cmd_o.imm = {{21{instr[12]}}, instr[8], instr[10:9], instr[6], instr[7], instr[2], instr[11], instr[5:3], 1'b0};
- end
- 3'b010 : begin
- // C.LI
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IMM;
- idu2exu_cmd_o.rd_addr = instr[11:7];
- idu2exu_cmd_o.imm = {{27{instr[12]}}, instr[6:2]};
-`ifdef SCR1_RVE_EXT
- if (instr[11]) rve_illegal = 1'b1;
-`endif // SCR1_RVE_EXT
- end
- 3'b011 : begin
- if (~|{instr[12], instr[6:2]}) rvc_illegal = 1'b1;
- if (instr[11:7] == SCR1_MPRF_SP_ADDR) begin
- // C.ADDI16SP
- idu2exu_use_rs1_o = 1'b1;
- idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_ADD;
- idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_IMM;
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IALU;
- idu2exu_cmd_o.rs1_addr = SCR1_MPRF_SP_ADDR;
- idu2exu_cmd_o.rd_addr = SCR1_MPRF_SP_ADDR;
- idu2exu_cmd_o.imm = {{23{instr[12]}}, instr[4:3], instr[5], instr[2], instr[6], 4'd0};
- end else begin
- // C.LUI
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IMM;
- idu2exu_cmd_o.rd_addr = instr[11:7];
- idu2exu_cmd_o.imm = {{15{instr[12]}}, instr[6:2], 12'd0};
-`ifdef SCR1_RVE_EXT
- if (instr[11]) rve_illegal = 1'b1;
-`endif // SCR1_RVE_EXT
- end
- end
- 3'b100 : begin
- idu2exu_cmd_o.rs1_addr = {2'b01, instr[9:7]};
- idu2exu_cmd_o.rd_addr = {2'b01, instr[9:7]};
- idu2exu_cmd_o.rs2_addr = {2'b01, instr[4:2]};
- idu2exu_use_rs1_o = 1'b1;
- idu2exu_use_rd_o = 1'b1;
- case (instr[11:10])
- 2'b00 : begin
- if (instr[12]) rvc_illegal = 1'b1;
- // C.SRLI
- idu2exu_use_imm_o = 1'b1;
- idu2exu_cmd_o.imm = {27'd0, instr[6:2]};
- idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SRL;
- idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_IMM;
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IALU;
- end
- 2'b01 : begin
- if (instr[12]) rvc_illegal = 1'b1;
- // C.SRAI
- idu2exu_use_imm_o = 1'b1;
- idu2exu_cmd_o.imm = {27'd0, instr[6:2]};
- idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SRA;
- idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_IMM;
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IALU;
- end
- 2'b10 : begin
- // C.ANDI
- idu2exu_use_imm_o = 1'b1;
- idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_AND;
- idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_IMM;
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IALU;
- idu2exu_cmd_o.imm = {{27{instr[12]}}, instr[6:2]};
- end
- 2'b11 : begin
- idu2exu_use_rs2_o = 1'b1;
- case ({instr[12], instr[6:5]})
- 3'b000 : begin
- // C.SUB
- idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SUB;
- idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_REG;
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IALU;
- end
- 3'b001 : begin
- // C.XOR
- idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_XOR;
- idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_REG;
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IALU;
- end
- 3'b010 : begin
- // C.OR
- idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_OR;
- idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_REG;
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IALU;
- end
- 3'b011 : begin
- // C.AND
- idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_AND;
- idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_REG;
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IALU;
- end
- default : begin
- rvc_illegal = 1'b1;
- end
- endcase // {instr[12], instr[6:5]}
- end
- endcase // instr[11:10]
- end // funct3 == 3'b100
- 3'b101 : begin
- // C.J
- idu2exu_use_imm_o = 1'b1;
- idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_PC_IMM;
- idu2exu_cmd_o.jump_req = 1'b1;
- idu2exu_cmd_o.imm = {{21{instr[12]}}, instr[8], instr[10:9], instr[6], instr[7], instr[2], instr[11], instr[5:3], 1'b0};
- end
- 3'b110 : begin
- // C.BEQZ
- idu2exu_use_rs1_o = 1'b1;
- idu2exu_use_rs2_o = 1'b1;
- idu2exu_use_imm_o = 1'b1;
- idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SUB_EQ;
- idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_REG;
- idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_PC_IMM;
- idu2exu_cmd_o.branch_req = 1'b1;
- idu2exu_cmd_o.rs1_addr = {2'b01, instr[9:7]};
- idu2exu_cmd_o.rs2_addr = SCR1_MPRF_ZERO_ADDR;
- idu2exu_cmd_o.imm = {{24{instr[12]}}, instr[6:5], instr[2], instr[11:10], instr[4:3], 1'b0};
- end
- 3'b111 : begin
- // C.BNEZ
- idu2exu_use_rs1_o = 1'b1;
- idu2exu_use_rs2_o = 1'b1;
- idu2exu_use_imm_o = 1'b1;
- idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SUB_NE;
- idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_REG;
- idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_PC_IMM;
- idu2exu_cmd_o.branch_req = 1'b1;
- idu2exu_cmd_o.rs1_addr = {2'b01, instr[9:7]};
- idu2exu_cmd_o.rs2_addr = SCR1_MPRF_ZERO_ADDR;
- idu2exu_cmd_o.imm = {{24{instr[12]}}, instr[6:5], instr[2], instr[11:10], instr[4:3], 1'b0};
- end
- endcase // funct3
- end // Quadrant 1
-
- // Quadrant 2
- SCR1_INSTR_RVC2 : begin
- idu2exu_cmd_o.instr_rvc = 1'b1;
- idu2exu_use_rs1_o = 1'b1;
- case (funct3)
- 3'b000 : begin
- if (instr[12]) rvc_illegal = 1'b1;
- // C.SLLI
- idu2exu_use_rd_o = 1'b1;
- idu2exu_use_imm_o = 1'b1;
- idu2exu_cmd_o.rs1_addr = instr[11:7];
- idu2exu_cmd_o.rd_addr = instr[11:7];
- idu2exu_cmd_o.imm = {27'd0, instr[6:2]};
- idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SLL;
- idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_IMM;
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IALU;
-`ifdef SCR1_RVE_EXT
- if (instr[11]) rve_illegal = 1'b1;
-`endif // SCR1_RVE_EXT
- end
- 3'b010 : begin
- if (~|instr[11:7]) rvc_illegal = 1'b1;
- // C.LWSP
- idu2exu_use_rd_o = 1'b1;
- idu2exu_use_imm_o = 1'b1;
- idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_REG_IMM;
- idu2exu_cmd_o.lsu_cmd = SCR1_LSU_CMD_LW;
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_LSU;
- idu2exu_cmd_o.rs1_addr = SCR1_MPRF_SP_ADDR;
- idu2exu_cmd_o.rd_addr = instr[11:7];
- idu2exu_cmd_o.imm = {24'd0, instr[3:2], instr[12], instr[6:4], 2'b00};
-`ifdef SCR1_RVE_EXT
- if (instr[11]) rve_illegal = 1'b1;
-`endif // SCR1_RVE_EXT
- end
- 3'b100 : begin
- if (~instr[12]) begin
- if (|instr[6:2]) begin
- // C.MV
- idu2exu_use_rs2_o = 1'b1;
- idu2exu_use_rd_o = 1'b1;
- idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_ADD;
- idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_REG;
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IALU;
- idu2exu_cmd_o.rs1_addr = SCR1_MPRF_ZERO_ADDR;
- idu2exu_cmd_o.rs2_addr = instr[6:2];
- idu2exu_cmd_o.rd_addr = instr[11:7];
-`ifdef SCR1_RVE_EXT
- if (instr[11]|instr[6]) rve_illegal = 1'b1;
-`endif // SCR1_RVE_EXT
- end else begin
- if (~|instr[11:7]) rvc_illegal = 1'b1;
- // C.JR
- idu2exu_use_imm_o = 1'b1;
- idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_REG_IMM;
- idu2exu_cmd_o.jump_req = 1'b1;
- idu2exu_cmd_o.rs1_addr = instr[11:7];
- idu2exu_cmd_o.imm = 0;
-`ifdef SCR1_RVE_EXT
- if (instr[11]) rve_illegal = 1'b1;
-`endif // SCR1_RVE_EXT
- end
- end else begin // instr[12] == 1
- if (~|instr[11:2]) begin
- // C.EBREAK
- idu2exu_cmd_o.exc_req = 1'b1;
- idu2exu_cmd_o.exc_code = SCR1_EXC_CODE_BREAKPOINT;
- end else if (~|instr[6:2]) begin
- // C.JALR
- idu2exu_use_rs1_o = 1'b1;
- idu2exu_use_rd_o = 1'b1;
- idu2exu_use_imm_o = 1'b1;
- idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_REG_IMM;
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_INC_PC;
- idu2exu_cmd_o.jump_req = 1'b1;
- idu2exu_cmd_o.rs1_addr = instr[11:7];
- idu2exu_cmd_o.rd_addr = SCR1_MPRF_RA_ADDR;
- idu2exu_cmd_o.imm = 0;
-`ifdef SCR1_RVE_EXT
- if (instr[11]) rve_illegal = 1'b1;
-`endif // SCR1_RVE_EXT
- end else begin
- // C.ADD
- idu2exu_use_rs1_o = 1'b1;
- idu2exu_use_rs2_o = 1'b1;
- idu2exu_use_rd_o = 1'b1;
- idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_ADD;
- idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_REG;
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IALU;
- idu2exu_cmd_o.rs1_addr = instr[11:7];
- idu2exu_cmd_o.rs2_addr = instr[6:2];
- idu2exu_cmd_o.rd_addr = instr[11:7];
-`ifdef SCR1_RVE_EXT
- if (instr[11]|instr[6]) rve_illegal = 1'b1;
-`endif // SCR1_RVE_EXT
- end
- end // instr[12] == 1
- end
- 3'b110 : begin
- // C.SWSP
- idu2exu_use_rs1_o = 1'b1;
- idu2exu_use_rs2_o = 1'b1;
- idu2exu_use_imm_o = 1'b1;
- idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_REG_IMM;
- idu2exu_cmd_o.lsu_cmd = SCR1_LSU_CMD_SW;
- idu2exu_cmd_o.rs1_addr = SCR1_MPRF_SP_ADDR;
- idu2exu_cmd_o.rs2_addr = instr[6:2];
- idu2exu_cmd_o.imm = {24'd0, instr[8:7], instr[12:9], 2'b00};
-`ifdef SCR1_RVE_EXT
- if (instr[6]) rve_illegal = 1'b1;
-`endif // SCR1_RVE_EXT
- end
- default : begin
- rvc_illegal = 1'b1;
- end
- endcase // funct3
- end // Quadrant 2
-
- default : begin
- end
-`else // SCR1_RVC_EXT
- default : begin
- idu2exu_cmd_o.instr_rvc = 1'b1;
- rvi_illegal = 1'b1;
- end
-`endif // SCR1_RVC_EXT
- endcase // instr_type
- end // no imem fault
-
- // At this point the instruction is fully decoded
- // given that no imem fault has happened
-
- // Check illegal instruction
- if (
- rvi_illegal
-`ifdef SCR1_RVC_EXT
- | rvc_illegal
-`endif
-`ifdef SCR1_RVE_EXT
- | rve_illegal
-`endif
- ) begin
- idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_NONE;
- idu2exu_cmd_o.lsu_cmd = SCR1_LSU_CMD_NONE;
- idu2exu_cmd_o.csr_cmd = SCR1_CSR_CMD_NONE;
- idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_NONE;
- idu2exu_cmd_o.jump_req = 1'b0;
- idu2exu_cmd_o.branch_req = 1'b0;
- idu2exu_cmd_o.mret_req = 1'b0;
- idu2exu_cmd_o.fencei_req = 1'b0;
- idu2exu_cmd_o.wfi_req = 1'b0;
-
- idu2exu_use_rs1_o = 1'b0;
- idu2exu_use_rs2_o = 1'b0;
- idu2exu_use_rd_o = 1'b0;
-
-`ifndef SCR1_MTVAL_ILLEGAL_INSTR_EN
- idu2exu_use_imm_o = 1'b0;
-`else // SCR1_MTVAL_ILLEGAL_INSTR_EN
- idu2exu_use_imm_o = 1'b1;
- idu2exu_cmd_o.imm = instr;
-`endif // SCR1_MTVAL_ILLEGAL_INSTR_EN
-
- idu2exu_cmd_o.exc_req = 1'b1;
- idu2exu_cmd_o.exc_code = SCR1_EXC_CODE_ILLEGAL_INSTR;
- end
-
-end // RV32I(MC) decode
-
-`ifdef SCR1_TRGT_SIMULATION
-//-------------------------------------------------------------------------------
-// Assertion
-//-------------------------------------------------------------------------------
-
-// X checks
-
-SCR1_SVA_IDU_XCHECK : assert property (
- @(negedge clk) disable iff (~rst_n)
- !$isunknown({ifu2idu_vd_i, exu2idu_rdy_i})
- ) else $error("IDU Error: unknown values");
-
-SCR1_SVA_IDU_XCHECK2 : assert property (
- @(negedge clk) disable iff (~rst_n)
- ifu2idu_vd_i |-> !$isunknown({ifu2idu_imem_err_i, (ifu2idu_imem_err_i ? 0 : ifu2idu_instr_i)})
- ) else $error("IDU Error: unknown values");
-
-// Behavior checks
-
-SCR1_SVA_IDU_IALU_CMD_RANGE : assert property (
- @(negedge clk) disable iff (~rst_n)
- (ifu2idu_vd_i & ~ifu2idu_imem_err_i) |->
- ((idu2exu_cmd_o.ialu_cmd >= SCR1_IALU_CMD_NONE) &
- (idu2exu_cmd_o.ialu_cmd <=
-`ifdef SCR1_RVM_EXT
- SCR1_IALU_CMD_REMU
-`else
- SCR1_IALU_CMD_SRA
-`endif // SCR1_RVM_EXT
- ))
- ) else $error("IDU Error: IALU_CMD out of range");
-
-`endif // SCR1_TRGT_SIMULATION
-
-endmodule : scr1_pipe_idu
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv
deleted file mode 100644
index 83e2ef1..0000000
--- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv
+++ /dev/null
@@ -1,846 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_pipe_ifu.sv>
-/// @brief Instruction Fetch Unit (IFU)
-///
-
-//------------------------------------------------------------------------------
- //
- // Functionality:
- // - Controls instruction fetching process:
- // - Fetches instructions either from IMEM or from Program Buffer, supporting
- // pending IMEM instructions handling
- // - Handles new PC misalignment and constructs the correct instruction (supports
- // RVI and RVC instructions)
- // - Either stores instructions in the instruction queue or bypasses to the
- // IDU if the corresponding option is used
- // - Flushes instruction queue if requested
- //
- // Structure:
- // - Instruction queue
- // - IFU FSM
- // - IFU <-> IMEM i/f
- // - IFU <-> IDU i/f
- // - IFU <-> HDU i/f
- //
-//------------------------------------------------------------------------------
-
-`include "scr1_memif.svh"
-`include "scr1_arch_description.svh"
-`ifdef SCR1_DBG_EN
-`include "scr1_hdu.svh"
-`endif // SCR1_DBG_EN
-
-module scr1_pipe_ifu
-(
- // Control signals
- input logic rst_n, // IFU reset
- input logic clk, // IFU clock
- input logic pipe2ifu_stop_fetch_i, // Stop instruction fetch
-
- // IFU <-> IMEM interface
- input logic imem2ifu_req_ack_i, // Instruction memory request acknowledgement
- output logic ifu2imem_req_o, // Instruction memory request
- output logic ifu2imem_cmd_o, // Instruction memory command (READ/WRITE)
- output logic [`SCR1_IMEM_AWIDTH-1:0] ifu2imem_addr_o, // Instruction memory address
- input logic [`SCR1_IMEM_DWIDTH-1:0] imem2ifu_rdata_i, // Instruction memory read data
- input logic [1:0] imem2ifu_resp_i, // Instruction memory response
-
- // IFU <-> EXU New PC interface
- input logic exu2ifu_pc_new_req_i, // New PC request (jumps, branches, traps etc)
- input logic [`SCR1_XLEN-1:0] exu2ifu_pc_new_i, // New PC
-
-`ifdef SCR1_DBG_EN
- // IFU <-> HDU Program Buffer interface
- input logic hdu2ifu_pbuf_fetch_i, // Fetch instructions provided by Program Buffer
- output logic ifu2hdu_pbuf_rdy_o, // Program Buffer Instruction i/f ready
- input logic hdu2ifu_pbuf_vd_i, // Program Buffer Instruction valid
- input logic hdu2ifu_pbuf_err_i, // Program Buffer Instruction i/f error
- input logic [SCR1_HDU_CORE_INSTR_WIDTH-1:0] hdu2ifu_pbuf_instr_i, // Program Buffer Instruction itself
-`endif // SCR1_DBG_EN
-
-`ifdef SCR1_CLKCTRL_EN
- output logic ifu2pipe_imem_txns_pnd_o, // There are pending imem transactions
-`endif // SCR1_CLKCTRL_EN
-
- // IFU <-> IDU interface
- input logic idu2ifu_rdy_i, // IDU ready for new data
- output logic [`SCR1_IMEM_DWIDTH-1:0] ifu2idu_instr_o, // IFU instruction
- output logic ifu2idu_imem_err_o, // Instruction access fault exception
- output logic ifu2idu_err_rvi_hi_o, // 1 - imem fault when trying to fetch second half of an unaligned RVI instruction
- output logic ifu2idu_vd_o // IFU request
-);
-
-//------------------------------------------------------------------------------
-// Local parameters declaration
-//------------------------------------------------------------------------------
-
-localparam SCR1_IFU_Q_SIZE_WORD = 2;
-localparam SCR1_IFU_Q_SIZE_HALF = SCR1_IFU_Q_SIZE_WORD * 2;
-localparam SCR1_TXN_CNT_W = 3;
-
-localparam SCR1_IFU_QUEUE_ADR_W = $clog2(SCR1_IFU_Q_SIZE_HALF);
-localparam SCR1_IFU_QUEUE_PTR_W = SCR1_IFU_QUEUE_ADR_W + 1;
-
-localparam SCR1_IFU_Q_FREE_H_W = $clog2(SCR1_IFU_Q_SIZE_HALF + 1);
-localparam SCR1_IFU_Q_FREE_W_W = $clog2(SCR1_IFU_Q_SIZE_WORD + 1);
-
-//------------------------------------------------------------------------------
-// Local types declaration
-//------------------------------------------------------------------------------
-
-//typedef enum logic {
-parameter SCR1_IFU_FSM_IDLE = 1'b0;
-parameter SCR1_IFU_FSM_FETCH = 1'b1;
-//} type_scr1_ifu_fsm_e;
-
-//typedef enum logic[1:0] {
-parameter SCR1_IFU_QUEUE_WR_NONE = 2'b00; // No write to queue
-parameter SCR1_IFU_QUEUE_WR_FULL = 2'b01; // Write 32 rdata bits to queue
-parameter SCR1_IFU_QUEUE_WR_HI = 2'b10; // Write 16 upper rdata bits to queue
-//} type_scr1_ifu_queue_wr_e;
-
-//typedef enum logic[1:0] {
-parameter SCR1_IFU_QUEUE_RD_NONE = 2'b00; // No queue read
-parameter SCR1_IFU_QUEUE_RD_HWORD = 2'b01; // Read halfword
-parameter SCR1_IFU_QUEUE_RD_WORD = 2'b10; // Read word
-//} type_scr1_ifu_queue_rd_e;
-
-`ifdef SCR1_NO_DEC_STAGE
-typedef enum logic[1:0] {
- SCR1_BYPASS_NONE, // No bypass
- SCR1_BYPASS_RVC, // Bypass RVC
- SCR1_BYPASS_RVI_RDATA_QUEUE, // Bypass RVI, rdata+queue
- SCR1_BYPASS_RVI_RDATA // Bypass RVI, rdata only
-} type_scr1_bypass_e;
-`endif // SCR1_NO_DEC_STAGE
-
-//typedef enum logic [2:0] {
- // SCR1_IFU_INSTR_<UPPER_16_BITS>_<LOWER_16_BITS>
-parameter SCR1_IFU_INSTR_NONE = 3'b000 ; // No valid instruction
-parameter SCR1_IFU_INSTR_RVI_HI_RVI_LO = 3'b001 ; // Full RV32I instruction
-parameter SCR1_IFU_INSTR_RVC_RVC = 3'b010 ;
-parameter SCR1_IFU_INSTR_RVI_LO_RVC = 3'b011 ;
-parameter SCR1_IFU_INSTR_RVC_RVI_HI = 3'b100 ;
-parameter SCR1_IFU_INSTR_RVI_LO_RVI_HI = 3'b101 ;
-parameter SCR1_IFU_INSTR_RVC_NV = 3'b110 ; // Instruction after unaligned new_pc
-parameter SCR1_IFU_INSTR_RVI_LO_NV = 3'b111 ; // Instruction after unaligned new_pc
-//} type_scr1_ifu_instr_e;
-
-//------------------------------------------------------------------------------
-// Local signals declaration
-//------------------------------------------------------------------------------
-
-// Instruction queue signals
-//------------------------------------------------------------------------------
-
-// New PC unaligned flag register
-logic new_pc_unaligned_ff;
-logic new_pc_unaligned_next;
-logic new_pc_unaligned_upd;
-
-// IMEM instruction type decoder
-logic instr_hi_is_rvi;
-logic instr_lo_is_rvi;
-logic [2:0] instr_type;
-
-// Register to store if the previous IMEM instruction had low part of RVI instruction
-// in its high part
-logic instr_hi_rvi_lo_ff;
-logic instr_hi_rvi_lo_next;
-
-// Queue read/write size decoders
-logic [1:0] q_rd_size;
-logic q_rd_vd;
-logic q_rd_none;
-logic q_rd_hword;
-logic [1:0] q_wr_size;
-logic q_wr_none;
-logic q_wr_full;
-
-// Write/read pointer registers
-logic [SCR1_IFU_QUEUE_PTR_W-1:0] q_rptr;
-logic [SCR1_IFU_QUEUE_PTR_W-1:0] q_rptr_next;
-logic q_rptr_upd;
-logic [SCR1_IFU_QUEUE_PTR_W-1:0] q_wptr;
-logic [SCR1_IFU_QUEUE_PTR_W-1:0] q_wptr_next;
-logic q_wptr_upd;
-
-// Instruction queue control signals
-logic q_wr_en;
-logic q_flush_req;
-
-// Queue data registers
-logic [`SCR1_IMEM_DWIDTH/2-1:0] q_data [SCR1_IFU_Q_SIZE_HALF];
-logic [`SCR1_IMEM_DWIDTH/2-1:0] q_data_head;
-logic [`SCR1_IMEM_DWIDTH/2-1:0] q_data_next;
-
-// Queue error flags registers
-logic q_err [SCR1_IFU_Q_SIZE_HALF];
-logic q_err_head;
-logic q_err_next;
-
-// Instruction queue status signals
-logic q_is_empty;
-logic q_has_free_slots;
-logic q_has_1_ocpd_hw;
-logic q_head_is_rvc;
-logic q_head_is_rvi;
-logic [SCR1_IFU_Q_FREE_H_W-1:0] q_ocpd_h;
-logic [SCR1_IFU_Q_FREE_H_W-1:0] q_free_h_next;
-logic [SCR1_IFU_Q_FREE_W_W-1:0] q_free_w_next;
-
-// IFU FSM signals
-//------------------------------------------------------------------------------
-
-// IFU FSM control signals
-logic ifu_fetch_req;
-logic ifu_stop_req;
-
-logic ifu_fsm_curr;
-logic ifu_fsm_next;
-logic ifu_fsm_fetch;
-
-// IMEM signals
-//------------------------------------------------------------------------------
-
-// IMEM response signals
-logic imem_resp_ok;
-logic imem_resp_er;
-logic imem_resp_er_discard_pnd;
-logic imem_resp_discard_req;
-logic imem_resp_received;
-logic imem_resp_vd;
-logic imem_handshake_done;
-
-logic [15:0] imem_rdata_lo;
-logic [31:16] imem_rdata_hi;
-
-// IMEM address signals
-logic imem_addr_upd;
-logic [`SCR1_XLEN-1:2] imem_addr_ff;
-logic [`SCR1_XLEN-1:2] imem_addr_next;
-
-// IMEM pending transactions counter
-logic imem_pnd_txns_cnt_upd;
-logic [SCR1_TXN_CNT_W-1:0] imem_pnd_txns_cnt;
-logic [SCR1_TXN_CNT_W-1:0] imem_pnd_txns_cnt_next;
-logic [SCR1_TXN_CNT_W-1:0] imem_vd_pnd_txns_cnt;
-logic imem_pnd_txns_q_full;
-
-// IMEM responses discard counter
-logic imem_resp_discard_cnt_upd;
-logic [SCR1_TXN_CNT_W-1:0] imem_resp_discard_cnt;
-logic [SCR1_TXN_CNT_W-1:0] imem_resp_discard_cnt_next;
-
-`ifdef SCR1_NEW_PC_REG
-logic new_pc_req_ff;
-`endif // SCR1_NEW_PC_REG
-
-// Instruction bypass signals
-`ifdef SCR1_NO_DEC_STAGE
-type_scr1_bypass_e instr_bypass_type;
-logic instr_bypass_vd;
-`endif // SCR1_NO_DEC_STAGE
-
-//------------------------------------------------------------------------------
-// Instruction queue
-//------------------------------------------------------------------------------
-//
- // Instruction queue consists of the following functional units:
- // - New PC unaligned flag register
- // - Instruction type decoder, including register to store if the previous
- // IMEM instruction had low part of RVI instruction in its high part
- // - Read/write size decoders
- // - Read/write pointer registers
- // - Data and error flag registers
- // - Status logic
-//
-
-// New PC unaligned flag register
-//------------------------------------------------------------------------------
-
-assign new_pc_unaligned_upd = exu2ifu_pc_new_req_i | imem_resp_vd;
-
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- new_pc_unaligned_ff <= 1'b0;
- end else if (new_pc_unaligned_upd) begin
- new_pc_unaligned_ff <= new_pc_unaligned_next;
- end
-end
-
-assign new_pc_unaligned_next = exu2ifu_pc_new_req_i ? exu2ifu_pc_new_i[1]
- : ~imem_resp_vd ? new_pc_unaligned_ff
- : 1'b0;
-
-// Instruction type decoder
-//------------------------------------------------------------------------------
-
-assign instr_hi_is_rvi = &imem2ifu_rdata_i[17:16];
-assign instr_lo_is_rvi = &imem2ifu_rdata_i[1:0];
-
-always_comb begin
- instr_type = SCR1_IFU_INSTR_NONE;
-
- if (imem_resp_ok & ~imem_resp_discard_req) begin
- if (new_pc_unaligned_ff) begin
- instr_type = instr_hi_is_rvi ? SCR1_IFU_INSTR_RVI_LO_NV
- : SCR1_IFU_INSTR_RVC_NV;
- end else begin // ~new_pc_unaligned_ff
- if (instr_hi_rvi_lo_ff) begin
- instr_type = instr_hi_is_rvi ? SCR1_IFU_INSTR_RVI_LO_RVI_HI
- : SCR1_IFU_INSTR_RVC_RVI_HI;
- end else begin // SCR1_OTHER
- casez ({instr_hi_is_rvi, instr_lo_is_rvi})
- 2'b?1 : instr_type = SCR1_IFU_INSTR_RVI_HI_RVI_LO;
- 2'b00 : instr_type = SCR1_IFU_INSTR_RVC_RVC;
- 2'b10 : instr_type = SCR1_IFU_INSTR_RVI_LO_RVC;
- endcase
- end
- end
- end
-end
-
-// Register to store if the previous IMEM instruction had low part of RVI
-// instruction in its high part
-//------------------------------------------------------------------------------
-
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- instr_hi_rvi_lo_ff <= 1'b0;
- end else begin
- if (exu2ifu_pc_new_req_i) begin
- instr_hi_rvi_lo_ff <= 1'b0;
- end else if (imem_resp_vd) begin
- instr_hi_rvi_lo_ff <= instr_hi_rvi_lo_next;
- end
- end
-end
-
-assign instr_hi_rvi_lo_next = (instr_type == SCR1_IFU_INSTR_RVI_LO_NV)
- | (instr_type == SCR1_IFU_INSTR_RVI_LO_RVI_HI)
- | (instr_type == SCR1_IFU_INSTR_RVI_LO_RVC);
-
-// Queue write/read size decoders
-//------------------------------------------------------------------------------
-
-// Queue read size decoder
-assign q_rd_vd = ~q_is_empty & ifu2idu_vd_o & idu2ifu_rdy_i;
-assign q_rd_hword = q_head_is_rvc | q_err_head
-`ifdef SCR1_NO_DEC_STAGE
- | (q_head_is_rvi & instr_bypass_vd)
-`endif // SCR1_NO_DEC_STAGE
- ;
-assign q_rd_size = ~q_rd_vd ? SCR1_IFU_QUEUE_RD_NONE
- : q_rd_hword ? SCR1_IFU_QUEUE_RD_HWORD
- : SCR1_IFU_QUEUE_RD_WORD;
-assign q_rd_none = (q_rd_size == SCR1_IFU_QUEUE_RD_NONE);
-
-// Queue write size decoder
-always_comb begin
- q_wr_size = SCR1_IFU_QUEUE_WR_NONE;
- if (~imem_resp_discard_req) begin
- if (imem_resp_ok) begin
-`ifdef SCR1_NO_DEC_STAGE
- case (instr_type)
- SCR1_IFU_INSTR_NONE : q_wr_size = SCR1_IFU_QUEUE_WR_NONE;
- SCR1_IFU_INSTR_RVI_LO_NV : q_wr_size = SCR1_IFU_QUEUE_WR_HI;
- SCR1_IFU_INSTR_RVC_NV : q_wr_size = (instr_bypass_vd & idu2ifu_rdy_i)
- ? SCR1_IFU_QUEUE_WR_NONE
- : SCR1_IFU_QUEUE_WR_HI;
- SCR1_IFU_INSTR_RVI_HI_RVI_LO: q_wr_size = (instr_bypass_vd & idu2ifu_rdy_i)
- ? SCR1_IFU_QUEUE_WR_NONE
- : SCR1_IFU_QUEUE_WR_FULL;
- SCR1_IFU_INSTR_RVC_RVC,
- SCR1_IFU_INSTR_RVI_LO_RVC,
- SCR1_IFU_INSTR_RVC_RVI_HI,
- SCR1_IFU_INSTR_RVI_LO_RVI_HI: q_wr_size = (instr_bypass_vd & idu2ifu_rdy_i)
- ? SCR1_IFU_QUEUE_WR_HI
- : SCR1_IFU_QUEUE_WR_FULL;
- endcase // instr_type
-`else // SCR1_NO_DEC_STAGE
- case (instr_type)
- SCR1_IFU_INSTR_NONE : q_wr_size = SCR1_IFU_QUEUE_WR_NONE;
- SCR1_IFU_INSTR_RVC_NV,
- SCR1_IFU_INSTR_RVI_LO_NV : q_wr_size = SCR1_IFU_QUEUE_WR_HI;
- default : q_wr_size = SCR1_IFU_QUEUE_WR_FULL;
- endcase // instr_type
-`endif // SCR1_NO_DEC_STAGE
- end else if (imem_resp_er) begin
- q_wr_size = SCR1_IFU_QUEUE_WR_FULL;
- end // imem_resp_er
- end // ~imem_resp_discard_req
-end
-
-assign q_wr_none = (q_wr_size == SCR1_IFU_QUEUE_WR_NONE);
-assign q_wr_full = (q_wr_size == SCR1_IFU_QUEUE_WR_FULL);
-
-// Write/read pointer registers
-//------------------------------------------------------------------------------
-
-assign q_flush_req = exu2ifu_pc_new_req_i | pipe2ifu_stop_fetch_i;
-
-// Queue write pointer register
-assign q_wptr_upd = q_flush_req | ~q_wr_none;
-
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- q_wptr <= '0;
- end else if (q_wptr_upd) begin
- q_wptr <= q_wptr_next;
- end
-end
-
-assign q_wptr_next = q_flush_req ? '0
- : ~q_wr_none ? q_wptr + (q_wr_full ? 2'd2 : 1'b1)
- : q_wptr;
-
-// Queue read pointer register
-assign q_rptr_upd = q_flush_req | ~q_rd_none;
-
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- q_rptr <= '0;
- end else if (q_rptr_upd) begin
- q_rptr <= q_rptr_next;
- end
-end
-
-assign q_rptr_next = q_flush_req ? '0
- : ~q_rd_none ? q_rptr + (q_rd_hword ? 1'b1 : 2'd2)
- : q_rptr;
-
-// Queue data and error flag registers
-//------------------------------------------------------------------------------
-
-assign imem_rdata_hi = imem2ifu_rdata_i[31:16];
-assign imem_rdata_lo = imem2ifu_rdata_i[15:0];
-
-assign q_wr_en = imem_resp_vd & ~q_flush_req;
-
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- `ifdef SCR1_MPRF_RST_EN // Two dimensional array init not allowed in YOSYS - cp.13
- q_data <= '{SCR1_IFU_Q_SIZE_HALF{'0}};
- q_err <= '{SCR1_IFU_Q_SIZE_HALF{1'b0}};
- `endif
- end else if (q_wr_en) begin
- case (q_wr_size)
- SCR1_IFU_QUEUE_WR_HI : begin
- q_data[SCR1_IFU_QUEUE_ADR_W'(q_wptr)] <= imem_rdata_hi;
- q_err [SCR1_IFU_QUEUE_ADR_W'(q_wptr)] <= imem_resp_er;
- end
- SCR1_IFU_QUEUE_WR_FULL : begin
- q_data[SCR1_IFU_QUEUE_ADR_W'(q_wptr)] <= imem_rdata_lo;
- q_err [SCR1_IFU_QUEUE_ADR_W'(q_wptr)] <= imem_resp_er;
- q_data[SCR1_IFU_QUEUE_ADR_W'(q_wptr + 1'b1)] <= imem_rdata_hi;
- q_err [SCR1_IFU_QUEUE_ADR_W'(q_wptr + 1'b1)] <= imem_resp_er;
- end
- endcase
- end
-end
-
-assign q_data_head = q_data [SCR1_IFU_QUEUE_ADR_W'(q_rptr)];
-assign q_data_next = q_data [SCR1_IFU_QUEUE_ADR_W'(q_rptr + 1'b1)];
-assign q_err_head = q_err [SCR1_IFU_QUEUE_ADR_W'(q_rptr)];
-assign q_err_next = q_err [SCR1_IFU_QUEUE_ADR_W'(q_rptr + 1'b1)];
-
-// Queue status logic
-//------------------------------------------------------------------------------
-
-assign q_ocpd_h = SCR1_IFU_Q_FREE_H_W'(q_wptr - q_rptr);
-assign q_free_h_next = SCR1_IFU_Q_FREE_H_W'(SCR1_IFU_Q_SIZE_HALF - (q_wptr - q_rptr_next));
-assign q_free_w_next = SCR1_IFU_Q_FREE_W_W'(q_free_h_next >> 1'b1);
-
-assign q_is_empty = (q_rptr == q_wptr);
-assign q_has_free_slots = (SCR1_TXN_CNT_W'(q_free_w_next) > imem_vd_pnd_txns_cnt);
-assign q_has_1_ocpd_hw = (q_ocpd_h == SCR1_IFU_Q_FREE_H_W'(1));
-
-assign q_head_is_rvi = &(q_data_head[1:0]);
-assign q_head_is_rvc = ~q_head_is_rvi;
-
-//------------------------------------------------------------------------------
-// IFU FSM
-//------------------------------------------------------------------------------
-
-// IFU FSM control signals
-assign ifu_fetch_req = exu2ifu_pc_new_req_i & ~pipe2ifu_stop_fetch_i;
-assign ifu_stop_req = pipe2ifu_stop_fetch_i
- | (imem_resp_er_discard_pnd & ~exu2ifu_pc_new_req_i);
-
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- ifu_fsm_curr <= SCR1_IFU_FSM_IDLE;
- end else begin
- ifu_fsm_curr <= ifu_fsm_next;
- end
-end
-
-always_comb begin
- case (ifu_fsm_curr)
- SCR1_IFU_FSM_IDLE : begin
- ifu_fsm_next = ifu_fetch_req ? SCR1_IFU_FSM_FETCH
- : SCR1_IFU_FSM_IDLE;
- end
- SCR1_IFU_FSM_FETCH : begin
- ifu_fsm_next = ifu_stop_req ? SCR1_IFU_FSM_IDLE
- : SCR1_IFU_FSM_FETCH;
- end
- endcase
-end
-
-assign ifu_fsm_fetch = (ifu_fsm_curr == SCR1_IFU_FSM_FETCH);
-
-//------------------------------------------------------------------------------
-// IFU <-> IMEM interface
-//------------------------------------------------------------------------------
-//
- // IFU <-> IMEM interface consists of the following functional units:
- // - IMEM response logic
- // - IMEM address register
- // - Pending IMEM transactions counter
- // - IMEM discard responses counter
- // - IFU <-> IMEM interface output signals
-//
-
-// IMEM response logic
-//------------------------------------------------------------------------------
-
-assign imem_resp_er = (imem2ifu_resp_i == SCR1_MEM_RESP_RDY_ER);
-assign imem_resp_ok = (imem2ifu_resp_i == SCR1_MEM_RESP_RDY_OK);
-assign imem_resp_received = imem_resp_ok | imem_resp_er;
-assign imem_resp_vd = imem_resp_received & ~imem_resp_discard_req;
-assign imem_resp_er_discard_pnd = imem_resp_er & ~imem_resp_discard_req;
-
-assign imem_handshake_done = ifu2imem_req_o & imem2ifu_req_ack_i;
-
-// IMEM address register
-//------------------------------------------------------------------------------
-
-assign imem_addr_upd = imem_handshake_done | exu2ifu_pc_new_req_i;
-
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- imem_addr_ff <= '0;
- end else if (imem_addr_upd) begin
- imem_addr_ff <= imem_addr_next;
- end
-end
-
-`ifndef SCR1_NEW_PC_REG
-assign imem_addr_next = exu2ifu_pc_new_req_i ? exu2ifu_pc_new_i[`SCR1_XLEN-1:2] + imem_handshake_done
- : &imem_addr_ff[5:2] ? imem_addr_ff + imem_handshake_done
- : {imem_addr_ff[`SCR1_XLEN-1:6], imem_addr_ff[5:2] + imem_handshake_done};
-`else // SCR1_NEW_PC_REG
-assign imem_addr_next = exu2ifu_pc_new_req_i ? exu2ifu_pc_new_i[`SCR1_XLEN-1:2]
- : &imem_addr_ff[5:2] ? imem_addr_ff + imem_handshake_done
- : {imem_addr_ff[`SCR1_XLEN-1:6], imem_addr_ff[5:2] + imem_handshake_done};
-`endif // SCR1_NEW_PC_REG
-
-// Pending IMEM transactions counter
-//------------------------------------------------------------------------------
-// Pending IMEM transactions occur if IFU request has been acknowledged, but
-// response comes in the next cycle or later
-
-assign imem_pnd_txns_cnt_upd = imem_handshake_done ^ imem_resp_received;
-
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- imem_pnd_txns_cnt <= '0;
- end else if (imem_pnd_txns_cnt_upd) begin
- imem_pnd_txns_cnt <= imem_pnd_txns_cnt_next;
- end
-end
-
-assign imem_pnd_txns_cnt_next = imem_pnd_txns_cnt + (imem_handshake_done - imem_resp_received);
-assign imem_pnd_txns_q_full = &imem_pnd_txns_cnt;
-
-// IMEM discard responses counter
-//------------------------------------------------------------------------------
-// IMEM instructions should be discarded in the following 2 cases:
-// 1. New PC is requested by jump, branch, mret or other instruction
-// 2. IMEM response was erroneous and not discarded
-//
-// In both cases the number of instructions to be discarded equals to the number
-// of pending instructions.
-// In the 1st case we don't need all the instructions that haven't been fetched
-// yet, since the PC has changed.
-// In the 2nd case, since the IMEM responce was erroneous there is no guarantee
-// that subsequent IMEM instructions would be valid.
-
-assign imem_resp_discard_cnt_upd = exu2ifu_pc_new_req_i | imem_resp_er
- | (imem_resp_ok & imem_resp_discard_req);
-
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- imem_resp_discard_cnt <= '0;
- end else if (imem_resp_discard_cnt_upd) begin
- imem_resp_discard_cnt <= imem_resp_discard_cnt_next;
- end
-end
-
-`ifndef SCR1_NEW_PC_REG
-assign imem_resp_discard_cnt_next = exu2ifu_pc_new_req_i ? imem_pnd_txns_cnt_next - imem_handshake_done
- : imem_resp_er_discard_pnd ? imem_pnd_txns_cnt_next
- : imem_resp_discard_cnt - 1'b1;
-`else // SCR1_NEW_PC_REG
-assign imem_resp_discard_cnt_next = exu2ifu_pc_new_req_i | imem_resp_er_discard_pnd
- ? imem_pnd_txns_cnt_next
- : imem_resp_discard_cnt - 1'b1;
-`endif // SCR1_NEW_PC_REG
-
-assign imem_vd_pnd_txns_cnt = imem_pnd_txns_cnt - imem_resp_discard_cnt;
-assign imem_resp_discard_req = |imem_resp_discard_cnt;
-
-// IFU <-> IMEM interface output signals
-//------------------------------------------------------------------------------
-
-`ifndef SCR1_NEW_PC_REG
-assign ifu2imem_req_o = (exu2ifu_pc_new_req_i & ~imem_pnd_txns_q_full & ~pipe2ifu_stop_fetch_i)
- | (ifu_fsm_fetch & ~imem_pnd_txns_q_full & q_has_free_slots);
-assign ifu2imem_addr_o = exu2ifu_pc_new_req_i
- ? {exu2ifu_pc_new_i[`SCR1_XLEN-1:2], 2'b00}
- : {imem_addr_ff, 2'b00};
-`else // SCR1_NEW_PC_REG
-assign ifu2imem_req_o = ifu_fsm_fetch & ~imem_pnd_txns_q_full & q_has_free_slots;
-assign ifu2imem_addr_o = {imem_addr_ff, 2'b00};
-`endif // SCR1_NEW_PC_REG
-
-assign ifu2imem_cmd_o = SCR1_MEM_CMD_RD;
-
-`ifdef SCR1_CLKCTRL_EN
-assign ifu2pipe_imem_txns_pnd_o = |imem_pnd_txns_cnt;
-`endif // SCR1_CLKCTRL_EN
-
-//------------------------------------------------------------------------------
-// IFU <-> IDU interface
-//------------------------------------------------------------------------------
-//
- // IFU <-> IDU interface consists of the following functional units:
- // - Instruction bypass type decoder
- // - IFU <-> IDU status signals
- // - Output instruction multiplexer
-//
-
-`ifdef SCR1_NO_DEC_STAGE
-
-// Instruction bypass type decoder
-//------------------------------------------------------------------------------
-
-assign instr_bypass_vd = (instr_bypass_type != SCR1_BYPASS_NONE);
-
-always_comb begin
- instr_bypass_type = SCR1_BYPASS_NONE;
-
- if (imem_resp_vd) begin
- if (q_is_empty) begin
- case (instr_type)
- SCR1_IFU_INSTR_RVC_NV,
- SCR1_IFU_INSTR_RVC_RVC,
- SCR1_IFU_INSTR_RVI_LO_RVC : begin
- instr_bypass_type = SCR1_BYPASS_RVC;
- end
- SCR1_IFU_INSTR_RVI_HI_RVI_LO : begin
- instr_bypass_type = SCR1_BYPASS_RVI_RDATA;
- end
- default : begin end
- endcase // instr_type
- end else if (q_has_1_ocpd_hw & q_head_is_rvi) begin
- if (instr_hi_rvi_lo_ff) begin
- instr_bypass_type = SCR1_BYPASS_RVI_RDATA_QUEUE;
- end
- end
- end // imem_resp_vd
-end
-
-// IFU <-> IDU interface status signals
-//------------------------------------------------------------------------------
-
-always_comb begin
- ifu2idu_vd_o = 1'b0;
- ifu2idu_imem_err_o = 1'b0;
- ifu2idu_err_rvi_hi_o = 1'b0;
-
- if (ifu_fsm_fetch | ~q_is_empty) begin
- if (instr_bypass_vd) begin
- ifu2idu_vd_o = 1'b1;
- ifu2idu_imem_err_o = (instr_bypass_type == SCR1_BYPASS_RVI_RDATA_QUEUE)
- ? (imem_resp_er | q_err_head)
- : imem_resp_er;
- ifu2idu_err_rvi_hi_o = (instr_bypass_type == SCR1_BYPASS_RVI_RDATA_QUEUE) & imem_resp_er;
- end else if (~q_is_empty) begin
- if (q_has_1_ocpd_hw) begin
- ifu2idu_vd_o = q_head_is_rvc | q_err_head;
- ifu2idu_imem_err_o = q_err_head;
- ifu2idu_err_rvi_hi_o = ~q_err_head & q_head_is_rvi & q_err_next;
- end else begin
- ifu2idu_vd_o = 1'b1;
- ifu2idu_imem_err_o = q_err_head ? 1'b1 : (q_head_is_rvi & q_err_next);
- end
- end // ~q_is_empty
- end
-`ifdef SCR1_DBG_EN
- if (hdu2ifu_pbuf_fetch_i) begin
- ifu2idu_vd_o = hdu2ifu_pbuf_vd_i;
- ifu2idu_imem_err_o = hdu2ifu_pbuf_err_i;
- end
-`endif // SCR1_DBG_EN
-end
-
-// Output instruction multiplexer
-//------------------------------------------------------------------------------
-
-always_comb begin
- case (instr_bypass_type)
- SCR1_BYPASS_RVC : begin
- ifu2idu_instr_o = `SCR1_IMEM_DWIDTH'(new_pc_unaligned_ff ? imem_rdata_hi
- : imem_rdata_lo);
- end
- SCR1_BYPASS_RVI_RDATA : begin
- ifu2idu_instr_o = imem2ifu_rdata_i;
- end
- SCR1_BYPASS_RVI_RDATA_QUEUE: begin
- ifu2idu_instr_o = {imem_rdata_lo, q_data_head};
- end
- default : begin
- ifu2idu_instr_o = `SCR1_IMEM_DWIDTH'(q_head_is_rvc ? q_data_head
- : {q_data_next, q_data_head});
- end
- endcase // instr_bypass_type
-`ifdef SCR1_DBG_EN
- if (hdu2ifu_pbuf_fetch_i) begin
- ifu2idu_instr_o = `SCR1_IMEM_DWIDTH'({'0, hdu2ifu_pbuf_instr_i});
- end
-`endif // SCR1_DBG_EN
-end
-
-`else // SCR1_NO_DEC_STAGE
-
-// IFU <-> IDU interface status signals
-//------------------------------------------------------------------------------
-
-always_comb begin
- ifu2idu_vd_o = 1'b0;
- ifu2idu_imem_err_o = 1'b0;
- ifu2idu_err_rvi_hi_o = 1'b0;
- if (~q_is_empty) begin
- if (q_has_1_ocpd_hw) begin
- ifu2idu_vd_o = q_head_is_rvc | q_err_head;
- ifu2idu_imem_err_o = q_err_head;
- end else begin
- ifu2idu_vd_o = 1'b1;
- ifu2idu_imem_err_o = q_err_head ? 1'b1 : (q_head_is_rvi & q_err_next);
- ifu2idu_err_rvi_hi_o = ~q_err_head & q_head_is_rvi & q_err_next;
- end
- end // ~q_is_empty
-`ifdef SCR1_DBG_EN
- if (hdu2ifu_pbuf_fetch_i) begin
- ifu2idu_vd_o = hdu2ifu_pbuf_vd_i;
- ifu2idu_imem_err_o = hdu2ifu_pbuf_err_i;
- end
-`endif // SCR1_DBG_EN
-end
-
-// Output instruction multiplexer
-//------------------------------------------------------------------------------
-
-always_comb begin
- ifu2idu_instr_o = q_head_is_rvc ? `SCR1_IMEM_DWIDTH'(q_data_head)
- : {q_data_next, q_data_head};
-`ifdef SCR1_DBG_EN
- if (hdu2ifu_pbuf_fetch_i) begin
- ifu2idu_instr_o = `SCR1_IMEM_DWIDTH'({'0, hdu2ifu_pbuf_instr_i});
- end
-`endif // SCR1_DBG_EN
-end
-
-`endif // SCR1_NO_DEC_STAGE
-
-`ifdef SCR1_DBG_EN
-assign ifu2hdu_pbuf_rdy_o = idu2ifu_rdy_i;
-`endif // SCR1_DBG_EN
-
-`ifdef SCR1_TRGT_SIMULATION
-
-//------------------------------------------------------------------------------
-// Assertions
-//------------------------------------------------------------------------------
-
-// X checks
-
-SCR1_SVA_IFU_XCHECK : assert property (
- @(negedge clk) disable iff (~rst_n)
- !$isunknown({imem2ifu_req_ack_i, idu2ifu_rdy_i, exu2ifu_pc_new_req_i})
- ) else $error("IFU Error: unknown values");
-
-SCR1_SVA_IFU_XCHECK_REQ : assert property (
- @(negedge clk) disable iff (~rst_n)
- ifu2imem_req_o |-> !$isunknown({ifu2imem_addr_o, ifu2imem_cmd_o})
- ) else $error("IFU Error: unknown {ifu2imem_addr_o, ifu2imem_cmd_o}");
-
-// Behavior checks
-`ifndef VERILATOR
-SCR1_SVA_IFU_DRC_UNDERFLOW : assert property (
- @(negedge clk) disable iff (~rst_n)
- ~imem_resp_discard_req |=> ~(imem_resp_discard_cnt == SCR1_TXN_CNT_W'('1))
- ) else $error("IFU Error: imem_resp_discard_cnt underflow");
-`endif // VERILATOR
-SCR1_SVA_IFU_DRC_RANGE : assert property (
- @(negedge clk) disable iff (~rst_n)
- (imem_resp_discard_cnt >= 0) & (imem_resp_discard_cnt <= imem_pnd_txns_cnt)
- ) else $error("IFU Error: imem_resp_discard_cnt out of range");
-
-SCR1_SVA_IFU_QUEUE_OVF : assert property (
- @(negedge clk) disable iff (~rst_n)
- (q_ocpd_h >= SCR1_IFU_Q_FREE_H_W'(SCR1_IFU_Q_SIZE_HALF-1)) |->
- ((q_ocpd_h == SCR1_IFU_Q_FREE_H_W'(SCR1_IFU_Q_SIZE_HALF-1)) ? (q_wr_size != SCR1_IFU_QUEUE_WR_FULL)
- : (q_wr_size == SCR1_IFU_QUEUE_WR_NONE))
- ) else $error("IFU Error: queue overflow");
-
-`ifndef VERILATOR
-SCR1_SVA_IFU_IMEM_ERR_BEH : assert property (
- @(negedge clk) disable iff (~rst_n)
- (imem_resp_er & ~imem_resp_discard_req & ~exu2ifu_pc_new_req_i) |=>
- (ifu_fsm_curr == SCR1_IFU_FSM_IDLE) & (imem_resp_discard_cnt == imem_pnd_txns_cnt)
- ) else $error("IFU Error: incorrect behavior after memory error");
-
-SCR1_SVA_IFU_NEW_PC_REQ_BEH : assert property (
- @(negedge clk) disable iff (~rst_n)
- exu2ifu_pc_new_req_i |=> q_is_empty
- ) else $error("IFU Error: incorrect behavior after exu2ifu_pc_new_req_i");
-`endif // VERILATOR
-SCR1_SVA_IFU_IMEM_ADDR_ALIGNED : assert property (
- @(negedge clk) disable iff (~rst_n)
- ifu2imem_req_o |-> ~|ifu2imem_addr_o[1:0]
- ) else $error("IFU Error: unaligned IMEM access");
-
-`ifndef VERILATOR
-SCR1_SVA_IFU_STOP_FETCH : assert property (
- @(negedge clk) disable iff (~rst_n)
- pipe2ifu_stop_fetch_i |=> (ifu_fsm_curr == SCR1_IFU_FSM_IDLE)
- ) else $error("IFU Error: fetch not stopped");
-`endif // VERILATOR
-SCR1_SVA_IFU_IMEM_FAULT_RVI_HI : assert property (
- @(negedge clk) disable iff (~rst_n)
- ifu2idu_err_rvi_hi_o |-> ifu2idu_imem_err_o
- ) else $error("IFU Error: ifu2idu_imem_err_o == 0");
-
-`endif // SCR1_TRGT_SIMULATION
-
-endmodule : scr1_pipe_ifu
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv
deleted file mode 100644
index e9f4574..0000000
--- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv
+++ /dev/null
@@ -1,370 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_pipe_lsu.sv>
-/// @brief Load/Store Unit (LSU)
-///
-
-//------------------------------------------------------------------------------
- //
- // Functionality:
- // - Performs load and store operations in Data Memory
- // - Generates DMEM address misalign and access fault exceptions
- // - Passes DMEM operations information to TDU and generates LSU breakpoint exception
- //
- // Structure:
- // - FSM
- // - Exceptions logic
- // - LSU <-> EXU interface
- // - LSU <-> DMEM interface
- // - LSU <-> TDU interface
- //
-//------------------------------------------------------------------------------
-
-`include "scr1_arch_description.svh"
-`include "scr1_arch_types.svh"
-`include "scr1_memif.svh"
-`include "scr1_riscv_isa_decoding.svh"
-`ifdef SCR1_TDU_EN
-`include "scr1_tdu.svh"
-`endif // SCR1_TDU_EN
-
-module scr1_pipe_lsu (
- // Common
- input logic rst_n, // LSU reset
- input logic clk, // LSU clock
-
- // LSU <-> EXU interface
- input logic exu2lsu_req_i, // Request to LSU
- input type_scr1_lsu_cmd_sel_e exu2lsu_cmd_i, // LSU command
- input logic [`SCR1_XLEN-1:0] exu2lsu_addr_i, // Address of DMEM
- input logic [`SCR1_XLEN-1:0] exu2lsu_sdata_i, // Data for store
- output logic lsu2exu_rdy_o, // LSU received DMEM response
- output logic [`SCR1_XLEN-1:0] lsu2exu_ldata_o, // Load data
- output logic lsu2exu_exc_o, // Exception from LSU
- output type_scr1_exc_code_e lsu2exu_exc_code_o, // Exception code
-
-`ifdef SCR1_TDU_EN
- // LSU <-> TDU interface
- output type_scr1_brkm_lsu_mon_s lsu2tdu_dmon_o, // Data address stream monitoring
- input logic tdu2lsu_ibrkpt_exc_req_i, // Instruction BP exception request
- input logic tdu2lsu_dbrkpt_exc_req_i, // Data BP exception request
-`endif // SCR1_TDU_EN
-
- // LSU <-> DMEM interface
- output logic lsu2dmem_req_o, // Data memory request
- output logic lsu2dmem_cmd_o, // Data memory command (READ/WRITE)
- output logic [1:0] lsu2dmem_width_o, // Data memory data width
- output logic [`SCR1_DMEM_AWIDTH-1:0] lsu2dmem_addr_o, // Data memory address
- output logic [`SCR1_DMEM_DWIDTH-1:0] lsu2dmem_wdata_o, // Data memory write data
- input logic dmem2lsu_req_ack_i, // Data memory request acknowledge
- input logic [`SCR1_DMEM_DWIDTH-1:0] dmem2lsu_rdata_i, // Data memory read data
- input logic [1:0] dmem2lsu_resp_i // Data memory response
-);
-
-//------------------------------------------------------------------------------
-// Local types declaration
-//------------------------------------------------------------------------------
-
-//typedef enum logic {
-parameter SCR1_LSU_FSM_IDLE = 1'b0;
-parameter SCR1_LSU_FSM_BUSY = 1'b1;
-//} type_scr1_lsu_fsm_e;
-
-//------------------------------------------------------------------------------
-// Local signals declaration
-//------------------------------------------------------------------------------
-
-// LSU FSM signals
-logic lsu_fsm_curr; // LSU FSM current state
-logic lsu_fsm_next; // LSU FSM next state
-logic lsu_fsm_idle; // LSU FSM is in IDLE state
-
-// LSU Command register signals
-logic lsu_cmd_upd; // LSU Command register update
-type_scr1_lsu_cmd_sel_e lsu_cmd_ff; // LSU Command register value
-logic lsu_cmd_ff_load; // Registered LSU Command is load
-logic lsu_cmd_ff_store; // Registered LSU Command is store
-
-// DMEM command and width flags
-logic dmem_cmd_load; // DMEM command is load
-logic dmem_cmd_store; // DMEM Command is store
-logic dmem_wdth_word; // DMEM data width is WORD
-logic dmem_wdth_hword; // DMEM data width is HALFWORD
-logic dmem_wdth_byte; // DMEM data width is BYTE
-
-// DMEM response and request control signals
-logic dmem_resp_ok; // DMEM response is OK
-logic dmem_resp_er; // DMEM response is erroneous
-logic dmem_resp_received; // DMEM response is received
-logic dmem_req_vd; // DMEM request is valid (req_ack received)
-
-// Exceptions signals
-logic lsu_exc_req; // LSU exception request
-logic dmem_addr_mslgn; // DMEM address is misaligned
-logic dmem_addr_mslgn_l; // DMEM load address is misaligned
-logic dmem_addr_mslgn_s; // DMEM store address is misaligned
-`ifdef SCR1_TDU_EN
-logic lsu_exc_hwbrk; // LSU hardware breakpoint exception
-`endif // SCR1_TDU_EN
-
-//------------------------------------------------------------------------------
-// Control logic
-//------------------------------------------------------------------------------
-
-// DMEM response and request control signals
-assign dmem_resp_ok = (dmem2lsu_resp_i == SCR1_MEM_RESP_RDY_OK);
-assign dmem_resp_er = (dmem2lsu_resp_i == SCR1_MEM_RESP_RDY_ER);
-assign dmem_resp_received = dmem_resp_ok | dmem_resp_er;
-assign dmem_req_vd = exu2lsu_req_i & dmem2lsu_req_ack_i & ~lsu_exc_req;
-
-// LSU load and store command flags
-assign dmem_cmd_load = (exu2lsu_cmd_i == SCR1_LSU_CMD_LB )
- | (exu2lsu_cmd_i == SCR1_LSU_CMD_LBU)
- | (exu2lsu_cmd_i == SCR1_LSU_CMD_LH )
- | (exu2lsu_cmd_i == SCR1_LSU_CMD_LHU)
- | (exu2lsu_cmd_i == SCR1_LSU_CMD_LW );
-assign dmem_cmd_store = (exu2lsu_cmd_i == SCR1_LSU_CMD_SB )
- | (exu2lsu_cmd_i == SCR1_LSU_CMD_SH )
- | (exu2lsu_cmd_i == SCR1_LSU_CMD_SW );
-
-// LSU data width flags
-assign dmem_wdth_word = (exu2lsu_cmd_i == SCR1_LSU_CMD_LW )
- | (exu2lsu_cmd_i == SCR1_LSU_CMD_SW );
-assign dmem_wdth_hword = (exu2lsu_cmd_i == SCR1_LSU_CMD_LH )
- | (exu2lsu_cmd_i == SCR1_LSU_CMD_LHU)
- | (exu2lsu_cmd_i == SCR1_LSU_CMD_SH );
-assign dmem_wdth_byte = (exu2lsu_cmd_i == SCR1_LSU_CMD_LB )
- | (exu2lsu_cmd_i == SCR1_LSU_CMD_LBU)
- | (exu2lsu_cmd_i == SCR1_LSU_CMD_SB );
-
-// LSU command register
-assign lsu_cmd_upd = lsu_fsm_idle & dmem_req_vd;
-
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- lsu_cmd_ff <= SCR1_LSU_CMD_NONE;
- end else if (lsu_cmd_upd) begin
- lsu_cmd_ff <= exu2lsu_cmd_i;
- end
-end
-
-// LSU registered load and store command flags
-assign lsu_cmd_ff_load = (lsu_cmd_ff == SCR1_LSU_CMD_LB )
- | (lsu_cmd_ff == SCR1_LSU_CMD_LBU)
- | (lsu_cmd_ff == SCR1_LSU_CMD_LH )
- | (lsu_cmd_ff == SCR1_LSU_CMD_LHU)
- | (lsu_cmd_ff == SCR1_LSU_CMD_LW );
-assign lsu_cmd_ff_store = (lsu_cmd_ff == SCR1_LSU_CMD_SB )
- | (lsu_cmd_ff == SCR1_LSU_CMD_SH )
- | (lsu_cmd_ff == SCR1_LSU_CMD_SW );
-
-//------------------------------------------------------------------------------
-// LSU FSM
-//------------------------------------------------------------------------------
- //
- // LSU FSM is used to control the LSU <-> DMEM interface
- //
-//
-
-// Updating LSU FSM state
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- lsu_fsm_curr <= SCR1_LSU_FSM_IDLE;
- end else begin
- lsu_fsm_curr <= lsu_fsm_next;
- end
-end
-
-// LSU FSM next state logic
-always_comb begin
- case (lsu_fsm_curr)
- SCR1_LSU_FSM_IDLE: begin
- lsu_fsm_next = dmem_req_vd ? SCR1_LSU_FSM_BUSY
- : SCR1_LSU_FSM_IDLE;
- end
- SCR1_LSU_FSM_BUSY: begin
- lsu_fsm_next = dmem_resp_received ? SCR1_LSU_FSM_IDLE
- : SCR1_LSU_FSM_BUSY;
- end
- endcase
-end
-
-assign lsu_fsm_idle = (lsu_fsm_curr == SCR1_LSU_FSM_IDLE);
-
-//------------------------------------------------------------------------------
-// Exceptions logic
-//------------------------------------------------------------------------------
- //
- // The following types of exceptions are supported:
- // - Load address misalign
- // - Load access fault
- // - Store address misalign
- // - Store access fault
- // - LSU breakpoint exception
-//
-
-// DMEM addr misalign logic
-assign dmem_addr_mslgn = exu2lsu_req_i & ( (dmem_wdth_hword & exu2lsu_addr_i[0])
- | (dmem_wdth_word & |exu2lsu_addr_i[1:0]));
-assign dmem_addr_mslgn_l = dmem_addr_mslgn & dmem_cmd_load;
-assign dmem_addr_mslgn_s = dmem_addr_mslgn & dmem_cmd_store;
-
-// Exception code logic
-always_comb begin
- case (1'b1)
- dmem_resp_er : if(lsu_cmd_ff_load)
- lsu2exu_exc_code_o = SCR1_EXC_CODE_LD_ACCESS_FAULT;
- else if(lsu_cmd_ff_store)
- lsu2exu_exc_code_o = SCR1_EXC_CODE_ST_ACCESS_FAULT;
- else
- lsu2exu_exc_code_o = SCR1_EXC_CODE_INSTR_MISALIGN;
-`ifdef SCR1_TDU_EN
- lsu_exc_hwbrk : lsu2exu_exc_code_o = SCR1_EXC_CODE_BREAKPOINT;
-`endif // SCR1_TDU_EN
- dmem_addr_mslgn_l: lsu2exu_exc_code_o = SCR1_EXC_CODE_LD_ADDR_MISALIGN;
- dmem_addr_mslgn_s: lsu2exu_exc_code_o = SCR1_EXC_CODE_ST_ADDR_MISALIGN;
- default : lsu2exu_exc_code_o = SCR1_EXC_CODE_INSTR_MISALIGN;
- endcase // 1'b1
-end
-
-assign lsu_exc_req = dmem_addr_mslgn_l | dmem_addr_mslgn_s
-`ifdef SCR1_TDU_EN
- | lsu_exc_hwbrk
-`endif // SCR1_TDU_EN
-;
-
-//------------------------------------------------------------------------------
-// LSU <-> EXU interface
-//------------------------------------------------------------------------------
-
-assign lsu2exu_rdy_o = dmem_resp_received;
-assign lsu2exu_exc_o = dmem_resp_er | lsu_exc_req;
-
-// Sign- or zero-extending data received from DMEM
-always_comb begin
- case (lsu_cmd_ff)
- SCR1_LSU_CMD_LH : lsu2exu_ldata_o = {{16{dmem2lsu_rdata_i[15]}}, dmem2lsu_rdata_i[15:0]};
- SCR1_LSU_CMD_LHU: lsu2exu_ldata_o = { 16'b0, dmem2lsu_rdata_i[15:0]};
- SCR1_LSU_CMD_LB : lsu2exu_ldata_o = {{24{dmem2lsu_rdata_i[7]}}, dmem2lsu_rdata_i[7:0]};
- SCR1_LSU_CMD_LBU: lsu2exu_ldata_o = { 24'b0, dmem2lsu_rdata_i[7:0]};
- default : lsu2exu_ldata_o = dmem2lsu_rdata_i;
- endcase // lsu_cmd_ff
-end
-
-//------------------------------------------------------------------------------
-// LSU <-> DMEM interface
-//------------------------------------------------------------------------------
-
-assign lsu2dmem_req_o = exu2lsu_req_i & ~lsu_exc_req & lsu_fsm_idle;
-assign lsu2dmem_addr_o = exu2lsu_addr_i;
-assign lsu2dmem_wdata_o = exu2lsu_sdata_i;
-assign lsu2dmem_cmd_o = dmem_cmd_store ? SCR1_MEM_CMD_WR : SCR1_MEM_CMD_RD;
-assign lsu2dmem_width_o = dmem_wdth_byte ? SCR1_MEM_WIDTH_BYTE
- : dmem_wdth_hword ? SCR1_MEM_WIDTH_HWORD
- : SCR1_MEM_WIDTH_WORD;
-
-`ifdef SCR1_TDU_EN
-//------------------------------------------------------------------------------
-// LSU <-> TDU interface
-//------------------------------------------------------------------------------
-
-assign lsu2tdu_dmon_o.vd = exu2lsu_req_i & lsu_fsm_idle & ~tdu2lsu_ibrkpt_exc_req_i;
-assign lsu2tdu_dmon_o.addr = exu2lsu_addr_i;
-assign lsu2tdu_dmon_o.load = dmem_cmd_load;
-assign lsu2tdu_dmon_o.store = dmem_cmd_store;
-
-assign lsu_exc_hwbrk = (exu2lsu_req_i & tdu2lsu_ibrkpt_exc_req_i)
- | tdu2lsu_dbrkpt_exc_req_i;
-
-`endif // SCR1_TDU_EN
-
-`ifdef SCR1_TRGT_SIMULATION
-//------------------------------------------------------------------------------
-// Assertions
-//------------------------------------------------------------------------------
-
-// X checks
-
-SCR1_SVA_LSU_XCHECK_CTRL : assert property (
- @(negedge clk) disable iff (~rst_n)
- !$isunknown({exu2lsu_req_i, lsu_fsm_curr
-`ifdef SCR1_TDU_EN
- , tdu2lsu_ibrkpt_exc_req_i, tdu2lsu_dbrkpt_exc_req_i
-`endif // SCR1_TDU_EN
- })
- ) else $error("LSU Error: unknown control value");
-
-SCR1_SVA_LSU_XCHECK_CMD : assert property (
- @(negedge clk) disable iff (~rst_n)
- exu2lsu_req_i |-> !$isunknown({exu2lsu_cmd_i, exu2lsu_addr_i})
- ) else $error("LSU Error: undefined CMD or address");
-
-SCR1_SVA_LSU_XCHECK_SDATA : assert property (
- @(negedge clk) disable iff (~rst_n)
- (exu2lsu_req_i & (lsu2dmem_cmd_o == SCR1_MEM_CMD_WR)) |-> !$isunknown({exu2lsu_sdata_i})
- ) else $error("LSU Error: undefined store data");
-
-SCR1_SVA_LSU_XCHECK_EXC : assert property (
- @(negedge clk) disable iff (~rst_n)
- lsu2exu_exc_o |-> !$isunknown(lsu2exu_exc_code_o)
- ) else $error("LSU Error: exception code undefined");
-
-SCR1_SVA_LSU_IMEM_CTRL : assert property (
- @(negedge clk) disable iff (~rst_n)
- lsu2dmem_req_o |-> !$isunknown({lsu2dmem_cmd_o, lsu2dmem_width_o, lsu2dmem_addr_o})
- ) else $error("LSU Error: undefined dmem control");
-
-SCR1_SVA_LSU_IMEM_ACK : assert property (
- @(negedge clk) disable iff (~rst_n)
- lsu2dmem_req_o |-> !$isunknown(dmem2lsu_req_ack_i)
- ) else $error("LSU Error: undefined dmem ack");
-
-SCR1_SVA_LSU_IMEM_WDATA : assert property (
- @(negedge clk) disable iff (~rst_n)
- lsu2dmem_req_o & (lsu2dmem_cmd_o == SCR1_MEM_CMD_WR)
- |-> !$isunknown(lsu2dmem_wdata_o[8:0])
- ) else $error("LSU Error: undefined dmem wdata");
-
-// Behavior checks
-
-SCR1_SVA_LSU_EXC_ONEHOT : assert property (
- @(negedge clk) disable iff (~rst_n)
- $onehot0({dmem_resp_er, dmem_addr_mslgn_l, dmem_addr_mslgn_s})
- ) else $error("LSU Error: more than one exception at a time");
-
-SCR1_SVA_LSU_UNEXPECTED_DMEM_RESP : assert property (
- @(negedge clk) disable iff (~rst_n)
- lsu_fsm_idle |-> ~dmem_resp_received
- ) else $error("LSU Error: not expecting memory response");
-
-SCR1_SVA_LSU_REQ_EXC : assert property (
- @(negedge clk) disable iff (~rst_n)
- lsu2exu_exc_o |-> exu2lsu_req_i
- ) else $error("LSU Error: impossible exception");
-
-`ifdef SCR1_TDU_EN
-
-SCR1_COV_LSU_MISALIGN_BRKPT : cover property (
- @(negedge clk) disable iff (~rst_n)
- (dmem_addr_mslgn_l | dmem_addr_mslgn_s) & lsu_exc_hwbrk
-);
-`endif // SCR1_TDU_EN
-
-`endif // SCR1_TRGT_SIMULATION
-
-endmodule : scr1_pipe_lsu
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv
deleted file mode 100644
index 3b7f493..0000000
--- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv
+++ /dev/null
@@ -1,240 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details
-/// @file <scr1_pipe_mprf.sv>
-/// @brief Multi Port Register File (MPRF)
-///
-/// Version 1.0 - Dinesh A - Project: yifive
-/// added additional stage FF to break timing path
-/// additional define SCRC1_MPRF_STAGE added
-//////////////////////////////////////////////////////////////////////////////
-`include "scr1_arch_description.svh"
-`include "scr1_arch_types.svh"
-
-module scr1_pipe_mprf (
- // Common
-`ifdef SCR1_MPRF_RST_EN
- input logic rst_n, // MPRF reset
-`endif // SCR1_MPRF_RST_EN
- input logic clk, // MPRF clock
-
- // EXU <-> MPRF interface
- input logic [`SCR1_MPRF_AWIDTH-1:0] exu2mprf_rs1_addr_i, // MPRF rs1 read address
- output logic [`SCR1_XLEN-1:0] mprf2exu_rs1_data_o, // MPRF rs1 read data
- input logic [`SCR1_MPRF_AWIDTH-1:0] exu2mprf_rs2_addr_i, // MPRF rs2 read address
- output logic [`SCR1_XLEN-1:0] mprf2exu_rs2_data_o, // MPRF rs2 read data
- input logic exu2mprf_w_req_i, // MPRF write request
- input logic [`SCR1_MPRF_AWIDTH-1:0] exu2mprf_rd_addr_i, // MPRF rd write address
- input logic [`SCR1_XLEN-1:0] exu2mprf_rd_data_i // MPRF rd write data
-);
-
-//-------------------------------------------------------------------------------
-// Local types declaration
-//-------------------------------------------------------------------------------
-
-logic wr_req_vd;
-
-logic rs1_addr_vd;
-logic rs2_addr_vd;
-
-`ifdef SCRC1_MPRF_STAGE
-logic rs1_addr_vd_ff;
-logic rs2_addr_vd_ff;
-
-logic rs1_new_data_req;
-logic rs2_new_data_req;
-logic rs1_new_data_req_ff;
-logic rs2_new_data_req_ff;
-logic read_new_data_req;
-
-logic [`SCR1_XLEN-1:0] rd_data_ff;
-
-logic [`SCR1_XLEN-1:0] rs1_data_ff;
-logic [`SCR1_XLEN-1:0] rs2_data_ff;
-
-
-`endif
-
-`ifdef SCR1_MPRF_RAM
-logic rs1_addr_vd_ff;
-logic rs2_addr_vd_ff;
-
-logic rs1_new_data_req;
-logic rs2_new_data_req;
-logic rs1_new_data_req_ff;
-logic rs2_new_data_req_ff;
-logic read_new_data_req;
-
-logic [`SCR1_XLEN-1:0] rd_data_ff;
-
-logic [`SCR1_XLEN-1:0] rs1_data_ff;
-logic [`SCR1_XLEN-1:0] rs2_data_ff;
-
-// when using RAM, 2 memories are needed because 3 simultaneous independent
-// write/read operations can occur
- `ifdef SCR1_TRGT_FPGA_INTEL_MAX10
-(* ramstyle = "M9K" *) logic [`SCR1_XLEN-1:0] mprf_int [1:`SCR1_MPRF_SIZE-1];
-(* ramstyle = "M9K" *) logic [`SCR1_XLEN-1:0] mprf_int2 [1:`SCR1_MPRF_SIZE-1];
- `elsif SCR1_TRGT_FPGA_INTEL_ARRIAV
-(* ramstyle = "M10K" *) logic [`SCR1_XLEN-1:0] mprf_int [1:`SCR1_MPRF_SIZE-1];
-(* ramstyle = "M10K" *) logic [`SCR1_XLEN-1:0] mprf_int2 [1:`SCR1_MPRF_SIZE-1];
- `else
-logic [`SCR1_XLEN-1:0] mprf_int [1:`SCR1_MPRF_SIZE-1];
-logic [`SCR1_XLEN-1:0] mprf_int2 [1:`SCR1_MPRF_SIZE-1];
- `endif
-`else // distributed logic implementation
-logic [`SCR1_XLEN-1:0] mprf_int [1:`SCR1_MPRF_SIZE-1];
-`endif
-
-//------------------------------------------------------------------------------
-// MPRF control logic
-//------------------------------------------------------------------------------
-
-// control signals common for distributed logic and RAM implementations
-assign rs1_addr_vd = |exu2mprf_rs1_addr_i;
-assign rs2_addr_vd = |exu2mprf_rs2_addr_i;
-
-assign wr_req_vd = exu2mprf_w_req_i & |exu2mprf_rd_addr_i;
-
-// RAM implementation specific control signals
-`ifdef SCR1_MPRF_RAM
-assign rs1_new_data_req = wr_req_vd & ( exu2mprf_rs1_addr_i == exu2mprf_rd_addr_i );
-assign rs2_new_data_req = wr_req_vd & ( exu2mprf_rs2_addr_i == exu2mprf_rd_addr_i );
-assign read_new_data_req = rs1_new_data_req | rs2_new_data_req;
-
-always_ff @( posedge clk ) begin
- rs1_addr_vd_ff <= rs1_addr_vd;
- rs2_addr_vd_ff <= rs2_addr_vd;
- rs1_new_data_req_ff <= rs1_new_data_req;
- rs2_new_data_req_ff <= rs2_new_data_req;
-end
-`endif // SCR1_MPRF_RAM
-
-`ifdef SCR1_MPRF_RAM
-//-------------------------------------------------------------------------------
-// RAM implementation
-//-------------------------------------------------------------------------------
-
-// RAM is implemented with 2 simple dual-port memories with sync read operation;
-// logic for "write-first" RDW behavior is implemented externally to the embedded
-// memory blocks
-
-// bypass new wr_data to the read output if write/read collision occurs
-assign mprf2exu_rs1_data_o = ( rs1_new_data_req_ff ) ? rd_data_ff
- : (( rs1_addr_vd_ff ) ? rs1_data_ff
- : '0 );
-
-assign mprf2exu_rs2_data_o = ( rs2_new_data_req_ff ) ? rd_data_ff
- : (( rs2_addr_vd_ff ) ? rs2_data_ff
- : '0 );
-
-always_ff @( posedge clk ) begin
- if ( read_new_data_req ) begin
- rd_data_ff <= exu2mprf_rd_data_i;
- end
-end
-
-// synchronous read operation
-always_ff @( posedge clk ) begin
- rs1_data_ff <= mprf_int[exu2mprf_rs1_addr_i];
- rs2_data_ff <= mprf_int2[exu2mprf_rs2_addr_i];
-end
-
-// write operation
-always_ff @( posedge clk ) begin
- if ( wr_req_vd ) begin
- mprf_int[exu2mprf_rd_addr_i] <= exu2mprf_rd_data_i;
- mprf_int2[exu2mprf_rd_addr_i] <= exu2mprf_rd_data_i;
- end
-end
-`else // distributed logic implementation
-//------------------------------------------------------------------------------
-// distributed logic implementation
-//------------------------------------------------------------------------------
-
-// asynchronous read operation
-//
-`ifdef SCRC1_MPRF_STAGE
- assign rs1_new_data_req = wr_req_vd & ( exu2mprf_rs1_addr_i == exu2mprf_rd_addr_i );
- assign rs2_new_data_req = wr_req_vd & ( exu2mprf_rs2_addr_i == exu2mprf_rd_addr_i );
- assign read_new_data_req = rs1_new_data_req | rs2_new_data_req;
-
-// bypass new wr_data to the read output if write/read collision occurs
- assign mprf2exu_rs1_data_o = ( rs1_new_data_req_ff ) ? rd_data_ff
- : (( rs1_addr_vd_ff ) ? rs1_data_ff
- : '0 );
-
- assign mprf2exu_rs2_data_o = ( rs2_new_data_req_ff ) ? rd_data_ff
- : (( rs2_addr_vd_ff ) ? rs2_data_ff
- : '0 );
-
-
- always_ff @( posedge clk ) begin
- if ( read_new_data_req ) begin
- rd_data_ff <= exu2mprf_rd_data_i;
- end
- end
-
- always_ff @( posedge clk ) begin
- rs1_addr_vd_ff <= rs1_addr_vd;
- rs2_addr_vd_ff <= rs2_addr_vd;
- rs1_new_data_req_ff <= rs1_new_data_req;
- rs2_new_data_req_ff <= rs2_new_data_req;
- end
- always_ff @( posedge clk ) begin
- rs1_data_ff <= mprf_int[exu2mprf_rs1_addr_i];
- rs2_data_ff <= mprf_int[exu2mprf_rs2_addr_i];
- end
-
-`else
- assign mprf2exu_rs1_data_o = ( rs1_addr_vd ) ? mprf_int[exu2mprf_rs1_addr_i] : '0;
- assign mprf2exu_rs2_data_o = ( rs2_addr_vd ) ? mprf_int[exu2mprf_rs2_addr_i] : '0;
-`endif
-
-// write operation
- `ifdef SCR1_MPRF_RST_EN
-always_ff @( posedge clk, negedge rst_n ) begin
- if ( ~rst_n ) begin
- mprf_int <= '{default: '0};
- end else if ( wr_req_vd ) begin
- mprf_int[exu2mprf_rd_addr_i] <= exu2mprf_rd_data_i;
- end
-end
- `else // ~SCR1_MPRF_RST_EN
-always_ff @( posedge clk ) begin
- if ( wr_req_vd ) begin
- mprf_int[exu2mprf_rd_addr_i] <= exu2mprf_rd_data_i;
- end
-end
- `endif // ~SCR1_MPRF_RST_EN
-`endif
-
-`ifdef SCR1_TRGT_SIMULATION
-//-------------------------------------------------------------------------------
-// Assertion
-//-------------------------------------------------------------------------------
-`ifdef SCR1_MPRF_RST_EN
-SCR1_SVA_MPRF_WRITEX : assert property (
- @(negedge clk) disable iff (~rst_n)
- exu2mprf_w_req_i |-> !$isunknown({exu2mprf_rd_addr_i, (|exu2mprf_rd_addr_i ? exu2mprf_rd_data_i : `SCR1_XLEN'd0)})
- ) else $error("MPRF error: unknown values");
-`endif // SCR1_MPRF_RST_EN
-
-`endif // SCR1_TRGT_SIMULATION
-
-endmodule : scr1_pipe_mprf
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mul.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mul.sv
deleted file mode 100755
index 524e52d..0000000
--- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mul.sv
+++ /dev/null
@@ -1,176 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: 2021, Dinesh Annayya
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
-// //////////////////////////////////////////////////////////////////////////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// 32x32 Multiplier with 8 stage pipe line ////
-//// ////
-//// This file is part of the yifive cores project ////
-//// https://github.com/dineshannayya/yifive_r0.git ////
-//// http://www.opencores.org/cores/yifive/ ////
-//// ////
-//// Description: ////
-//// 32x32 Multiplier with 8 stage pipe line for timing reason ////
-//// Support signed multiplication, bit[32] indicate sign ////
-//// ////
-//// To Do: ////
-//// nothing ////
-//// ////
-//// Author(s): ////
-//// - Dinesh Annayya, dinesha@opencores.org ////
-//// ////
-//// Revision : ////
-//// 0.1 - 25th July 2021 ////
-//// Breaking two's completement into two stage for ////
-//// timing reason, When all lower 32 bit zero and ////
-//// it's complement will be '1', this will cause ////
-//// increment in higer bits ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-module scr1_pipe_mul (
- input logic clk,
- input logic rstn,
- input logic data_valid, // input valid
- input logic [32:0] Din1, // first operand
- input logic [32:0] Din2, // second operand
- output logic [31:0] des_hig, // first result
- output logic [31:0] des_low, // second result
- output logic mul_rdy_o, // Multiply result ready
- input logic data_done // Result processing complete indication
- );
-
-parameter WAIT_CMD = 2'b00; // Accept command and Do Signed to unsigned
-parameter WAIT_COMP = 2'b01; // Wait for COMPUTATION
-parameter WAIT_DONE = 2'b10; // Do Signed to Unsigned conversion
-parameter WAIT_EXIT = 2'b11; // Wait for Data Completion
-
-// wires
-logic [35:0] tmp_mul1;
-logic [64:0] tmp_mul, shifted;
-logic [31:0] src1,src2; // Unsigned number
-
-// real registers
-logic [2:0] cycle,next_cycle;
-logic [63:0] mul_result,mul_next;
-logic [1:0] state, next_state;
-logic mul_rdy_i;
-logic mul_32b_zero_b;
-
-assign tmp_mul1 = src1 * src2[31:28];
-//assign shifted = (cycle == 3'h0 ? 64'h0 : {mul_result[59:0], 4'b0000});
-assign tmp_mul = tmp_mul1 + shifted;
-assign des_hig = mul_result[63:32];
-assign des_low = mul_result[31:0];
-
-always_ff @(posedge clk or negedge rstn)
-begin
- if (!rstn) begin
- state <= WAIT_CMD;
- cycle <= 3'b0;
- mul_result <= 65'b0;
- mul_rdy_o <= 1'b0;
- src1 <= 32'h0;
- src2 <= 32'h0;
- shifted <= 'h0;
- mul_32b_zero_b <= '0;
- end else begin
- cycle <= next_cycle;
- state <= next_state;
- shifted <= {mul_next[59:0], 4'b0000};
-
- mul_rdy_o <= mul_rdy_i;
- if(data_valid && state== WAIT_CMD ) begin
- src1 <= (Din1[32] == 1'b1) ? (32'hFFFF_FFFF ^ Din1[31:0])+1 : Din1[31:0];
- src2 <= (Din2[32] == 1'b1) ? (32'hFFFF_FFFF ^ Din2[31:0])+1 : Din2[31:0];
- end else begin
- src2 <= src2 << 4;
- end
- if(state== WAIT_DONE ) begin
- // If Number is negative, then do 2's complement
- // Breaking 2's complement to timing reason
- if(Din1[32] ^ Din2[32]) begin
- mul_result[31:0] <= (32'hFFFF_FFFF ^ mul_result[31:0]) + 1;
- mul_result[63:32] <= (mul_32b_zero_b == 1'b0) ? (32'hFFFF_FFFF ^ mul_result[63:32]) + 1 : (32'hFFFF_FFFF ^ mul_result[63:32]) ;
- end
- end else begin
- mul_result <= mul_next;
- mul_32b_zero_b <= |mul_next[31:0]; // check all bit are zero
- end
- end
-end
-
-always_comb
-begin
- mul_rdy_i = 0;
- next_cycle = cycle;
- next_state = state;
- mul_next = mul_result;
- case(state)
- WAIT_CMD: if(data_valid) begin // Start only on active High Edge
- mul_next = 0;
- next_cycle = 0;
- next_state = WAIT_COMP;
- end
- // WAIT for Computation
- WAIT_COMP:
- begin
- mul_next = tmp_mul;
- next_cycle = cycle +1;
- if(cycle == 7) begin
- next_state = WAIT_DONE;
- end else begin
- next_cycle = cycle +1;
- end
- end
- WAIT_DONE: begin
- mul_rdy_i = 1'b1;
- next_state = WAIT_EXIT;
- end
- WAIT_EXIT: begin
- if(data_done) // Wait for data completion command
- next_state = WAIT_CMD;
- end
- endcase
-end
-
-endmodule
-
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv
deleted file mode 100644
index 888a313..0000000
--- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv
+++ /dev/null
@@ -1,628 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_pipe_tdu.sv>
-/// @brief Trigger Debug Unit (TDU)
-///
-
-//------------------------------------------------------------------------------
- //
- // Functionality:
- // - Provides read/write interface for TDU CSRs
- // - Provides triggers functionality:
- // - Supports triggers either in both Debug and M modes or in Debug mode only
- // - Supports virtual address matching (load, store, exec) triggers
- // - Supports instruction count triggers
- // - Supports the following actions on trigger firing:
- // - Breakpoint exception raising
- // - Debug Mode entering
- // - Supports triggers chaining
- //
- // Structure:
- // - CSR read/write i/f
- // - TDU CSRs:
- // - TSELECT
- // - TDATA1/MCONTROL/ICOUNT
- // - TDATA2
- // - TINFO
- // - TDU <-> EXU i/f
- // - TDU <-> LSU i/f
- // - TDU <-> HDU i/f
-//------------------------------------------------------------------------------
-
-`include "scr1_arch_description.svh"
-
-`ifdef SCR1_TDU_EN
-`include "scr1_riscv_isa_decoding.svh"
-`include "scr1_tdu.svh"
-
-module scr1_pipe_tdu (
- // Common signals
- input logic rst_n, // TDU reset
- input logic clk, // TDU clock
- input logic clk_en, // TDU clock enable
- input logic tdu_dsbl_i, // TDU Disable
-
- // TDU <-> CSR interface
- input logic csr2tdu_req_i, // CSR-TDU i/f request
- input type_scr1_csr_cmd_sel_e csr2tdu_cmd_i, // CSR-TDU i/f command
- input logic [SCR1_CSR_ADDR_TDU_OFFS_W-1:0] csr2tdu_addr_i, // CSR-TDU i/f address
- input logic [SCR1_TDU_DATA_W-1:0] csr2tdu_wdata_i, // CSR-TDU i/f write data
- output logic [SCR1_TDU_DATA_W-1:0] tdu2csr_rdata_o, // CSR-TDU i/f read data
- output type_scr1_csr_resp_e tdu2csr_resp_o, // CSR-TDU i/f response
-
- // TDU <-> EXU interface
- input type_scr1_brkm_instr_mon_s exu2tdu_imon_i, // Instruction stream monitoring
- output logic [SCR1_TDU_ALLTRIG_NUM-1 : 0] tdu2exu_ibrkpt_match_o, // Instruction BP match
- output logic tdu2exu_ibrkpt_exc_req_o, // Instruction BP exception request
- input logic [SCR1_TDU_ALLTRIG_NUM-1 : 0] exu2tdu_bp_retire_i, // Map of BPs being retired
-
- // TDU <-> LSU interface
-`ifndef SCR1_TDU_EN
- output logic tdu2lsu_brk_en_o, // TDU-LSU Breakpoint enable
-`endif // SCR1_TDU_EN
- output logic tdu2lsu_ibrkpt_exc_req_o, // TDU-LSU Instruction BP exception request
- input type_scr1_brkm_lsu_mon_s lsu2tdu_dmon_i, // TDU-LSU Data address stream monitoring
- output logic [SCR1_TDU_MTRIG_NUM-1 : 0] tdu2lsu_dbrkpt_match_o, // TDU-LSU Data BP match
- output logic tdu2lsu_dbrkpt_exc_req_o, // TDU-LSU Data BP exception request
-
- // TDU <-> HDU interface
- output logic tdu2hdu_dmode_req_o // Debug Mode redirection request
-);
-
-//------------------------------------------------------------------------------
-// Local parameters declaration
-//------------------------------------------------------------------------------
-
-localparam int unsigned MTRIG_NUM = SCR1_TDU_MTRIG_NUM;
-localparam int unsigned ALLTRIG_NUM = SCR1_TDU_ALLTRIG_NUM;
-localparam int unsigned ALLTRIG_W = $clog2(ALLTRIG_NUM+1);
-
-//------------------------------------------------------------------------------
-// Local signals declaration
-//------------------------------------------------------------------------------
-
-// TDU CSRs read/write i/f signals
-//------------------------------------------------------------------------------
-
-// Write signals
-logic csr_wr_req;
-logic [SCR1_TDU_DATA_W-1:0] csr_wr_data;
-
-// Register select
-logic csr_addr_tselect;
-logic [MTRIG_NUM-1:0] csr_addr_mcontrol;
-logic [MTRIG_NUM-1:0] csr_addr_tdata2;
-`ifdef SCR1_TDU_ICOUNT_EN
-logic csr_addr_icount;
-`endif // SCR1_TDU_ICOUNT_EN
-
-// TDU CSRs
-//------------------------------------------------------------------------------
-
-// TSELECT register
-logic csr_tselect_upd;
-logic [ALLTRIG_W-1:0] csr_tselect_ff;
-
-// MCONTROL register
-logic [MTRIG_NUM-1:0] csr_mcontrol_wr_req;
-logic [MTRIG_NUM-1:0] csr_mcontrol_clk_en;
-logic [MTRIG_NUM-1:0] csr_mcontrol_upd;
-
-logic [MTRIG_NUM-1:0] csr_mcontrol_dmode_ff;
-logic [MTRIG_NUM-1:0] csr_mcontrol_dmode_next;
-logic [MTRIG_NUM-1:0] csr_mcontrol_m_ff;
-logic [MTRIG_NUM-1:0] csr_mcontrol_m_next;
-logic [MTRIG_NUM-1:0] csr_mcontrol_exec_ff;
-logic [MTRIG_NUM-1:0] csr_mcontrol_exec_next;
-logic [MTRIG_NUM-1:0] csr_mcontrol_load_ff;
-logic [MTRIG_NUM-1:0] csr_mcontrol_load_next;
-logic [MTRIG_NUM-1:0] csr_mcontrol_store_ff;
-logic [MTRIG_NUM-1:0] csr_mcontrol_store_next;
-logic [MTRIG_NUM-1:0] csr_mcontrol_action_ff;
-logic [MTRIG_NUM-1:0] csr_mcontrol_action_next;
-logic [MTRIG_NUM-1:0] csr_mcontrol_hit_ff;
-logic [MTRIG_NUM-1:0] csr_mcontrol_hit_next;
-
-logic [MTRIG_NUM-1:0] csr_mcontrol_exec_hit;
-logic [MTRIG_NUM-1:0] csr_mcontrol_ldst_hit;
-
-// ICOUNT register
-`ifdef SCR1_TDU_ICOUNT_EN
-logic csr_icount_wr_req;
-logic csr_icount_clk_en;
-logic csr_icount_upd;
-
-logic csr_icount_dmode_ff;
-logic csr_icount_dmode_next;
-logic csr_icount_m_ff;
-logic csr_icount_m_next;
-logic csr_icount_action_ff;
-logic csr_icount_action_next;
-logic csr_icount_hit_ff;
-logic csr_icount_hit_next;
-logic [SCR1_TDU_ICOUNT_COUNT_HI-SCR1_TDU_ICOUNT_COUNT_LO:0]
- csr_icount_count_ff;
-logic [SCR1_TDU_ICOUNT_COUNT_HI-SCR1_TDU_ICOUNT_COUNT_LO:0]
- csr_icount_count_next;
-logic csr_icount_skip_ff;
-logic csr_icount_skip_next;
-
-logic csr_icount_decr_en;
-logic csr_icount_count_decr;
-logic csr_icount_skip_dsbl;
-logic csr_icount_hit;
-`endif // SCR1_TDU_ICOUNT_EN
-
-// TDATA2 register
-logic [MTRIG_NUM-1:0] csr_tdata2_upd;
-logic [MTRIG_NUM-1:0] csr_tdata2_ff [SCR1_TDU_DATA_W-1:0];
-
-//------------------------------------------------------------------------------
-// CSR read/write interface
-//------------------------------------------------------------------------------
-
-// Read logic
-//------------------------------------------------------------------------------
-
-assign tdu2csr_resp_o = csr2tdu_req_i ? SCR1_CSR_RESP_OK : SCR1_CSR_RESP_ER;
-integer i;
-always_comb begin
- i = 0; // yosys latch warning fix
- tdu2csr_rdata_o = '0;
- if (csr2tdu_req_i) begin
- case (csr2tdu_addr_i)
- SCR1_CSR_ADDR_TDU_OFFS_TSELECT: begin
- tdu2csr_rdata_o = {'0, csr_tselect_ff};
- end
- SCR1_CSR_ADDR_TDU_OFFS_TDATA2 : begin
- for(i = 0; i < MTRIG_NUM; i=i+1) begin // cp.4
- if(csr_tselect_ff == ALLTRIG_W'(i)) begin
- tdu2csr_rdata_o = csr_tdata2_ff[i];
- end
- end
- end
- SCR1_CSR_ADDR_TDU_OFFS_TDATA1 : begin
- for(i = 0; i < MTRIG_NUM; i=i+1) begin // cp.4
- if(csr_tselect_ff == ALLTRIG_W'(i)) begin
- tdu2csr_rdata_o[SCR1_TDU_TDATA1_TYPE_HI:
- SCR1_TDU_TDATA1_TYPE_LO] = SCR1_TDU_MCONTROL_TYPE_VAL;
- tdu2csr_rdata_o[SCR1_TDU_TDATA1_DMODE] = csr_mcontrol_dmode_ff[i];
- tdu2csr_rdata_o[SCR1_TDU_MCONTROL_MASKMAX_HI:
- SCR1_TDU_MCONTROL_MASKMAX_LO] = SCR1_TDU_MCONTROL_MASKMAX_VAL;
- tdu2csr_rdata_o[SCR1_TDU_MCONTROL_HIT] = csr_mcontrol_hit_ff[i];
- tdu2csr_rdata_o[SCR1_TDU_MCONTROL_SELECT] = SCR1_TDU_MCONTROL_SELECT_VAL;
- tdu2csr_rdata_o[SCR1_TDU_MCONTROL_TIMING] = SCR1_TDU_MCONTROL_TIMING_VAL;
- tdu2csr_rdata_o[SCR1_TDU_MCONTROL_ACTION_HI:
- SCR1_TDU_MCONTROL_ACTION_LO] = {5'b0, csr_mcontrol_action_ff[i]};
- tdu2csr_rdata_o[SCR1_TDU_MCONTROL_CHAIN] = 1'b0;
- tdu2csr_rdata_o[SCR1_TDU_MCONTROL_MATCH_HI:
- SCR1_TDU_MCONTROL_MATCH_LO] = 4'b0;
- tdu2csr_rdata_o[SCR1_TDU_MCONTROL_M] = csr_mcontrol_m_ff[i];
- tdu2csr_rdata_o[SCR1_TDU_MCONTROL_RESERVEDA] = SCR1_TDU_MCONTROL_RESERVEDA_VAL;
- tdu2csr_rdata_o[SCR1_TDU_MCONTROL_S] = 1'b0;
- tdu2csr_rdata_o[SCR1_TDU_MCONTROL_U] = 1'b0;
- tdu2csr_rdata_o[SCR1_TDU_MCONTROL_EXECUTE] = csr_mcontrol_exec_ff [i];
- tdu2csr_rdata_o[SCR1_TDU_MCONTROL_STORE] = csr_mcontrol_store_ff[i];
- tdu2csr_rdata_o[SCR1_TDU_MCONTROL_LOAD] = csr_mcontrol_load_ff [i];
- end
- end
-`ifdef SCR1_TDU_ICOUNT_EN
- if(csr_tselect_ff == ALLTRIG_W'(SCR1_TDU_ALLTRIG_NUM - 1'b1)) begin
- tdu2csr_rdata_o[SCR1_TDU_TDATA1_TYPE_HI:
- SCR1_TDU_TDATA1_TYPE_LO] = SCR1_TDU_ICOUNT_TYPE_VAL;
- tdu2csr_rdata_o[SCR1_TDU_TDATA1_DMODE] = csr_icount_dmode_ff;
- tdu2csr_rdata_o[SCR1_TDU_ICOUNT_HIT] = csr_icount_hit_ff;
- tdu2csr_rdata_o[SCR1_TDU_ICOUNT_COUNT_HI:
- SCR1_TDU_ICOUNT_COUNT_LO] = csr_icount_count_ff;
- tdu2csr_rdata_o[SCR1_TDU_ICOUNT_U] = 1'b0;
- tdu2csr_rdata_o[SCR1_TDU_ICOUNT_S] = 1'b0;
- tdu2csr_rdata_o[SCR1_TDU_ICOUNT_M] = csr_icount_m_ff;
- tdu2csr_rdata_o[SCR1_TDU_ICOUNT_ACTION_HI:
- SCR1_TDU_ICOUNT_ACTION_LO] = {5'b0, csr_icount_action_ff};
- end
-`endif // SCR1_TDU_ICOUNT_EN
- end
- SCR1_CSR_ADDR_TDU_OFFS_TINFO : begin
- for(i = 0; i < MTRIG_NUM; i=i+1) begin // cp.4
- if(csr_tselect_ff == ALLTRIG_W'(i)) begin
- tdu2csr_rdata_o[SCR1_TDU_MCONTROL_TYPE_VAL] = 1'b1;
- end
- end
-`ifdef SCR1_TDU_ICOUNT_EN
- if(csr_tselect_ff == ALLTRIG_W'(SCR1_TDU_ALLTRIG_NUM - 1'b1)) begin
- tdu2csr_rdata_o[SCR1_TDU_ICOUNT_TYPE_VAL] = 1'b1;
- end
-`endif // SCR1_TDU_ICOUNT_EN
- end
- default : begin
- end
- endcase
- end
-end
-
-// Write logic
-//------------------------------------------------------------------------------
-
-always_comb begin
- csr_wr_req = 1'b0;
- csr_wr_data = '0;
-
- case (csr2tdu_cmd_i)
- SCR1_CSR_CMD_WRITE: begin
- csr_wr_req = 1'b1;
- csr_wr_data = csr2tdu_wdata_i;
- end
- SCR1_CSR_CMD_SET : begin
- csr_wr_req = |csr2tdu_wdata_i;
- csr_wr_data = tdu2csr_rdata_o | csr2tdu_wdata_i;
- end
- SCR1_CSR_CMD_CLEAR: begin
- csr_wr_req = |csr2tdu_wdata_i;
- csr_wr_data = tdu2csr_rdata_o & ~csr2tdu_wdata_i;
- end
- default : begin
- end
- endcase
-end
-
-// Register selection
-//------------------------------------------------------------------------------
-integer k;
-always_comb begin
- k = 0; // yosys latch warning fix
- csr_addr_tselect = 1'b0;
- csr_addr_tdata2 = '0;
- csr_addr_mcontrol = '0;
-`ifdef SCR1_TDU_ICOUNT_EN
- csr_addr_icount = '0;
-`endif // SCR1_TDU_ICOUNT_EN
-
- if (csr2tdu_req_i) begin
- case (csr2tdu_addr_i)
- SCR1_CSR_ADDR_TDU_OFFS_TSELECT: begin
- csr_addr_tselect = 1'b1;
- end
- SCR1_CSR_ADDR_TDU_OFFS_TDATA1 : begin
- for(k = 0; k < MTRIG_NUM; k=k+1) begin
- if(csr_tselect_ff == ALLTRIG_W'(k)) begin
- csr_addr_mcontrol[k] = 1'b1;
- end
- end
-`ifdef SCR1_TDU_ICOUNT_EN
- if(csr_tselect_ff == ALLTRIG_W'(SCR1_TDU_ALLTRIG_NUM - 1'b1)) begin
- csr_addr_icount = 1'b1;
- end
-`endif // SCR1_TDU_ICOUNT_EN
- end
- SCR1_CSR_ADDR_TDU_OFFS_TDATA2 : begin
- for(k = 0; k < MTRIG_NUM; k=k+1) begin // cp.4
- if(csr_tselect_ff == ALLTRIG_W'(k) ) begin
- csr_addr_tdata2[k] = 1'b1;
- end
- end
- end
- default : begin
- end
- endcase
- end
-end
-
-//------------------------------------------------------------------------------
-// TDU CSRs
-//------------------------------------------------------------------------------
-//
- // TDU CSRs consist of the following registers:
- // - TSELECT
- // - TDATA1/MCONTROL/ICOUNT (depending on the type field value)
- // - TDATA2
-//
-
-// TSELECT register
-//------------------------------------------------------------------------------
-// Determines which trigger is accessible through the other trigger registers
-
-assign csr_tselect_upd = clk_en & csr_addr_tselect & csr_wr_req
- & (csr_wr_data[ALLTRIG_W-1:0] < ALLTRIG_W'(ALLTRIG_NUM));
-
-always_ff @(negedge rst_n, posedge clk) begin
- if(~rst_n) begin
- csr_tselect_ff <= '0;
- end else if(csr_tselect_upd) begin
- csr_tselect_ff <= csr_wr_data[ALLTRIG_W-1:0];
- end
-end
-
-`ifdef SCR1_TDU_ICOUNT_EN
-// ICOUNT register
-//------------------------------------------------------------------------------
-// Provides a trigger that fires when the certain number of instructions has retired
-// Is intended to be used as a single step trigger (in this case count must be 1)
-
-assign csr_icount_wr_req = csr_addr_icount & csr_wr_req;
-assign csr_icount_clk_en = clk_en & (csr_icount_wr_req | csr_icount_m_ff);
-assign csr_icount_upd = ~csr_icount_dmode_ff
- ? csr_icount_wr_req
- : tdu_dsbl_i & csr_icount_wr_req;
-
-always_ff @(negedge rst_n, posedge clk) begin
- if(~rst_n) begin
- csr_icount_dmode_ff <= 1'b0;
- csr_icount_m_ff <= 1'b0;
- csr_icount_action_ff <= 1'b0;
- csr_icount_hit_ff <= 1'b0;
- csr_icount_count_ff <= '0;
- csr_icount_skip_ff <= 1'b0;
- end else if (csr_icount_clk_en) begin
- csr_icount_dmode_ff <= csr_icount_dmode_next;
- csr_icount_m_ff <= csr_icount_m_next;
- csr_icount_action_ff <= csr_icount_action_next;
- csr_icount_hit_ff <= csr_icount_hit_next;
- csr_icount_count_ff <= csr_icount_count_next;
- csr_icount_skip_ff <= csr_icount_skip_next;
- end
-end
-
-assign csr_icount_decr_en = (~tdu_dsbl_i & csr_icount_m_ff)
- ? exu2tdu_imon_i.vd & (csr_icount_count_ff != 14'b0)
- : 1'b0;
-assign csr_icount_count_decr = exu2tdu_imon_i.req & csr_icount_decr_en & ~csr_icount_skip_ff;
-assign csr_icount_skip_dsbl = exu2tdu_imon_i.req & csr_icount_decr_en & csr_icount_skip_ff;
-
-always_comb begin
- if (csr_icount_upd) begin
- csr_icount_dmode_next = csr_wr_data[SCR1_TDU_TDATA1_DMODE];
- csr_icount_m_next = csr_wr_data[SCR1_TDU_ICOUNT_M];
- csr_icount_action_next = (csr_wr_data[SCR1_TDU_ICOUNT_ACTION_HI
- :SCR1_TDU_ICOUNT_ACTION_LO] == 'b1);
- csr_icount_hit_next = csr_wr_data[SCR1_TDU_ICOUNT_HIT];
- csr_icount_count_next = csr_wr_data[SCR1_TDU_ICOUNT_COUNT_HI:SCR1_TDU_ICOUNT_COUNT_LO];
- end else begin
- csr_icount_dmode_next = csr_icount_dmode_ff;
- csr_icount_m_next = csr_icount_m_ff;
- csr_icount_action_next = csr_icount_action_ff;
- csr_icount_hit_next = exu2tdu_bp_retire_i[ALLTRIG_NUM - 1'b1]
- ? 1'b1
- : csr_icount_hit_ff;
- csr_icount_count_next = csr_icount_count_decr
- ? csr_icount_count_ff - 1'b1
- : csr_icount_count_ff;
- end
-end
-
-assign csr_icount_skip_next = csr_icount_wr_req ? csr_wr_data[SCR1_TDU_ICOUNT_M]
- : csr_icount_skip_dsbl ? 1'b0
- : csr_icount_skip_ff;
-`endif // SCR1_TDU_ICOUNT_EN
-
-// MCONTROL registers
-//------------------------------------------------------------------------------
-// Provides a trigger that fires on the virtual address (stored in TDATA2) match
-// (load, store, exec options supported). Triggers chaining supported
-
-genvar trig;
-generate
-for (trig = 0; $unsigned(trig) < MTRIG_NUM; trig=trig+1) begin : gblock_mtrig
-
-assign csr_mcontrol_wr_req[trig] = csr_addr_mcontrol[trig] & csr_wr_req;
-assign csr_mcontrol_clk_en[trig] = clk_en
- & (csr_mcontrol_wr_req[trig] | csr_mcontrol_m_ff[trig]);
-assign csr_mcontrol_upd [trig] = ~csr_mcontrol_dmode_ff[trig]
- ? csr_mcontrol_wr_req[trig]
- : tdu_dsbl_i & csr_mcontrol_wr_req[trig];
-
-always_ff @(negedge rst_n, posedge clk) begin
- if(~rst_n) begin
- csr_mcontrol_dmode_ff [trig] <= 1'b0;
- csr_mcontrol_m_ff [trig] <= 1'b0;
- csr_mcontrol_exec_ff [trig] <= 1'b0;
- csr_mcontrol_load_ff [trig] <= 1'b0;
- csr_mcontrol_store_ff [trig] <= 1'b0;
- csr_mcontrol_action_ff[trig] <= 1'b0;
- csr_mcontrol_hit_ff [trig] <= 1'b0;
- end else if(csr_mcontrol_clk_en[trig]) begin
- csr_mcontrol_dmode_ff [trig] <= csr_mcontrol_dmode_next[trig];
- csr_mcontrol_m_ff [trig] <= csr_mcontrol_m_next[trig];
- csr_mcontrol_exec_ff [trig] <= csr_mcontrol_exec_next[trig];
- csr_mcontrol_load_ff [trig] <= csr_mcontrol_load_next[trig];
- csr_mcontrol_store_ff [trig] <= csr_mcontrol_store_next[trig];
- csr_mcontrol_action_ff[trig] <= csr_mcontrol_action_next[trig];
- csr_mcontrol_hit_ff [trig] <= csr_mcontrol_hit_next[trig];
- end
-end
-
-always_comb begin
- if (csr_mcontrol_upd[trig]) begin
- csr_mcontrol_dmode_next [trig] = csr_wr_data[SCR1_TDU_TDATA1_DMODE];
- csr_mcontrol_m_next [trig] = csr_wr_data[SCR1_TDU_MCONTROL_M];
- csr_mcontrol_exec_next [trig] = csr_wr_data[SCR1_TDU_MCONTROL_EXECUTE];
- csr_mcontrol_load_next [trig] = csr_wr_data[SCR1_TDU_MCONTROL_LOAD];
- csr_mcontrol_store_next [trig] = csr_wr_data[SCR1_TDU_MCONTROL_STORE];
- csr_mcontrol_action_next[trig] = (csr_wr_data[SCR1_TDU_MCONTROL_ACTION_HI
- :SCR1_TDU_MCONTROL_ACTION_LO] == 'b1);
- csr_mcontrol_hit_next [trig] = csr_wr_data[SCR1_TDU_MCONTROL_HIT];
- end else begin
- csr_mcontrol_dmode_next [trig] = csr_mcontrol_dmode_ff [trig];
- csr_mcontrol_m_next [trig] = csr_mcontrol_m_ff [trig];
- csr_mcontrol_exec_next [trig] = csr_mcontrol_exec_ff [trig];
- csr_mcontrol_load_next [trig] = csr_mcontrol_load_ff [trig];
- csr_mcontrol_store_next [trig] = csr_mcontrol_store_ff [trig];
- csr_mcontrol_action_next[trig] = csr_mcontrol_action_ff[trig];
- csr_mcontrol_hit_next [trig] = exu2tdu_bp_retire_i[trig]
- ? 1'b1
- : csr_mcontrol_hit_ff[trig];
- end
-end
-
-// TDATA2 register
-//------------------------------------------------------------------------------
-
-assign csr_tdata2_upd[trig] = ~csr_mcontrol_dmode_ff[trig]
- ? clk_en & csr_addr_tdata2[trig] & csr_wr_req
- : clk_en & csr_addr_tdata2[trig] & csr_wr_req & tdu_dsbl_i;
-
-always_ff @(posedge clk) begin
- if (csr_tdata2_upd[trig]) begin
- csr_tdata2_ff[trig] <= csr_wr_data;
- end
-end
-
-end
-endgenerate // gblock_mtrig
-
-//------------------------------------------------------------------------------
-// TDU <-> EXU interface
-//------------------------------------------------------------------------------
-
-assign csr_icount_hit = ~tdu_dsbl_i & csr_icount_m_ff
- ? exu2tdu_imon_i.vd & (csr_icount_count_ff == 14'b1) & ~csr_icount_skip_ff
- : 1'b0;
-
-`ifndef SCR1_TDU_ICOUNT_EN
-assign tdu2exu_ibrkpt_match_o = csr_mcontrol_exec_hit;
-assign tdu2exu_ibrkpt_exc_req_o = |csr_mcontrol_exec_hit;
-`else
-assign tdu2exu_ibrkpt_match_o = {csr_icount_hit, csr_mcontrol_exec_hit};
-assign tdu2exu_ibrkpt_exc_req_o = |csr_mcontrol_exec_hit | csr_icount_hit;
-`endif // SCR1_TDU_ICOUNT_EN
-
-//------------------------------------------------------------------------------
-// TDU <-> LSU interface
-//------------------------------------------------------------------------------
-
-// Breakpoint logic
-//------------------------------------------------------------------------------
-
-generate
-for (trig = 0; $unsigned(trig) < MTRIG_NUM; trig=trig+1) begin : gblock_break_trig
-assign csr_mcontrol_exec_hit[trig] = ~tdu_dsbl_i
- & csr_mcontrol_m_ff[trig]
- & csr_mcontrol_exec_ff[trig]
- & exu2tdu_imon_i.vd
- & exu2tdu_imon_i.addr == csr_tdata2_ff[trig];
-end
-endgenerate
-
-`ifndef SCR1_TDU_ICOUNT_EN
-assign tdu2lsu_ibrkpt_exc_req_o = |csr_mcontrol_exec_hit;
-`else
-assign tdu2lsu_ibrkpt_exc_req_o = |csr_mcontrol_exec_hit | csr_icount_hit;
-`endif // SCR1_TDU_ICOUNT_EN
-
-// Watchpoint logic
-//------------------------------------------------------------------------------
-
-generate
-for( trig = 0; $unsigned(trig) < MTRIG_NUM; trig=trig+1 ) begin : gblock_watch_trig
-assign csr_mcontrol_ldst_hit[trig] = ~tdu_dsbl_i
- & csr_mcontrol_m_ff[trig]
- & lsu2tdu_dmon_i.vd
- & ( (csr_mcontrol_load_ff [trig] & lsu2tdu_dmon_i.load)
- | (csr_mcontrol_store_ff[trig] & lsu2tdu_dmon_i.store))
- & lsu2tdu_dmon_i.addr == csr_tdata2_ff[trig];
-end
-endgenerate
-
-assign tdu2lsu_dbrkpt_match_o = csr_mcontrol_ldst_hit;
-assign tdu2lsu_dbrkpt_exc_req_o = |csr_mcontrol_ldst_hit;
-
-`ifndef SCR1_TDU_EN
-assign tdu2lsu_brk_en_o = |csr_mcontrol_m_ff | csr_icount_m_ff;
-`endif // SCR1_TDU_EN
-
-//------------------------------------------------------------------------------
-// TDU <-> HDU interface
-//------------------------------------------------------------------------------
-integer j;
-always_comb begin
- tdu2hdu_dmode_req_o = 1'b0;
-
- for(j = 0; j < MTRIG_NUM; j=j+1) begin
- tdu2hdu_dmode_req_o |= (csr_mcontrol_action_ff[j] & exu2tdu_bp_retire_i[j]);
- end
-`ifdef SCR1_TDU_ICOUNT_EN
- tdu2hdu_dmode_req_o |= (csr_icount_action_ff & exu2tdu_bp_retire_i[ALLTRIG_NUM-1]);
-`endif // SCR1_TDU_ICOUNT_EN
-end
-
-`ifdef SCR1_TRGT_SIMULATION
-//------------------------------------------------------------------------------
-// Assertion
-//------------------------------------------------------------------------------
-
-SVA_TDU_X_CONTROL : assert property (
- @(negedge clk) disable iff (~rst_n)
- !$isunknown({clk_en, tdu_dsbl_i, csr2tdu_req_i,
- exu2tdu_imon_i.vd, lsu2tdu_dmon_i.vd, exu2tdu_bp_retire_i})
- ) else $error("TDU Error: control signals is X - %0b", {clk_en,
- tdu_dsbl_i, csr2tdu_req_i, exu2tdu_imon_i.vd, lsu2tdu_dmon_i.vd, exu2tdu_bp_retire_i});
-
-SVA_DM_X_CLK_EN : assert property (
- @(negedge clk) disable iff (~rst_n)
- !$isunknown(clk_en)
- ) else $error("TDU Error: clk_en control signals is X");
-
-SVA_DM_X_DSBL : assert property (
- @(negedge clk) disable iff (~rst_n)
- !$isunknown(tdu_dsbl_i)
- ) else $error("TDU Error: tdu_dsbl_i control signals is X");
-
-SVA_DM_X_CSR2TDU_REQ : assert property (
- @(negedge clk) disable iff (~rst_n)
- !$isunknown(csr2tdu_req_i)
- ) else $error("TDU Error: csr2tdu_req_i control signals is X");
-
-SVA_DM_X_I_MON_VD : assert property (
- @(negedge clk) disable iff (~rst_n)
- !$isunknown(exu2tdu_imon_i.vd)
- ) else $error("TDU Error: exu2tdu_imon_i.vd control signals is X");
-
-SVA_DM_X_D_MON_VD : assert property (
- @(negedge clk) disable iff (~rst_n)
- !$isunknown(lsu2tdu_dmon_i.vd)
- ) else $error("TDU Error: lsu2tdu_dmon_i.vd control signals is X");
-
-SVA_DM_X_BP_RETIRE : assert property (
- @(negedge clk) disable iff (~rst_n)
- !$isunknown(exu2tdu_bp_retire_i)
- ) else $error("TDU Error: exu2tdu_bp_retire_i control signals is X");
-
-SVA_TDU_X_CSR : assert property (
- @(negedge clk) disable iff (~rst_n)
- csr2tdu_req_i |-> !$isunknown({csr2tdu_cmd_i,csr2tdu_addr_i})
- ) else $error("TDU Error: csr is X");
-
-SVA_TDU_XW_CSR : assert property (
- @(negedge clk) disable iff (~rst_n)
- (csr2tdu_req_i & csr_wr_req) |-> !$isunknown(csr2tdu_wdata_i)
- ) else $error("TDU Error: csr wdata is X ");
-
-SVA_TDU_X_IMON : assert property (
- @(negedge clk) disable iff (~rst_n)
- exu2tdu_imon_i.vd |-> !$isunknown({exu2tdu_imon_i.req,exu2tdu_imon_i.addr})
- ) else $error("TDU Error: imonitor is X");
-
-SVA_TDU_X_DMON : assert property (
- @(negedge clk) disable iff (~rst_n)
- lsu2tdu_dmon_i.vd |-> !$isunknown({lsu2tdu_dmon_i})
- ) else $error("TDU Error: dmonitor is X");
-
-`endif // SCR1_TRGT_SIMULATION
-
-endmodule : scr1_pipe_tdu
-
-`endif // SCR1_TDU_EN
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv
deleted file mode 100644
index 467dd10..0000000
--- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv
+++ /dev/null
@@ -1,838 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_pipe_top.sv>
-/// @brief SCR1 pipeline top
-///
-
-//----------------------------------------------------------------------------------
-// project : YiFive
-// Rev: June 10, 2021, Dinesh A
-// Bugfix- reset correction for scr1_pipe_tdu when debug is not enabled
-// Note: previously reset rst_n is floating at simulation is failing
-// when SCR1_DBG_EN is disabled
-//---------------------------------------------------------------------------------
-
-`include "scr1_arch_description.svh"
-`include "scr1_memif.svh"
-`include "scr1_riscv_isa_decoding.svh"
-`include "scr1_csr.svh"
-
-`ifdef SCR1_IPIC_EN
-`include "scr1_ipic.svh"
-`endif // SCR1_IPIC_EN
-
-`ifdef SCR1_DBG_EN
-`include "scr1_hdu.svh"
-`endif // SCR1_DBG_EN
-
-`ifdef SCR1_TDU_EN
-`include "scr1_tdu.svh"
-`endif // SCR1_TDU_EN
-
-module scr1_pipe_top (
- // Common
- input logic pipe_rst_n, // Pipe reset
- output logic [48:0] pipe_debug,
-`ifdef SCR1_DBG_EN
- input logic pipe2hdu_rdc_qlfy_i, // Pipe RDC qualifier
- input logic dbg_rst_n, // Debug reset
-`endif // SCR1_DBG_EN
- input logic clk, // Pipe clock
-
- // Instruction Memory Interface
- output logic pipe2imem_req_o, // IMEM request
- output logic pipe2imem_cmd_o, // IMEM command
- output logic [`SCR1_IMEM_AWIDTH-1:0] pipe2imem_addr_o, // IMEM address
- input logic imem2pipe_req_ack_i, // IMEM request acknowledge
- input logic [`SCR1_IMEM_DWIDTH-1:0] imem2pipe_rdata_i, // IMEM read data
- input logic [1:0] imem2pipe_resp_i, // IMEM response
-
- // Data Memory Interface
- output logic pipe2dmem_req_o, // DMEM request
- output logic pipe2dmem_cmd_o, // DMEM command
- output logic [1:0] pipe2dmem_width_o, // DMEM data width
- output logic [`SCR1_DMEM_AWIDTH-1:0] pipe2dmem_addr_o, // DMEM address
- output logic [`SCR1_DMEM_DWIDTH-1:0] pipe2dmem_wdata_o, // DMEM write data
- input logic dmem2pipe_req_ack_i, // DMEM request acknowledge
- input logic [`SCR1_DMEM_DWIDTH-1:0] dmem2pipe_rdata_i, // DMEM read data
- input logic [1:0] dmem2pipe_resp_i, // DMEM response
-
-`ifdef SCR1_DBG_EN
- // Debug interface:
- input logic dbg_en, // 1 - debug operations enabled
- // DM <-> Pipeline: HART Run Control i/f
- input logic dm2pipe_active_i, // Debug Module active flag
- input logic dm2pipe_cmd_req_i, // Request from Debug Module
- input type_scr1_hdu_dbgstates_e dm2pipe_cmd_i, // Command from Debug Module
- output logic pipe2dm_cmd_resp_o, // Response to Debug Module
- output logic pipe2dm_cmd_rcode_o, // Debug Module return code: 0 - Ok; 1 - Error
- output logic pipe2dm_hart_event_o, // HART event flag
- output type_scr1_hdu_hartstatus_s pipe2dm_hart_status_o, // HART status
-
- // DM <-> Pipeline: Program Buffer - HART instruction execution i/f
- output logic [SCR1_HDU_PBUF_ADDR_WIDTH-1:0] pipe2dm_pbuf_addr_o, // Program Buffer address
- input logic [SCR1_HDU_CORE_INSTR_WIDTH-1:0] dm2pipe_pbuf_instr_i, // Program Buffer instruction
-
- // DM <-> Pipeline: HART Abstract Data regs i/f
- output logic pipe2dm_dreg_req_o, // Abstract Data Register request
- output logic pipe2dm_dreg_wr_o, // Abstract Data Register write
- output logic [`SCR1_XLEN-1:0] pipe2dm_dreg_wdata_o, // Abstract Data Register write data
- input logic dm2pipe_dreg_resp_i, // Abstract Data Register response
- input logic dm2pipe_dreg_fail_i, // Abstract Data Register fail - possibly not needed?
- input logic [`SCR1_XLEN-1:0] dm2pipe_dreg_rdata_i, // Abstract Data Register read data
-
- // DM <-> Pipeling: PC i/f
- output logic [`SCR1_XLEN-1:0] pipe2dm_pc_sample_o, // Current PC for sampling
-`endif // SCR1_DBG_EN
-
- // IRQ
-`ifdef SCR1_IPIC_EN
- input logic [SCR1_IRQ_LINES_NUM-1:0] soc2pipe_irq_lines_i, // External interrupt request lines
-`else // SCR1_IPIC_EN
- input logic soc2pipe_irq_ext_i, // External interrupt request
-`endif // SCR1_IPIC_EN
- input logic soc2pipe_irq_soft_i, // Software generated interrupt request
- input logic soc2pipe_irq_mtimer_i, // Machine timer interrupt request
-
- // Memory-mapped external timer
- input logic [63:0] soc2pipe_mtimer_val_i, // Machine timer value
-
-`ifdef SCR1_CLKCTRL_EN
- // CLK_CTRL interface
- output logic pipe2clkctl_sleep_req_o, // CLK disable request to CLK gating circuit
- output logic pipe2clkctl_wake_req_o, // CLK enable request to CLK gating circuit
- input logic clkctl2pipe_clk_alw_on_i, // Not gated CLK
- input logic clkctl2pipe_clk_dbgc_i, // CLK for HDU (not gated for now)
- input logic clkctl2pipe_clk_en_i, // CLK enabled flag
-`endif // SCR1_CLKCTRL_EN
-
- // Fuse
- input logic [`SCR1_XLEN-1:0] soc2pipe_fuse_mhartid_i // Fuse MHARTID value
-);
-
-//-------------------------------------------------------------------------------
-// Local signals declaration
-//-------------------------------------------------------------------------------
-
-// Pipeline control
-logic [`SCR1_XLEN-1:0] curr_pc; // Current PC
-logic [`SCR1_XLEN-1:0] next_pc; // Is written to MEPC on interrupt trap
-logic new_pc_req; // New PC request (jumps, branches, traps etc)
-logic [`SCR1_XLEN-1:0] new_pc; // New PC
-
-logic stop_fetch; // Stop IFU
-logic exu_exc_req; // Exception request
-logic brkpt; // Breakpoint (sw) on current instruction
-logic exu_init_pc; // Reset exit
-logic wfi_run2halt; // Transition to WFI halted state
-logic instret; // Instruction retirement (with or without exception)
-logic instret_nexc; // Instruction retirement (without exception)
-`ifdef SCR1_IPIC_EN
-logic ipic2csr_irq; // IRQ request from IPIC
-`endif // SCR1_IPIC_EN
-`ifdef SCR1_TDU_EN
-logic brkpt_hw; // Hardware breakpoint on current instruction
-`endif // SCR1_TDU_EN
-`ifdef SCR1_CLKCTRL_EN
-logic imem_txns_pending; // There are pending imem transactions
-logic wfi_halted; // WFI halted state
-`endif // SCR1_CLKCTRL_EN
-
-// IFU <-> IDU
-logic ifu2idu_vd; // IFU request
-logic [`SCR1_IMEM_DWIDTH-1:0] ifu2idu_instr; // IFU instruction
-logic ifu2idu_imem_err; // IFU instruction access fault
-logic ifu2idu_err_rvi_hi; // 1 - imem fault when trying to fetch second half of an unaligned RVI instruction
-logic idu2ifu_rdy; // IDU ready for new data
-
-// IDU <-> EXU
-logic idu2exu_req; // IDU request
-type_scr1_exu_cmd_s idu2exu_cmd; // IDU command (see scr1_riscv_isa_decoding.svh)
-logic idu2exu_use_rs1; // Instruction uses rs1
-logic idu2exu_use_rs2; // Instruction uses rs2
-logic idu2exu_use_rd; // Instruction uses rd
-logic idu2exu_use_imm; // Instruction uses immediate
-logic exu2idu_rdy; // EXU ready for new data
-
-// EXU <-> MPRF
-logic [`SCR1_MPRF_AWIDTH-1:0] exu2mprf_rs1_addr; // MPRF rs1 read address
-logic [`SCR1_XLEN-1:0] mprf2exu_rs1_data; // MPRF rs1 read data
-logic [`SCR1_MPRF_AWIDTH-1:0] exu2mprf_rs2_addr; // MPRF rs2 read address
-logic [`SCR1_XLEN-1:0] mprf2exu_rs2_data; // MPRF rs2 read data
-logic exu2mprf_w_req; // MPRF write request
-logic [`SCR1_MPRF_AWIDTH-1:0] exu2mprf_rd_addr; // MPRF rd write address
-logic [`SCR1_XLEN-1:0] exu2mprf_rd_data; // MPRF rd write data
-
-// EXU <-> CSR
-logic [SCR1_CSR_ADDR_WIDTH-1:0] exu2csr_rw_addr; // CSR read/write address
-logic exu2csr_r_req; // CSR read request
-logic [`SCR1_XLEN-1:0] csr2exu_r_data; // CSR read data
-logic exu2csr_w_req; // CSR write request
-type_scr1_csr_cmd_sel_e exu2csr_w_cmd; // CSR write command
-logic [`SCR1_XLEN-1:0] exu2csr_w_data; // CSR write data
-logic csr2exu_rw_exc; // CSR read/write access exception
-
-// EXU <-> CSR event interface
-logic exu2csr_take_irq; // Take IRQ trap
-logic exu2csr_take_exc; // Take exception trap
-logic exu2csr_mret_update; // MRET update CSR
-logic exu2csr_mret_instr; // MRET instruction
-logic [SCR1_EXC_CODE_WIDTH_E-1:0] exu2csr_exc_code; // Exception code (see scr1_arch_types.svh)
-logic [`SCR1_XLEN-1:0] exu2csr_trap_val; // Trap value
-logic [`SCR1_XLEN-1:0] csr2exu_new_pc; // Exception/IRQ/MRET new PC
-logic csr2exu_irq; // IRQ request
-logic csr2exu_ip_ie; // Some IRQ pending and locally enabled
-logic csr2exu_mstatus_mie_up; // MSTATUS or MIE update in the current cycle
-
-`ifdef SCR1_IPIC_EN
-// CSR <-> IPIC
-logic csr2ipic_r_req; // IPIC read request
-logic csr2ipic_w_req; // IPIC write request
-logic [2:0] csr2ipic_addr; // IPIC address
-logic [`SCR1_XLEN-1:0] csr2ipic_wdata; // IPIC write data
-logic [`SCR1_XLEN-1:0] ipic2csr_rdata; // IPIC read data
-`endif // SCR1_IPIC_EN
-
-`ifdef SCR1_TDU_EN
-// CSR <-> TDU
-logic csr2tdu_req; // Request to TDU
-type_scr1_csr_cmd_sel_e csr2tdu_cmd; // TDU command
-logic [SCR1_CSR_ADDR_TDU_OFFS_W-1:0] csr2tdu_addr; // TDU address
-logic [`SCR1_XLEN-1:0] csr2tdu_wdata; // TDU write data
-logic [`SCR1_XLEN-1:0] tdu2csr_rdata; // TDU read data
-type_scr1_csr_resp_e tdu2csr_resp; // TDU response
- `ifdef SCR1_DBG_EN
- // Qualified TDU input signals from pipe_rst_n
- // reset domain:
-logic csr2tdu_req_qlfy; // Request to TDU
- `endif // SCR1_DBG_EN
-
-// EXU/LSU <-> TDU
-type_scr1_brkm_instr_mon_s exu2tdu_i_mon; // Instruction monitor
-type_scr1_brkm_lsu_mon_s lsu2tdu_d_mon; // Data monitor
-logic [SCR1_TDU_ALLTRIG_NUM-1:0] tdu2exu_i_match; // Instruction breakpoint(s) match
-logic [SCR1_TDU_MTRIG_NUM-1:0] tdu2lsu_d_match; // Data breakpoint(s) match
-logic tdu2exu_i_x_req; // Instruction breakpoint exception
-logic tdu2lsu_i_x_req; // Instruction breakpoint exception
-logic tdu2lsu_d_x_req; // Data breakpoint exception
-logic [SCR1_TDU_ALLTRIG_NUM-1:0] exu2tdu_bp_retire; // Instruction with breakpoint flag retire
- `ifdef SCR1_DBG_EN
- // Qualified TDU input signals from pipe_rst_n
- // reset domain:
-type_scr1_brkm_instr_mon_s exu2tdu_i_mon_qlfy; // Instruction monitor
-type_scr1_brkm_lsu_mon_s lsu2tdu_d_mon_qlfy; // Data monitor
-logic [SCR1_TDU_ALLTRIG_NUM-1:0] exu2tdu_bp_retire_qlfy; // Instruction with breakpoint flag retire
- `endif // SCR1_DBG_EN
-`endif // SCR1_TDU_EN
-
-`ifdef SCR1_DBG_EN
-// Debug signals:
-logic fetch_pbuf; // Fetch instructions provided by Program Buffer (via HDU)
-logic csr2hdu_req; // Request to HDU
-type_scr1_csr_cmd_sel_e csr2hdu_cmd; // HDU command
-logic [SCR1_HDU_DEBUGCSR_ADDR_WIDTH-1:0] csr2hdu_addr; // HDU address
-logic [`SCR1_XLEN-1:0] csr2hdu_wdata; // HDU write data
-logic [`SCR1_XLEN-1:0] hdu2csr_rdata; // HDU read data
-type_scr1_csr_resp_e hdu2csr_resp; // HDU response
- // Qualified HDU input signals from pipe_rst_n
- // reset domain:
-logic csr2hdu_req_qlfy; // Request to HDU
-
-logic hwbrk_dsbl; // Disables TDU
-logic hdu_hwbrk_dsbl; // Disables TDU
-logic tdu2hdu_dmode_req; // TDU requests transition to debug mode
-
-logic exu_no_commit; // Forbid instruction commitment
-logic exu_irq_dsbl; // Disable IRQ
-logic exu_pc_advmt_dsbl; // Forbid PC advancement
-logic exu_dmode_sstep_en; // Enable single-step
-
-logic dbg_halted; // Debug halted state
-logic dbg_run2halt; // Transition to debug halted state
-logic dbg_halt2run; // Transition to run state
-logic dbg_run_start; // First cycle of run state
-logic [`SCR1_XLEN-1:0] dbg_new_pc; // New PC as starting point for HART Resume
-
-logic ifu2hdu_pbuf_rdy;
-logic hdu2ifu_pbuf_vd;
-logic hdu2ifu_pbuf_err;
-logic [SCR1_HDU_CORE_INSTR_WIDTH-1:0] hdu2ifu_pbuf_instr;
-
-// Qualified HDU input signals from pipe_rst_n reset domain:
-logic ifu2hdu_pbuf_rdy_qlfy;
-logic exu_busy_qlfy;
-logic instret_qlfy;
-logic exu_init_pc_qlfy;
-logic exu_exc_req_qlfy;
-logic brkpt_qlfy;
-
-`endif // SCR1_DBG_EN
-
-logic exu_busy;
-
-
-`ifndef SCR1_CLKCTRL_EN
-logic pipe2clkctl_wake_req_o;
-`endif // SCR1_CLKCTRL_EN
-
-
-assign pipe_debug = {curr_pc[31:0],new_pc_req,stop_fetch, exu_exc_req,brkpt,exu_init_pc,wfi_run2halt,instret,
- ifu2idu_vd,idu2ifu_rdy,idu2exu_req,exu2idu_rdy,exu2mprf_w_req,exu2csr_r_req,csr2exu_rw_exc,
- exu2csr_mret_update,csr2exu_irq,csr2exu_mstatus_mie_up};
-//-------------------------------------------------------------------------------
-// Pipeline logic
-//-------------------------------------------------------------------------------
-assign stop_fetch = wfi_run2halt
-`ifdef SCR1_DBG_EN
- | fetch_pbuf
-`endif // SCR1_DBG_EN
- ;
-
-`ifdef SCR1_CLKCTRL_EN
-assign pipe2clkctl_sleep_req_o = wfi_halted & ~imem_txns_pending;
-assign pipe2clkctl_wake_req_o = csr2exu_ip_ie
-`ifdef SCR1_DBG_EN
- | dm2pipe_active_i
-`endif // SCR1_DBG_EN
- ;
-`endif // SCR1_CLKCTRL_EN
-
-`ifdef SCR1_DBG_EN
-assign pipe2dm_pc_sample_o = curr_pc;
-`endif // SCR1_DBG_EN
-
-//-------------------------------------------------------------------------------
-// Instruction fetch unit
-//-------------------------------------------------------------------------------
-scr1_pipe_ifu i_pipe_ifu (
- .rst_n (pipe_rst_n ),
- .clk (clk ),
-
- // Instruction memory interface
- .imem2ifu_req_ack_i (imem2pipe_req_ack_i),
- .ifu2imem_req_o (pipe2imem_req_o ),
- .ifu2imem_cmd_o (pipe2imem_cmd_o ),
- .ifu2imem_addr_o (pipe2imem_addr_o ),
- .imem2ifu_rdata_i (imem2pipe_rdata_i ),
- .imem2ifu_resp_i (imem2pipe_resp_i ),
-
- // New PC interface
- .exu2ifu_pc_new_req_i (new_pc_req ),
- .exu2ifu_pc_new_i (new_pc ),
- .pipe2ifu_stop_fetch_i (stop_fetch ),
-
-`ifdef SCR1_DBG_EN
- // IFU <-> HDU Program Buffer interface
- .hdu2ifu_pbuf_fetch_i (fetch_pbuf ),
- .ifu2hdu_pbuf_rdy_o (ifu2hdu_pbuf_rdy ),
- .hdu2ifu_pbuf_vd_i (hdu2ifu_pbuf_vd ),
- .hdu2ifu_pbuf_err_i (hdu2ifu_pbuf_err ),
- .hdu2ifu_pbuf_instr_i (hdu2ifu_pbuf_instr ),
-`endif // SCR1_DBG_EN
-`ifdef SCR1_CLKCTRL_EN
- .ifu2pipe_imem_txns_pnd_o (imem_txns_pending ),
-`endif // SCR1_CLKCTRL_EN
-
- // IFU <-> IDU interface
- .idu2ifu_rdy_i (idu2ifu_rdy ),
- .ifu2idu_instr_o (ifu2idu_instr ),
- .ifu2idu_imem_err_o (ifu2idu_imem_err ),
- .ifu2idu_err_rvi_hi_o (ifu2idu_err_rvi_hi ),
- .ifu2idu_vd_o (ifu2idu_vd )
-);
-
-//-------------------------------------------------------------------------------
-// Instruction decode unit
-//-------------------------------------------------------------------------------
-scr1_pipe_idu i_pipe_idu (
-`ifdef SCR1_TRGT_SIMULATION
- .rst_n (pipe_rst_n ),
- .clk (clk ),
-`endif // SCR1_TRGT_SIMULATION
- .idu2ifu_rdy_o (idu2ifu_rdy ),
- .ifu2idu_instr_i (ifu2idu_instr ),
- .ifu2idu_imem_err_i (ifu2idu_imem_err ),
- .ifu2idu_err_rvi_hi_i (ifu2idu_err_rvi_hi),
- .ifu2idu_vd_i (ifu2idu_vd ),
-
- .idu2exu_req_o (idu2exu_req ),
- .idu2exu_cmd_o (idu2exu_cmd ),
- .idu2exu_use_rs1_o (idu2exu_use_rs1 ),
- .idu2exu_use_rs2_o (idu2exu_use_rs2 ),
- .idu2exu_use_rd_o (idu2exu_use_rd ),
- .idu2exu_use_imm_o (idu2exu_use_imm ),
- .exu2idu_rdy_i (exu2idu_rdy )
-);
-
-//-------------------------------------------------------------------------------
-// Execution unit
-//-------------------------------------------------------------------------------
-scr1_pipe_exu i_pipe_exu (
- .rst_n (pipe_rst_n ),
- .clk (clk ),
-`ifdef SCR1_CLKCTRL_EN
- .clk_alw_on (clkctl2pipe_clk_alw_on_i),
- .clk_pipe_en (clkctl2pipe_clk_en_i),
-`endif // SCR1_CLKCTRL_EN
-
- // IDU <-> EXU interface
- .idu2exu_req_i (idu2exu_req ),
- .exu2idu_rdy_o (exu2idu_rdy ),
- .idu2exu_cmd_i (idu2exu_cmd ),
- .idu2exu_use_rs1_i (idu2exu_use_rs1 ),
- .idu2exu_use_rs2_i (idu2exu_use_rs2 ),
-`ifndef SCR1_NO_EXE_STAGE
- .idu2exu_use_rd_i (idu2exu_use_rd ),
- .idu2exu_use_imm_i (idu2exu_use_imm ),
-`endif // SCR1_NO_EXE_STAGE
-
- // EXU <-> MPRF interface
- .exu2mprf_rs1_addr_o (exu2mprf_rs1_addr ),
- .mprf2exu_rs1_data_i (mprf2exu_rs1_data ),
- .exu2mprf_rs2_addr_o (exu2mprf_rs2_addr ),
- .mprf2exu_rs2_data_i (mprf2exu_rs2_data ),
- .exu2mprf_w_req_o (exu2mprf_w_req ),
- .exu2mprf_rd_addr_o (exu2mprf_rd_addr ),
- .exu2mprf_rd_data_o (exu2mprf_rd_data ),
-
- // EXU <-> CSR read/write interface
- .exu2csr_rw_addr_o (exu2csr_rw_addr ),
- .exu2csr_r_req_o (exu2csr_r_req ),
- .csr2exu_r_data_i (csr2exu_r_data ),
- .exu2csr_w_req_o (exu2csr_w_req ),
- .exu2csr_w_cmd_o (exu2csr_w_cmd ),
- .exu2csr_w_data_o (exu2csr_w_data ),
- .csr2exu_rw_exc_i (csr2exu_rw_exc ),
-
- // EXU <-> CSR event interface
- .exu2csr_take_irq_o (exu2csr_take_irq ),
- .exu2csr_take_exc_o (exu2csr_take_exc ),
- .exu2csr_mret_update_o (exu2csr_mret_update ),
- .exu2csr_mret_instr_o (exu2csr_mret_instr ),
- .exu2csr_exc_code_o (exu2csr_exc_code ),
- .exu2csr_trap_val_o (exu2csr_trap_val ),
- .csr2exu_new_pc_i (csr2exu_new_pc ),
- .csr2exu_irq_i (csr2exu_irq ),
- .csr2exu_ip_ie_i (csr2exu_ip_ie ),
- .csr2exu_mstatus_mie_up_i (csr2exu_mstatus_mie_up ),
-
- // EXU <-> DMEM interface
- .exu2dmem_req_o (pipe2dmem_req_o ),
- .exu2dmem_cmd_o (pipe2dmem_cmd_o ),
- .exu2dmem_width_o (pipe2dmem_width_o ),
- .exu2dmem_addr_o (pipe2dmem_addr_o ),
- .exu2dmem_wdata_o (pipe2dmem_wdata_o ),
- .dmem2exu_req_ack_i (dmem2pipe_req_ack_i ),
- .dmem2exu_rdata_i (dmem2pipe_rdata_i ),
- .dmem2exu_resp_i (dmem2pipe_resp_i ),
-
-`ifdef SCR1_DBG_EN
- // EXU <-> HDU interface
- .hdu2exu_no_commit_i (exu_no_commit ),
- .hdu2exu_irq_dsbl_i (exu_irq_dsbl ),
- .hdu2exu_pc_advmt_dsbl_i (exu_pc_advmt_dsbl ),
- .hdu2exu_dmode_sstep_en_i (exu_dmode_sstep_en ),
- .hdu2exu_pbuf_fetch_i (fetch_pbuf ),
- .hdu2exu_dbg_halted_i (dbg_halted ),
- .hdu2exu_dbg_run2halt_i (dbg_run2halt ),
- .hdu2exu_dbg_halt2run_i (dbg_halt2run ),
- .hdu2exu_dbg_run_start_i (dbg_run_start ),
- .hdu2exu_dbg_new_pc_i (dbg_new_pc ),
-`endif // SCR1_DBG_EN
-
-`ifdef SCR1_TDU_EN
- // EXU <-> TDU interface
- .exu2tdu_imon_o (exu2tdu_i_mon ),
- .tdu2exu_ibrkpt_match_i (tdu2exu_i_match ),
- .tdu2exu_ibrkpt_exc_req_i (tdu2exu_i_x_req ),
- .lsu2tdu_dmon_o (lsu2tdu_d_mon ),
- .tdu2lsu_ibrkpt_exc_req_i (tdu2lsu_i_x_req ),
- .tdu2lsu_dbrkpt_match_i (tdu2lsu_d_match ),
- .tdu2lsu_dbrkpt_exc_req_i (tdu2lsu_d_x_req ),
- .exu2tdu_ibrkpt_ret_o (exu2tdu_bp_retire ),
- .exu2hdu_ibrkpt_hw_o (brkpt_hw ),
-`endif // SCR1_TDU_EN
-
- // EXU control
- .exu2pipe_exc_req_o (exu_exc_req ),
- .exu2pipe_brkpt_o (brkpt ),
- .exu2pipe_init_pc_o (exu_init_pc ),
- .exu2pipe_wfi_run2halt_o (wfi_run2halt ),
- .exu2pipe_instret_o (instret ),
- .exu2csr_instret_no_exc_o (instret_nexc ),
- .exu2pipe_exu_busy_o (exu_busy ),
-
- // PC interface
-`ifdef SCR1_CLKCTRL_EN
- .exu2pipe_wfi_halted_o (wfi_halted ),
-`endif // SCR1_CLKCTRL_EN
- .exu2pipe_pc_curr_o (curr_pc ),
- .exu2csr_pc_next_o (next_pc ),
- .exu2ifu_pc_new_req_o (new_pc_req ),
- .exu2ifu_pc_new_o (new_pc )
-);
-
-//-------------------------------------------------------------------------------
-// Multi-port register file
-//-------------------------------------------------------------------------------
-scr1_pipe_mprf i_pipe_mprf (
-`ifdef SCR1_MPRF_RST_EN
- .rst_n (pipe_rst_n ),
-`endif // SCR1_MPRF_RST_EN
- .clk (clk ),
-
- // EXU <-> MPRF interface
- .exu2mprf_rs1_addr_i (exu2mprf_rs1_addr),
- .mprf2exu_rs1_data_o (mprf2exu_rs1_data),
- .exu2mprf_rs2_addr_i (exu2mprf_rs2_addr),
- .mprf2exu_rs2_data_o (mprf2exu_rs2_data),
- .exu2mprf_w_req_i (exu2mprf_w_req ),
- .exu2mprf_rd_addr_i (exu2mprf_rd_addr ),
- .exu2mprf_rd_data_i (exu2mprf_rd_data )
-);
-
-//-------------------------------------------------------------------------------
-// Control and status registers
-//-------------------------------------------------------------------------------
-scr1_pipe_csr i_pipe_csr (
- .rst_n (pipe_rst_n ),
- .clk (clk ),
-`ifdef SCR1_CLKCTRL_EN
- .clk_alw_on (clkctl2pipe_clk_alw_on_i),
-`endif // SCR1_CLKCTRL_EN
-
- // EXU <-> CSR read/write interface
- .exu2csr_r_req_i (exu2csr_r_req ),
- .exu2csr_rw_addr_i (exu2csr_rw_addr ),
- .csr2exu_r_data_o (csr2exu_r_data ),
- .exu2csr_w_req_i (exu2csr_w_req ),
- .exu2csr_w_cmd_i (exu2csr_w_cmd ),
- .exu2csr_w_data_i (exu2csr_w_data ),
- .csr2exu_rw_exc_o (csr2exu_rw_exc ),
-
- // EXU <-> CSR event interface
- .exu2csr_take_irq_i (exu2csr_take_irq ),
- .exu2csr_take_exc_i (exu2csr_take_exc ),
- .exu2csr_mret_update_i (exu2csr_mret_update ),
- .exu2csr_mret_instr_i (exu2csr_mret_instr ),
- .exu2csr_exc_code_i (exu2csr_exc_code ),
- .exu2csr_trap_val_i (exu2csr_trap_val ),
- .csr2exu_new_pc_o (csr2exu_new_pc ),
- .csr2exu_irq_o (csr2exu_irq ),
- .csr2exu_ip_ie_o (csr2exu_ip_ie ),
- .csr2exu_mstatus_mie_up_o (csr2exu_mstatus_mie_up ),
-
-`ifdef SCR1_IPIC_EN
- // CSR <-> IPIC interface
- .csr2ipic_r_req_o (csr2ipic_r_req ),
- .csr2ipic_w_req_o (csr2ipic_w_req ),
- .csr2ipic_addr_o (csr2ipic_addr ),
- .csr2ipic_wdata_o (csr2ipic_wdata ),
- .ipic2csr_rdata_i (ipic2csr_rdata ),
-`endif // SCR1_IPIC_EN
-
- // CSR <-> PC interface
- .exu2csr_pc_curr_i (curr_pc ),
- .exu2csr_pc_next_i (next_pc ),
-`ifndef SCR1_CSR_REDUCED_CNT
- .exu2csr_instret_no_exc_i (instret_nexc ),
-`endif // SCR1_CSR_REDUCED_CNT
-
- // IRQ
-`ifdef SCR1_IPIC_EN
- .soc2csr_irq_ext_i (ipic2csr_irq ),
-`else // SCR1_IPIC_EN
- .soc2csr_irq_ext_i (soc2pipe_irq_ext_i ),
-`endif // SCR1_IPIC_EN
- .soc2csr_irq_soft_i (soc2pipe_irq_soft_i ),
- .soc2csr_irq_mtimer_i (soc2pipe_irq_mtimer_i ),
-
- // Memory-mapped external timer
- .soc2csr_mtimer_val_i (soc2pipe_mtimer_val_i ),
-
-`ifdef SCR1_DBG_EN
- // CSR <-> HDU interface
- .csr2hdu_req_o (csr2hdu_req ),
- .csr2hdu_cmd_o (csr2hdu_cmd ),
- .csr2hdu_addr_o (csr2hdu_addr ),
- .csr2hdu_wdata_o (csr2hdu_wdata ),
- .hdu2csr_rdata_i (hdu2csr_rdata ),
- .hdu2csr_resp_i (hdu2csr_resp ),
- .hdu2csr_no_commit_i (exu_no_commit ),
-`endif // SCR1_DBG_EN
-
-`ifdef SCR1_TDU_EN
- // CSR <-> TDU interface
- .csr2tdu_req_o (csr2tdu_req ),
- .csr2tdu_cmd_o (csr2tdu_cmd ),
- .csr2tdu_addr_o (csr2tdu_addr ),
- .csr2tdu_wdata_o (csr2tdu_wdata ),
- .tdu2csr_rdata_i (tdu2csr_rdata ),
- .tdu2csr_resp_i (tdu2csr_resp ),
-`endif // SCR1_TDU_EN
- .soc2csr_fuse_mhartid_i (soc2pipe_fuse_mhartid_i )
-);
-
-//-------------------------------------------------------------------------------
-// Integrated programmable interrupt controller
-//-------------------------------------------------------------------------------
-`ifdef SCR1_IPIC_EN
-scr1_ipic i_pipe_ipic (
- .rst_n (pipe_rst_n ),
-`ifdef SCR1_CLKCTRL_EN
- .clk (clkctl2pipe_clk_alw_on_i),
-`else // SCR1_CLKCTRL_EN
- .clk (clk ),
-`endif // SCR1_CLKCTRL_EN
- .soc2ipic_irq_lines_i (soc2pipe_irq_lines_i ),
- .csr2ipic_r_req_i (csr2ipic_r_req ),
- .csr2ipic_w_req_i (csr2ipic_w_req ),
- .csr2ipic_addr_i (csr2ipic_addr ),
- .csr2ipic_wdata_i (csr2ipic_wdata ),
- .ipic2csr_rdata_o (ipic2csr_rdata ),
- .ipic2csr_irq_m_req_o (ipic2csr_irq )
-);
-`endif // SCR1_IPIC_EN
-
-//-------------------------------------------------------------------------------
-// Breakpoint module
-//-------------------------------------------------------------------------------
-`ifdef SCR1_TDU_EN
-scr1_pipe_tdu i_pipe_tdu (
- // Common signals
- `ifdef SCR1_DBG_EN
- .rst_n (dbg_rst_n ),
- `else
- .rst_n (pipe_rst_n ),
- `endif // SCR1_DBG_EN
- .clk (clk ),
- .clk_en (1'b1 ),
- `ifdef SCR1_DBG_EN
- .tdu_dsbl_i (hwbrk_dsbl ),
- `else // SCR1_DBG_EN
- .tdu_dsbl_i (1'b0 ),
- `endif // SCR1_DBG_EN
-
- // TDU <-> CSR interface
- `ifdef SCR1_DBG_EN
- .csr2tdu_req_i (csr2tdu_req_qlfy ),
- .csr2tdu_cmd_i (csr2tdu_cmd ),
- .csr2tdu_addr_i (csr2tdu_addr ),
- .csr2tdu_wdata_i (csr2tdu_wdata ),
- `else // SCR1_DBG_EN
- .csr2tdu_req_i (csr2tdu_req ),
- .csr2tdu_cmd_i (csr2tdu_cmd ),
- .csr2tdu_addr_i (csr2tdu_addr ),
- .csr2tdu_wdata_i (csr2tdu_wdata ),
- `endif // SCR1_DBG_EN
- .tdu2csr_rdata_o (tdu2csr_rdata ),
- .tdu2csr_resp_o (tdu2csr_resp ),
-
- // TDU <-> EXU interface
- `ifdef SCR1_DBG_EN
- .exu2tdu_imon_i (exu2tdu_i_mon_qlfy ),
- `else // SCR1_DBG_EN
- .exu2tdu_imon_i (exu2tdu_i_mon ),
- `endif // SCR1_DBG_EN
- .tdu2exu_ibrkpt_match_o (tdu2exu_i_match ),
- .tdu2exu_ibrkpt_exc_req_o (tdu2exu_i_x_req ),
- `ifdef SCR1_DBG_EN
- .exu2tdu_bp_retire_i (exu2tdu_bp_retire_qlfy),
- `else // SCR1_DBG_EN
- .exu2tdu_bp_retire_i (exu2tdu_bp_retire ),
- `endif // SCR1_DBG_EN
-
- // TDU <-> LSU interface
- .tdu2lsu_ibrkpt_exc_req_o (tdu2lsu_i_x_req ),
- `ifdef SCR1_DBG_EN
- .lsu2tdu_dmon_i (lsu2tdu_d_mon_qlfy ),
- `else // SCR1_DBG_EN
- .lsu2tdu_dmon_i (lsu2tdu_d_mon ),
- `endif // SCR1_DBG_EN
- .tdu2lsu_dbrkpt_match_o (tdu2lsu_d_match ),
- .tdu2lsu_dbrkpt_exc_req_o (tdu2lsu_d_x_req ),
- // EPU I/F
- `ifdef SCR1_DBG_EN
- .tdu2hdu_dmode_req_o (tdu2hdu_dmode_req )
- `else // SCR1_DBG_EN
- .tdu2hdu_dmode_req_o ( )
- `endif // SCR1_DBG_EN
-);
-
- `ifdef SCR1_DBG_EN
-assign hwbrk_dsbl = (~dbg_en) | hdu_hwbrk_dsbl;
-//
-assign csr2tdu_req_qlfy = dbg_en & csr2tdu_req & pipe2hdu_rdc_qlfy_i;
-//
-assign exu2tdu_i_mon_qlfy.vd = exu2tdu_i_mon.vd & pipe2hdu_rdc_qlfy_i;
-assign exu2tdu_i_mon_qlfy.req = exu2tdu_i_mon.req;
-assign exu2tdu_i_mon_qlfy.addr = exu2tdu_i_mon.addr;
-assign lsu2tdu_d_mon_qlfy.vd = lsu2tdu_d_mon.vd & pipe2hdu_rdc_qlfy_i;
-assign lsu2tdu_d_mon_qlfy.load = lsu2tdu_d_mon.load;
-assign lsu2tdu_d_mon_qlfy.store = lsu2tdu_d_mon.store;
-assign lsu2tdu_d_mon_qlfy.addr = lsu2tdu_d_mon.addr;
-assign exu2tdu_bp_retire_qlfy = exu2tdu_bp_retire & {$bits(exu2tdu_bp_retire){pipe2hdu_rdc_qlfy_i}};
- `endif // SCR1_DBG_EN
-
-`endif // SCR1_TDU_EN
-
-//-------------------------------------------------------------------------------
-// HART Debug Unit (HDU)
-//-------------------------------------------------------------------------------
-`ifdef SCR1_DBG_EN
-scr1_pipe_hdu i_pipe_hdu (
- // Common signals
- .rst_n (dbg_rst_n ),
- .clk_en (dm2pipe_active_i ),
-`ifdef SCR1_CLKCTRL_EN
- .clk_pipe_en (clkctl2pipe_clk_en_i ),
- .clk (clkctl2pipe_clk_dbgc_i),
-`else
- .clk (clk ),
-`endif // SCR1_CLKCTRL_EN
-
- // Control/status registers i/f
- .csr2hdu_req_i (csr2hdu_req_qlfy ),
- .csr2hdu_cmd_i (csr2hdu_cmd ),
- .csr2hdu_addr_i (csr2hdu_addr ),
- .csr2hdu_wdata_i (csr2hdu_wdata ),
- .hdu2csr_resp_o (hdu2csr_resp ),
- .hdu2csr_rdata_o (hdu2csr_rdata ),
-
- // HART Run Control i/f
- .pipe2hdu_rdc_qlfy_i (pipe2hdu_rdc_qlfy_i ),
- .dm2hdu_cmd_req_i (dm2pipe_cmd_req_i ),
- .dm2hdu_cmd_i (dm2pipe_cmd_i ),
- .hdu2dm_cmd_resp_o (pipe2dm_cmd_resp_o ),
- .hdu2dm_cmd_rcode_o (pipe2dm_cmd_rcode_o ),
- .hdu2dm_hart_event_o (pipe2dm_hart_event_o ),
- .hdu2dm_hart_status_o (pipe2dm_hart_status_o ),
-
- // Program Buffer - HART instruction execution i/f
- .hdu2dm_pbuf_addr_o (pipe2dm_pbuf_addr_o ),
- .dm2hdu_pbuf_instr_i (dm2pipe_pbuf_instr_i ),
-
- // HART Abstract Data regs i/f
- .hdu2dm_dreg_req_o (pipe2dm_dreg_req_o ),
- .hdu2dm_dreg_wr_o (pipe2dm_dreg_wr_o ),
- .hdu2dm_dreg_wdata_o (pipe2dm_dreg_wdata_o ),
- .dm2hdu_dreg_resp_i (dm2pipe_dreg_resp_i ),
- .dm2hdu_dreg_fail_i (dm2pipe_dreg_fail_i ),
- .dm2hdu_dreg_rdata_i (dm2pipe_dreg_rdata_i ),
- //
-`ifdef SCR1_TDU_EN
- // HDU <-> TDU interface
- .hdu2tdu_hwbrk_dsbl_o (hdu_hwbrk_dsbl ),
- .tdu2hdu_dmode_req_i (tdu2hdu_dmode_req ),
- .exu2hdu_ibrkpt_hw_i (brkpt_hw ),
-`endif // SCR1_TDU_EN
-
- // HART Run Status
- .pipe2hdu_exu_busy_i (exu_busy_qlfy ),
- .pipe2hdu_instret_i (instret_qlfy ),
- .pipe2hdu_init_pc_i (exu_init_pc_qlfy ),
-
- // HART Halt Status
- .pipe2hdu_exu_exc_req_i (exu_exc_req_qlfy ),
- .pipe2hdu_brkpt_i (brkpt_qlfy ),
-
- // HART Run Control
- .hdu2exu_pbuf_fetch_o (fetch_pbuf ),
- .hdu2exu_no_commit_o (exu_no_commit ),
- .hdu2exu_irq_dsbl_o (exu_irq_dsbl ),
- .hdu2exu_pc_advmt_dsbl_o (exu_pc_advmt_dsbl ),
- .hdu2exu_dmode_sstep_en_o (exu_dmode_sstep_en ),
-
- // HART state
- .hdu2exu_dbg_halted_o (dbg_halted ),
- .hdu2exu_dbg_run2halt_o (dbg_run2halt ),
- .hdu2exu_dbg_halt2run_o (dbg_halt2run ),
- .hdu2exu_dbg_run_start_o (dbg_run_start ),
-
- // PC interface
- .pipe2hdu_pc_curr_i (curr_pc ),
- .hdu2exu_dbg_new_pc_o (dbg_new_pc ),
-
- // Prgram Buffer Instruction interface
- .ifu2hdu_pbuf_instr_rdy_i (ifu2hdu_pbuf_rdy_qlfy ),
- .hdu2ifu_pbuf_instr_vd_o (hdu2ifu_pbuf_vd ),
- .hdu2ifu_pbuf_instr_err_o (hdu2ifu_pbuf_err ),
- .hdu2ifu_pbuf_instr_o (hdu2ifu_pbuf_instr )
-);
-
-assign csr2hdu_req_qlfy = csr2hdu_req & dbg_en & pipe2hdu_rdc_qlfy_i;
-//
-assign exu_busy_qlfy = exu_busy & {$bits(exu_busy){pipe2hdu_rdc_qlfy_i}};
-assign instret_qlfy = instret & {$bits(instret){pipe2hdu_rdc_qlfy_i}};
-assign exu_init_pc_qlfy = exu_init_pc & {$bits(exu_init_pc){pipe2hdu_rdc_qlfy_i}};
-assign exu_exc_req_qlfy = exu_exc_req & {$bits(exu_exc_req){pipe2hdu_rdc_qlfy_i}};
-assign brkpt_qlfy = brkpt & {$bits(brkpt){pipe2hdu_rdc_qlfy_i}};
-assign ifu2hdu_pbuf_rdy_qlfy = ifu2hdu_pbuf_rdy & {$bits(ifu2hdu_pbuf_rdy){pipe2hdu_rdc_qlfy_i}};
-
-`endif // SCR1_DBG_EN
-
-`ifdef SCR1_TRGT_SIMULATION
-//-------------------------------------------------------------------------------
-// Tracelog
-//-------------------------------------------------------------------------------
-
-scr1_tracelog i_tracelog (
- .rst_n (pipe_rst_n ),
- .clk (clk ),
- .soc2pipe_fuse_mhartid_i (soc2pipe_fuse_mhartid_i ),
-
- // MPRF
- .mprf2trace_int_i (i_pipe_mprf.mprf_int ),
- .mprf2trace_wr_en_i (i_pipe_mprf.exu2mprf_w_req_i ),
- .mprf2trace_wr_addr_i (i_pipe_mprf.exu2mprf_rd_addr_i ),
- .mprf2trace_wr_data_i (i_pipe_mprf.exu2mprf_rd_data_i ),
-
- // EXU
- .exu2trace_update_pc_en_i (i_pipe_exu.update_pc_en ),
- .exu2trace_update_pc_i (i_pipe_exu.update_pc ),
-
- // IFU
- .ifu2trace_instr_i (i_pipe_ifu.ifu2idu_instr_o ),
-
- // CSR
- .csr2trace_mstatus_mie_i (i_pipe_csr.csr_mstatus_mie_ff ),
- .csr2trace_mstatus_mpie_i (i_pipe_csr.csr_mstatus_mpie_ff ),
- .csr2trace_mtvec_base_i (i_pipe_csr.csr_mtvec_base ),
- .csr2trace_mtvec_mode_i (i_pipe_csr.csr_mtvec_mode ),
- .csr2trace_mie_meie_i (i_pipe_csr.csr_mie_meie_ff ),
- .csr2trace_mie_mtie_i (i_pipe_csr.csr_mie_mtie_ff ),
- .csr2trace_mie_msie_i (i_pipe_csr.csr_mie_msie_ff ),
- .csr2trace_mip_meip_i (i_pipe_csr.csr_mip_meip ),
- .csr2trace_mip_mtip_i (i_pipe_csr.csr_mip_mtip ),
- .csr2trace_mip_msip_i (i_pipe_csr.csr_mip_msip ),
- .csr2trace_mepc_i (i_pipe_csr.csr_mepc_ff ),
- .csr2trace_mcause_irq_i (i_pipe_csr.csr_mcause_i_ff ),
- .csr2trace_mcause_ec_i (i_pipe_csr.csr_mcause_ec_ff ),
- .csr2trace_mtval_i (i_pipe_csr.csr_mtval_ff ),
- .csr2trace_mstatus_mie_up_i (i_pipe_csr.csr2exu_mstatus_mie_up_o),
-
- // Events
- .csr2trace_e_exc_i (i_pipe_csr.e_exc ),
- .csr2trace_e_irq_i (i_pipe_csr.e_irq ),
- .pipe2trace_e_wake_i (pipe2clkctl_wake_req_o ),
- .csr2trace_e_mret_i (i_pipe_csr.e_mret )
-);
-
-`endif // SCR1_TRGT_SIMULATION
-
-endmodule : scr1_pipe_top
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_tracelog.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_tracelog.sv
deleted file mode 100644
index 4b845d8..0000000
--- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_tracelog.sv
+++ /dev/null
@@ -1,471 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_tracelog.sv>
-/// @brief Core tracelog module
-///
-
-`include "scr1_arch_description.svh"
-`include "scr1_arch_types.svh"
-`include "scr1_csr.svh"
-
-`ifdef SCR1_TRGT_SIMULATION
-
-module scr1_tracelog (
- input logic rst_n, // Tracelog reset
- input logic clk, // Tracelog clock
- input logic [`SCR1_XLEN-1:0] soc2pipe_fuse_mhartid_i, // Fuse MHARTID
-
- // MPRF
-`ifdef SCR1_MPRF_RAM
- input logic [`SCR1_XLEN-1:0] mprf2trace_int_i [1:`SCR1_MPRF_SIZE-1], // MPRF registers content
-`else // SCR1_MPRF_RAM
- logic [`SCR1_XLEN-1:0] mprf2trace_int_i[1:`SCR1_MPRF_SIZE-1], // MPRF registers content
-`endif // SCR1_MPRF_RAM
- input logic mprf2trace_wr_en_i, // MPRF write enable
- input logic [`SCR1_MPRF_AWIDTH-1:0] mprf2trace_wr_addr_i, // MPRF write address
- input logic [`SCR1_XLEN-1:0] mprf2trace_wr_data_i, // MPRF write data
-
- // EXU
- input logic exu2trace_update_pc_en_i, // PC updated flag
- input logic [`SCR1_XLEN-1:0] exu2trace_update_pc_i, // Next PC value
-
- // IFU
- input logic [`SCR1_IMEM_DWIDTH-1:0] ifu2trace_instr_i, // Current instruction from IFU stage
-
- // CSR
- input logic csr2trace_mstatus_mie_i, // CSR MSTATUS.mie bit
- input logic csr2trace_mstatus_mpie_i, // CSR MSTATUS.mpie bit
- input logic [`SCR1_XLEN-1:6] csr2trace_mtvec_base_i, // CSR MTVEC.
- input logic csr2trace_mtvec_mode_i, // CSR MTVEC.
- input logic csr2trace_mie_meie_i, // CSR MIE.meie bit
- input logic csr2trace_mie_mtie_i, // CSR MIE.mtie bit
- input logic csr2trace_mie_msie_i, // CSR MIE.msie bit
- input logic csr2trace_mip_meip_i, // CSR MIP.meip bit
- input logic csr2trace_mip_mtip_i, // CSR MIP.mtip bit
- input logic csr2trace_mip_msip_i, // CSR MIP.msip bit
- `ifdef SCR1_RVC_EXT
- input logic [`SCR1_XLEN-1:1] csr2trace_mepc_i, // CSR MEPC register
- `else // SCR1_RVC_EXT
- input logic [`SCR1_XLEN-1:2] csr2trace_mepc_i, // CSR MEPC register
- `endif // SCR1_RVC_EXT
- input logic csr2trace_mcause_irq_i, // CSR MCAUSE.interrupt bit
- input [SCR1_EXC_CODE_WIDTH_E-1:0] csr2trace_mcause_ec_i, // CSR MCAUSE.exception_code bit
- input logic [`SCR1_XLEN-1:0] csr2trace_mtval_i, // CSR MTVAL register
- input logic csr2trace_mstatus_mie_up_i, // CSR MSTATUS.mie update flag
-
- // Events
- input logic csr2trace_e_exc_i, // exception event
- input logic csr2trace_e_irq_i, // interrupt event
- input logic pipe2trace_e_wake_i, // pipe wakeup event
- input logic csr2trace_e_mret_i // MRET instruction
-);
-
-//-------------------------------------------------------------------------------
-// Local types declaration
-//-------------------------------------------------------------------------------
-typedef struct {
- logic [`SCR1_XLEN-1:0] INT_00_ZERO ;
- logic [`SCR1_XLEN-1:0] INT_01_RA ;
- logic [`SCR1_XLEN-1:0] INT_02_SP ;
- logic [`SCR1_XLEN-1:0] INT_03_GP ;
- logic [`SCR1_XLEN-1:0] INT_04_TP ;
- logic [`SCR1_XLEN-1:0] INT_05_T0 ;
- logic [`SCR1_XLEN-1:0] INT_06_T1 ;
- logic [`SCR1_XLEN-1:0] INT_07_T2 ;
- logic [`SCR1_XLEN-1:0] INT_08_S0 ;
- logic [`SCR1_XLEN-1:0] INT_09_S1 ;
- logic [`SCR1_XLEN-1:0] INT_10_A0 ;
- logic [`SCR1_XLEN-1:0] INT_11_A1 ;
- logic [`SCR1_XLEN-1:0] INT_12_A2 ;
- logic [`SCR1_XLEN-1:0] INT_13_A3 ;
- logic [`SCR1_XLEN-1:0] INT_14_A4 ;
- logic [`SCR1_XLEN-1:0] INT_15_A5 ;
-`ifndef SCR1_RVE_EXT
- logic [`SCR1_XLEN-1:0] INT_16_A6 ;
- logic [`SCR1_XLEN-1:0] INT_17_A7 ;
- logic [`SCR1_XLEN-1:0] INT_18_S2 ;
- logic [`SCR1_XLEN-1:0] INT_19_S3 ;
- logic [`SCR1_XLEN-1:0] INT_20_S4 ;
- logic [`SCR1_XLEN-1:0] INT_21_S5 ;
- logic [`SCR1_XLEN-1:0] INT_22_S6 ;
- logic [`SCR1_XLEN-1:0] INT_23_S7 ;
- logic [`SCR1_XLEN-1:0] INT_24_S8 ;
- logic [`SCR1_XLEN-1:0] INT_25_S9 ;
- logic [`SCR1_XLEN-1:0] INT_26_S10 ;
- logic [`SCR1_XLEN-1:0] INT_27_S11 ;
- logic [`SCR1_XLEN-1:0] INT_28_T3 ;
- logic [`SCR1_XLEN-1:0] INT_29_T4 ;
- logic [`SCR1_XLEN-1:0] INT_30_T5 ;
- logic [`SCR1_XLEN-1:0] INT_31_T6 ;
-`endif // SCR1_RVE_EXT
-} type_scr1_ireg_name_s;
-
-typedef struct packed {
- logic [`SCR1_XLEN-1:0] mstatus;
- logic [`SCR1_XLEN-1:0] mtvec;
- logic [`SCR1_XLEN-1:0] mie;
- logic [`SCR1_XLEN-1:0] mip;
- logic [`SCR1_XLEN-1:0] mepc;
- logic [`SCR1_XLEN-1:0] mcause;
- logic [`SCR1_XLEN-1:0] mtval;
-} type_scr1_csr_trace_s;
-
-//-------------------------------------------------------------------------------
-// Local Signal Declaration
-//-------------------------------------------------------------------------------
-
-type_scr1_ireg_name_s mprf_int_alias;
-
-`ifdef SCR1_TRACE_LOG_EN
-
-time current_time;
-
-// Tracelog control signals
-logic trace_flag;
-logic trace_update;
-logic trace_update_r;
-byte event_type;
-
-logic [`SCR1_XLEN-1:0] trace_pc;
-logic [`SCR1_XLEN-1:0] trace_npc;
-logic [`SCR1_IMEM_DWIDTH-1:0] trace_instr;
-
-type_scr1_csr_trace_s csr_trace1;
-
-// File handlers
-int unsigned trace_fhandler_core;
-
-// MPRF signals
-logic mprf_up;
-logic [`SCR1_MPRF_AWIDTH-1:0] mprf_addr;
-logic [`SCR1_XLEN-1:0] mprf_wdata;
-
-string hart;
-string test_name;
-
-`endif // SCR1_TRACE_LOG_EN
-
-//-------------------------------------------------------------------------------
-// Local tasks
-//-------------------------------------------------------------------------------
-
-`ifdef SCR1_TRACE_LOG_EN
-
-task trace_write_common;
- $fwrite(trace_fhandler_core, "%16d ", current_time);
- // $fwrite(trace_fhandler_core, " 0 ");
- $fwrite(trace_fhandler_core, " %s ", event_type);
- $fwrite(trace_fhandler_core, " %8x ", trace_pc);
- $fwrite(trace_fhandler_core, " %8x ", trace_instr);
- $fwrite(trace_fhandler_core, " %8x ", trace_npc);
-endtask // trace_write_common
-
-task trace_write_int_walias;
- case (mprf_addr)
- 0 : $fwrite(trace_fhandler_core, " x00_zero ");
- 1 : $fwrite(trace_fhandler_core, " x01_ra ");
- 2 : $fwrite(trace_fhandler_core, " x02_sp ");
- 3 : $fwrite(trace_fhandler_core, " x03_gp ");
- 4 : $fwrite(trace_fhandler_core, " x04_tp ");
- 5 : $fwrite(trace_fhandler_core, " x05_t0 ");
- 6 : $fwrite(trace_fhandler_core, " x06_t1 ");
- 7 : $fwrite(trace_fhandler_core, " x07_t2 ");
- 8 : $fwrite(trace_fhandler_core, " x08_s0 ");
- 9 : $fwrite(trace_fhandler_core, " x09_s1 ");
- 10 : $fwrite(trace_fhandler_core, " x10_a0 ");
- 11 : $fwrite(trace_fhandler_core, " x11_a1 ");
- 12 : $fwrite(trace_fhandler_core, " x12_a2 ");
- 13 : $fwrite(trace_fhandler_core, " x13_a3 ");
- 14 : $fwrite(trace_fhandler_core, " x14_a4 ");
- 15 : $fwrite(trace_fhandler_core, " x15_a5 ");
-`ifndef SCR1_RVE_EXT
- 16 : $fwrite(trace_fhandler_core, " x16_a6 ");
- 17 : $fwrite(trace_fhandler_core, " x17_a7 ");
- 18 : $fwrite(trace_fhandler_core, " x18_s2 ");
- 19 : $fwrite(trace_fhandler_core, " x19_s3 ");
- 20 : $fwrite(trace_fhandler_core, " x20_s4 ");
- 21 : $fwrite(trace_fhandler_core, " x21_s5 ");
- 22 : $fwrite(trace_fhandler_core, " x22_s6 ");
- 23 : $fwrite(trace_fhandler_core, " x23_s7 ");
- 24 : $fwrite(trace_fhandler_core, " x24_s8 ");
- 25 : $fwrite(trace_fhandler_core, " x25_s9 ");
- 26 : $fwrite(trace_fhandler_core, " x26_s10 ");
- 27 : $fwrite(trace_fhandler_core, " x27_s11 ");
- 28 : $fwrite(trace_fhandler_core, " x28_t3 ");
- 29 : $fwrite(trace_fhandler_core, " x29_t4 ");
- 30 : $fwrite(trace_fhandler_core, " x30_t5 ");
- 31 : $fwrite(trace_fhandler_core, " x31_t6 ");
-`endif // SCR1_RVE_EXT
- default: begin
- $fwrite(trace_fhandler_core, " xxx ");
- end
- endcase
-endtask
-
-`endif // SCR1_TRACE_LOG_EN
-
-//-------------------------------------------------------------------------------
-// MPRF Registers assignment
-//-------------------------------------------------------------------------------
-assign mprf_int_alias.INT_00_ZERO = '0;
-assign mprf_int_alias.INT_01_RA = mprf2trace_int_i[1];
-assign mprf_int_alias.INT_02_SP = mprf2trace_int_i[2];
-assign mprf_int_alias.INT_03_GP = mprf2trace_int_i[3];
-assign mprf_int_alias.INT_04_TP = mprf2trace_int_i[4];
-assign mprf_int_alias.INT_05_T0 = mprf2trace_int_i[5];
-assign mprf_int_alias.INT_06_T1 = mprf2trace_int_i[6];
-assign mprf_int_alias.INT_07_T2 = mprf2trace_int_i[7];
-assign mprf_int_alias.INT_08_S0 = mprf2trace_int_i[8];
-assign mprf_int_alias.INT_09_S1 = mprf2trace_int_i[9];
-assign mprf_int_alias.INT_10_A0 = mprf2trace_int_i[10];
-assign mprf_int_alias.INT_11_A1 = mprf2trace_int_i[11];
-assign mprf_int_alias.INT_12_A2 = mprf2trace_int_i[12];
-assign mprf_int_alias.INT_13_A3 = mprf2trace_int_i[13];
-assign mprf_int_alias.INT_14_A4 = mprf2trace_int_i[14];
-assign mprf_int_alias.INT_15_A5 = mprf2trace_int_i[15];
-`ifndef SCR1_RVE_EXT
-assign mprf_int_alias.INT_16_A6 = mprf2trace_int_i[16];
-assign mprf_int_alias.INT_17_A7 = mprf2trace_int_i[17];
-assign mprf_int_alias.INT_18_S2 = mprf2trace_int_i[18];
-assign mprf_int_alias.INT_19_S3 = mprf2trace_int_i[19];
-assign mprf_int_alias.INT_20_S4 = mprf2trace_int_i[20];
-assign mprf_int_alias.INT_21_S5 = mprf2trace_int_i[21];
-assign mprf_int_alias.INT_22_S6 = mprf2trace_int_i[22];
-assign mprf_int_alias.INT_23_S7 = mprf2trace_int_i[23];
-assign mprf_int_alias.INT_24_S8 = mprf2trace_int_i[24];
-assign mprf_int_alias.INT_25_S9 = mprf2trace_int_i[25];
-assign mprf_int_alias.INT_26_S10 = mprf2trace_int_i[26];
-assign mprf_int_alias.INT_27_S11 = mprf2trace_int_i[27];
-assign mprf_int_alias.INT_28_T3 = mprf2trace_int_i[28];
-assign mprf_int_alias.INT_29_T4 = mprf2trace_int_i[29];
-assign mprf_int_alias.INT_30_T5 = mprf2trace_int_i[30];
-assign mprf_int_alias.INT_31_T6 = mprf2trace_int_i[31];
-`endif // SCR1_RVE_EXT
-
-//-------------------------------------------------------------------------------
-// Legacy time counter
-//-------------------------------------------------------------------------------
-// The counter is left for compatibility with the current UVM environment
-
-int time_cnt;
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- time_cnt <= 0;
- end else begin
- time_cnt <= time_cnt + 1;
- end
-end
-
-//-------------------------------------------------------------------------------
-// Initial part pipeline tracelog
-//-------------------------------------------------------------------------------
-
-`ifdef SCR1_TRACE_LOG_EN
-// Files opening and writing initial header
-initial begin
- $timeformat(-9, 0, " ns", 10);
- #1 hart.hextoa(soc2pipe_fuse_mhartid_i);
-
- trace_fhandler_core = $fopen({"tracelog_core_", hart, ".log"}, "w");
-
- // Writing initial header
- $fwrite(trace_fhandler_core, "# RTL_ID %h\n", SCR1_CSR_MIMPID);
- $fwrite(trace_fhandler_core, "#\n");
- // $fwrite(trace_fhandler_core, "# R - return from trap:\n");
- // $fwrite(trace_fhandler_core, "# 1 - MRET\n");
- // $fwrite(trace_fhandler_core, "# 0 - no return\n");
- $fwrite(trace_fhandler_core, "# Events:\n");
- $fwrite(trace_fhandler_core, "# N - no event\n");
- $fwrite(trace_fhandler_core, "# E - exception\n");
- $fwrite(trace_fhandler_core, "# I - interrupt\n");
- $fwrite(trace_fhandler_core, "# W - wakeup\n");
-end
-
-// Core reset logging and header printing
-always @(posedge rst_n) begin
- $fwrite(trace_fhandler_core, "# =====================================================================================\n");
-`ifndef VERILATOR
- $fwrite(trace_fhandler_core, "# %14t : Core Reset\n", $time());
-`else
- $fwrite(trace_fhandler_core, "# : Core Reset\n");
-`endif
- $fwrite(trace_fhandler_core, "# =====================================================================================\n");
- $fwrite(trace_fhandler_core, "# Test: %s\n", test_name);
- $fwrite(trace_fhandler_core, "# Time ");
- // $fwrite(trace_fhandler_core, " R ");
- $fwrite(trace_fhandler_core, " Ev ");
- $fwrite(trace_fhandler_core, " Curr_PC ");
- $fwrite(trace_fhandler_core, " Instr ");
- $fwrite(trace_fhandler_core, " Next_PC ");
- $fwrite(trace_fhandler_core, " Reg ");
- $fwrite(trace_fhandler_core, " Value ");
- $fwrite(trace_fhandler_core, "\n");
- $fwrite(trace_fhandler_core, "# =====================================================================================\n");
-end
-
-//-------------------------------------------------------------------------------
-// Common trace part
-//-------------------------------------------------------------------------------
-
-assign trace_flag = 1'b1;
-assign trace_update = (exu2trace_update_pc_en_i | mprf2trace_wr_en_i) & trace_flag;
-
-always_ff @(posedge clk) begin
- if (~rst_n) begin
- current_time <= 0;
- event_type <= "N";
-
- trace_pc <= 'x;
- trace_npc <= 'x;
- trace_instr <= 'x;
-
- trace_update_r <= 1'b0;
-
- mprf_up <= '0;
- mprf_addr <= '0;
- mprf_wdata <= '0;
- end else begin
- trace_update_r <= trace_update;
- if (trace_update) begin
-`ifdef VERILATOR
- current_time <= time_cnt;
-`else
- current_time <= $time();
-`endif
- trace_pc <= trace_npc;
- trace_npc <= exu2trace_update_pc_i;
- trace_instr <= ifu2trace_instr_i;
-
- if (csr2trace_e_exc_i) begin
- // Exception
- event_type <= "E";
- end
- else if (csr2trace_e_irq_i) begin
- // IRQ
- event_type <= "I";
- end
- else if (pipe2trace_e_wake_i) begin
- // Wake
- event_type <= "W";
- end
- // if (csr2trace_e_mret_i) begin
- // // MRET
- // event_type <= "R";
- // end
- else begin
- // No event
- event_type <= "N";
- end
- end
-
- // Write log signals
- mprf_up <= mprf2trace_wr_en_i;
- mprf_addr <= mprf2trace_wr_en_i ? mprf2trace_wr_addr_i : 'x;
- mprf_wdata <= mprf2trace_wr_en_i ? mprf2trace_wr_data_i : 'x;
- end
-end
-
-//-------------------------------------------------------------------------------
-// Core MPRF logging
-//-------------------------------------------------------------------------------
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- end else begin
- if (trace_update_r) begin
-
- trace_write_common();
-
- case (event_type)
- "W" : begin
- // Wakeup
- if (csr_trace1.mip & csr_trace1.mie) begin
- $fwrite(trace_fhandler_core, " mip %08x\n", csr_trace1.mip );
- trace_write_common();
- $fwrite(trace_fhandler_core, " mie %08x", csr_trace1.mie );
- end
- end
- "N" : begin
- // Regular
- if (mprf_up && mprf_addr != 0) begin
- // $fwrite(trace_fhandler_core, " x%2d %08x", mprf_addr, mprf_wdata);
- trace_write_int_walias();
- $fwrite(trace_fhandler_core, " %08x", mprf_wdata);
- end else begin
- $fwrite(trace_fhandler_core, " --- --------");
- end
- end
- "R" : begin
- // MRET
- $fwrite(trace_fhandler_core, " mstatus %08x", csr_trace1.mstatus);
- end
- "E", "I": begin
- // IRQ/Exception
- $fwrite(trace_fhandler_core, " mstatus %08x\n", csr_trace1.mstatus);
- trace_write_common();
- $fwrite(trace_fhandler_core, " mepc %08x\n", csr_trace1.mepc);
- trace_write_common();
- $fwrite(trace_fhandler_core, " mcause %08x\n", csr_trace1.mcause);
- trace_write_common();
- $fwrite(trace_fhandler_core, " mtval %08x", csr_trace1.mtval);
- end
- default : begin
- $fwrite(trace_fhandler_core, "\n");
- end
- endcase
- $fwrite(trace_fhandler_core, "\n");
- end
- end
-end
-
-//-------------------------------------------------------------------------------
-// Core CSR logging
-//-------------------------------------------------------------------------------
-
-always_comb begin
- csr_trace1.mtvec = {csr2trace_mtvec_base_i, 4'd0, 2'(csr2trace_mtvec_mode_i)};
- csr_trace1.mepc =
-`ifdef SCR1_RVC_EXT
- {csr2trace_mepc_i, 1'b0};
-`else // SCR1_RVC_EXT
- {csr2trace_mepc_i, 2'b00};
-`endif // SCR1_RVC_EXT
- csr_trace1.mcause = {csr2trace_mcause_irq_i, csr2trace_mcause_ec_i};
- csr_trace1.mtval = csr2trace_mtval_i;
-
- csr_trace1.mstatus = '0;
- csr_trace1.mie = '0;
- csr_trace1.mip = '0;
-
- csr_trace1.mstatus[SCR1_CSR_MSTATUS_MIE_OFFSET] = csr2trace_mstatus_mie_i;
- csr_trace1.mstatus[SCR1_CSR_MSTATUS_MPIE_OFFSET] = csr2trace_mstatus_mpie_i;
- csr_trace1.mstatus[SCR1_CSR_MSTATUS_MPP_OFFSET+1:SCR1_CSR_MSTATUS_MPP_OFFSET] = SCR1_CSR_MSTATUS_MPP;
- csr_trace1.mie[SCR1_CSR_MIE_MSIE_OFFSET] = csr2trace_mie_msie_i;
- csr_trace1.mie[SCR1_CSR_MIE_MTIE_OFFSET] = csr2trace_mie_mtie_i;
- csr_trace1.mie[SCR1_CSR_MIE_MEIE_OFFSET] = csr2trace_mie_meie_i;
- csr_trace1.mip[SCR1_CSR_MIE_MSIE_OFFSET] = csr2trace_mip_msip_i;
- csr_trace1.mip[SCR1_CSR_MIE_MTIE_OFFSET] = csr2trace_mip_mtip_i;
- csr_trace1.mip[SCR1_CSR_MIE_MEIE_OFFSET] = csr2trace_mip_meip_i;
-end
-
-`endif // SCR1_TRACE_LOG_EN
-
-endmodule : scr1_tracelog
-
-`endif // SCR1_TRGT_SIMULATION
diff --git a/verilog/rtl/syntacore/scr1/src/core/primitives/scr1_cg.sv b/verilog/rtl/syntacore/scr1/src/core/primitives/scr1_cg.sv
deleted file mode 100644
index edc513b..0000000
--- a/verilog/rtl/syntacore/scr1/src/core/primitives/scr1_cg.sv
+++ /dev/null
@@ -1,48 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_cg.sv>
-/// @brief SCR1 clock gate primitive
-///
-
-`include "scr1_arch_description.svh"
-
-`ifdef SCR1_CLKCTRL_EN
-module scr1_cg (
- input logic clk,
- input logic clk_en,
- input logic test_mode,
- output logic clk_out
-);
-
-// The code below is a clock gate model for simulation.
-// For synthesis, it should be replaced by implementation-specific
-// clock gate code.
-
-logic latch_en;
-
-always_latch begin
- if (~clk) begin
- latch_en <= test_mode | clk_en;
- end
-end
-
-assign clk_out = latch_en & clk;
-
-endmodule : scr1_cg
-
-`endif // SCR1_CLKCTRL_EN
diff --git a/verilog/rtl/syntacore/scr1/src/core/primitives/scr1_reset_cells.sv b/verilog/rtl/syntacore/scr1/src/core/primitives/scr1_reset_cells.sv
deleted file mode 100644
index f7eadfa..0000000
--- a/verilog/rtl/syntacore/scr1/src/core/primitives/scr1_reset_cells.sv
+++ /dev/null
@@ -1,247 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_sync_rstn.sv>
-/// @brief Cells for reset handling
-///
-
-//--------------------------------------------------------------------
-// Reset Buffer Cell
-//--------------------------------------------------------------------
-module scr1_reset_buf_cell (
- input logic rst_n,
- input logic clk,
- input logic test_mode,
- input logic test_rst_n,
- input logic reset_n_in,
- output logic reset_n_out,
- output logic reset_n_status
-);
-
-logic reset_n_ff;
-logic reset_n_status_ff;
-logic rst_n_mux;
-
-assign rst_n_mux = (test_mode == 1'b1) ? test_rst_n : rst_n;
-
-always_ff @(negedge rst_n_mux, posedge clk) begin
- if (~rst_n_mux) begin
- reset_n_ff <= 1'b0;
- end else begin
- reset_n_ff <= reset_n_in;
- end
-end
-
-assign reset_n_out = (test_mode == 1'b1) ? test_rst_n : reset_n_ff;
-
-always_ff @(negedge rst_n_mux, posedge clk) begin
- if (~rst_n_mux) begin
- reset_n_status_ff <= 1'b0;
- end else begin
- reset_n_status_ff <= reset_n_in;
- end
-end
-assign reset_n_status = reset_n_status_ff;
-
-endmodule : scr1_reset_buf_cell
-
-//--------------------------------------------------------------------
-// Reset CDC Synchronization Cell
-//--------------------------------------------------------------------
-module scr1_reset_sync_cell #(
- parameter int unsigned STAGES_AMOUNT = 2
-) (
- input logic rst_n,
- input logic clk,
- input logic test_rst_n,
- input logic test_mode,
- input logic rst_n_in,
- output logic rst_n_out
-);
-
-logic [STAGES_AMOUNT-1:0] rst_n_dff;
-logic local_rst_n_in;
-
-assign local_rst_n_in = (test_mode == 1'b1) ? test_rst_n : rst_n;
-
-generate
-
-if (STAGES_AMOUNT == 1)
-
-begin : gen_reset_sync_cell_single
- always_ff @(negedge local_rst_n_in, posedge clk) begin
- if (~local_rst_n_in) begin
- rst_n_dff <= 1'b0;
- end else begin
- rst_n_dff <= rst_n_in;
- end
- end
-end : gen_reset_sync_cell_single
-
-else // STAGES_AMOUNT > 1
-
-begin : gen_reset_sync_cell_multi
- always_ff @(negedge local_rst_n_in, posedge clk)
- begin
- if (~local_rst_n_in) begin
- rst_n_dff <= '0;
- end else begin
- rst_n_dff <= {rst_n_dff[STAGES_AMOUNT-2:0], rst_n_in};
- end
- end
-end : gen_reset_sync_cell_multi
-
-endgenerate
-
-assign rst_n_out = (test_mode == 1'b1) ? test_rst_n : rst_n_dff[STAGES_AMOUNT-1];
-
-endmodule : scr1_reset_sync_cell
-
-//--------------------------------------------------------------------
-// Data CDC/RDC Synchronization Cell
-//--------------------------------------------------------------------
-module scr1_data_sync_cell #(
- parameter int unsigned STAGES_AMOUNT = 1
-) (
- input logic rst_n,
- input logic clk,
- input logic data_in,
- output logic data_out
-);
-
-logic [STAGES_AMOUNT-1:0] data_dff;
-
-generate
-
-if (STAGES_AMOUNT == 1)
-
-begin : gen_data_sync_cell_single
- always_ff @(negedge rst_n, posedge clk)
- begin
- if (~rst_n) begin
- data_dff <= 1'b0;
- end else begin
- data_dff <= data_in;
- end
- end
-end : gen_data_sync_cell_single
-
-else // STAGES_AMOUNT > 1
-
-begin : gen_data_sync_cell_multi
- always_ff @(negedge rst_n, posedge clk)
- begin
- if (~rst_n) begin
- data_dff <= '0;
- end else begin
- data_dff <= {data_dff[STAGES_AMOUNT-2:0], data_in};
- end
- end
-end : gen_data_sync_cell_multi
-
-endgenerate
-
-assign data_out = data_dff[STAGES_AMOUNT-1];
-
-endmodule : scr1_data_sync_cell
-
-//--------------------------------------------------------------------
-// Reset / RDC Qualifyer Adapter Cell
-// (Reset Generation Cell w/ RDC Qualifyer Adaptation circuitry)
-//--------------------------------------------------------------------
-// Total stages amount =
-// 1 Front Sync stage \
-// + 1 (delay introduced by the reset output buffer register)
-//--------------------------------------------------------------------
-module scr1_reset_qlfy_adapter_cell_sync (
- input logic rst_n,
- input logic clk,
- input logic test_rst_n,
- input logic test_mode,
- input logic reset_n_in_sync,
- output logic reset_n_out_qlfy,
- output logic reset_n_out,
- output logic reset_n_status
-);
-
-logic rst_n_mux;
-logic reset_n_front_ff;
-
-// Front sync stage
-assign rst_n_mux = (test_mode == 1'b1) ? test_rst_n : rst_n;
-
-always_ff @(negedge rst_n_mux, posedge clk) begin
- if (~rst_n_mux) begin
- reset_n_front_ff <= 1'b0;
- end else begin
- reset_n_front_ff <= reset_n_in_sync;
- end
-end
-
-// Sync reset output for all reset qualifier chains targeting this reset domain
-// (for reset-domain-crossings with the given reset domain as a destination).
-assign reset_n_out_qlfy = reset_n_front_ff;
-
-// Reset output buffer
-scr1_reset_buf_cell
-i_reset_output_buf (
- .rst_n (rst_n),
- .clk (clk),
- .test_mode (test_mode),
- .test_rst_n (test_rst_n),
- .reset_n_in (reset_n_front_ff),
- .reset_n_out (reset_n_out),
- .reset_n_status (reset_n_status)
-);
-
-endmodule : scr1_reset_qlfy_adapter_cell_sync
-
-module scr1_reset_and2_cell (
- input logic [1:0] rst_n_in,
- input logic test_rst_n,
- input logic test_mode,
- output logic rst_n_out
-);
-
-assign rst_n_out = (test_mode == 1'b1) ? test_rst_n : (&rst_n_in);
-
-endmodule : scr1_reset_and2_cell
-
-
-module scr1_reset_and3_cell (
- input logic [2:0] rst_n_in,
- input logic test_rst_n,
- input logic test_mode,
- output logic rst_n_out
-);
-
-assign rst_n_out = (test_mode == 1'b1) ? test_rst_n : (&rst_n_in);
-
-endmodule : scr1_reset_and3_cell
-
-
-module scr1_reset_mux2_cell (
- input logic [1:0] rst_n_in,
- input logic select,
- input logic test_rst_n,
- input logic test_mode,
- output logic rst_n_out
-);
-
-assign rst_n_out = (test_mode == 1'b1) ? test_rst_n : rst_n_in[select];
-
-endmodule : scr1_reset_mux2_cell
diff --git a/verilog/rtl/syntacore/scr1/src/core/scr1_clk_ctrl.sv b/verilog/rtl/syntacore/scr1/src/core/scr1_clk_ctrl.sv
deleted file mode 100644
index 62fc837..0000000
--- a/verilog/rtl/syntacore/scr1/src/core/scr1_clk_ctrl.sv
+++ /dev/null
@@ -1,71 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_clk_ctrl.sv>
-/// @brief SCR1 clock control
-///
-
-`include "scr1_arch_description.svh"
-
-`ifdef SCR1_CLKCTRL_EN
-module scr1_clk_ctrl (
- input logic clk, // Clock control module clock
- input logic rst_n, // Clock control module reset
- input logic test_mode, // DFT Test Mode
- input logic test_rst_n, // DFT Test reset
-
- input logic pipe2clkctl_sleep_req_i, // CLK disable request from pipe
- input logic pipe2clkctl_wake_req_i, // CLK enable request from pipe
-
- output logic clkctl2pipe_clk_alw_on_o, // Not gated pipe CLK
- output logic clkctl2pipe_clk_o, // Gated pipe
- output logic clkctl2pipe_clk_en_o, // CLK enabled flag
- output logic clkctl2pipe_clk_dbgc_o // CLK for pipe debug subsystem
-);
-
-logic ctrl_rst_n;
-
-assign clkctl2pipe_clk_alw_on_o = clk;
-assign clkctl2pipe_clk_dbgc_o = clk;
-assign ctrl_rst_n = (test_mode) ? test_rst_n : rst_n;
-
-always_ff @(posedge clk, negedge ctrl_rst_n) begin
- if (~ctrl_rst_n) begin
- clkctl2pipe_clk_en_o <= 1'b1;
- end else begin
- if (clkctl2pipe_clk_en_o) begin
- if (pipe2clkctl_sleep_req_i & ~pipe2clkctl_wake_req_i) begin
- clkctl2pipe_clk_en_o <= 1'b0;
- end
- end else begin // ~clkctl2pipe_clk_en_o
- if (pipe2clkctl_wake_req_i) begin
- clkctl2pipe_clk_en_o <= 1'b1;
- end
- end // pipeline
- end
-end
-
-scr1_cg i_scr1_cg_pipe (
- .clk (clk ),
- .clk_en (clkctl2pipe_clk_en_o),
- .test_mode (test_mode ),
- .clk_out (clkctl2pipe_clk_o )
-);
-
-endmodule : scr1_clk_ctrl
-
-`endif // SCR1_CLKCTRL_EN
diff --git a/verilog/rtl/syntacore/scr1/src/core/scr1_core_top.sv b/verilog/rtl/syntacore/scr1/src/core/scr1_core_top.sv
deleted file mode 100644
index 92bbb10..0000000
--- a/verilog/rtl/syntacore/scr1/src/core/scr1_core_top.sv
+++ /dev/null
@@ -1,537 +0,0 @@
-///////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_core_top.sv>
-/// @brief SCR1 core top
-///
-
-`include "scr1_arch_description.svh"
-`include "scr1_arch_types.svh"
-`include "scr1_memif.svh"
-
-`ifdef SCR1_DBG_EN
-`include "scr1_tapc.svh"
-`include "scr1_dm.svh"
-`include "scr1_hdu.svh"
-`endif // SCR1_DBG_EN
-
-`ifdef SCR1_IPIC_EN
-`include "scr1_ipic.svh"
-`endif // SCR1_IPIC_EN
-
-module scr1_core_top (
- // Common
- input logic pwrup_rst_n, // Power-Up reset
- input logic rst_n, // Regular reset
- input logic cpu_rst_n, // CPU reset
- input logic test_mode, // DFT Test Mode
- input logic test_rst_n, // DFT Test Reset
- input logic clk, // Core clock
- output logic core_rst_n_o, // Core reset
- output logic core_rdc_qlfy_o, // Core RDC qualifier
- output logic [48:0] core_debug ,
-`ifdef SCR1_DBG_EN
- output logic sys_rst_n_o, // System reset
- output logic sys_rdc_qlfy_o, // System RDC qualifier
-`endif // SCR1_DBG_EN
-
- // Fuses
- input logic [`SCR1_XLEN-1:0] core_fuse_mhartid_i, // Fuse MHARTID value
-`ifdef SCR1_DBG_EN
- input logic [31:0] tapc_fuse_idcode_i, // Fuse IDCODE value
-`endif // SCR1_DBG_EN
-
- // IRQ
-`ifdef SCR1_IPIC_EN
- input logic [SCR1_IRQ_LINES_NUM-1:0] core_irq_lines_i, // External interrupt request lines
-`else
- input logic core_irq_ext_i, // External interrupt request
-`endif // SCR1_IPIC_EN
- input logic core_irq_soft_i, // Software generated interrupt request
- input logic core_irq_mtimer_i, // Machine timer interrupt request
-
- // Memory-mapped external timer
- input logic [63:0] core_mtimer_val_i, // Machine timer value
-
-`ifdef SCR1_DBG_EN
- // Debug Interface
- input logic tapc_trst_n, // Test Reset (TRSTn)
- input logic tapc_tck, // Test Clock (TCK)
- input logic tapc_tms, // Test Mode Select (TMS)
- input logic tapc_tdi, // Test Data Input (TDI)
- output logic tapc_tdo, // Test Data Output (TDO)
- output logic tapc_tdo_en, // TDO Enable, signal for TDO buffer control
-`endif // SCR1_DBG_EN
-
- // Instruction Memory Interface
- input logic imem2core_req_ack_i, // IMEM request acknowledge
- output logic core2imem_req_o, // IMEM request
- output logic core2imem_cmd_o, // IMEM command
- output logic [`SCR1_IMEM_AWIDTH-1:0] core2imem_addr_o, // IMEM address
- input logic [`SCR1_IMEM_DWIDTH-1:0] imem2core_rdata_i, // IMEM read data
- input logic [1:0] imem2core_resp_i, // IMEM response
-
- // Data Memory Interface
- input logic dmem2core_req_ack_i, // DMEM request acknowledge
- output logic core2dmem_req_o, // DMEM request
- output logic core2dmem_cmd_o, // DMEM command
- output logic[1:0] core2dmem_width_o, // DMEM data width
- output logic [`SCR1_DMEM_AWIDTH-1:0] core2dmem_addr_o, // DMEM address
- output logic [`SCR1_DMEM_DWIDTH-1:0] core2dmem_wdata_o, // DMEM write data
- input logic [`SCR1_DMEM_DWIDTH-1:0] dmem2core_rdata_i, // DMEM read data
- input logic [1:0] dmem2core_resp_i // DMEM response
-);
-
-//-------------------------------------------------------------------------------
-// Local parameters
-//-------------------------------------------------------------------------------
-localparam int unsigned SCR1_CORE_TOP_RST_SYNC_STAGES_NUM = 2;
-
-//-------------------------------------------------------------------------------
-// Local signals declaration
-//-------------------------------------------------------------------------------
-
-// Reset Logic
-`ifdef SCR1_DBG_EN
-`else // SCR1_DBG_EN
-logic core_rst_n_in_sync;
-logic core_rst_n_qlfy;
-logic core_rst_n_status;
-`endif // SCR1_DBG_EN
-logic core_rst_n;
-logic core_rst_n_status_sync;
-logic core_rst_status;
-logic core2hdu_rdc_qlfy;
-logic core2dm_rdc_qlfy;
-logic pwrup_rst_n_sync;
-logic rst_n_sync;
-logic cpu_rst_n_sync;
-
-`ifdef SCR1_DBG_EN
-// TAPC-DM Interface
-logic tapc_dmi_ch_sel;
-logic [SCR1_DBG_DMI_CH_ID_WIDTH-1:0] tapc_dmi_ch_id;
-logic tapc_dmi_ch_capture;
-logic tapc_dmi_ch_shift;
-logic tapc_dmi_ch_update;
-logic tapc_dmi_ch_tdi;
-logic tapc_dmi_ch_tdo;
-//
-logic tapc_dmi_ch_sel_tapout;
-logic [SCR1_DBG_DMI_CH_ID_WIDTH-1:0] tapc_dmi_ch_id_tapout;
-logic tapc_dmi_ch_capture_tapout;
-logic tapc_dmi_ch_shift_tapout;
-logic tapc_dmi_ch_update_tapout;
-logic tapc_dmi_ch_tdi_tapout;
-logic tapc_dmi_ch_tdo_tapin;
-//
-logic dmi_req;
-logic dmi_wr;
-logic [SCR1_DBG_DMI_ADDR_WIDTH-1:0] dmi_addr;
-logic [SCR1_DBG_DMI_DATA_WIDTH-1:0] dmi_wdata;
-logic dmi_resp;
-logic [SCR1_DBG_DMI_DATA_WIDTH-1:0] dmi_rdata;
-// TAPC-SCU Interface
-logic tapc_scu_ch_sel;
-logic tapc_scu_ch_sel_tapout;
-logic tapc_scu_ch_tdo;
-logic tapc_ch_tdo;
-// SCU nets
-logic sys_rst_n;
-logic sys_rst_status;
-logic hdu_rst_n;
-logic hdu2dm_rdc_qlfy;
-logic ndm_rst_n;
-logic dm_rst_n;
-logic hart_rst_n;
-`endif // SCR1_DBG_EN
-
-`ifdef SCR1_DBG_EN
-// DM-Pipeline Interface
-// HART Run Control i/f
-logic dm_active;
-logic dm_cmd_req;
-type_scr1_hdu_dbgstates_e dm_cmd;
-logic dm_cmd_resp;
-logic dm_cmd_resp_qlfy;
-logic dm_cmd_rcode;
-logic dm_hart_event;
-logic dm_hart_event_qlfy;
-type_scr1_hdu_hartstatus_s dm_hart_status;
-type_scr1_hdu_hartstatus_s dm_hart_status_qlfy;
-// Program Buffer - HART instruction execution i/f
-logic [SCR1_HDU_PBUF_ADDR_WIDTH-1:0] dm_pbuf_addr;
-logic [SCR1_HDU_PBUF_ADDR_WIDTH-1:0] dm_pbuf_addr_qlfy;
-logic [SCR1_HDU_CORE_INSTR_WIDTH-1:0] dm_pbuf_instr;
-// HART Abstract Data regs i/f
-logic dm_dreg_req;
-logic dm_dreg_req_qlfy;
-logic dm_dreg_wr;
-logic [SCR1_HDU_DATA_REG_WIDTH-1:0] dm_dreg_wdata;
-logic dm_dreg_resp;
-logic dm_dreg_fail;
-logic [SCR1_HDU_DATA_REG_WIDTH-1:0] dm_dreg_rdata;
-
-logic [`SCR1_XLEN-1 : 0] dm_pc_sample;
-logic [`SCR1_XLEN-1 : 0] dm_pc_sample_qlfy;
-`endif // SCR1_DBG_EN
-
-`ifdef SCR1_CLKCTRL_EN
-// Global clock gating logic
-logic sleep_pipe;
-logic wake_pipe;
-logic clk_pipe;
-logic clk_pipe_en;
-logic clk_dbgc;
-logic clk_alw_on;
-`endif // SCR1_CLKCTRL_EN
-
-
-//-------------------------------------------------------------------------------
-// Reset Logic
-//-------------------------------------------------------------------------------
-`ifdef SCR1_DBG_EN
-scr1_scu i_scu (
- // Global signals
- .pwrup_rst_n (pwrup_rst_n ),
- .rst_n (rst_n ),
- .cpu_rst_n (cpu_rst_n ),
- .test_mode (test_mode ),
- .test_rst_n (test_rst_n ),
- .clk (clk ),
-
- // TAPC scan-chains
- .tapcsync2scu_ch_sel_i (tapc_scu_ch_sel ),
- .tapcsync2scu_ch_id_i ('0 ),
- .tapcsync2scu_ch_capture_i (tapc_dmi_ch_capture),
- .tapcsync2scu_ch_shift_i (tapc_dmi_ch_shift ),
- .tapcsync2scu_ch_update_i (tapc_dmi_ch_update ),
- .tapcsync2scu_ch_tdi_i (tapc_dmi_ch_tdi ),
- .scu2tapcsync_ch_tdo_o (tapc_scu_ch_tdo ),
-
- // Input sync resets:
- .ndm_rst_n_i (ndm_rst_n ),
- .hart_rst_n_i (hart_rst_n ),
-
- // Generated resets
- .sys_rst_n_o (sys_rst_n ),
- .core_rst_n_o (core_rst_n ),
- .dm_rst_n_o (dm_rst_n ),
- .hdu_rst_n_o (hdu_rst_n ),
-
- // Resets statuses
- .sys_rst_status_o (sys_rst_status ),
- .core_rst_status_o (core_rst_status ),
-
- // Reset Domain Crossing (RDC) qualifiers
- .sys_rdc_qlfy_o (sys_rdc_qlfy_o ),
- .core_rdc_qlfy_o (core_rdc_qlfy_o ),
- .core2hdu_rdc_qlfy_o (core2hdu_rdc_qlfy ),
- .core2dm_rdc_qlfy_o (core2dm_rdc_qlfy ),
- .hdu2dm_rdc_qlfy_o (hdu2dm_rdc_qlfy )
-);
-
-assign sys_rst_n_o = sys_rst_n;
-
-// Reset inputs are assumed synchronous
-assign pwrup_rst_n_sync = pwrup_rst_n;
-
-`else // SCR1_DBG_EN
-
-// Reset inputs are assumed synchronous
-assign pwrup_rst_n_sync = pwrup_rst_n;
-assign rst_n_sync = rst_n;
-assign cpu_rst_n_sync = cpu_rst_n;
-assign core_rst_n_in_sync = rst_n_sync & cpu_rst_n_sync;
-
-// Core Reset: core_rst_n
-scr1_reset_qlfy_adapter_cell_sync i_core_rstn_qlfy_adapter_cell_sync (
- .rst_n (pwrup_rst_n_sync ),
- .clk (clk ),
- .test_rst_n (test_rst_n ),
- .test_mode (test_mode ),
- .reset_n_in_sync (core_rst_n_in_sync),
- .reset_n_out_qlfy (core_rst_n_qlfy ),
- .reset_n_out (core_rst_n ),
- .reset_n_status (core_rst_n_status )
-);
-
-scr1_data_sync_cell #(
- .STAGES_AMOUNT (SCR1_CORE_TOP_RST_SYNC_STAGES_NUM)
-) i_core_rstn_status_sync (
- .rst_n (pwrup_rst_n_sync ),
- .clk (clk ),
- .data_in (core_rst_n_status ),
- .data_out (core_rst_n_status_sync)
-);
-
-assign core_rst_status = ~core_rst_n_status_sync;
-assign core_rdc_qlfy_o = core_rst_n_qlfy;
-
-`endif // SCR1_DBG_EN
-assign core_rst_n_o = core_rst_n;
-
-//-------------------------------------------------------------------------------
-// SCR1 pipeline
-//-------------------------------------------------------------------------------
-scr1_pipe_top i_pipe_top (
- // Control
- .pipe_rst_n (core_rst_n ),
- .pipe_debug (core_debug ),
-`ifdef SCR1_DBG_EN
- .pipe2hdu_rdc_qlfy_i (core2hdu_rdc_qlfy ),
- .dbg_rst_n (hdu_rst_n ),
-`endif // SCR1_DBG_EN
-`ifndef SCR1_CLKCTRL_EN
- .clk (clk ),
-`else // SCR1_CLKCTRL_EN
- .clk (clk_pipe ),
- .pipe2clkctl_sleep_req_o (sleep_pipe ),
- .pipe2clkctl_wake_req_o (wake_pipe ),
- .clkctl2pipe_clk_alw_on_i (clk_alw_on ),
- .clkctl2pipe_clk_dbgc_i (clk_dbgc ),
- .clkctl2pipe_clk_en_i (clk_pipe_en ),
-`endif // SCR1_CLKCTRL_EN
-
- // Instruction memory interface
- .pipe2imem_req_o (core2imem_req_o ),
- .pipe2imem_cmd_o (core2imem_cmd_o ),
- .pipe2imem_addr_o (core2imem_addr_o ),
- .imem2pipe_req_ack_i (imem2core_req_ack_i ),
- .imem2pipe_rdata_i (imem2core_rdata_i ),
- .imem2pipe_resp_i (imem2core_resp_i ),
-
- // Data memory interface
- .pipe2dmem_req_o (core2dmem_req_o ),
- .pipe2dmem_cmd_o (core2dmem_cmd_o ),
- .pipe2dmem_width_o (core2dmem_width_o ),
- .pipe2dmem_addr_o (core2dmem_addr_o ),
- .pipe2dmem_wdata_o (core2dmem_wdata_o ),
- .dmem2pipe_req_ack_i (dmem2core_req_ack_i ),
- .dmem2pipe_rdata_i (dmem2core_rdata_i ),
- .dmem2pipe_resp_i (dmem2core_resp_i ),
-
-`ifdef SCR1_DBG_EN
- // Debug interface:
- .dbg_en (1'b1 ),
- // Debug interface:
- // DM <-> Pipeline: HART Run Control i/f
- .dm2pipe_active_i (dm_active ),
- .dm2pipe_cmd_req_i (dm_cmd_req ),
- .dm2pipe_cmd_i (dm_cmd ),
- .pipe2dm_cmd_resp_o (dm_cmd_resp ),
- .pipe2dm_cmd_rcode_o (dm_cmd_rcode ),
- .pipe2dm_hart_event_o (dm_hart_event ),
- .pipe2dm_hart_status_o (dm_hart_status ),
-
- // DM <-> Pipeline: Program Buffer - HART instruction execution i/f
- .pipe2dm_pbuf_addr_o (dm_pbuf_addr ),
- .dm2pipe_pbuf_instr_i (dm_pbuf_instr ),
-
- // DM <-> Pipeline: HART Abstract Data regs i/f
- .pipe2dm_dreg_req_o (dm_dreg_req ),
- .pipe2dm_dreg_wr_o (dm_dreg_wr ),
- .pipe2dm_dreg_wdata_o (dm_dreg_wdata ),
- .dm2pipe_dreg_resp_i (dm_dreg_resp ),
- .dm2pipe_dreg_fail_i (dm_dreg_fail ),
- .dm2pipe_dreg_rdata_i (dm_dreg_rdata ),
-
- // DM <-> Pipeline: PC i/f
- .pipe2dm_pc_sample_o (dm_pc_sample ),
-`endif // SCR1_DBG_EN
-
- // IRQ
-`ifdef SCR1_IPIC_EN
- .soc2pipe_irq_lines_i (core_irq_lines_i ),
-`else // SCR1_IPIC_EN
- .soc2pipe_irq_ext_i (core_irq_ext_i ),
-`endif // SCR1_IPIC_EN
- .soc2pipe_irq_soft_i (core_irq_soft_i ),
- .soc2pipe_irq_mtimer_i (core_irq_mtimer_i ),
-
- // Memory-mapped external timer
- .soc2pipe_mtimer_val_i (core_mtimer_val_i ),
-
- // Fuse
- .soc2pipe_fuse_mhartid_i (core_fuse_mhartid_i )
-);
-
-
-`ifdef SCR1_DBG_EN
-//-------------------------------------------------------------------------------
-// TAP Controller (TAPC)
-//-------------------------------------------------------------------------------
-scr1_tapc i_tapc (
- // JTAG signals
- .tapc_trst_n (tapc_trst_n ),
- .tapc_tck (tapc_tck ),
- .tapc_tms (tapc_tms ),
- .tapc_tdi (tapc_tdi ),
- .tapc_tdo (tapc_tdo ),
- .tapc_tdo_en (tapc_tdo_en ),
-
- // Fuses
- .soc2tapc_fuse_idcode_i (tapc_fuse_idcode_i ),
-
- // DMI/SCU scan-chains
- .tapc2tapcsync_scu_ch_sel_o (tapc_scu_ch_sel_tapout ),
- .tapc2tapcsync_dmi_ch_sel_o (tapc_dmi_ch_sel_tapout ),
- .tapc2tapcsync_ch_id_o (tapc_dmi_ch_id_tapout ),
- .tapc2tapcsync_ch_capture_o (tapc_dmi_ch_capture_tapout),
- .tapc2tapcsync_ch_shift_o (tapc_dmi_ch_shift_tapout ),
- .tapc2tapcsync_ch_update_o (tapc_dmi_ch_update_tapout ),
- .tapc2tapcsync_ch_tdi_o (tapc_dmi_ch_tdi_tapout ),
- .tapcsync2tapc_ch_tdo_i (tapc_dmi_ch_tdo_tapin )
-);
-
-scr1_tapc_synchronizer i_tapc_synchronizer (
- // System common signals
- .pwrup_rst_n (pwrup_rst_n_sync ),
- .dm_rst_n (dm_rst_n ),
- .clk (clk ),
-
- // JTAG common signals
- .tapc_trst_n (tapc_trst_n ),
- .tapc_tck (tapc_tck ),
-
- // DMI/SCU scan-chains
- .tapc2tapcsync_scu_ch_sel_i (tapc_scu_ch_sel_tapout ),
- .tapcsync2scu_ch_sel_o (tapc_scu_ch_sel ),
- .tapc2tapcsync_dmi_ch_sel_i (tapc_dmi_ch_sel_tapout ),
- .tapcsync2dmi_ch_sel_o (tapc_dmi_ch_sel ),
-
- .tapc2tapcsync_ch_id_i (tapc_dmi_ch_id_tapout ),
- .tapcsync2core_ch_id_o (tapc_dmi_ch_id ),
- .tapc2tapcsync_ch_capture_i (tapc_dmi_ch_capture_tapout),
- .tapcsync2core_ch_capture_o (tapc_dmi_ch_capture ),
- .tapc2tapcsync_ch_shift_i (tapc_dmi_ch_shift_tapout ),
- .tapcsync2core_ch_shift_o (tapc_dmi_ch_shift ),
- .tapc2tapcsync_ch_update_i (tapc_dmi_ch_update_tapout ),
- .tapcsync2core_ch_update_o (tapc_dmi_ch_update ),
- .tapc2tapcsync_ch_tdi_i (tapc_dmi_ch_tdi_tapout ),
- .tapcsync2core_ch_tdi_o (tapc_dmi_ch_tdi ),
- .tapc2tapcsync_ch_tdo_i (tapc_dmi_ch_tdo_tapin ),
- .tapcsync2core_ch_tdo_o (tapc_ch_tdo )
-);
-assign tapc_ch_tdo = (tapc_scu_ch_tdo & tapc_scu_ch_sel)
- | (tapc_dmi_ch_tdo & tapc_dmi_ch_sel);
-
-scr1_dmi i_dmi (
- .rst_n (dm_rst_n ),
- .clk (clk ),
-
- // TAP scan-chains
- .tapcsync2dmi_ch_sel_i (tapc_dmi_ch_sel ),
- .tapcsync2dmi_ch_id_i (tapc_dmi_ch_id ),
- .tapcsync2dmi_ch_capture_i (tapc_dmi_ch_capture),
- .tapcsync2dmi_ch_shift_i (tapc_dmi_ch_shift ),
- .tapcsync2dmi_ch_update_i (tapc_dmi_ch_update ),
- .tapcsync2dmi_ch_tdi_i (tapc_dmi_ch_tdi ),
- .dmi2tapcsync_ch_tdo_o (tapc_dmi_ch_tdo ),
-
- // DMI
- .dm2dmi_resp_i (dmi_resp ),
- .dm2dmi_rdata_i (dmi_rdata ),
- .dmi2dm_req_o (dmi_req ),
- .dmi2dm_wr_o (dmi_wr ),
- .dmi2dm_addr_o (dmi_addr ),
- .dmi2dm_wdata_o (dmi_wdata )
-);
-
-`endif // SCR1_DBG_EN
-
-
-`ifdef SCR1_DBG_EN
-
-//-------------------------------------------------------------------------------
-// Debug Module (DM)
-//-------------------------------------------------------------------------------
-assign dm_cmd_resp_qlfy = dm_cmd_resp & {$bits(dm_cmd_resp){hdu2dm_rdc_qlfy}};
-assign dm_hart_event_qlfy = dm_hart_event & {$bits(dm_hart_event){hdu2dm_rdc_qlfy}};
-assign dm_hart_status_qlfy.dbg_state = hdu2dm_rdc_qlfy ? dm_hart_status.dbg_state
- : SCR1_HDU_DBGSTATE_RESET;
-assign dm_hart_status_qlfy.except = dm_hart_status.except;
-assign dm_hart_status_qlfy.ebreak = dm_hart_status.ebreak;
-assign dm_pbuf_addr_qlfy = dm_pbuf_addr & {$bits(dm_pbuf_addr){hdu2dm_rdc_qlfy}};
-assign dm_dreg_req_qlfy = dm_dreg_req & {$bits(dm_dreg_req){hdu2dm_rdc_qlfy}};
-assign dm_pc_sample_qlfy = dm_pc_sample & {$bits(dm_pc_sample){core2dm_rdc_qlfy}};
-
-scr1_dm i_dm (
- // Common signals
- .rst_n (dm_rst_n ),
- .clk (clk ),
-
- // DM internal interface
- .dmi2dm_req_i (dmi_req ),
- .dmi2dm_wr_i (dmi_wr ),
- .dmi2dm_addr_i (dmi_addr ),
- .dmi2dm_wdata_i (dmi_wdata ),
- .dm2dmi_resp_o (dmi_resp ),
- .dm2dmi_rdata_o (dmi_rdata ),
-
- // DM <-> Pipeline: HART Run Control i/f
- .ndm_rst_n_o (ndm_rst_n ),
- .hart_rst_n_o (hart_rst_n ),
- .dm2pipe_active_o (dm_active ),
- .dm2pipe_cmd_req_o (dm_cmd_req ),
- .dm2pipe_cmd_o (dm_cmd ),
- .pipe2dm_cmd_resp_i (dm_cmd_resp_qlfy ),
- .pipe2dm_cmd_rcode_i (dm_cmd_rcode ),
- .pipe2dm_hart_event_i (dm_hart_event_qlfy ),
- .pipe2dm_hart_status_i (dm_hart_status_qlfy ),
-
- .soc2dm_fuse_mhartid_i (core_fuse_mhartid_i ),
- .pipe2dm_pc_sample_i (dm_pc_sample_qlfy ),
-
- // DM <-> Pipeline: HART Abstract Command / Program Buffer i/f
- .pipe2dm_pbuf_addr_i (dm_pbuf_addr_qlfy ),
- .dm2pipe_pbuf_instr_o (dm_pbuf_instr ),
-
- // DM <-> Pipeline: HART Abstract Data regs i/f
- .pipe2dm_dreg_req_i (dm_dreg_req_qlfy ),
- .pipe2dm_dreg_wr_i (dm_dreg_wr ),
- .pipe2dm_dreg_wdata_i (dm_dreg_wdata ),
- .dm2pipe_dreg_resp_o (dm_dreg_resp ),
- .dm2pipe_dreg_fail_o (dm_dreg_fail ),
- .dm2pipe_dreg_rdata_o (dm_dreg_rdata )
-);
-`endif // SCR1_DBG_EN
-
-
-`ifdef SCR1_CLKCTRL_EN
-//-------------------------------------------------------------------------------
-// Global clock gating logic
-//-------------------------------------------------------------------------------
-scr1_clk_ctrl i_clk_ctrl (
- .clk (clk ),
- .rst_n (core_rst_n ),
- .test_mode (test_mode ),
- .test_rst_n (test_rst_n ),
-
- // Sleep/wake interface
- .pipe2clkctl_sleep_req_i (sleep_pipe ),
- .pipe2clkctl_wake_req_i (wake_pipe ),
-
- // Clocks
- .clkctl2pipe_clk_alw_on_o (clk_alw_on ),
- .clkctl2pipe_clk_o (clk_pipe ),
- .clkctl2pipe_clk_en_o (clk_pipe_en),
- .clkctl2pipe_clk_dbgc_o (clk_dbgc )
-);
-`endif // SCR1_CLKCTRL_EN
-
-endmodule : scr1_core_top
diff --git a/verilog/rtl/syntacore/scr1/src/core/scr1_dm.sv b/verilog/rtl/syntacore/scr1/src/core/scr1_dm.sv
deleted file mode 100644
index febeaee..0000000
--- a/verilog/rtl/syntacore/scr1/src/core/scr1_dm.sv
+++ /dev/null
@@ -1,1443 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_dm.sv>
-/// @brief Debug Module (DM)
-///
-
-//------------------------------------------------------------------------------
- //
- // Functionality:
- // - Allows debugger to perform a system reset (ndm_rst)
- // - Allows debugger to control the HART's state
- // - Provides debugger with information about the current HART's state
- // - Provides debugger with Abstract Command interface that allows to:
- // - Access MPRF registers
- // - Access CSR registers
- // - Access memory with the same view and permission as the hart has
- // - Provides debugger with Abstract Command status information (busy flag and error code)
- // - Provides debugger with Program Buffer functionality that allows to execute
- // small programs on a halted HART
- //
- // Structure:
- // - DM <-> DMI interface
- // - DM registers:
- // - DMCONTROL
- // - DMSTATUS
- // - Abstract Command Control logic
- // - Abstract Command FSM
- // - Abstract Command Status logic
- // - Abstract Instruction logic
- // - Abstract registers:
- // - COMMAND
- // - ABSTRACTAUTO
- // - PROGBUF0..5
- // - DATA0..1
- // - DHI FSM
- // - HART command registers
- // - DHI interface
- //
-//
-
-`include "scr1_arch_description.svh"
-
-`ifdef SCR1_DBG_EN
-`include "scr1_csr.svh"
-`include "scr1_dm.svh"
-
-module scr1_dm (
- // System
- input logic rst_n, // DM reset
- input logic clk, // DM clock
-
- // DM internal interface
- input logic dmi2dm_req_i, // DMI request
- input logic dmi2dm_wr_i, // DMI write
- input logic [SCR1_DBG_DMI_ADDR_WIDTH-1:0] dmi2dm_addr_i, // DMI address
- input logic [SCR1_DBG_DMI_DATA_WIDTH-1:0] dmi2dm_wdata_i, // DMI write data
- output logic dm2dmi_resp_o, // DMI response
- output logic [SCR1_DBG_DMI_DATA_WIDTH-1:0] dm2dmi_rdata_o, // DMI read data
-
- // DM <-> Pipeline: HART Run Control i/f
- output logic ndm_rst_n_o, // Non-DM Reset output
- output logic hart_rst_n_o, // HART reset output
- output logic dm2pipe_active_o, // Debug Module active flag
- output logic dm2pipe_cmd_req_o, // Request to pipe
- output type_scr1_hdu_dbgstates_e dm2pipe_cmd_o, // Command to pipe
- input logic pipe2dm_cmd_resp_i, // Response to Debug Module
- input logic pipe2dm_cmd_rcode_i, // HART Command return code: 0 - Ok; 1 - Error
- input logic pipe2dm_hart_event_i, // HART event flag
- input type_scr1_hdu_hartstatus_s pipe2dm_hart_status_i, // HART Status
-
- input logic [`SCR1_XLEN-1:0] soc2dm_fuse_mhartid_i, // RO MHARTID value
- input logic [`SCR1_XLEN-1:0] pipe2dm_pc_sample_i, // RO PC value for sampling
-
- // HART Abstract Command / Program Buffer i/f
- input logic [SCR1_HDU_PBUF_ADDR_WIDTH-1:0] pipe2dm_pbuf_addr_i, // Program Buffer address
- output logic [SCR1_HDU_CORE_INSTR_WIDTH-1:0] dm2pipe_pbuf_instr_o, // Program Buffer instruction
-
- // HART Abstract Data regs i/f
- input logic pipe2dm_dreg_req_i, // Abstract Data Register request
- input logic pipe2dm_dreg_wr_i, // Abstract Data Register write
- input logic [`SCR1_XLEN-1:0] pipe2dm_dreg_wdata_i, // Abstract Data Register write data
- output logic dm2pipe_dreg_resp_o, // Abstract Data Register response
- output logic dm2pipe_dreg_fail_o, // Abstract Data Register fail - possibly not needed ?
- output logic [`SCR1_XLEN-1:0] dm2pipe_dreg_rdata_o // Abstract Data Register read data
-);
-
-//------------------------------------------------------------------------------
-// Local types declaration
-//------------------------------------------------------------------------------
-
-typedef enum logic [3:0] {
- ABS_STATE_IDLE,
- ABS_STATE_ERR,
- ABS_STATE_EXEC,
- ABS_STATE_XREG_RW,
- ABS_STATE_MEM_SAVE_XREG,
- ABS_STATE_MEM_SAVE_XREG_FORADDR,
- ABS_STATE_MEM_RW,
- ABS_STATE_MEM_RETURN_XREG,
- ABS_STATE_MEM_RETURN_XREG_FORADDR,
- ABS_STATE_CSR_RO,
- ABS_STATE_CSR_SAVE_XREG,
- ABS_STATE_CSR_RW,
- ABS_STATE_CSR_RETURN_XREG
-} type_scr1_abs_fsm_e;
-
-typedef enum logic [2:0] {
- DHI_STATE_IDLE,
- DHI_STATE_EXEC,
- DHI_STATE_EXEC_RUN,
- DHI_STATE_EXEC_HALT,
- DHI_STATE_HALT_REQ,
- DHI_STATE_RESUME_REQ,
- DHI_STATE_RESUME_RUN
-} type_scr1_dhi_fsm_e;
-
-//typedef enum logic [SCR1_DBG_ABSTRACTCS_CMDERR_WDTH:0] {
-parameter ABS_ERR_NONE = (SCR1_DBG_ABSTRACTCS_CMDERR_WDTH+1)'('d0);
-parameter ABS_ERR_BUSY = (SCR1_DBG_ABSTRACTCS_CMDERR_WDTH+1)'('d1);
-parameter ABS_ERR_CMD = (SCR1_DBG_ABSTRACTCS_CMDERR_WDTH+1)'('d2);
-parameter ABS_ERR_EXCEPTION = (SCR1_DBG_ABSTRACTCS_CMDERR_WDTH+1)'('d3);
-parameter ABS_ERR_NOHALT = (SCR1_DBG_ABSTRACTCS_CMDERR_WDTH+1)'('d4);
-//} type_scr1_abs_err_e;
-
-
-//------------------------------------------------------------------------------
-// Local parameters declaration
-//------------------------------------------------------------------------------
-
-// Abstract instruction opcode parameters
-localparam SCR1_OP_SYSTEM = 7'b111_0011;
-localparam SCR1_OP_LOAD = 7'b000_0011;
-localparam SCR1_OP_STORE = 7'b010_0011;
-
-// Abstract instruction funct3 parameters
-localparam SCR1_FUNCT3_CSRRW = 3'b001;
-localparam SCR1_FUNCT3_CSRRS = 3'b010;
-localparam SCR1_FUNCT3_SB = 3'b000;
-localparam SCR1_FUNCT3_SH = 3'b001;
-localparam SCR1_FUNCT3_SW = 3'b010;
-localparam SCR1_FUNCT3_LW = 3'b010;
-localparam SCR1_FUNCT3_LBU = 3'b100;
-localparam SCR1_FUNCT3_LHU = 3'b101;
-
-// DMCONTROL parameters
-//------------------------------------------------------------------------------
-localparam DMCONTROL_HARTRESET = 1'd0;
-localparam DMCONTROL_RESERVEDB = 1'd0;
-localparam DMCONTROL_HASEL = 1'd0;
-localparam DMCONTROL_HARTSELLO = 1'd0;
-localparam DMCONTROL_HARTSELHI = 1'd0;
-localparam DMCONTROL_RESERVEDA = 1'd0;
-
-// DMSTATUS parameters
-//------------------------------------------------------------------------------
-localparam DMSTATUS_RESERVEDC = 1'd0;
-localparam DMSTATUS_IMPEBREAK = 1'd1;
-localparam DMSTATUS_RESERVEDB = 1'd0;
-localparam DMSTATUS_ALLUNAVAIL = 1'd0;
-localparam DMSTATUS_ANYUNAVAIL = 1'd0;
-localparam DMSTATUS_ALLANYUNAVAIL = 1'd0;
-localparam DMSTATUS_ALLANYNONEXIST = 1'b0;
-localparam DMSTATUS_AUTHENTICATED = 1'd1;
-localparam DMSTATUS_AUTHBUSY = 1'd0;
-localparam DMSTATUS_RESERVEDA = 1'd0;
-localparam DMSTATUS_DEVTREEVALID = 1'd0;
-localparam DMSTATUS_VERSION = 2'd2;
-
-// HARTINFO parameters
-//------------------------------------------------------------------------------
-localparam HARTINFO_RESERVEDB = 1'd0;
-localparam HARTINFO_NSCRATCH = 4'd1;
-localparam HARTINFO_RESERVEDA = 1'd0;
-localparam HARTINFO_DATAACCESS = 1'd0;
-localparam HARTINFO_DATASIZE = 4'd1;
-localparam HARTINFO_DATAADDR = 12'h7b2;
-
-// ABSTRACTCS parameters
-//------------------------------------------------------------------------------
-localparam ABSTRACTCS_RESERVEDD = 1'd0;
-localparam ABSTRACTCS_PROGBUFSIZE = 5'd6;
-localparam ABSTRACTCS_RESERVEDC = 1'd0;
-localparam ABSTRACTCS_RESERVEDB = 1'd0;
-localparam ABSTRACTCS_RESERVEDA = 1'd0;
-localparam ABSTRACTCS_DATACOUNT = 4'd2;
-
-localparam ABS_CMD_HARTREG = 1'd0;
-localparam ABS_CMD_HARTMEM = 2'd2;
-localparam ABS_CMD_HARTREG_CSR = 4'b0000;
-localparam ABS_CMD_HARTREG_INTFPU = 4'b0001;
-localparam ABS_CMD_HARTREG_INT = 7'b000_0000;
-localparam ABS_CMD_HARTREG_FPU = 7'b000_0001;
-localparam ABS_EXEC_EBREAK = 32'b000000000001_00000_000_00000_1110011;
-
-//------------------------------------------------------------------------------
-// Local signals declaration
-//------------------------------------------------------------------------------
-
-// DM <-> DMI interface internal signals
-//------------------------------------------------------------------------------
-
-// Register selection signals
-logic dmi_req_dmcontrol;
-logic dmi_req_abstractcs;
-logic dmi_req_abstractauto;
-logic dmi_req_command;
-logic dmi_rpt_command;
-logic dmi_req_data0;
-logic dmi_req_data1;
-logic dmi_req_progbuf0;
-logic dmi_req_progbuf1;
-logic dmi_req_progbuf2;
-logic dmi_req_progbuf3;
-logic dmi_req_progbuf4;
-logic dmi_req_progbuf5;
-
-logic dmi_req_any;
-
-// Registers write request signals
-logic dmcontrol_wr_req;
-logic abstractcs_wr_req;
-logic data0_wr_req;
-logic data1_wr_req;
-logic dreg_wr_req;
-logic command_wr_req;
-logic autoexec_wr_req;
-logic progbuf0_wr_req;
-logic progbuf1_wr_req;
-logic progbuf2_wr_req;
-logic progbuf3_wr_req;
-logic progbuf4_wr_req;
-logic progbuf5_wr_req;
-
-// DM registers
-//------------------------------------------------------------------------------
-
-// DM clock enable signals
-logic clk_en_dm;
-logic clk_en_dm_ff;
-
-// DMCONTROL register signals
-logic dmcontrol_haltreq_ff;
-logic dmcontrol_haltreq_next;
-logic dmcontrol_resumereq_ff;
-logic dmcontrol_resumereq_next;
-logic dmcontrol_ackhavereset_ff;
-logic dmcontrol_ackhavereset_next;
-logic dmcontrol_ndmreset_ff;
-logic dmcontrol_ndmreset_next;
-logic dmcontrol_dmactive_ff;
-logic dmcontrol_dmactive_next;
-
-// Auxilary Skip Reset On Powerup register
-logic havereset_skip_pwrup_ff;
-logic havereset_skip_pwrup_next;
-
-// DMSTATUS register signals
-logic dmstatus_allany_havereset_ff;
-logic dmstatus_allany_havereset_next;
-logic dmstatus_allany_resumeack_ff;
-logic dmstatus_allany_resumeack_next;
-logic dmstatus_allany_halted_ff;
-logic dmstatus_allany_halted_next;
-
-// Abstract command control logic signals
-//------------------------------------------------------------------------------
-
-logic [SCR1_DBG_DMI_DATA_WIDTH-1:0] abs_cmd;
-
-logic abs_cmd_csr_ro;
-logic [SCR1_DBG_COMMAND_TYPE_WDTH:0] abs_cmd_type;
-logic abs_cmd_regacs;
-logic [SCR1_DBG_COMMAND_ACCESSREG_REGNO_HI-12:0] abs_cmd_regtype;
-logic [6:0] abs_cmd_regfile;
-logic abs_cmd_regwr;
-logic [SCR1_DBG_COMMAND_ACCESSREG_SIZE_WDTH:0] abs_cmd_regsize;
-logic abs_cmd_execprogbuf;
-logic abs_cmd_regvalid;
-logic [2:0] abs_cmd_memsize;
-logic abs_cmd_memwr;
-logic abs_cmd_memvalid;
-
-logic abs_cmd_regsize_vd;
-logic abs_cmd_memsize_vd;
-
-logic abs_cmd_wr_ff;
-logic abs_cmd_wr_next;
-logic abs_cmd_postexec_ff;
-logic abs_cmd_postexec_next;
-logic [11:0] abs_cmd_regno;
-logic [11:0] abs_cmd_regno_ff;
-logic [1:0] abs_cmd_size_ff;
-logic [1:0] abs_cmd_size_next;
-
-logic abs_reg_access_csr;
-logic abs_reg_access_mprf;
-
-logic abs_cmd_hartreg_vd;
-logic abs_cmd_hartmem_vd;
-
-logic abs_cmd_reg_access_req;
-logic abs_cmd_csr_access_req;
-logic abs_cmd_mprf_access_req;
-logic abs_cmd_execprogbuf_req;
-
-logic abs_cmd_csr_ro_access_vd;
-logic abs_cmd_csr_rw_access_vd;
-logic abs_cmd_mprf_access_vd;
-logic abs_cmd_mem_access_vd;
-
-// Abstract FSM signals
-//------------------------------------------------------------------------------
-
-type_scr1_abs_fsm_e abs_fsm_ff;
-type_scr1_abs_fsm_e abs_fsm_next;
-logic abs_fsm_idle;
-logic abs_fsm_exec;
-logic abs_fsm_csr_ro;
-logic abs_fsm_err;
-logic abs_fsm_use_addr;
-
-// Abstract registers
-//------------------------------------------------------------------------------
-
-logic clk_en_abs;
-
-// ABSTRACTCS register signals
-logic abstractcs_busy;
-logic abstractcs_ro_en;
-
-// COMMAND register signals
-logic [`SCR1_XLEN-1:0] abs_command_ff;
-logic [`SCR1_XLEN-1:0] abs_command_next;
-
-// ABSTRACTAUTO register signals
-logic abs_autoexec_ff;
-logic abs_autoexec_next;
-
-// Program buffer registers
-logic [`SCR1_XLEN-1:0] abs_progbuf0_ff;
-logic [`SCR1_XLEN-1:0] abs_progbuf1_ff;
-logic [`SCR1_XLEN-1:0] abs_progbuf2_ff;
-logic [`SCR1_XLEN-1:0] abs_progbuf3_ff;
-logic [`SCR1_XLEN-1:0] abs_progbuf4_ff;
-logic [`SCR1_XLEN-1:0] abs_progbuf5_ff;
-
-// Data 0/1 registers
-logic data0_xreg_save;
-logic [`SCR1_XLEN-1:0] abs_data0_ff;
-logic [`SCR1_XLEN-1:0] abs_data0_next;
-logic [`SCR1_XLEN-1:0] abs_data1_ff;
-logic [`SCR1_XLEN-1:0] abs_data1_next;
-
-// Abstract command status logic signals
-//------------------------------------------------------------------------------
-
-// Abstract error exception flag register
-logic abs_err_exc_upd;
-logic abs_err_exc_ff;
-logic abs_err_exc_next;
-
-logic abs_err_acc_busy_upd;
-logic abs_err_acc_busy_ff;
-logic abs_err_acc_busy_next;
-
-logic [SCR1_DBG_ABSTRACTCS_CMDERR_WDTH:0] abstractcs_cmderr_ff;
-logic [SCR1_DBG_ABSTRACTCS_CMDERR_WDTH:0] abstractcs_cmderr_next;
-
-// Abstract instruction signals
-//------------------------------------------------------------------------------
-
-// Abstract instruction execution request register
-logic abs_exec_req_next;
-logic abs_exec_req_ff;
-
-// Abstract instruction register
-logic [4:0] abs_instr_rd;
-logic [4:0] abs_instr_rs1;
-logic [4:0] abs_instr_rs2;
-logic [2:0] abs_instr_mem_funct3;
-logic [`SCR1_XLEN-1:0] abs_exec_instr_next;
-logic [`SCR1_XLEN-1:0] abs_exec_instr_ff;
-
-// DHI FSM signals
-//------------------------------------------------------------------------------
-
-type_scr1_dhi_fsm_e dhi_fsm_next;
-type_scr1_dhi_fsm_e dhi_fsm_ff;
-type_scr1_dhi_fsm_e dhi_req;
-
-logic dhi_fsm_idle;
-logic dhi_fsm_exec;
-logic dhi_fsm_exec_halt;
-logic dhi_fsm_halt_req;
-logic dhi_fsm_resume_req;
-
-// DHI interface signals
-//------------------------------------------------------------------------------
-
-logic cmd_resp_ok;
-logic hart_rst_unexp;
-logic halt_req_vd;
-logic resume_req_vd;
-
-logic dhi_resp;
-logic dhi_resp_exc;
-
-logic hart_pbuf_ebreak_ff;
-logic hart_pbuf_ebreak_next;
-
-// HART command registers
-//------------------------------------------------------------------------------
-
-logic hart_cmd_req_ff;
-logic hart_cmd_req_next;
-
-type_scr1_hdu_dbgstates_e hart_cmd_ff;
-type_scr1_hdu_dbgstates_e hart_cmd_next;
-
-// HART state signals
-//------------------------------------------------------------------------------
-
-logic hart_state_reset;
-logic hart_state_run;
-logic hart_state_drun;
-logic hart_state_dhalt;
-
-//------------------------------------------------------------------------------
-// DM <-> DMI interface
-//------------------------------------------------------------------------------
-
-// Register selection logic
-//------------------------------------------------------------------------------
-
-always_comb begin
- dmi_req_dmcontrol = dmi2dm_req_i & (dmi2dm_addr_i == SCR1_DBG_DMCONTROL);
- dmi_req_abstractcs = dmi2dm_req_i & (dmi2dm_addr_i == SCR1_DBG_ABSTRACTCS);
- dmi_req_abstractauto = dmi2dm_req_i & (dmi2dm_addr_i == SCR1_DBG_ABSTRACTAUTO);
- dmi_req_data0 = dmi2dm_req_i & (dmi2dm_addr_i == SCR1_DBG_DATA0);
- dmi_req_data1 = dmi2dm_req_i & (dmi2dm_addr_i == SCR1_DBG_DATA1);
- dmi_req_command = dmi2dm_req_i & (dmi2dm_addr_i == SCR1_DBG_COMMAND);
- dmi_rpt_command = (abs_autoexec_ff & dmi_req_data0);
- dmi_req_progbuf0 = dmi2dm_req_i & (dmi2dm_addr_i == SCR1_DBG_PROGBUF0);
- dmi_req_progbuf1 = dmi2dm_req_i & (dmi2dm_addr_i == SCR1_DBG_PROGBUF1);
- dmi_req_progbuf2 = dmi2dm_req_i & (dmi2dm_addr_i == SCR1_DBG_PROGBUF2);
- dmi_req_progbuf3 = dmi2dm_req_i & (dmi2dm_addr_i == SCR1_DBG_PROGBUF3);
- dmi_req_progbuf4 = dmi2dm_req_i & (dmi2dm_addr_i == SCR1_DBG_PROGBUF4);
- dmi_req_progbuf5 = dmi2dm_req_i & (dmi2dm_addr_i == SCR1_DBG_PROGBUF5);
-end
-
-assign dmi_req_any = dmi_req_command | dmi_rpt_command | dmi_req_abstractauto
- | dmi_req_data0 | dmi_req_data1 | dmi_req_progbuf0
- | dmi_req_progbuf1 | dmi_req_progbuf2 | dmi_req_progbuf3
- | dmi_req_progbuf4 | dmi_req_progbuf5;
-
-
-// Read data multiplexer
-//------------------------------------------------------------------------------
-
-always_comb begin
- dm2dmi_rdata_o = '0;
-
- case (dmi2dm_addr_i)
- SCR1_DBG_DMSTATUS: begin
- dm2dmi_rdata_o[SCR1_DBG_DMSTATUS_RESERVEDC_HI:
- SCR1_DBG_DMSTATUS_RESERVEDC_LO] = DMSTATUS_RESERVEDC;
- dm2dmi_rdata_o[SCR1_DBG_DMSTATUS_IMPEBREAK] = DMSTATUS_IMPEBREAK;
- dm2dmi_rdata_o[SCR1_DBG_DMSTATUS_RESERVEDB_HI:
- SCR1_DBG_DMSTATUS_RESERVEDB_LO] = DMSTATUS_RESERVEDB;
- dm2dmi_rdata_o[SCR1_DBG_DMSTATUS_ALLHAVERESET] = dmstatus_allany_havereset_ff;
- dm2dmi_rdata_o[SCR1_DBG_DMSTATUS_ANYHAVERESET] = dmstatus_allany_havereset_ff;
- dm2dmi_rdata_o[SCR1_DBG_DMSTATUS_ALLRESUMEACK] = dmstatus_allany_resumeack_ff;
- dm2dmi_rdata_o[SCR1_DBG_DMSTATUS_ANYRESUMEACK] = dmstatus_allany_resumeack_ff;
- dm2dmi_rdata_o[SCR1_DBG_DMSTATUS_ALLNONEXISTENT] = DMSTATUS_ALLANYNONEXIST;
- dm2dmi_rdata_o[SCR1_DBG_DMSTATUS_ANYNONEXISTENT] = DMSTATUS_ALLANYNONEXIST;
- dm2dmi_rdata_o[SCR1_DBG_DMSTATUS_ALLUNAVAIL] = DMSTATUS_ALLANYUNAVAIL;
- dm2dmi_rdata_o[SCR1_DBG_DMSTATUS_ANYUNAVAIL] = DMSTATUS_ALLANYUNAVAIL;
- dm2dmi_rdata_o[SCR1_DBG_DMSTATUS_ALLRUNNING] = ~dmstatus_allany_halted_ff;
- dm2dmi_rdata_o[SCR1_DBG_DMSTATUS_ANYRUNNING] = ~dmstatus_allany_halted_ff;
- dm2dmi_rdata_o[SCR1_DBG_DMSTATUS_ALLHALTED] = dmstatus_allany_halted_ff;
- dm2dmi_rdata_o[SCR1_DBG_DMSTATUS_ANYHALTED] = dmstatus_allany_halted_ff;
- dm2dmi_rdata_o[SCR1_DBG_DMSTATUS_AUTHENTICATED] = DMSTATUS_AUTHENTICATED;
- dm2dmi_rdata_o[SCR1_DBG_DMSTATUS_AUTHBUSY] = DMSTATUS_AUTHBUSY;
- dm2dmi_rdata_o[SCR1_DBG_DMSTATUS_RESERVEDA] = DMSTATUS_RESERVEDA;
- dm2dmi_rdata_o[SCR1_DBG_DMSTATUS_DEVTREEVALID] = DMSTATUS_DEVTREEVALID;
- dm2dmi_rdata_o[SCR1_DBG_DMSTATUS_VERSION_HI:
- SCR1_DBG_DMSTATUS_VERSION_LO] = DMSTATUS_VERSION;;
- end
-
- SCR1_DBG_DMCONTROL: begin
- dm2dmi_rdata_o[SCR1_DBG_DMCONTROL_HALTREQ] = dmcontrol_haltreq_ff;
- dm2dmi_rdata_o[SCR1_DBG_DMCONTROL_RESUMEREQ] = dmcontrol_resumereq_ff;
- dm2dmi_rdata_o[SCR1_DBG_DMCONTROL_HARTRESET] = DMCONTROL_HARTRESET;
- dm2dmi_rdata_o[SCR1_DBG_DMCONTROL_ACKHAVERESET] = dmcontrol_ackhavereset_ff;
- dm2dmi_rdata_o[SCR1_DBG_DMCONTROL_RESERVEDB] = DMCONTROL_RESERVEDB;
- dm2dmi_rdata_o[SCR1_DBG_DMCONTROL_HASEL] = DMCONTROL_HASEL;
- dm2dmi_rdata_o[SCR1_DBG_DMCONTROL_HARTSELLO_HI:
- SCR1_DBG_DMCONTROL_HARTSELLO_LO] = DMCONTROL_HARTSELLO;
- dm2dmi_rdata_o[SCR1_DBG_DMCONTROL_HARTSELHI_HI:
- SCR1_DBG_DMCONTROL_HARTSELHI_LO] = DMCONTROL_HARTSELHI;
- dm2dmi_rdata_o[SCR1_DBG_DMCONTROL_RESERVEDA_HI:
- SCR1_DBG_DMCONTROL_RESERVEDA_LO] = DMCONTROL_RESERVEDA;
- dm2dmi_rdata_o[SCR1_DBG_DMCONTROL_NDMRESET] = dmcontrol_ndmreset_ff;
- dm2dmi_rdata_o[SCR1_DBG_DMCONTROL_DMACTIVE] = dmcontrol_dmactive_ff;
- end
-
- SCR1_DBG_ABSTRACTCS: begin
- dm2dmi_rdata_o[SCR1_DBG_ABSTRACTCS_RESERVEDD_HI:
- SCR1_DBG_ABSTRACTCS_RESERVEDD_LO] = ABSTRACTCS_RESERVEDD;
- dm2dmi_rdata_o[SCR1_DBG_ABSTRACTCS_PROGBUFSIZE_HI:
- SCR1_DBG_ABSTRACTCS_PROGBUFSIZE_LO] = ABSTRACTCS_PROGBUFSIZE;
- dm2dmi_rdata_o[SCR1_DBG_ABSTRACTCS_RESERVEDC_HI:
- SCR1_DBG_ABSTRACTCS_RESERVEDC_LO] = ABSTRACTCS_RESERVEDC;
- dm2dmi_rdata_o[SCR1_DBG_ABSTRACTCS_BUSY] = abstractcs_busy;
- dm2dmi_rdata_o[SCR1_DBG_ABSTRACTCS_RESERVEDB] = ABSTRACTCS_RESERVEDB;
- dm2dmi_rdata_o[SCR1_DBG_ABSTRACTCS_CMDERR_HI:
- SCR1_DBG_ABSTRACTCS_CMDERR_LO] = abstractcs_cmderr_ff;
- dm2dmi_rdata_o[SCR1_DBG_ABSTRACTCS_RESERVEDA_HI:
- SCR1_DBG_ABSTRACTCS_RESERVEDA_LO] = ABSTRACTCS_RESERVEDA;
- dm2dmi_rdata_o[SCR1_DBG_ABSTRACTCS_DATACOUNT_HI:
- SCR1_DBG_ABSTRACTCS_DATACOUNT_LO] = ABSTRACTCS_DATACOUNT;
- end
-
- SCR1_DBG_HARTINFO: begin
- dm2dmi_rdata_o[SCR1_DBG_HARTINFO_RESERVEDB_HI:
- SCR1_DBG_HARTINFO_RESERVEDB_LO] = HARTINFO_RESERVEDB;
- dm2dmi_rdata_o[SCR1_DBG_HARTINFO_NSCRATCH_HI:
- SCR1_DBG_HARTINFO_NSCRATCH_LO] = HARTINFO_NSCRATCH;
- dm2dmi_rdata_o[SCR1_DBG_HARTINFO_RESERVEDA_HI:
- SCR1_DBG_HARTINFO_RESERVEDA_LO] = HARTINFO_RESERVEDA;
- dm2dmi_rdata_o[SCR1_DBG_HARTINFO_DATAACCESS] = HARTINFO_DATAACCESS;
- dm2dmi_rdata_o[SCR1_DBG_HARTINFO_DATASIZE_HI:
- SCR1_DBG_HARTINFO_DATASIZE_LO] = HARTINFO_DATASIZE;
- dm2dmi_rdata_o[SCR1_DBG_HARTINFO_DATAADDR_HI:
- SCR1_DBG_HARTINFO_DATAADDR_LO] = HARTINFO_DATAADDR;
- end
-
- SCR1_DBG_ABSTRACTAUTO: dm2dmi_rdata_o[0] = abs_autoexec_ff;
- SCR1_DBG_DATA0 : dm2dmi_rdata_o = abs_data0_ff;
- SCR1_DBG_DATA1 : dm2dmi_rdata_o = abs_data1_ff;
- SCR1_DBG_PROGBUF0 : dm2dmi_rdata_o = abs_progbuf0_ff;
- SCR1_DBG_PROGBUF1 : dm2dmi_rdata_o = abs_progbuf1_ff;
- SCR1_DBG_PROGBUF2 : dm2dmi_rdata_o = abs_progbuf2_ff;
- SCR1_DBG_PROGBUF3 : dm2dmi_rdata_o = abs_progbuf3_ff;
- SCR1_DBG_PROGBUF4 : dm2dmi_rdata_o = abs_progbuf4_ff;
- SCR1_DBG_PROGBUF5 : dm2dmi_rdata_o = abs_progbuf5_ff;
- SCR1_DBG_HALTSUM0 : dm2dmi_rdata_o[0] = dmstatus_allany_halted_ff;
-
- default: begin
- dm2dmi_rdata_o = '0;
- end
- endcase
-end
-
-// Response
-assign dm2dmi_resp_o = 1'b1;
-
-// Write requests signals
-//------------------------------------------------------------------------------
-
-assign dmcontrol_wr_req = dmi_req_dmcontrol & dmi2dm_wr_i;
-assign data0_wr_req = dmi_req_data0 & dmi2dm_wr_i;
-assign data1_wr_req = dmi_req_data1 & dmi2dm_wr_i;
-assign dreg_wr_req = pipe2dm_dreg_req_i & pipe2dm_dreg_wr_i;
-assign command_wr_req = dmi_req_command & dmi2dm_wr_i;
-assign autoexec_wr_req = dmi_req_abstractauto & dmi2dm_wr_i;
-assign progbuf0_wr_req = dmi_req_progbuf0 & dmi2dm_wr_i;
-assign progbuf1_wr_req = dmi_req_progbuf1 & dmi2dm_wr_i;
-assign progbuf2_wr_req = dmi_req_progbuf2 & dmi2dm_wr_i;
-assign progbuf3_wr_req = dmi_req_progbuf3 & dmi2dm_wr_i;
-assign progbuf4_wr_req = dmi_req_progbuf4 & dmi2dm_wr_i;
-assign progbuf5_wr_req = dmi_req_progbuf5 & dmi2dm_wr_i;
-assign abstractcs_wr_req = dmi_req_abstractcs & dmi2dm_wr_i;
-
-// HART state signals
-//------------------------------------------------------------------------------
-
-assign hart_state_reset = (pipe2dm_hart_status_i.dbg_state == SCR1_HDU_DBGSTATE_RESET);
-assign hart_state_run = (pipe2dm_hart_status_i.dbg_state == SCR1_HDU_DBGSTATE_RUN);
-assign hart_state_dhalt = (pipe2dm_hart_status_i.dbg_state == SCR1_HDU_DBGSTATE_DHALTED);
-assign hart_state_drun = (pipe2dm_hart_status_i.dbg_state == SCR1_HDU_DBGSTATE_DRUN);
-
-//------------------------------------------------------------------------------
-// DM registers
-//------------------------------------------------------------------------------
-//
- // Registers:
- // - DM clock enable register
- // - Auxilary Skip Reset On Powerup register
- // - DMCONTROL register
- // - DMSTATUS register
-
-// DM clock enable logic
-//------------------------------------------------------------------------------
-
-assign clk_en_dm = dmcontrol_wr_req | dmcontrol_dmactive_ff | clk_en_dm_ff;
-
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- clk_en_dm_ff <= 1'b0;
- end else if (clk_en_dm) begin
- clk_en_dm_ff <= dmcontrol_dmactive_ff;
- end
-end
-
-assign dm2pipe_active_o = clk_en_dm_ff;
-
-// DMCONTROL register
-//------------------------------------------------------------------------------
-
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- dmcontrol_dmactive_ff <= 1'b0;
- dmcontrol_ndmreset_ff <= 1'b0;
- dmcontrol_ackhavereset_ff <= 1'b0;
- dmcontrol_haltreq_ff <= 1'b0;
- dmcontrol_resumereq_ff <= 1'b0;
- end else if (clk_en_dm) begin
- dmcontrol_dmactive_ff <= dmcontrol_dmactive_next;
- dmcontrol_ndmreset_ff <= dmcontrol_ndmreset_next;
- dmcontrol_ackhavereset_ff <= dmcontrol_ackhavereset_next;
- dmcontrol_haltreq_ff <= dmcontrol_haltreq_next;
- dmcontrol_resumereq_ff <= dmcontrol_resumereq_next;
- end
-end
-
-assign dmcontrol_dmactive_next = dmcontrol_wr_req
- ? dmi2dm_wdata_i[SCR1_DBG_DMCONTROL_DMACTIVE]
- : dmcontrol_dmactive_ff;
-
-always_comb begin
- dmcontrol_ndmreset_next = dmcontrol_ndmreset_ff;
- dmcontrol_ackhavereset_next = dmcontrol_ackhavereset_ff;
- dmcontrol_haltreq_next = dmcontrol_haltreq_ff;
- dmcontrol_resumereq_next = dmcontrol_resumereq_ff;
- if (~dmcontrol_dmactive_ff) begin
- dmcontrol_ndmreset_next = 1'b0;
- dmcontrol_ackhavereset_next = 1'b0;
- dmcontrol_haltreq_next = 1'b0;
- dmcontrol_resumereq_next = 1'b0;
- end else if (dmcontrol_wr_req) begin
- dmcontrol_ndmreset_next = dmi2dm_wdata_i[SCR1_DBG_DMCONTROL_NDMRESET];
- dmcontrol_ackhavereset_next = dmi2dm_wdata_i[SCR1_DBG_DMCONTROL_ACKHAVERESET];
- dmcontrol_haltreq_next = dmi2dm_wdata_i[SCR1_DBG_DMCONTROL_HALTREQ];
- dmcontrol_resumereq_next = dmi2dm_wdata_i[SCR1_DBG_DMCONTROL_RESUMEREQ];
- end
-end
-
-// Reset signal for system controlled by Debug Module
-assign hart_rst_n_o = ~dmcontrol_ndmreset_ff;
-assign ndm_rst_n_o = ~dmcontrol_ndmreset_ff;
-
-// Skip reset on powerup register
-//------------------------------------------------------------------------------
-
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- havereset_skip_pwrup_ff <= 1'b1;
- end else if (clk_en_dm) begin
- havereset_skip_pwrup_ff <= havereset_skip_pwrup_next;
- end
-end
-
-assign havereset_skip_pwrup_next = ~dmcontrol_dmactive_ff ? 1'b1
- : havereset_skip_pwrup_ff ? hart_state_reset & ndm_rst_n_o & hart_rst_n_o
- : havereset_skip_pwrup_ff;
-
-// DMSTATUS register
-//------------------------------------------------------------------------------
-
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- dmstatus_allany_havereset_ff <= 1'b0;
- dmstatus_allany_resumeack_ff <= 1'b0;
- dmstatus_allany_halted_ff <= 1'b0;
- end else if (clk_en_dm) begin
- dmstatus_allany_havereset_ff <= dmstatus_allany_havereset_next;
- dmstatus_allany_resumeack_ff <= dmstatus_allany_resumeack_next;
- dmstatus_allany_halted_ff <= dmstatus_allany_halted_next;
- end
-end
-
-assign dmstatus_allany_havereset_next = ~dmcontrol_dmactive_ff ? 1'b0
- : ~havereset_skip_pwrup_ff & hart_state_reset ? 1'b1
- : dmcontrol_ackhavereset_ff ? 1'b0
- : dmstatus_allany_havereset_ff;
-assign dmstatus_allany_resumeack_next = ~dmcontrol_dmactive_ff ? 1'b0
- : ~dmcontrol_resumereq_ff ? 1'b0
- : hart_state_run ? 1'b1
- : dmstatus_allany_resumeack_ff;
-
-assign dmstatus_allany_halted_next = ~dmcontrol_dmactive_ff ? 1'b0
- : hart_state_dhalt ? 1'b1
- : hart_state_run ? 1'b0
- : dmstatus_allany_halted_ff;
-
-//------------------------------------------------------------------------------
-// Abstract Command control logic
-//------------------------------------------------------------------------------
-//
- // Consists of the following functional units:
- // - Abstract command decoder
- // - Abstract command access valid flags
- // - Abstract command control registers
-
-assign clk_en_abs = clk_en_dm & dmcontrol_dmactive_ff;
-
-// Abstract command decoder
-//------------------------------------------------------------------------------
-
-assign abs_cmd = dmi_req_command ? dmi2dm_wdata_i : abs_command_ff;
-
-always_comb begin
- abs_cmd_regno = abs_cmd[SCR1_DBG_COMMAND_ACCESSREG_REGNO_LO +: 12];
-
- abs_cmd_csr_ro = (abs_cmd_regno == SCR1_CSR_ADDR_MISA)
- | (abs_cmd_regno == SCR1_CSR_ADDR_MVENDORID)
- | (abs_cmd_regno == SCR1_CSR_ADDR_MARCHID)
- | (abs_cmd_regno == SCR1_CSR_ADDR_MIMPID)
- | (abs_cmd_regno == SCR1_CSR_ADDR_MHARTID)
- | (abs_cmd_regno == SCR1_HDU_DBGCSR_ADDR_DPC);
-
- abs_cmd_type = abs_cmd[SCR1_DBG_COMMAND_TYPE_HI:SCR1_DBG_COMMAND_TYPE_LO];
- abs_cmd_regacs = abs_cmd[SCR1_DBG_COMMAND_ACCESSREG_TRANSFER];
- abs_cmd_regtype = abs_cmd[SCR1_DBG_COMMAND_ACCESSREG_REGNO_HI:12];
- abs_cmd_regfile = abs_cmd[11:5];
- abs_cmd_regsize = abs_cmd[SCR1_DBG_COMMAND_ACCESSREG_SIZE_HI:
- SCR1_DBG_COMMAND_ACCESSREG_SIZE_LO];
- abs_cmd_regwr = abs_cmd[SCR1_DBG_COMMAND_ACCESSREG_WRITE];
- abs_cmd_execprogbuf = abs_cmd[SCR1_DBG_COMMAND_ACCESSREG_POSTEXEC];
-
- abs_cmd_regvalid = ~(|{abs_cmd[SCR1_DBG_COMMAND_ACCESSREG_RESERVEDB],
- abs_cmd[SCR1_DBG_COMMAND_ACCESSREG_RESERVEDA]});
-
- abs_cmd_memsize = abs_cmd[SCR1_DBG_COMMAND_ACCESSMEM_AAMSIZE_HI:
- SCR1_DBG_COMMAND_ACCESSMEM_AAMSIZE_LO];
- abs_cmd_memwr = abs_cmd[SCR1_DBG_COMMAND_ACCESSMEM_WRITE];
-
- abs_cmd_memvalid = ~(|{abs_cmd[SCR1_DBG_COMMAND_ACCESSMEM_AAMVIRTUAL],
- abs_cmd[SCR1_DBG_COMMAND_ACCESSMEM_AAMPOSTINC],
- abs_cmd[SCR1_DBG_COMMAND_ACCESSMEM_RESERVEDB_HI:
- SCR1_DBG_COMMAND_ACCESSMEM_RESERVEDB_HI],
- abs_cmd[SCR1_DBG_COMMAND_ACCESSMEM_RESERVEDA_HI:
- SCR1_DBG_COMMAND_ACCESSMEM_RESERVEDA_HI]});
-end
-
-assign abs_reg_access_csr = (abs_cmd_regtype == ABS_CMD_HARTREG_CSR);
-assign abs_reg_access_mprf = (abs_cmd_regtype == ABS_CMD_HARTREG_INTFPU)
- & (abs_cmd_regfile == ABS_CMD_HARTREG_INT);
-
-// Abstract command access request and valid flags
-//------------------------------------------------------------------------------
-
-assign abs_cmd_regsize_vd = (abs_cmd_regsize == 3'h2);
-assign abs_cmd_memsize_vd = (abs_cmd_memsize < 3'h3);
-
-assign abs_cmd_hartreg_vd = (abs_cmd_type == ABS_CMD_HARTREG) & abs_cmd_regvalid;
-assign abs_cmd_hartmem_vd = (abs_cmd_type == ABS_CMD_HARTMEM) & abs_cmd_memvalid;
-
-// Abstract command requests
-assign abs_cmd_reg_access_req = abs_cmd_hartreg_vd & abs_cmd_regacs;
-assign abs_cmd_csr_access_req = abs_cmd_reg_access_req & abs_reg_access_csr;
-assign abs_cmd_mprf_access_req = abs_cmd_reg_access_req & abs_reg_access_mprf;
-assign abs_cmd_execprogbuf_req = abs_cmd_hartreg_vd & abs_cmd_execprogbuf;
-
-// Abstract command access valid flags
-assign abs_cmd_csr_ro_access_vd = abs_cmd_csr_access_req & abs_cmd_regsize_vd & ~abs_cmd_regwr
- & ~abs_cmd_execprogbuf & abs_cmd_csr_ro & hart_state_run;
-assign abs_cmd_csr_rw_access_vd = abs_cmd_csr_access_req & abs_cmd_regsize_vd
- & (abs_cmd_regwr | ~abs_cmd_csr_ro_access_vd);
-assign abs_cmd_mprf_access_vd = abs_cmd_mprf_access_req & abs_cmd_regsize_vd;
-assign abs_cmd_mem_access_vd = abs_cmd_hartmem_vd & abs_cmd_memsize_vd;
-
-// Abstract command control registers
-//------------------------------------------------------------------------------
-
-always_ff @(posedge clk) begin
- if (clk_en_abs & abs_fsm_idle) begin
- abs_cmd_postexec_ff <= abs_cmd_postexec_next;
- abs_cmd_wr_ff <= abs_cmd_wr_next;
- abs_cmd_regno_ff <= abs_cmd_regno;
- abs_cmd_size_ff <= abs_cmd_size_next;
- end
-end
-
-always_comb begin
- abs_cmd_wr_next = 1'b0;
- abs_cmd_postexec_next = 1'b0;
- abs_cmd_size_next = abs_cmd_size_ff;
- if ((command_wr_req | dmi_rpt_command) & hart_state_dhalt & abs_fsm_idle) begin
- if (abs_cmd_csr_rw_access_vd) begin
- abs_cmd_wr_next = abs_cmd_regwr;
- abs_cmd_postexec_next = abs_cmd_execprogbuf;
- end else if (abs_cmd_mprf_access_vd) begin
- abs_cmd_wr_next = abs_cmd_regwr;
- abs_cmd_size_next = abs_cmd_regsize[1:0];
- abs_cmd_postexec_next = abs_cmd_execprogbuf;
- end else if (abs_cmd_mem_access_vd) begin
- abs_cmd_wr_next = abs_cmd_memwr;
- abs_cmd_size_next = abs_cmd_memsize[1:0];
- end
- end
-end
-
-//------------------------------------------------------------------------------
-// Abstract command FSM
-//------------------------------------------------------------------------------
-
-always_ff @(posedge clk) begin
- if (clk_en_dm) begin
- if (~dmcontrol_dmactive_ff) begin
- abs_fsm_ff <= ABS_STATE_IDLE;
- end else begin
- abs_fsm_ff <= abs_fsm_next;
- end
- end
-end
-
-always_comb begin
- abs_fsm_next = abs_fsm_ff;
-
- case (abs_fsm_ff)
- ABS_STATE_IDLE: begin
- if (command_wr_req | dmi_rpt_command) begin
- case (1'b1)
- abs_cmd_csr_ro_access_vd: abs_fsm_next = ABS_STATE_CSR_RO;
- abs_cmd_csr_rw_access_vd: abs_fsm_next = hart_state_dhalt ? ABS_STATE_CSR_SAVE_XREG : ABS_STATE_ERR;
- abs_cmd_mprf_access_vd : abs_fsm_next = hart_state_dhalt ? ABS_STATE_XREG_RW : ABS_STATE_ERR;
- abs_cmd_execprogbuf_req : abs_fsm_next = ABS_STATE_EXEC;
- abs_cmd_mem_access_vd : abs_fsm_next = hart_state_dhalt ? ABS_STATE_MEM_SAVE_XREG : ABS_STATE_ERR;
- default : abs_fsm_next = ABS_STATE_ERR;
- endcase
- end
- end
-
- ABS_STATE_EXEC: begin
- if (dhi_resp) begin
- if (dhi_resp_exc | abs_err_acc_busy_ff) begin
- abs_fsm_next = ABS_STATE_ERR;
- end else begin
- abs_fsm_next = ABS_STATE_IDLE;
- end
- end
- end
-
- ABS_STATE_XREG_RW: begin
- if (dhi_resp) begin
- case (1'b1)
- abs_err_acc_busy_ff: abs_fsm_next = ABS_STATE_ERR;
- abs_cmd_postexec_ff: abs_fsm_next = ABS_STATE_EXEC;
- default : abs_fsm_next = ABS_STATE_IDLE;
- endcase
- end
- end
-
- ABS_STATE_CSR_RO : abs_fsm_next = abs_err_acc_busy_ff ? ABS_STATE_ERR : ABS_STATE_IDLE;
- ABS_STATE_CSR_SAVE_XREG: abs_fsm_next = dhi_resp ? ABS_STATE_CSR_RW : ABS_STATE_CSR_SAVE_XREG;
- ABS_STATE_CSR_RW : abs_fsm_next = dhi_resp ? ABS_STATE_CSR_RETURN_XREG : ABS_STATE_CSR_RW;
-
- ABS_STATE_CSR_RETURN_XREG: begin
- if (dhi_resp) begin
- case (1'b1)
- abs_err_exc_ff : abs_fsm_next = ABS_STATE_ERR;
- abs_err_acc_busy_ff : abs_fsm_next = ABS_STATE_ERR;
- abs_cmd_postexec_ff : abs_fsm_next = ABS_STATE_EXEC;
- default : abs_fsm_next = ABS_STATE_IDLE;
- endcase
- end
- end
-
- ABS_STATE_MEM_SAVE_XREG : abs_fsm_next = dhi_resp ? ABS_STATE_MEM_SAVE_XREG_FORADDR : ABS_STATE_MEM_SAVE_XREG;
- ABS_STATE_MEM_SAVE_XREG_FORADDR : abs_fsm_next = dhi_resp ? ABS_STATE_MEM_RW : ABS_STATE_MEM_SAVE_XREG_FORADDR;
- ABS_STATE_MEM_RW : abs_fsm_next = dhi_resp ? ABS_STATE_MEM_RETURN_XREG : ABS_STATE_MEM_RW;
- ABS_STATE_MEM_RETURN_XREG : abs_fsm_next = dhi_resp ? ABS_STATE_MEM_RETURN_XREG_FORADDR : ABS_STATE_MEM_RETURN_XREG;
-
- ABS_STATE_MEM_RETURN_XREG_FORADDR: begin
- if (dhi_resp) begin
- case (1'b1)
- abs_err_exc_ff: abs_fsm_next = ABS_STATE_ERR;
- abs_err_acc_busy_ff : abs_fsm_next = ABS_STATE_ERR;
- abs_cmd_postexec_ff : abs_fsm_next = ABS_STATE_EXEC;
- default : abs_fsm_next = ABS_STATE_IDLE;
- endcase
- end
- end
-
- ABS_STATE_ERR: begin
- if (abstractcs_wr_req & (abstractcs_cmderr_next == 3'b0)) begin
- abs_fsm_next = ABS_STATE_IDLE;
- end
- end
- endcase
-
- if (~abs_fsm_idle & hart_state_reset) begin
- abs_fsm_next = ABS_STATE_ERR;
- end
-end
-
-assign abs_fsm_idle = (abs_fsm_ff == ABS_STATE_IDLE);
-assign abs_fsm_exec = (abs_fsm_ff == ABS_STATE_EXEC);
-assign abs_fsm_csr_ro = (abs_fsm_ff == ABS_STATE_CSR_RO);
-assign abs_fsm_err = (abs_fsm_ff == ABS_STATE_ERR);
-assign abs_fsm_use_addr = (abs_fsm_ff == ABS_STATE_MEM_SAVE_XREG_FORADDR)
- | (abs_fsm_ff == ABS_STATE_MEM_RETURN_XREG_FORADDR);
-
-//------------------------------------------------------------------------------
-// Abstract command status logic
-//------------------------------------------------------------------------------
-
-// Abstract command access busy error register
-//------------------------------------------------------------------------------
-
-assign abs_err_acc_busy_upd = clk_en_abs & (abs_fsm_idle | dmi_req_any);
-
-always_ff @(posedge clk) begin
- if (abs_err_acc_busy_upd) abs_err_acc_busy_ff <= abs_err_acc_busy_next;
-end
-
-assign abs_err_acc_busy_next = ~abs_fsm_idle & dmi_req_any;
-
-// Abstract command access exception error register
-//------------------------------------------------------------------------------
-
-assign abs_err_exc_upd = clk_en_abs & (abs_fsm_idle | (dhi_resp & dhi_resp_exc));
-
-always_ff @(posedge clk) begin
- if (abs_err_exc_upd) abs_err_exc_ff <= abs_err_exc_next;
-end
-
-assign abs_err_exc_next = ~abs_fsm_idle & dhi_resp & dhi_resp_exc;
-
-//------------------------------------------------------------------------------
-// Abstract Instruction logic
-//------------------------------------------------------------------------------
-//
- // Cosists of the following functional units:
- // - Instruction execution request register
- // - Instruction memory FUNCT3 field multiplexer
- // - Instruction RS1 multiplexer
- // - Instruction RD multiplexer
- // - Abstract Instruction register
-
-// Abstract instruction execution request register
-//------------------------------------------------------------------------------
-
-assign abs_exec_req_next = ~(abs_fsm_idle | abs_fsm_csr_ro | abs_fsm_err) & ~dhi_resp;
-
-always_ff @(posedge clk) begin
- if (clk_en_dm) begin
- if (~dmcontrol_dmactive_ff) begin
- abs_exec_req_ff <= 1'b0;
- end else begin
- abs_exec_req_ff <= abs_exec_req_next;
- end
- end
-end
-
-// Abstract instruction memory FUNCT3 field multiplexer
-//------------------------------------------------------------------------------
-
-always_comb begin
- case (abs_cmd_size_ff)
- 2'b00 : abs_instr_mem_funct3 = abs_cmd_wr_ff ? SCR1_FUNCT3_SB : SCR1_FUNCT3_LBU;
- 2'b01 : abs_instr_mem_funct3 = abs_cmd_wr_ff ? SCR1_FUNCT3_SH : SCR1_FUNCT3_LHU;
- 2'b10 : abs_instr_mem_funct3 = abs_cmd_wr_ff ? SCR1_FUNCT3_SW : SCR1_FUNCT3_LW;
- default: abs_instr_mem_funct3 = SCR1_FUNCT3_SB;
- endcase
-end
-
-// Abstract instruction RS1 multiplexer
-//------------------------------------------------------------------------------
-
-always_comb begin
- abs_instr_rs1 = 5'h0;
- case (abs_fsm_ff)
- ABS_STATE_XREG_RW : abs_instr_rs1 = abs_cmd_wr_ff ? 5'h0 : abs_cmd_regno_ff[4:0];
- ABS_STATE_CSR_SAVE_XREG : abs_instr_rs1 = 5'h5;
- ABS_STATE_MEM_SAVE_XREG : abs_instr_rs1 = 5'h5;
- ABS_STATE_CSR_RETURN_XREG : abs_instr_rs1 = 5'h5;
- ABS_STATE_MEM_RETURN_XREG : abs_instr_rs1 = 5'h5;
- ABS_STATE_CSR_RW : abs_instr_rs1 = abs_cmd_wr_ff ? 5'h5 : 5'h0;
- ABS_STATE_MEM_SAVE_XREG_FORADDR : abs_instr_rs1 = 5'h6;
- ABS_STATE_MEM_RETURN_XREG_FORADDR: abs_instr_rs1 = 5'h6;
- ABS_STATE_MEM_RW : abs_instr_rs1 = 5'h6;
- default : begin end
- endcase
-end
-
-assign abs_instr_rs2 = 5'h5;
-
-// Abstract instruction RD multiplexer
-//------------------------------------------------------------------------------
-
-always_comb begin
- abs_instr_rd = 5'h0;
- case (abs_fsm_ff)
- ABS_STATE_XREG_RW : abs_instr_rd = abs_cmd_wr_ff ? abs_cmd_regno_ff[4:0] : 5'h0;
- ABS_STATE_CSR_SAVE_XREG : abs_instr_rd = abs_cmd_wr_ff ? 5'h5 : 5'h0;
- ABS_STATE_MEM_SAVE_XREG : abs_instr_rd = abs_cmd_wr_ff ? 5'h5 : 5'h0;
- ABS_STATE_CSR_RW : abs_instr_rd = abs_cmd_wr_ff ? 5'h0 : 5'h5;
- ABS_STATE_MEM_RW : abs_instr_rd = abs_cmd_wr_ff ? 5'h0 : 5'h5;
- ABS_STATE_CSR_RETURN_XREG : abs_instr_rd = 5'h5;
- ABS_STATE_MEM_RETURN_XREG : abs_instr_rd = 5'h5;
- ABS_STATE_MEM_SAVE_XREG_FORADDR : abs_instr_rd = 5'h6;
- ABS_STATE_MEM_RETURN_XREG_FORADDR: abs_instr_rd = 5'h6;
- default : begin end
- endcase
-end
-
-// Abstract instruction register
-//------------------------------------------------------------------------------
-
-always_ff @(posedge clk) begin
- if (clk_en_abs) begin
- abs_exec_instr_ff <= abs_exec_instr_next;
- end
-end
-
-always_comb begin
- abs_exec_instr_next = abs_exec_instr_ff;
- case (abs_fsm_ff)
- ABS_STATE_XREG_RW,
- ABS_STATE_CSR_SAVE_XREG,
- ABS_STATE_CSR_RETURN_XREG,
- ABS_STATE_MEM_SAVE_XREG,
- ABS_STATE_MEM_SAVE_XREG_FORADDR,
- ABS_STATE_MEM_RETURN_XREG,
- ABS_STATE_MEM_RETURN_XREG_FORADDR: begin
- abs_exec_instr_next = {SCR1_HDU_DBGCSR_ADDR_DSCRATCH0, abs_instr_rs1, SCR1_FUNCT3_CSRRW, abs_instr_rd, SCR1_OP_SYSTEM};
- end
-
- ABS_STATE_CSR_RW: begin
- abs_exec_instr_next = abs_cmd_wr_ff
- ? {abs_cmd_regno_ff[11:0], abs_instr_rs1, SCR1_FUNCT3_CSRRW, abs_instr_rd, SCR1_OP_SYSTEM}
- : {abs_cmd_regno_ff[11:0], abs_instr_rs1, SCR1_FUNCT3_CSRRS, abs_instr_rd, SCR1_OP_SYSTEM};
- end
-
- ABS_STATE_MEM_RW: begin
- abs_exec_instr_next = abs_cmd_wr_ff
- ? {7'h0, abs_instr_rs2, abs_instr_rs1, abs_instr_mem_funct3, 5'h0, SCR1_OP_STORE}
- : {12'h0, abs_instr_rs1, abs_instr_mem_funct3, abs_instr_rd, SCR1_OP_LOAD};
- end
-
- default: begin end
- endcase
-end
-
-//------------------------------------------------------------------------------
-// Abstract registers
-//------------------------------------------------------------------------------
-//
- // Registers:
- // - ABSTRACTCS register
- // - COMMAND register
- // - ABSTRACTAUTO register
- // - PROGBUF0..5 registers
- // - DATA0..1 registers
-
-// ABSTRACTCS register
-//------------------------------------------------------------------------------
-
-always_ff @(posedge clk) begin
- if (clk_en_dm) begin
- if (~dmcontrol_dmactive_ff) begin
- abstractcs_cmderr_ff <= ABS_ERR_NONE;
- end else begin
- abstractcs_cmderr_ff <= abstractcs_cmderr_next;
- end
- end
-end
-
-always_comb begin
- abstractcs_cmderr_next = abstractcs_cmderr_ff;
-
- case (abs_fsm_ff)
- ABS_STATE_IDLE: begin
- if (command_wr_req | dmi_rpt_command) begin
- if (abs_cmd_hartreg_vd) begin
- case (1'b1)
- abs_cmd_reg_access_req : begin
- case (1'b1)
- abs_cmd_csr_rw_access_vd: abstractcs_cmderr_next = hart_state_dhalt
- ? abstractcs_cmderr_ff
- : ABS_ERR_NOHALT;
- abs_cmd_mprf_access_vd : abstractcs_cmderr_next = hart_state_dhalt
- ? abstractcs_cmderr_ff
- : ABS_ERR_NOHALT;
- abs_cmd_csr_ro_access_vd: abstractcs_cmderr_next = abstractcs_cmderr_ff;
- default : abstractcs_cmderr_next = ABS_ERR_CMD;
- endcase
- end
- abs_cmd_execprogbuf_req : abstractcs_cmderr_next = abstractcs_cmderr_ff;
- default : abstractcs_cmderr_next = ABS_ERR_CMD;
- endcase
- end else if (abs_cmd_hartmem_vd) begin
- abstractcs_cmderr_next = ~abs_cmd_memsize_vd ? ABS_ERR_CMD
- : ~hart_state_dhalt ? ABS_ERR_NOHALT
- : abstractcs_cmderr_ff;
- end else begin
- abstractcs_cmderr_next = ABS_ERR_CMD;
- end
- end
- end
-
- ABS_STATE_EXEC: begin
- if (dhi_resp) begin
- if (dhi_resp_exc) begin
- abstractcs_cmderr_next = ABS_ERR_EXCEPTION;
- end else if (abs_err_acc_busy_ff) begin
- abstractcs_cmderr_next = ABS_ERR_BUSY;
- end
- end
- end
-
- ABS_STATE_XREG_RW,
- ABS_STATE_CSR_RO: begin
- if (abs_err_acc_busy_ff) begin
- abstractcs_cmderr_next = ABS_ERR_BUSY;
- end
- end
-
- ABS_STATE_CSR_RETURN_XREG,
- ABS_STATE_MEM_RETURN_XREG_FORADDR: begin
- if (dhi_resp) begin
- case (1'b1)
- abs_err_exc_ff : abstractcs_cmderr_next = ABS_ERR_EXCEPTION;
- abs_err_acc_busy_ff: abstractcs_cmderr_next = ABS_ERR_BUSY;
- default: abstractcs_cmderr_next = abstractcs_cmderr_ff;
- endcase
- end
- end
-
- ABS_STATE_ERR: begin
- if (dmi_req_abstractcs & dmi2dm_wr_i) begin
- abstractcs_cmderr_next = abstractcs_cmderr_ff // cp.7
- & (~dmi2dm_wdata_i[SCR1_DBG_ABSTRACTCS_CMDERR_HI:
- SCR1_DBG_ABSTRACTCS_CMDERR_LO]);
- end
- end
-
- default: begin
- end
- endcase
-
- if (~abs_fsm_idle & hart_state_reset) begin
- abstractcs_cmderr_next = ABS_ERR_EXCEPTION;
- end
-end
-
-assign abstractcs_busy = ~abs_fsm_idle & ~abs_fsm_err;
-
-// Abstract COMMAND register
-//------------------------------------------------------------------------------
-
-always_ff @(posedge clk) begin
- if (clk_en_dm) abs_command_ff <= abs_command_next;
-end
-
-assign abs_command_next = ~dmcontrol_dmactive_ff ? '0
- : (command_wr_req & abs_fsm_idle) ? dmi2dm_wdata_i
- : abs_command_ff;
-
-// Abstract ABSTRACTAUTO register
-//------------------------------------------------------------------------------
-
-always_ff @(posedge clk) begin
- if (clk_en_dm) abs_autoexec_ff <= abs_autoexec_next;
-end
-
-assign abs_autoexec_next = ~dmcontrol_dmactive_ff ? 1'b0
- : (autoexec_wr_req & abs_fsm_idle) ? dmi2dm_wdata_i[0]
- : abs_autoexec_ff;
-
-// Program Buffer registers
-//------------------------------------------------------------------------------
-
-always_ff @(posedge clk) begin
- if (clk_en_abs & abs_fsm_idle) begin
- if (progbuf0_wr_req) abs_progbuf0_ff <= dmi2dm_wdata_i;
- if (progbuf1_wr_req) abs_progbuf1_ff <= dmi2dm_wdata_i;
- if (progbuf2_wr_req) abs_progbuf2_ff <= dmi2dm_wdata_i;
- if (progbuf3_wr_req) abs_progbuf3_ff <= dmi2dm_wdata_i;
- if (progbuf4_wr_req) abs_progbuf4_ff <= dmi2dm_wdata_i;
- if (progbuf5_wr_req) abs_progbuf5_ff <= dmi2dm_wdata_i;
- end
-end
-
-// Data 0 register
-//------------------------------------------------------------------------------
-
-always_ff @(posedge clk) begin
- if (clk_en_abs) begin
- abs_data0_ff <= abs_data0_next;
- end
-end
-
-assign data0_xreg_save = dreg_wr_req & ~abs_cmd_wr_ff;
-
-always_comb begin
- abs_data0_next = abs_data0_ff;
-
- case (abs_fsm_ff)
- ABS_STATE_IDLE : abs_data0_next = data0_wr_req ? dmi2dm_wdata_i : abs_data0_ff;
- ABS_STATE_EXEC : abs_data0_next = dreg_wr_req ? pipe2dm_dreg_wdata_i : abs_data0_ff;
- ABS_STATE_CSR_SAVE_XREG : abs_data0_next = dreg_wr_req ? pipe2dm_dreg_wdata_i : abs_data0_ff;
- ABS_STATE_CSR_RETURN_XREG: abs_data0_next = dreg_wr_req ? pipe2dm_dreg_wdata_i : abs_data0_ff;
- ABS_STATE_MEM_SAVE_XREG : abs_data0_next = dreg_wr_req ? pipe2dm_dreg_wdata_i : abs_data0_ff;
- ABS_STATE_MEM_RETURN_XREG: abs_data0_next = dreg_wr_req ? pipe2dm_dreg_wdata_i : abs_data0_ff;
- ABS_STATE_XREG_RW : abs_data0_next = data0_xreg_save ? pipe2dm_dreg_wdata_i : abs_data0_ff;
-
- ABS_STATE_CSR_RO: begin
- case (abs_cmd_regno_ff[11:0])
- SCR1_CSR_ADDR_MISA : abs_data0_next = SCR1_CSR_MISA;
- SCR1_CSR_ADDR_MVENDORID: abs_data0_next = SCR1_CSR_MVENDORID;
- SCR1_CSR_ADDR_MARCHID : abs_data0_next = SCR1_CSR_MARCHID;
- SCR1_CSR_ADDR_MIMPID : abs_data0_next = SCR1_CSR_MIMPID;
- SCR1_CSR_ADDR_MHARTID : abs_data0_next = soc2dm_fuse_mhartid_i;
- default : abs_data0_next = pipe2dm_pc_sample_i;
- endcase
- end
-
- default : begin end
- endcase
-end
-
-// Data 1 register
-//------------------------------------------------------------------------------
-
-always_ff @(posedge clk) begin
- if (clk_en_abs) begin
- abs_data1_ff <= abs_data1_next;
- end
-end
-
-always_comb begin
- abs_data1_next = abs_data1_ff;
- case (abs_fsm_ff)
- ABS_STATE_IDLE : abs_data1_next = data1_wr_req ? dmi2dm_wdata_i : abs_data1_ff;
- ABS_STATE_MEM_SAVE_XREG_FORADDR : abs_data1_next = dreg_wr_req ? pipe2dm_dreg_wdata_i : abs_data1_ff;
- ABS_STATE_MEM_RETURN_XREG_FORADDR: abs_data1_next = dreg_wr_req ? pipe2dm_dreg_wdata_i : abs_data1_ff;
- default : begin end
- endcase
-end
-
-//------------------------------------------------------------------------------
-// Debug Hart Interface : control
-//------------------------------------------------------------------------------
-
-assign cmd_resp_ok = pipe2dm_cmd_resp_i & ~pipe2dm_cmd_rcode_i;
-assign hart_rst_unexp = ~dhi_fsm_idle & ~dhi_fsm_halt_req & hart_state_reset;
-
-assign halt_req_vd = dmcontrol_haltreq_ff & ~hart_state_dhalt;
-assign resume_req_vd = dmcontrol_resumereq_ff & ~dmstatus_allany_resumeack_ff
- & hart_state_dhalt;
-
-// DHI fsm
-//------------------------------------------------------------------------------
-
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- dhi_fsm_ff <= DHI_STATE_IDLE;
- end else if (clk_en_dm) begin
- dhi_fsm_ff <= dhi_fsm_next;
- end
-end
-
-always_comb begin
- dhi_fsm_next = dhi_fsm_ff;
- if (~hart_rst_unexp & dmcontrol_dmactive_ff) begin
- // Normal work
- case (dhi_fsm_ff)
- DHI_STATE_IDLE : dhi_fsm_next = dhi_req;
- DHI_STATE_EXEC : dhi_fsm_next = cmd_resp_ok ? DHI_STATE_EXEC_RUN : DHI_STATE_EXEC;
- DHI_STATE_EXEC_RUN : dhi_fsm_next = hart_state_drun ? DHI_STATE_EXEC_HALT : DHI_STATE_EXEC_RUN;
- DHI_STATE_HALT_REQ : dhi_fsm_next = cmd_resp_ok ? DHI_STATE_EXEC_HALT : DHI_STATE_HALT_REQ;
- DHI_STATE_EXEC_HALT : dhi_fsm_next = hart_state_dhalt ? DHI_STATE_IDLE : DHI_STATE_EXEC_HALT;
- DHI_STATE_RESUME_REQ: dhi_fsm_next = cmd_resp_ok ? DHI_STATE_RESUME_RUN : DHI_STATE_RESUME_REQ;
- DHI_STATE_RESUME_RUN: dhi_fsm_next = hart_state_run ? DHI_STATE_IDLE : DHI_STATE_RESUME_RUN;
- default : dhi_fsm_next = dhi_fsm_ff;
- endcase
- end else begin
- // In case of DM reset or core unexpected reset
- dhi_fsm_next = DHI_STATE_IDLE;
- end
-end
-
-assign dhi_fsm_idle = (dhi_fsm_ff == DHI_STATE_IDLE);
-assign dhi_fsm_halt_req = (dhi_fsm_ff == DHI_STATE_HALT_REQ);
-assign dhi_fsm_exec = (dhi_fsm_ff == DHI_STATE_EXEC);
-assign dhi_fsm_exec_halt = (dhi_fsm_ff == DHI_STATE_EXEC_HALT);
-assign dhi_fsm_resume_req = (dhi_fsm_ff == DHI_STATE_RESUME_REQ);
-
-always_comb begin
- case (1'b1)
- abs_exec_req_ff: dhi_req = DHI_STATE_EXEC;
- halt_req_vd : dhi_req = DHI_STATE_HALT_REQ;
- resume_req_vd : dhi_req = DHI_STATE_RESUME_REQ;
- default : dhi_req = DHI_STATE_IDLE;
- endcase
-end
-
-assign dhi_resp = dhi_fsm_exec_halt & hart_state_dhalt;
-assign dhi_resp_exc = pipe2dm_hart_event_i & pipe2dm_hart_status_i.except
- & ~pipe2dm_hart_status_i.ebreak;
-
-// HART command registers
-//------------------------------------------------------------------------------
-
-// HART command request register
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- hart_cmd_req_ff <= 1'b0;
- end else if (clk_en_dm) begin
- hart_cmd_req_ff <= hart_cmd_req_next;
- end
-end
-
-assign hart_cmd_req_next = (dhi_fsm_exec | dhi_fsm_halt_req | dhi_fsm_resume_req)
- & ~cmd_resp_ok & dmcontrol_dmactive_ff;
-
-// HART command register
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- hart_cmd_ff <= SCR1_HDU_DBGSTATE_RUN;
- end else if (clk_en_dm) begin
- hart_cmd_ff <= hart_cmd_next;
- end
-end
-
-always_comb begin
- hart_cmd_next = SCR1_HDU_DBGSTATE_RUN;
- if (dmcontrol_dmactive_ff) begin
- case (dhi_fsm_ff)
- DHI_STATE_EXEC : hart_cmd_next = SCR1_HDU_DBGSTATE_DRUN;
- DHI_STATE_HALT_REQ : hart_cmd_next = SCR1_HDU_DBGSTATE_DHALTED;
- DHI_STATE_RESUME_REQ: hart_cmd_next = SCR1_HDU_DBGSTATE_RUN;
- default : hart_cmd_next = dm2pipe_cmd_o;
- endcase
- end
-end
-
-assign dm2pipe_cmd_req_o = hart_cmd_req_ff;
-assign dm2pipe_cmd_o = hart_cmd_ff;
-
-//------------------------------------------------------------------------------
-// Debug Hart Interface : program buffer
-//------------------------------------------------------------------------------
-
-// Program Buffer execution EBREAK flag
-//------------------------------------------------------------------------------
-
-always_ff @(posedge clk) begin
- if (clk_en_dm) hart_pbuf_ebreak_ff <= hart_pbuf_ebreak_next;
-end
-
-assign hart_pbuf_ebreak_next = abs_fsm_exec & (dm2pipe_pbuf_instr_o == ABS_EXEC_EBREAK);
-
-// Program Buffer instruction multiplexer
-//------------------------------------------------------------------------------
-
-always_comb begin
- dm2pipe_pbuf_instr_o = ABS_EXEC_EBREAK;
-
- if (abs_fsm_exec & ~hart_pbuf_ebreak_ff) begin
- case (pipe2dm_pbuf_addr_i)
- 3'h0: dm2pipe_pbuf_instr_o = abs_progbuf0_ff;
- 3'h1: dm2pipe_pbuf_instr_o = abs_progbuf1_ff;
- 3'h2: dm2pipe_pbuf_instr_o = abs_progbuf2_ff;
- 3'h3: dm2pipe_pbuf_instr_o = abs_progbuf3_ff;
- 3'h4: dm2pipe_pbuf_instr_o = abs_progbuf4_ff;
- 3'h5: dm2pipe_pbuf_instr_o = abs_progbuf5_ff;
- default: ;
- endcase
- end else if (pipe2dm_pbuf_addr_i == 3'b0) begin
- dm2pipe_pbuf_instr_o = abs_exec_instr_ff;
- end
-end
-
-//------------------------------------------------------------------------------
-// Debug Hart Interface : abstract command data
-//------------------------------------------------------------------------------
-
-assign dm2pipe_dreg_resp_o = 1'b1;
-assign dm2pipe_dreg_fail_o = 1'b0;
-assign dm2pipe_dreg_rdata_o = abs_fsm_use_addr ? abs_data1_ff : abs_data0_ff;
-
-`ifdef SCR1_TRGT_SIMULATION
-//------------------------------------------------------------------------------
-// Assertions
-//------------------------------------------------------------------------------
-
-SVA_DM_X_CONTROL : assert property (
- @(negedge clk) disable iff (~rst_n)
- !$isunknown({dmi2dm_req_i, pipe2dm_dreg_req_i, pipe2dm_cmd_resp_i,
- pipe2dm_hart_event_i})
-) else $error("DM error: control signals is X - %0b", {dmi2dm_req_i,
- pipe2dm_dreg_req_i, pipe2dm_cmd_resp_i, pipe2dm_hart_event_i});
-
-SVA_DM_X_DMI : assert property (
- @(negedge clk) disable iff (~rst_n)
- dmi2dm_req_i |-> !$isunknown({dmi2dm_wr_i, dmi2dm_addr_i, dmi2dm_wdata_i})
-) else $error("DM error: data signals is X on dmi");
-
-SVA_DM_X_HART_PBUF : assert property (
- @(negedge clk) disable iff (~rst_n)
- !$isunknown (pipe2dm_pbuf_addr_i)
-) else $error("DM error: data signals is X on hart_pbuf");
-
-SVA_DM_X_HART_DREG : assert property (
- @(negedge clk) disable iff (~rst_n)
- pipe2dm_dreg_req_i |-> !$isunknown({pipe2dm_dreg_wr_i, pipe2dm_dreg_wdata_i})
-) else $error("DM error: data signals is X on hart_dreg");
-
-SVA_DM_X_HART_CMD : assert property (
- @(negedge clk) disable iff (~rst_n)
- pipe2dm_cmd_resp_i |-> !$isunknown({pipe2dm_cmd_rcode_i})
-) else $error("DM error: data signals is X on dm2pipe_cmd_o");
-
-SVA_DM_X_HART_EVENT : assert property (
- @(negedge clk) disable iff (~rst_n)
- pipe2dm_hart_event_i |-> !$isunknown(pipe2dm_hart_status_i)
-) else $error("DM error: data signals is X on pipe2dm_hart_event_i");
-
-`endif // SCR1_TRGT_SIMULATION
-
-endmodule : scr1_dm
-
-`endif // SCR1_DBG_EN
diff --git a/verilog/rtl/syntacore/scr1/src/core/scr1_dmi.sv b/verilog/rtl/syntacore/scr1/src/core/scr1_dmi.sv
deleted file mode 100644
index edb621e..0000000
--- a/verilog/rtl/syntacore/scr1/src/core/scr1_dmi.sv
+++ /dev/null
@@ -1,198 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_dmi.sv>
-/// @brief Debug Module Interface (DMI)
-///
-
-//------------------------------------------------------------------------------
- //
- // Functionality:
- // - Provides TAPC with access to Debug Module (DM) and DTMCS
- //
- // Structure:
- // - DMI <-> TAP interface
- // - DMI <-> DM interface
- //
-//------------------------------------------------------------------------------
-
-`include "scr1_arch_description.svh"
-
-`ifdef SCR1_DBG_EN
-`include "scr1_dm.svh"
-
-module scr1_dmi (
- // System
- input logic rst_n, // DMI unit reset
- input logic clk, // DMI unit clock
-
- // TAP interface
- input logic tapcsync2dmi_ch_sel_i, // Debug Transport Module Chain Select
- input logic [SCR1_DBG_DMI_CH_ID_WIDTH-1:0] tapcsync2dmi_ch_id_i, // Debug Transport Module Chain ID
- input logic tapcsync2dmi_ch_capture_i, // Debug Transport Module Chain Capture
- input logic tapcsync2dmi_ch_shift_i, // Debug Transport Module Chain Shift
- input logic tapcsync2dmi_ch_update_i, // Debug Transport Module Chain Update
- input logic tapcsync2dmi_ch_tdi_i, // Debug Transport Module Chain TDI
- output logic dmi2tapcsync_ch_tdo_o, // Debug Transport Module Chain TDO
-
- // DM interface
- input logic dm2dmi_resp_i, // DMI response
- input logic [SCR1_DBG_DMI_DATA_WIDTH-1:0] dm2dmi_rdata_i, // DMI read data
- output logic dmi2dm_req_o, // DMI request
- output logic dmi2dm_wr_o, // DMI write
- output logic [SCR1_DBG_DMI_ADDR_WIDTH-1:0] dmi2dm_addr_o, // DMI address
- output logic [SCR1_DBG_DMI_DATA_WIDTH-1:0] dmi2dm_wdata_o // DMI write data
-);
-
-//------------------------------------------------------------------------------
-// Local parameters declaration
-//------------------------------------------------------------------------------
-
-// Debug Transport Module Status parameters
-//------------------------------------------------------------------------------
-
-localparam DTMCS_RESERVEDB_HI = 5'd31;
-localparam DTMCS_RESERVEDB_LO = 5'd18;
-localparam DTMCS_DMIHARDRESET = 5'd17;
-localparam DTMCS_DMIRESET = 5'd16;
-localparam DTMCS_RESERVEDA = 5'd15;
-localparam DTMCS_IDLE_HI = 5'd14;
-localparam DTMCS_IDLE_LO = 5'd12;
-localparam DTMCS_DMISTAT_HI = 5'd11;
-localparam DTMCS_DMISTAT_LO = 5'd10;
-localparam DTMCS_ABITS_HI = 5'd9;
-localparam DTMCS_ABITS_LO = 5'd4;
-localparam DTMCS_VERSION_HI = 5'd3;
-localparam DTMCS_VERSION_LO = 5'd0;
-
-// Debug Module Interface parameters
-//------------------------------------------------------------------------------
-
-localparam DMI_OP_LO = 5'd0;
-localparam DMI_OP_HI = DMI_OP_LO + SCR1_DBG_DMI_OP_WIDTH - 1;
-localparam DMI_DATA_LO = DMI_OP_HI + 1;
-localparam DMI_DATA_HI = DMI_DATA_LO + SCR1_DBG_DMI_DATA_WIDTH - 1;
-localparam DMI_ADDR_LO = DMI_DATA_HI + 1;
-localparam DMI_ADDR_HI = DMI_ADDR_LO + SCR1_DBG_DMI_ADDR_WIDTH - 1;
-
-//------------------------------------------------------------------------------
-// Local signals declaration
-//------------------------------------------------------------------------------
-
-// TAP data register
-logic tap_dr_upd;
-logic [SCR1_DBG_DMI_DR_DMI_ACCESS_WIDTH-1:0] tap_dr_ff;
-logic [SCR1_DBG_DMI_DR_DMI_ACCESS_WIDTH-1:0] tap_dr_shift;
-logic [SCR1_DBG_DMI_DR_DMI_ACCESS_WIDTH-1:0] tap_dr_rdata;
-logic [SCR1_DBG_DMI_DR_DMI_ACCESS_WIDTH-1:0] tap_dr_next;
-
-// DM read data register
-logic dm_rdata_upd;
-logic [SCR1_DBG_DMI_DATA_WIDTH-1:0] dm_rdata_ff;
-
-logic tapc_dmi_access_req;
-logic tapc_dtmcs_sel;
-
-//------------------------------------------------------------------------------
-// DMI <-> TAP interface
-//------------------------------------------------------------------------------
-
-// TAPC read data multiplexer
-//------------------------------------------------------------------------------
-
-assign tapc_dtmcs_sel = (tapcsync2dmi_ch_id_i == 1'd1);
-
-// DMI operation is always successful in the current implementation
-always_comb begin
- tap_dr_rdata = '0;
-
- if(tapc_dtmcs_sel) begin
- tap_dr_rdata[DTMCS_RESERVEDB_HI:DTMCS_RESERVEDB_LO] = 'b0;
- tap_dr_rdata[DTMCS_DMIHARDRESET] = 'b0;
- tap_dr_rdata[DTMCS_DMIRESET] = 'b0;
- tap_dr_rdata[DTMCS_RESERVEDA] = 'b0;
- tap_dr_rdata[DTMCS_IDLE_HI:DTMCS_IDLE_LO] = 'b0;
- tap_dr_rdata[DTMCS_DMISTAT_HI:DTMCS_DMISTAT_LO] = 'b0;
- tap_dr_rdata[DTMCS_ABITS_HI :DTMCS_ABITS_LO] = SCR1_DBG_DMI_ADDR_WIDTH;
- tap_dr_rdata[DTMCS_VERSION_LO] = 1'b1;
- end else begin
- tap_dr_rdata[DMI_ADDR_HI:DMI_ADDR_LO] = 'b0;
- tap_dr_rdata[DMI_DATA_HI:DMI_DATA_LO] = dm_rdata_ff;
- tap_dr_rdata[DMI_OP_HI :DMI_OP_LO] = 'b0;
- end
-end
-
-assign tap_dr_shift = tapc_dtmcs_sel
- ? {9'b0, tapcsync2dmi_ch_tdi_i, tap_dr_ff[SCR1_DBG_DMI_DR_DTMCS_WIDTH-1:1]}
- : {tapcsync2dmi_ch_tdi_i, tap_dr_ff[SCR1_DBG_DMI_DR_DMI_ACCESS_WIDTH-1:1]};
-
-// TAP data register
-//------------------------------------------------------------------------------
-
-assign tap_dr_upd = tapcsync2dmi_ch_capture_i | tapcsync2dmi_ch_shift_i;
-
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- tap_dr_ff <= '0;
- end else if(tap_dr_upd) begin
- tap_dr_ff <= tap_dr_next;
- end
-end
-
-assign tap_dr_next = tapcsync2dmi_ch_capture_i ? tap_dr_rdata
- : tapcsync2dmi_ch_shift_i ? tap_dr_shift
- : tap_dr_ff;
-
-assign dmi2tapcsync_ch_tdo_o = tap_dr_ff[0];
-
-//------------------------------------------------------------------------------
-// DMI <-> DM interface
-//------------------------------------------------------------------------------
-
-assign tapc_dmi_access_req = tapcsync2dmi_ch_update_i & tapcsync2dmi_ch_sel_i
- & (tapcsync2dmi_ch_id_i == 2'd2);
-
-always_comb begin
- dmi2dm_req_o = 1'b0;
- dmi2dm_wr_o = 1'b0;
- dmi2dm_addr_o = 1'b0;
- dmi2dm_wdata_o = 1'b0;
-
- if(tapc_dmi_access_req) begin
- dmi2dm_req_o = tap_dr_ff[DMI_OP_HI :DMI_OP_LO] != 2'b00;
- dmi2dm_wr_o = tap_dr_ff[DMI_OP_HI :DMI_OP_LO] == 2'b10;
- dmi2dm_addr_o = tap_dr_ff[DMI_ADDR_HI:DMI_ADDR_LO];
- dmi2dm_wdata_o = tap_dr_ff[DMI_DATA_HI:DMI_DATA_LO];
- end
-end
-
-// DM read data register
-//------------------------------------------------------------------------------
-
-assign dm_rdata_upd = dmi2dm_req_o & dm2dmi_resp_i & ~dmi2dm_wr_o;
-
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- dm_rdata_ff <= '0;
- end else if (dm_rdata_upd) begin
- dm_rdata_ff <= dm2dmi_rdata_i;
- end
-end
-
-endmodule : scr1_dmi
-
-`endif // SCR1_DBG_EN
diff --git a/verilog/rtl/syntacore/scr1/src/core/scr1_scu.sv b/verilog/rtl/syntacore/scr1/src/core/scr1_scu.sv
deleted file mode 100644
index b63972e..0000000
--- a/verilog/rtl/syntacore/scr1/src/core/scr1_scu.sv
+++ /dev/null
@@ -1,533 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_scu.sv>
-/// @brief System Control Unit (SCU)
-///
-
-//------------------------------------------------------------------------------
- //
- // Functionality:
- // - Generates System, Core, HDU and DM resets and their qualifier signals
- // - Provides debugger with software System and Core resets generation functionality
- // - Allows to set the behavior of DM and HDU resets
- // - Shows resets Statuses and Sticky Statuses
-
- // Structure:
- // - TAPC scan-chain interface
- // - SCU CSRs write/read interface
- // - SCU CSRS:
- // - CONTROL register
- // - MODE register
- // - STATUS register
- // - STICKY_STATUS register
- // - Reset logic
- // - System Reset
- // - Core Reset
- // - DM Reset
- // - HDU Reset
-//------------------------------------------------------------------------------
-
-`include "scr1_arch_description.svh"
-`include "scr1_scu.svh"
-
-`ifdef SCR1_DBG_EN
-
-module scr1_scu (
- // Global signals
- input logic pwrup_rst_n, // Power-Up Reset
- input logic rst_n, // Regular Reset
- input logic cpu_rst_n, // CPU Reset
- input logic test_mode, // DFT Test Mode
- input logic test_rst_n, // DFT Test Reset
- input logic clk, // SCU clock
-
- // TAPC scan-chains
- input logic tapcsync2scu_ch_sel_i, // TAPC Chain Select
- input logic tapcsync2scu_ch_id_i, // TAPC Chain ID
- input logic tapcsync2scu_ch_capture_i, // TAPC Chain Capture
- input logic tapcsync2scu_ch_shift_i, // TAPC Chain Shift
- input logic tapcsync2scu_ch_update_i, // TAPC Chain Update
- input logic tapcsync2scu_ch_tdi_i, // TAPC Chain TDI
- output logic scu2tapcsync_ch_tdo_o, // TAPC Chain TDO
-
- // Input sync resets:
- input logic ndm_rst_n_i, // Non-DM Reset input from DM
- input logic hart_rst_n_i, // HART Reset from DM
-
- // Generated resets
- output logic sys_rst_n_o, // System/Cluster Reset
- output logic core_rst_n_o, // Core Reset
- output logic dm_rst_n_o, // Debug Module Reset
- output logic hdu_rst_n_o, // HART Debug Unit Reset
-
- // Resets statuses
- output logic sys_rst_status_o, // System Reset Status (sync'ed to POR reset domain)
- output logic core_rst_status_o, // Core Reset Status (sync'ed to POR reset domain)
-
- // Reset Domain Crossing (RDC) qualifiers
- output logic sys_rdc_qlfy_o, // System/Cluster-to-ExternalSOC Reset Domain Crossing Qualifier
- output logic core_rdc_qlfy_o, // Core-to-ExternalSOC Reset Domain Crossing Qualifier
- output logic core2hdu_rdc_qlfy_o, // Core-to-HDU Reset Domain Crossing Qualifier
- output logic core2dm_rdc_qlfy_o, // Core-to-DM Reset Domain Crossing Qualifier
- output logic hdu2dm_rdc_qlfy_o // HDU-to-DM Reset Domain Crossing Qualifier
-);
-
-//------------------------------------------------------------------------------
-// Local Parameters
-//======================================================================================================================
-localparam int unsigned SCR1_SCU_RST_SYNC_STAGES_NUM = 2;
-
-//------------------------------------------------------------------------------
-// Local Signals
-//------------------------------------------------------------------------------
-
-// SCU CSR write/read i/f
-//------------------------------------------------------------------------------
-
-// TAPC scan-chain control logic
-logic scu_csr_req;
-logic tapc_dr_cap_req;
-logic tapc_dr_shft_req;
-logic tapc_dr_upd_req;
-
-// TAPC shift register signals
-logic tapc_shift_upd;
-type_scr1_scu_sysctrl_dr_s tapc_shift_ff;
-type_scr1_scu_sysctrl_dr_s tapc_shift_next;
-
-// TAPC shadow register signals
-type_scr1_scu_sysctrl_dr_s tapc_shadow_ff;
-
-// SCU CSR write/read i/f
-//------------------------------------------------------------------------------
-
-logic [SCR1_SCU_DR_SYSCTRL_DATA_WIDTH-1:0] scu_csr_wdata;
-logic [SCR1_SCU_DR_SYSCTRL_DATA_WIDTH-1:0] scu_csr_rdata;
-
-// SCU CSRs signals
-//------------------------------------------------------------------------------
-
-// Control register
-type_scr1_scu_sysctrl_control_reg_s scu_control_ff;
-logic scu_control_wr_req;
-
-// Mode register
-type_scr1_scu_sysctrl_mode_reg_s scu_mode_ff;
-logic scu_mode_wr_req;
-
-// Status register
-type_scr1_scu_sysctrl_status_reg_s scu_status_ff;
-type_scr1_scu_sysctrl_status_reg_s scu_status_ff_dly;
-type_scr1_scu_sysctrl_status_reg_s scu_status_ff_posedge;
-
-// Sticky Status register
-type_scr1_scu_sysctrl_status_reg_s scu_sticky_sts_ff;
-logic scu_sticky_sts_wr_req;
-
-// Reset logic signals
-//------------------------------------------------------------------------------
-
-// Input resets synchronization signals
-logic pwrup_rst_n_sync;
-logic rst_n_sync;
-logic cpu_rst_n_sync;
-
-// System Reset signals
-logic sys_rst_n_in;
-logic sys_rst_n_status;
-logic sys_rst_n_status_sync;
-logic sys_rst_n_qlfy;
-logic sys_reset_n;
-
-// Core Reset signals
-logic core_rst_n_in_sync;
-logic core_rst_n_status;
-logic core_rst_n_status_sync;
-logic core_rst_n_qlfy;
-logic core_reset_n;
-
-// HDU Reset signals
-logic hdu_rst_n_in_sync;
-logic hdu_rst_n_status;
-logic hdu_rst_n_status_sync;
-logic hdu_rst_n_qlfy;
-
-// DM Reset signals
-logic dm_rst_n_in;
-logic dm_rst_n_status;
-
-//------------------------------------------------------------------------------
-// TAPC scan-chain i/f
-//------------------------------------------------------------------------------
-//
- // Consists of the following functional units:
- // - TAPC scan-chain control logic
- // - TAPC shift register
- // - TAPC shadow register
-//
-
-// TAPC scan-chain control logic
-//------------------------------------------------------------------------------
-
-assign scu_csr_req = tapcsync2scu_ch_sel_i & (tapcsync2scu_ch_id_i == '0);
-assign tapc_dr_cap_req = scu_csr_req & tapcsync2scu_ch_capture_i;
-assign tapc_dr_shft_req = scu_csr_req & tapcsync2scu_ch_shift_i;
-assign tapc_dr_upd_req = scu_csr_req & tapcsync2scu_ch_update_i;
-
-// TAPC shift register
-//------------------------------------------------------------------------------
-
-assign tapc_shift_upd = tapc_dr_cap_req | tapc_dr_shft_req;
-
-always_ff @(posedge clk, negedge pwrup_rst_n_sync) begin
- if (~pwrup_rst_n_sync) begin
- tapc_shift_ff <= '0;
- end else if (tapc_shift_upd) begin
- tapc_shift_ff <= tapc_shift_next;
- end
-end
-
-assign tapc_shift_next = tapc_dr_cap_req ? tapc_shadow_ff
- : tapc_dr_shft_req ? {tapcsync2scu_ch_tdi_i, tapc_shift_ff[SCR1_SCU_DR_SYSCTRL_WIDTH-1:1]}// cp.5
- : tapc_shift_ff;
-
-// TAPC shadow register
-//------------------------------------------------------------------------------
-
-always_ff @(posedge clk, negedge pwrup_rst_n_sync) begin
- if (~pwrup_rst_n_sync) begin
- tapc_shadow_ff <= '0;
- end else if (tapc_dr_upd_req) begin
- tapc_shadow_ff.op <= tapc_shift_ff.op;
- tapc_shadow_ff.addr <= tapc_shift_ff.addr;
- tapc_shadow_ff.data <= scu_csr_wdata;
- end
-end
-
-assign scu2tapcsync_ch_tdo_o = tapc_shift_ff[0];
-
-//------------------------------------------------------------------------------
-// SCU CSRs write/read interface
-//------------------------------------------------------------------------------
-
-// Write interface
-//------------------------------------------------------------------------------
-
-// Register selection logic
-always_comb begin
- scu_control_wr_req = 1'b0;
- scu_mode_wr_req = 1'b0;
- scu_sticky_sts_wr_req = 1'b0;
-
- if (tapc_dr_upd_req && (tapc_shift_ff.op != SCR1_SCU_SYSCTRL_OP_READ)) begin
- case (tapc_shift_ff.addr)
- SCR1_SCU_SYSCTRL_ADDR_CONTROL: scu_control_wr_req = 1'b1;
- SCR1_SCU_SYSCTRL_ADDR_MODE : scu_mode_wr_req = 1'b1;
- SCR1_SCU_SYSCTRL_ADDR_STICKY : scu_sticky_sts_wr_req = (tapc_shift_ff.op == SCR1_SCU_SYSCTRL_OP_CLRBITS);
- default : begin end
- endcase
- end
-end
-
-// Write data construction
-always_comb begin
- scu_csr_wdata = '0;
-
- if (tapc_dr_upd_req) begin
- case (tapc_shift_ff.op)
- SCR1_SCU_SYSCTRL_OP_WRITE : scu_csr_wdata = tapc_shift_ff.data;
- SCR1_SCU_SYSCTRL_OP_READ : scu_csr_wdata = scu_csr_rdata;
- SCR1_SCU_SYSCTRL_OP_SETBITS: scu_csr_wdata = scu_csr_rdata | tapc_shift_ff.data;
- SCR1_SCU_SYSCTRL_OP_CLRBITS: scu_csr_wdata = scu_csr_rdata & (~tapc_shift_ff.data);
- default : begin end
- endcase
- end
-end
-
-// Read interface
-//------------------------------------------------------------------------------
-
-// Read data multiplexer
-always_comb begin
- scu_csr_rdata = '0;
-
- if (tapc_dr_upd_req) begin
- case (tapc_shift_ff.addr)
- SCR1_SCU_SYSCTRL_ADDR_CONTROL: scu_csr_rdata = scu_control_ff;
- SCR1_SCU_SYSCTRL_ADDR_MODE : scu_csr_rdata = scu_mode_ff;
- SCR1_SCU_SYSCTRL_ADDR_STATUS : scu_csr_rdata = scu_status_ff;
- SCR1_SCU_SYSCTRL_ADDR_STICKY : scu_csr_rdata = scu_sticky_sts_ff;
- default : scu_csr_rdata = 'x;
- endcase
- end
-end
-
-//------------------------------------------------------------------------------
-// SCU CSRs
-//------------------------------------------------------------------------------
-//
- // Registers:
- // - CONTROL register
- // - MODE register
- // - STATUS register
- // - STICKY_STATUS register
-//
-
-// CONTROL register
-//------------------------------------------------------------------------------
-// Allows debugger to generate System and Core resets
-
-always_ff @(posedge clk, negedge pwrup_rst_n_sync) begin
- if (~pwrup_rst_n_sync) begin
- scu_control_ff <= '0;
- end else if (scu_control_wr_req) begin
- scu_control_ff <= scu_csr_wdata;
- end
-end
-
-// MODE register
-//------------------------------------------------------------------------------
-// Sets reset behavior for DM Reset and HDU Reset signals
-
-always_ff @(posedge clk, negedge pwrup_rst_n_sync) begin
- if (~pwrup_rst_n_sync) begin
- scu_mode_ff <= '0;
- end else if (scu_mode_wr_req) begin
- scu_mode_ff <= scu_csr_wdata;
- end
-end
-
-// STATUS register
-//------------------------------------------------------------------------------
-// Holds the status of every output reset signal (System, Core, DM and HDU)
-
-assign scu_status_ff.sys_reset = sys_rst_status_o ;
-assign scu_status_ff.core_reset = core_rst_status_o;
-assign scu_status_ff.dm_reset = ~dm_rst_n_status;
-assign scu_status_ff.hdu_reset = ~hdu_rst_n_status_sync;
-
-// Status Register positive edge detection logic
-always_ff @(posedge clk, negedge pwrup_rst_n_sync) begin
- if (~pwrup_rst_n_sync) begin
- scu_status_ff_dly <= '0;
- end else begin
- scu_status_ff_dly <= scu_status_ff;
- end
-end
-
-assign scu_status_ff_posedge = scu_status_ff & ~scu_status_ff_dly;
-
-// STICKY_STATUS register
-//------------------------------------------------------------------------------
-// For every output reset signal shows if it was asserted since the last bit clearing
-integer i;
-always_ff @(posedge clk, negedge pwrup_rst_n_sync) begin
- if (~pwrup_rst_n_sync) begin
- scu_sticky_sts_ff <= '0;
- end else begin
- for (i = 0; i < SCR1_SCU_SYSCTRL_STATUS_REG_WIDTH ; i=i+1) begin // cp.4
- if (scu_status_ff_posedge[i]) begin
- scu_sticky_sts_ff[i] <= 1'b1;
- end else if (scu_sticky_sts_wr_req) begin
- scu_sticky_sts_ff[i] <= scu_csr_wdata[i];
- end
- end
- end
-end
-
-//------------------------------------------------------------------------------
-// Reset logic
-//------------------------------------------------------------------------------
-//
- // Consists of the following functional units:
- // - System Reset logic
- // - Core Reset logic
- // - Hart Debug Unit Reset logic
- // - Debug Module Reset logic
-//
-
-// Reset inputs are assumed synchronous
-assign pwrup_rst_n_sync = pwrup_rst_n;
-assign rst_n_sync = rst_n;
-assign cpu_rst_n_sync = cpu_rst_n;
-
-// Intermediate resets:
-assign sys_reset_n = ~scu_control_ff.sys_reset;
-assign core_reset_n = ~scu_control_ff.core_reset;
-
-// System/Cluster Reset: sys_rst_n_o
-//------------------------------------------------------------------------------
-
-scr1_reset_qlfy_adapter_cell_sync i_sys_rstn_qlfy_adapter_cell_sync (
- .rst_n (pwrup_rst_n_sync),
- .clk (clk ),
- .test_rst_n (test_rst_n ),
- .test_mode (test_mode ),
- .reset_n_in_sync (sys_rst_n_in ),
- .reset_n_out_qlfy (sys_rst_n_qlfy ),
- .reset_n_out (sys_rst_n_o ),
- .reset_n_status (sys_rst_n_status)
-);
-
-assign sys_rst_n_in = sys_reset_n & ndm_rst_n_i & rst_n_sync;
-
-scr1_data_sync_cell #(
- .STAGES_AMOUNT (SCR1_SCU_RST_SYNC_STAGES_NUM)
-) i_sys_rstn_status_sync (
- .rst_n (pwrup_rst_n_sync ),
- .clk (clk ),
- .data_in (sys_rst_n_status ),
- .data_out (sys_rst_n_status_sync)
-);
-
-assign sys_rst_status_o = ~sys_rst_n_status_sync;
-
-// System/Cluster-to-ExternalSOC RDC qualifier
-assign sys_rdc_qlfy_o = sys_rst_n_qlfy;
-
-// Core Reset: core_rst_n_o
-//------------------------------------------------------------------------------
-
-scr1_reset_qlfy_adapter_cell_sync i_core_rstn_qlfy_adapter_cell_sync (
- .rst_n (pwrup_rst_n_sync ),
- .clk (clk ),
- .test_rst_n (test_rst_n ),
- .test_mode (test_mode ),
- .reset_n_in_sync (core_rst_n_in_sync),
- .reset_n_out_qlfy (core_rst_n_qlfy ),
- .reset_n_out (core_rst_n_o ),
- .reset_n_status (core_rst_n_status )
-);
-
-assign core_rst_n_in_sync = sys_rst_n_in & hart_rst_n_i & core_reset_n & cpu_rst_n_sync;
-
-scr1_data_sync_cell #(
- .STAGES_AMOUNT (SCR1_SCU_RST_SYNC_STAGES_NUM)
-) i_core_rstn_status_sync (
- .rst_n (pwrup_rst_n_sync ),
- .clk (clk ),
- .data_in (core_rst_n_status ),
- .data_out (core_rst_n_status_sync)
-);
-
-assign core_rst_status_o = ~core_rst_n_status_sync;
-
-// Core Reset RDC Qualifiers:
-// - Core-to-ExternalSOC RDC Qlfy
-assign core_rdc_qlfy_o = core_rst_n_qlfy;
-// - Core-to-HDU RDC Qlfy
-assign core2hdu_rdc_qlfy_o = core_rst_n_qlfy;
-// - Core-to-DebugModule RDC Qlfy
-assign core2dm_rdc_qlfy_o = core_rst_n_qlfy;
-
-// Hart Debug Unit Reset: hdu_rst_n_o
-//------------------------------------------------------------------------------
-
-scr1_reset_qlfy_adapter_cell_sync i_hdu_rstn_qlfy_adapter_cell_sync (
- .rst_n (pwrup_rst_n_sync ),
- .clk (clk ),
- .test_rst_n (test_rst_n ),
- .test_mode (test_mode ),
- .reset_n_in_sync (hdu_rst_n_in_sync),
- .reset_n_out_qlfy (hdu_rst_n_qlfy ),
- .reset_n_out (hdu_rst_n_o ),
- .reset_n_status (hdu_rst_n_status )
-);
-
-assign hdu_rst_n_in_sync = scu_mode_ff.hdu_rst_bhv | core_rst_n_in_sync;
-
-scr1_data_sync_cell #(
- .STAGES_AMOUNT (SCR1_SCU_RST_SYNC_STAGES_NUM)
-) i_hdu_rstn_status_sync (
- .rst_n (pwrup_rst_n_sync ),
- .clk (clk ),
- .data_in (hdu_rst_n_status ),
- .data_out (hdu_rst_n_status_sync)
-);
-
-// Hart Debug Unit Reset RDC Qualifiers:
-// - HDU-to-DebugModule RDC Qlfy
-assign hdu2dm_rdc_qlfy_o = hdu_rst_n_qlfy;
-
-// Debug Module Reset: dm_rst_n_o
-//------------------------------------------------------------------------------
-
-scr1_reset_buf_cell i_dm_rstn_buf_cell (
- .rst_n (pwrup_rst_n_sync),
- .clk (clk ),
- .test_mode (test_mode ),
- .test_rst_n (test_rst_n ),
- .reset_n_in (dm_rst_n_in ),
- .reset_n_out (dm_rst_n_o ),
- .reset_n_status (dm_rst_n_status )
-);
-
-assign dm_rst_n_in = ~scu_mode_ff.dm_rst_bhv | sys_reset_n;
-
-`ifdef SCR1_TRGT_SIMULATION
-//--------------------------------------------------------------------
-// Assertions
-//--------------------------------------------------------------------
-
-`ifndef VERILATOR
-// Preventing some assertions to be raised at 0 sim time or in the first cycle
-initial begin
-$assertoff(0, scr1_scu);
-repeat (2) @(posedge clk);
-$asserton(0, scr1_scu);
-end
-`endif // VERILATOR
-
-// X checks
-SCR1_SVA_SCU_RESETS_XCHECK : assert property (
- @(negedge clk)
- !$isunknown({pwrup_rst_n, rst_n, cpu_rst_n, ndm_rst_n_i, hart_rst_n_i})
-) else $error("SCU resets error: unknown values of input resets");
-
-`ifndef VERILATOR
-// Qualifiers checks
-SCR1_SVA_SCU_SYS2SOC_QLFY_CHECK : assert property (
- @(negedge clk) disable iff (~pwrup_rst_n)
- $fell(sys_rst_n_o) |-> $fell($past(sys_rdc_qlfy_o))
-) else $error("SCU sys2soc qlfy error: qlfy wasn't raised prior to reset");
-
-SCR1_SVA_SCU_CORE2SOC_QLFY_CHECK : assert property (
- @(negedge clk) disable iff (~pwrup_rst_n)
- $fell(core_rst_n_o) |-> $fell($past(core_rdc_qlfy_o))
-) else $error("SCU core2soc qlfy error: qlfy wasn't raised prior to reset");
-
-SCR1_SVA_SCU_CORE2HDU_QLFY_CHECK : assert property (
- @(negedge clk) disable iff (~pwrup_rst_n)
- $fell(core_rst_n_o) |-> $fell($past(core2hdu_rdc_qlfy_o))
-) else $error("SCU core2hdu qlfy error: qlfy wasn't raised prior to reset");
-
-SCR1_SVA_SCU_CORE2DM_QLFY_CHECK : assert property (
- @(negedge clk) disable iff (~pwrup_rst_n)
- $fell(core_rst_n_o) |-> $fell($past(core2dm_rdc_qlfy_o))
-) else $error("SCU core2dm qlfy error: qlfy wasn't raised prior to reset");
-
-SCR1_SVA_SCU_HDU2DM_QLFY_CHECK : assert property (
- @(negedge clk) disable iff (~pwrup_rst_n)
- $fell(hdu_rst_n_o) |-> $fell($past(hdu2dm_rdc_qlfy_o))
-) else $error("SCU hdu2dm qlfy error: qlfy wasn't raised prior to reset");
-`endif // VERILATOR
-`endif // SCR1_TRGT_SIMULATION
-
-endmodule : scr1_scu
-`endif // SCR1_DBG_EN
-
diff --git a/verilog/rtl/syntacore/scr1/src/core/scr1_tapc.sv b/verilog/rtl/syntacore/scr1/src/core/scr1_tapc.sv
deleted file mode 100644
index 2761057..0000000
--- a/verilog/rtl/syntacore/scr1/src/core/scr1_tapc.sv
+++ /dev/null
@@ -1,473 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_tapc.sv>
-/// @brief TAP Controller (TAPC)
-///
-
-//------------------------------------------------------------------------------
- //
- // Functionality:
- // - Controls TAP operation
- // - Allows debugger to access TAP Data registers and DMI/SCU scan-chains via
- // command written in Instruction register
- //
- // Structure:
- // - Synchronous reset generation
- // - TAPC FSM
- // - TAPC Instruction Registers
- // - TAPC DRs/DMI/SCU scan-chains
- // - TAPC TDO enable and output Registers
- // - TAPC Data Registers
- // - BYPASS
- // - IDCODE
- // - BUILD ID
- //
-//------------------------------------------------------------------------------
-
-`include "scr1_arch_description.svh"
-
-`ifdef SCR1_DBG_EN
-`include "scr1_tapc.svh"
-`include "scr1_dm.svh"
-
-module scr1_tapc (
- // JTAG signals
- input logic tapc_trst_n, // Test Reset (TRSTn)
- input logic tapc_tck, // Test Clock (TCK)
- input logic tapc_tms, // Test Mode Select (TMS)
- input logic tapc_tdi, // Test Data Input (TDI)
- output logic tapc_tdo, // Test Data Output (TDO)
- output logic tapc_tdo_en, // TDO Enable, signal for TDO buffer control
-
- // Fuses:
- input logic [31:0] soc2tapc_fuse_idcode_i, // IDCODE value from fuses
-
- // DMI/SCU scan-chains
- output logic tapc2tapcsync_scu_ch_sel_o, // SCU Chain Select
- output logic tapc2tapcsync_dmi_ch_sel_o, // DMI Chain Select
- output logic [SCR1_DBG_DMI_CH_ID_WIDTH-1:0] tapc2tapcsync_ch_id_o, // DMI/SCU Chain Identifier
- output logic tapc2tapcsync_ch_capture_o, // DMI/SCU Chain Capture
- output logic tapc2tapcsync_ch_shift_o, // DMI/SCU Chain Shift
- output logic tapc2tapcsync_ch_update_o, // DMI/SCU Chain Update
- output logic tapc2tapcsync_ch_tdi_o, // DMI/SCU Chain TDI
- input logic tapcsync2tapc_ch_tdo_i // DMI/SCU Chain TDO
-);
-
-//------------------------------------------------------------------------------
-// Local Signals
-//------------------------------------------------------------------------------
-
-logic trst_n_int; // Sync reset signal
-
-// TAPC FSM signals
-//------------------------------------------------------------------------------
-
-type_scr1_tap_state_e tap_fsm_ff; // TAP's current state
-type_scr1_tap_state_e tap_fsm_next; // TAP's next state
-
-// Control signals
-logic tap_fsm_reset;
-logic tap_fsm_ir_upd;
-logic tap_fsm_ir_cap;
-logic tap_fsm_ir_shft;
-
-// Registered control signals
-logic tap_fsm_ir_shift_ff;
-logic tap_fsm_ir_shift_next;
-logic tap_fsm_dr_capture_ff;
-logic tap_fsm_dr_capture_next;
-logic tap_fsm_dr_shift_ff;
-logic tap_fsm_dr_shift_next;
-logic tap_fsm_dr_update_ff;
-logic tap_fsm_dr_update_next;
-
-// TAPC Instruction Registers signals
-//------------------------------------------------------------------------------
-
-logic [SCR1_TAP_INSTRUCTION_WIDTH-1:0] tap_ir_shift_ff; // Instruction Shift Register
-logic [SCR1_TAP_INSTRUCTION_WIDTH-1:0] tap_ir_shift_next; // Instruction Shift Register next value
-logic [SCR1_TAP_INSTRUCTION_WIDTH-1:0] tap_ir_ff; // Instruction Register
-logic [SCR1_TAP_INSTRUCTION_WIDTH-1:0] tap_ir_next; // Instruction Register next value
-
-// TAPC Data Registers signals
-//------------------------------------------------------------------------------
-
-// BYPASS register
-logic dr_bypass_sel;
-logic dr_bypass_tdo;
-
-// IDCODE register
-logic dr_idcode_sel;
-logic dr_idcode_tdo;
-
-// BUILD ID register
-logic dr_bld_id_sel;
-logic dr_bld_id_tdo;
-
-logic dr_out;
-
-// TDO registers
-//------------------------------------------------------------------------------
-
-// TDO enable register
-logic tdo_en_ff;
-logic tdo_en_next;
-
-// TDO output register
-logic tdo_out_ff;
-logic tdo_out_next;
-
-//------------------------------------------------------------------------------
-// TAPC Synchronous Reset logic
-//------------------------------------------------------------------------------
-
-always_ff @(negedge tapc_tck, negedge tapc_trst_n) begin
- if (~tapc_trst_n) begin
- trst_n_int <= 1'b0;
- end else begin
- trst_n_int <= ~tap_fsm_reset;
- end
-end
-
-//------------------------------------------------------------------------------
-// TAP's FSM
-//------------------------------------------------------------------------------
-
-always_ff @(posedge tapc_tck, negedge tapc_trst_n) begin
- if (~tapc_trst_n) begin
- tap_fsm_ff <= SCR1_TAP_STATE_RESET;
- end else begin
- tap_fsm_ff <= tap_fsm_next;
- end
-end
-
-always_comb begin
- case (tap_fsm_ff)
- SCR1_TAP_STATE_RESET : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_RESET : SCR1_TAP_STATE_IDLE;
- SCR1_TAP_STATE_IDLE : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_DR_SEL_SCAN : SCR1_TAP_STATE_IDLE;
- SCR1_TAP_STATE_DR_SEL_SCAN: tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_IR_SEL_SCAN : SCR1_TAP_STATE_DR_CAPTURE;
- SCR1_TAP_STATE_DR_CAPTURE : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_DR_EXIT1 : SCR1_TAP_STATE_DR_SHIFT;
- SCR1_TAP_STATE_DR_SHIFT : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_DR_EXIT1 : SCR1_TAP_STATE_DR_SHIFT;
- SCR1_TAP_STATE_DR_EXIT1 : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_DR_UPDATE : SCR1_TAP_STATE_DR_PAUSE;
- SCR1_TAP_STATE_DR_PAUSE : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_DR_EXIT2 : SCR1_TAP_STATE_DR_PAUSE;
- SCR1_TAP_STATE_DR_EXIT2 : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_DR_UPDATE : SCR1_TAP_STATE_DR_SHIFT;
- SCR1_TAP_STATE_DR_UPDATE : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_DR_SEL_SCAN : SCR1_TAP_STATE_IDLE;
- SCR1_TAP_STATE_IR_SEL_SCAN: tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_RESET : SCR1_TAP_STATE_IR_CAPTURE;
- SCR1_TAP_STATE_IR_CAPTURE : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_IR_EXIT1 : SCR1_TAP_STATE_IR_SHIFT;
- SCR1_TAP_STATE_IR_SHIFT : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_IR_EXIT1 : SCR1_TAP_STATE_IR_SHIFT;
- SCR1_TAP_STATE_IR_EXIT1 : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_IR_UPDATE : SCR1_TAP_STATE_IR_PAUSE;
- SCR1_TAP_STATE_IR_PAUSE : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_IR_EXIT2 : SCR1_TAP_STATE_IR_PAUSE;
- SCR1_TAP_STATE_IR_EXIT2 : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_IR_UPDATE : SCR1_TAP_STATE_IR_SHIFT;
- SCR1_TAP_STATE_IR_UPDATE : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_DR_SEL_SCAN : SCR1_TAP_STATE_IDLE;
-`ifdef SCR1_XPROP_EN
- default : tap_fsm_next = SCR1_TAP_STATE_XXX;
-`else // SCR1_XPROP_EN
- default : tap_fsm_next = tap_fsm_ff;
-`endif // SCR1_XPROP_EN
- endcase
-end
-
-assign tap_fsm_reset = (tap_fsm_ff == SCR1_TAP_STATE_RESET);
-assign tap_fsm_ir_upd = (tap_fsm_ff == SCR1_TAP_STATE_IR_UPDATE);
-assign tap_fsm_ir_cap = (tap_fsm_ff == SCR1_TAP_STATE_IR_CAPTURE);
-assign tap_fsm_ir_shft = (tap_fsm_ff == SCR1_TAP_STATE_IR_SHIFT);
-
-//------------------------------------------------------------------------------
-// TAPC Instruction Registers
-//------------------------------------------------------------------------------
-
-// TAPC Instruction Shift register
-//------------------------------------------------------------------------------
-
-always_ff @(posedge tapc_tck, negedge tapc_trst_n) begin
- if (~tapc_trst_n) begin
- tap_ir_shift_ff <= '0;
- end else if (~trst_n_int) begin
- tap_ir_shift_ff <= '0;
- end else begin
- tap_ir_shift_ff <= tap_ir_shift_next;
- end
-end
-
-assign tap_ir_shift_next = tap_fsm_ir_cap ? {{($bits(tap_ir_shift_ff)-1){1'b0}}, 1'b1}
- : tap_fsm_ir_shft ? {tapc_tdi, tap_ir_shift_ff[$left(tap_ir_shift_ff):1]}
- : tap_ir_shift_ff;
-
-// TAPC Instruction register
-//------------------------------------------------------------------------------
-
-always_ff @(negedge tapc_tck, negedge tapc_trst_n) begin
- if (~tapc_trst_n) begin
- tap_ir_ff <= SCR1_TAP_INSTR_IDCODE;
- end else if (~trst_n_int) begin
- tap_ir_ff <= SCR1_TAP_INSTR_IDCODE;
- end else begin
- tap_ir_ff <= tap_ir_next;
- end
-end
-
-assign tap_ir_next = tap_fsm_ir_upd ? tap_ir_shift_ff : tap_ir_ff;
-
-//------------------------------------------------------------------------------
-// Control signals
-//------------------------------------------------------------------------------
-
-always_ff @(posedge tapc_tck, negedge tapc_trst_n) begin
- if (~tapc_trst_n) begin
- tap_fsm_ir_shift_ff <= 1'b0;
- end else if (~trst_n_int) begin
- tap_fsm_ir_shift_ff <= 1'b0;
- end else begin
- tap_fsm_ir_shift_ff <= tap_fsm_ir_shift_next;
- end
-end
-
-assign tap_fsm_ir_shift_next = (tap_fsm_next == SCR1_TAP_STATE_IR_SHIFT);
-
-always_ff @(posedge tapc_tck, negedge tapc_trst_n) begin
- if (~tapc_trst_n) begin
- tap_fsm_dr_capture_ff <= 1'b0;
- end else if (~trst_n_int) begin
- tap_fsm_dr_capture_ff <= 1'b0;
- end else begin
- tap_fsm_dr_capture_ff <= tap_fsm_dr_capture_next;
- end
-end
-
-assign tap_fsm_dr_capture_next = (tap_fsm_next == SCR1_TAP_STATE_DR_CAPTURE);
-
-always_ff @(posedge tapc_tck, negedge tapc_trst_n) begin
- if (~tapc_trst_n) begin
- tap_fsm_dr_shift_ff <= 1'b0;
- end else if (~trst_n_int) begin
- tap_fsm_dr_shift_ff <= 1'b0;
- end else begin
- tap_fsm_dr_shift_ff <= tap_fsm_dr_shift_next;
- end
-end
-
-assign tap_fsm_dr_shift_next = (tap_fsm_next == SCR1_TAP_STATE_DR_SHIFT);
-
-always_ff @(posedge tapc_tck, negedge tapc_trst_n) begin
- if (~tapc_trst_n) begin
- tap_fsm_dr_update_ff <= 1'b0;
- end else if (~trst_n_int) begin
- tap_fsm_dr_update_ff <= 1'b0;
- end else begin
- tap_fsm_dr_update_ff <= tap_fsm_dr_update_next;
- end
-end
-
-assign tap_fsm_dr_update_next = (tap_fsm_next == SCR1_TAP_STATE_DR_UPDATE);
-
-//------------------------------------------------------------------------------
-// TAPC DRs/DMI/SCU scan-chains
-//------------------------------------------------------------------------------
-//
- // Consists of the following functional units:
- // - Data source/destination decoder
- // - DMI channel ID decoder
-
-// - Read data multiplexer
-// Data source/destination decoder
-//------------------------------------------------------------------------------
-
-always_comb begin
- dr_bypass_sel = 1'b0;
- dr_idcode_sel = 1'b0;
- dr_bld_id_sel = 1'b0;
- tapc2tapcsync_scu_ch_sel_o = 1'b0;
- tapc2tapcsync_dmi_ch_sel_o = 1'b0;
- case (tap_ir_ff)
- SCR1_TAP_INSTR_DTMCS : tapc2tapcsync_dmi_ch_sel_o = 1'b1;
- SCR1_TAP_INSTR_DMI_ACCESS: tapc2tapcsync_dmi_ch_sel_o = 1'b1;
- SCR1_TAP_INSTR_IDCODE : dr_idcode_sel = 1'b1;
- SCR1_TAP_INSTR_BYPASS : dr_bypass_sel = 1'b1;
- SCR1_TAP_INSTR_BLD_ID : dr_bld_id_sel = 1'b1;
- SCR1_TAP_INSTR_SCU_ACCESS: tapc2tapcsync_scu_ch_sel_o = 1'b1;
- default : dr_bypass_sel = 1'b1;
- endcase
-end
-
-// DMI channel ID decoder
-//------------------------------------------------------------------------------
-
-always_comb begin
- tapc2tapcsync_ch_id_o = '0;
- case (tap_ir_ff)
- SCR1_TAP_INSTR_DTMCS : tapc2tapcsync_ch_id_o = 'd1;
- SCR1_TAP_INSTR_DMI_ACCESS: tapc2tapcsync_ch_id_o = 'd2;
- default : tapc2tapcsync_ch_id_o = '0;
- endcase
-end
-
-// Read data multiplexer
-//------------------------------------------------------------------------------
-
-always_comb begin
- dr_out = 1'b0;
- case (tap_ir_ff)
- SCR1_TAP_INSTR_DTMCS : dr_out = tapcsync2tapc_ch_tdo_i;
- SCR1_TAP_INSTR_DMI_ACCESS: dr_out = tapcsync2tapc_ch_tdo_i;
- SCR1_TAP_INSTR_IDCODE : dr_out = dr_idcode_tdo;
- SCR1_TAP_INSTR_BYPASS : dr_out = dr_bypass_tdo;
- SCR1_TAP_INSTR_BLD_ID : dr_out = dr_bld_id_tdo;
- SCR1_TAP_INSTR_SCU_ACCESS: dr_out = tapcsync2tapc_ch_tdo_i;
- default : dr_out = dr_bypass_tdo;
- endcase
-end
-
-//------------------------------------------------------------------------------
-// TDO enable and output registers
-//------------------------------------------------------------------------------
-
-// TDO enable register
-//------------------------------------------------------------------------------
-
-always_ff @(negedge tapc_tck, negedge tapc_trst_n) begin
- if (~tapc_trst_n) begin
- tdo_en_ff <= 1'b0;
- end else if (~trst_n_int) begin
- tdo_en_ff <= 1'b0;
- end else begin
- tdo_en_ff <= tdo_en_next;
- end
-end
-
-assign tdo_en_next = tap_fsm_dr_shift_ff | tap_fsm_ir_shift_ff;
-
-// TDO output register
-//------------------------------------------------------------------------------
-
-always_ff @(negedge tapc_tck, negedge tapc_trst_n) begin
- if (~tapc_trst_n) begin
- tdo_out_ff <= 1'b0;
- end else if (~trst_n_int) begin
- tdo_out_ff <= 1'b0;
- end else begin
- tdo_out_ff <= tdo_out_next;
- end
-end
-
-assign tdo_out_next = tap_fsm_dr_shift_ff ? dr_out
- : tap_fsm_ir_shift_ff ? tap_ir_shift_ff[0]
- : 1'b0;
-
-// TAPC TDO signals
-assign tapc_tdo_en = tdo_en_ff;
-assign tapc_tdo = tdo_out_ff;
-
-//------------------------------------------------------------------------------
-// TAPC Data Registers
-//------------------------------------------------------------------------------
-//
- // Registers:
- // - BYPASS register
- // - IDCODE register
- // - BUILD ID register
-
-// BYPASS register
-//------------------------------------------------------------------------------
-// 1-bit mandatory IEEE 1149.1 compliant register
-
-scr1_tapc_shift_reg #(
- .SCR1_WIDTH (SCR1_TAP_DR_BYPASS_WIDTH),
- .SCR1_RESET_VALUE (SCR1_TAP_DR_BYPASS_WIDTH'(0))
-) i_bypass_reg (
- .clk (tapc_tck ),
- .rst_n (tapc_trst_n ),
- .rst_n_sync (trst_n_int ),
- .fsm_dr_select (dr_bypass_sel ),
- .fsm_dr_capture (tap_fsm_dr_capture_ff),
- .fsm_dr_shift (tap_fsm_dr_shift_ff ),
- .din_serial (tapc_tdi ),
- .din_parallel (1'b0 ),
- .dout_serial (dr_bypass_tdo ),
- .dout_parallel ( )
-);
-
-// IDCODE register
-//------------------------------------------------------------------------------
-// Holds the Device ID value (mandatory IEEE 1149.1 compliant register)
-
-scr1_tapc_shift_reg #(
- .SCR1_WIDTH (SCR1_TAP_DR_IDCODE_WIDTH),
- .SCR1_RESET_VALUE (SCR1_TAP_DR_IDCODE_WIDTH'(0))
-) i_tap_idcode_reg (
- .clk (tapc_tck ),
- .rst_n (tapc_trst_n ),
- .rst_n_sync (trst_n_int ),
- .fsm_dr_select (dr_idcode_sel ),
- .fsm_dr_capture (tap_fsm_dr_capture_ff ),
- .fsm_dr_shift (tap_fsm_dr_shift_ff ),
- .din_serial (tapc_tdi ),
- .din_parallel (soc2tapc_fuse_idcode_i),
- .dout_serial (dr_idcode_tdo ),
- .dout_parallel ( )
-);
-
-// BUILD ID register
-//------------------------------------------------------------------------------
-// Holds the BUILD ID value
-
-scr1_tapc_shift_reg #(
- .SCR1_WIDTH (SCR1_TAP_DR_BLD_ID_WIDTH),
- .SCR1_RESET_VALUE (SCR1_TAP_DR_BLD_ID_WIDTH'(0))
-) i_tap_dr_bld_id_reg (
- .clk (tapc_tck ),
- .rst_n (tapc_trst_n ),
- .rst_n_sync (trst_n_int ),
- .fsm_dr_select (dr_bld_id_sel ),
- .fsm_dr_capture (tap_fsm_dr_capture_ff),
- .fsm_dr_shift (tap_fsm_dr_shift_ff ),
- .din_serial (tapc_tdi ),
- .din_parallel (SCR1_TAP_BLD_ID_VALUE),
- .dout_serial (dr_bld_id_tdo ),
- .dout_parallel ( )
-);
-
-//------------------------------------------------------------------------------
-// DMI/SCU scan-chains signals
-//------------------------------------------------------------------------------
-
-assign tapc2tapcsync_ch_tdi_o = tapc_tdi;
-assign tapc2tapcsync_ch_capture_o = tap_fsm_dr_capture_ff;
-assign tapc2tapcsync_ch_shift_o = tap_fsm_dr_shift_ff;
-assign tapc2tapcsync_ch_update_o = tap_fsm_dr_update_ff;
-
-`ifdef SCR1_TRGT_SIMULATION
-//-------------------------------------------------------------------------------
-// Assertion
-//-------------------------------------------------------------------------------
-
-// X checks
-SCR1_SVA_TAPC_XCHECK : assert property (
- @(posedge tapc_tck) disable iff (~tapc_trst_n)
- !$isunknown({tapc_tms, tapc_tdi})
-) else $error("TAPC error: unknown values");
-
-SCR1_SVA_TAPC_XCHECK_NEGCLK : assert property (
- @(negedge tapc_tck) disable iff (tap_fsm_ff != SCR1_TAP_STATE_DR_SHIFT)
- !$isunknown({tapcsync2tapc_ch_tdo_i})
-) else $error("TAPC @negedge error: unknown values");
-
-`endif // SCR1_TRGT_SIMULATION
-
-endmodule : scr1_tapc
-
-`endif // SCR1_DBG_EN
diff --git a/verilog/rtl/syntacore/scr1/src/core/scr1_tapc_shift_reg.sv b/verilog/rtl/syntacore/scr1/src/core/scr1_tapc_shift_reg.sv
deleted file mode 100644
index a9da091..0000000
--- a/verilog/rtl/syntacore/scr1/src/core/scr1_tapc_shift_reg.sv
+++ /dev/null
@@ -1,128 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_tapc_shift_reg.sv>
-/// @brief TAPC shift register. Parameterized implementation of JTAG TAPC's Shift Register.
-///
-
-`include "scr1_arch_description.svh"
-
-`ifdef SCR1_DBG_EN
-module scr1_tapc_shift_reg #(
- parameter int unsigned SCR1_WIDTH = 8, // Register width, bits
- parameter logic [SCR1_WIDTH-1:0] SCR1_RESET_VALUE = '0 // Register's value after reset
-) (
- input logic clk, // Clock
- input logic rst_n, // Async reset
- input logic rst_n_sync, // Sync reset
- // TAP FSM's control signals:
- input logic fsm_dr_select, // - for this DR selection (operation enabling);
- input logic fsm_dr_capture, // - to capture parallel input's data into shift register;
- input logic fsm_dr_shift, // - to enable data shifting;
- // Inputs:
- input logic din_serial, // - serial (shift_reg[msb/SCR1_WIDTH]);
- input logic [SCR1_WIDTH-1:0] din_parallel, // - parallel (shift register's input).
- // Outputs:
- output logic dout_serial, // - serial (shift_reg[0]);
- output logic [SCR1_WIDTH-1:0] dout_parallel // - parallel (shift register's output).
-);
-
-//-------------------------------------------------------------------------------
-// Local signals declaration
-//-------------------------------------------------------------------------------
-logic [SCR1_WIDTH-1:0] shift_reg;
-
-//-------------------------------------------------------------------------------
-// Shift register
-//-------------------------------------------------------------------------------
-generate
- if (SCR1_WIDTH > 1)
- begin : dr_shift_reg
-
- always_ff @(posedge clk, negedge rst_n)
- begin
- if (~rst_n) begin
- shift_reg <= SCR1_RESET_VALUE;
- end
- else if (~rst_n_sync) begin
- shift_reg <= SCR1_RESET_VALUE;
- end
- else if (fsm_dr_select & fsm_dr_capture) begin
- shift_reg <= din_parallel;
- end
- else if (fsm_dr_select & fsm_dr_shift) begin
- shift_reg <= {din_serial, shift_reg[SCR1_WIDTH-1:1]};
- end
- end
-
- end
- else begin : dr_shift_reg
-
- always_ff @(posedge clk, negedge rst_n)
- begin
- if (~rst_n) begin
- shift_reg <= SCR1_RESET_VALUE;
- end
- else if (~rst_n_sync) begin
- shift_reg <= SCR1_RESET_VALUE;
- end
- else if (fsm_dr_select & fsm_dr_capture) begin
- shift_reg <= din_parallel;
- end
- else if (fsm_dr_select & fsm_dr_shift) begin
- shift_reg <= din_serial;
- end
- end
-
- end
-endgenerate
-
-//-------------------------------------------------------------------------------
-// Parallel output
-//-------------------------------------------------------------------------------
-assign dout_parallel = shift_reg;
-
-//-------------------------------------------------------------------------------
-// Serial output
-//-------------------------------------------------------------------------------
-assign dout_serial = shift_reg[0];
-
-`ifdef SCR1_TRGT_SIMULATION
-//-------------------------------------------------------------------------------
-// Assertion
-//-------------------------------------------------------------------------------
-
-// X checks
-SCR1_SVA_TAPC_SHIFTREG_XCHECK : assert property (
- @(negedge clk) disable iff (~rst_n)
- !$isunknown({
- rst_n_sync,
- fsm_dr_select,
- fsm_dr_capture,
- fsm_dr_shift,
- din_serial,
- din_parallel
- })
-) else begin
- $error("TAPC Shift Reg error: unknown values");
-end
-
-`endif // SCR1_TRGT_SIMULATION
-
-endmodule : scr1_tapc_shift_reg
-
-`endif // SCR1_DBG_EN
diff --git a/verilog/rtl/syntacore/scr1/src/core/scr1_tapc_synchronizer.sv b/verilog/rtl/syntacore/scr1/src/core/scr1_tapc_synchronizer.sv
deleted file mode 100644
index 39715d9..0000000
--- a/verilog/rtl/syntacore/scr1/src/core/scr1_tapc_synchronizer.sv
+++ /dev/null
@@ -1,199 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_tapc_synchronizer.sv>
-/// @brief TAPC clock domain crossing synchronizer
-///
-
-`include "scr1_arch_description.svh"
-
-`ifdef SCR1_DBG_EN
-`include "scr1_tapc.svh"
-`include "scr1_dm.svh"
-
-module scr1_tapc_synchronizer (
- // System common signals
- input logic pwrup_rst_n, // Power-Up Reset
- input logic dm_rst_n, // Debug Module Reset
- input logic clk, // System Clock (SysCLK)
-
- // JTAG common signals
- input logic tapc_trst_n, // JTAG Test Reset (TRSTn)
- input logic tapc_tck, // JTAG Test Clock (TCK)
-
-
- // DMI/SCU scan-chains
- input logic tapc2tapcsync_scu_ch_sel_i, // SCU Chain Select input (TCK domain)
- output logic tapcsync2scu_ch_sel_o, // SCU Chain Select output (SysCLK domain)
- input logic tapc2tapcsync_dmi_ch_sel_i, // DMI Chain Select input (TCK domain)
- output logic tapcsync2dmi_ch_sel_o, // DMI Chain Select output (SysCLK domain)
-
- input logic [SCR1_DBG_DMI_CH_ID_WIDTH-1:0] tapc2tapcsync_ch_id_i, // DMI/SCU Chain Identifier input (TCK domain)
- output logic [SCR1_DBG_DMI_CH_ID_WIDTH-1:0] tapcsync2core_ch_id_o, // DMI/SCU Chain Identifier output (SysCLK domain)
-
- input logic tapc2tapcsync_ch_capture_i, // DMI/SCU Chain Capture input (TCK domain)
- output logic tapcsync2core_ch_capture_o, // DMI/SCU Chain Capture output (SysCLK domain)
-
- input logic tapc2tapcsync_ch_shift_i, // DMI/SCU Chain Shift input (TCK domain)
- output logic tapcsync2core_ch_shift_o, // DMI/SCU Chain Shift output (SysCLK domain)
-
- input logic tapc2tapcsync_ch_update_i, // DMI/SCU Chain Update input (TCK domain)
- output logic tapcsync2core_ch_update_o, // DMI/SCU Chain Update output (SysCLK domain)
-
- input logic tapc2tapcsync_ch_tdi_i, // DMI/SCU Chain TDI input (TCK domain)
- output logic tapcsync2core_ch_tdi_o, // DMI/SCU Chain TDI output (SysCLK domain)
-
- output logic tapc2tapcsync_ch_tdo_i, // DMI/SCU Chain TDO output (TCK domain)
- input logic tapcsync2core_ch_tdo_o // DMI/SCU Chain TDO input (SysCLK domain)
-);
-
-//-------------------------------------------------------------------------------
-// Local signals declaration
-//-------------------------------------------------------------------------------
-
-logic tck_divpos;
-logic tck_divneg;
-logic tck_rise_load;
-logic tck_rise_reset;
-logic tck_fall_load;
-logic tck_fall_reset;
-logic [3:0] tck_divpos_sync;
-logic [3:0] tck_divneg_sync;
-logic [2:0] dmi_ch_capture_sync;
-logic [2:0] dmi_ch_shift_sync;
-logic [2:0] dmi_ch_tdi_sync;
-
-//-------------------------------------------------------------------------------
-// Logic
-//-------------------------------------------------------------------------------
-
-always_ff @(posedge tapc_tck, negedge tapc_trst_n) begin
- if (~tapc_trst_n) begin
- tck_divpos <= 1'b0;
- end else begin
- tck_divpos <= ~tck_divpos;
- end
-end
-
-always_ff @(negedge tapc_tck, negedge tapc_trst_n) begin
- if (~tapc_trst_n) begin
- tck_divneg <= 1'b0;
- end else begin
- tck_divneg <= ~tck_divneg;
- end
-end
-
-always_ff @(posedge clk, negedge pwrup_rst_n) begin
- if (~pwrup_rst_n) begin
- tck_divpos_sync <= 4'd0;
- tck_divneg_sync <= 4'd0;
- end else begin
- tck_divpos_sync <= {tck_divpos_sync[2:0], tck_divpos};
- tck_divneg_sync <= {tck_divneg_sync[2:0], tck_divneg};
- end
-end
-
-assign tck_rise_load = tck_divpos_sync[2] ^ tck_divpos_sync[1];
-assign tck_rise_reset = tck_divpos_sync[3] ^ tck_divpos_sync[2];
-assign tck_fall_load = tck_divneg_sync[2] ^ tck_divneg_sync[1];
-assign tck_fall_reset = tck_divneg_sync[3] ^ tck_divneg_sync[2];
-
-always_ff @(posedge clk, negedge pwrup_rst_n) begin
- if (~pwrup_rst_n) begin
- tapcsync2core_ch_update_o <= '0;
- end else begin
- if (tck_fall_load) begin
- tapcsync2core_ch_update_o <= tapc2tapcsync_ch_update_i;
- end else if (tck_fall_reset) begin
- tapcsync2core_ch_update_o <= '0;
- end
- end
-end
-
-always_ff @(negedge tapc_tck, negedge tapc_trst_n) begin
- if (~tapc_trst_n) begin
- dmi_ch_capture_sync[0] <= '0;
- dmi_ch_shift_sync[0] <= '0;
- end else begin
- dmi_ch_capture_sync[0] <= tapc2tapcsync_ch_capture_i;
- dmi_ch_shift_sync[0] <= tapc2tapcsync_ch_shift_i;
- end
-end
-
-always_ff @(posedge clk, negedge pwrup_rst_n) begin
- if (~pwrup_rst_n) begin
- dmi_ch_capture_sync[2:1] <= '0;
- dmi_ch_shift_sync[2:1] <= '0;
- end else begin
- dmi_ch_capture_sync[2:1] <= {dmi_ch_capture_sync[1], dmi_ch_capture_sync[0]};
- dmi_ch_shift_sync[2:1] <= {dmi_ch_shift_sync[1], dmi_ch_shift_sync[0]};
- end
-end
-
-always_ff @(posedge clk, negedge pwrup_rst_n) begin
- if (~pwrup_rst_n) begin
- dmi_ch_tdi_sync <= '0;
- end else begin
- dmi_ch_tdi_sync <= {dmi_ch_tdi_sync[1:0], tapc2tapcsync_ch_tdi_i};
- end
-end
-
-always_ff @(posedge clk, negedge pwrup_rst_n) begin
- if (~pwrup_rst_n) begin
- tapcsync2core_ch_capture_o <= '0;
- tapcsync2core_ch_shift_o <= '0;
- tapcsync2core_ch_tdi_o <= '0;
- end else begin
- if (tck_rise_load) begin
- tapcsync2core_ch_capture_o <= dmi_ch_capture_sync[2];
- tapcsync2core_ch_shift_o <= dmi_ch_shift_sync[2];
- tapcsync2core_ch_tdi_o <= dmi_ch_tdi_sync[2];
- end else if (tck_rise_reset) begin
- tapcsync2core_ch_capture_o <= '0;
- tapcsync2core_ch_shift_o <= '0;
- tapcsync2core_ch_tdi_o <= '0;
- end
- end
-end
-
-always_ff @(posedge clk, negedge dm_rst_n) begin
- if (~dm_rst_n) begin
- tapcsync2dmi_ch_sel_o <= '0;
- tapcsync2core_ch_id_o <= '0;
- end else begin
- if (tck_rise_load) begin
- tapcsync2dmi_ch_sel_o <= tapc2tapcsync_dmi_ch_sel_i;
- tapcsync2core_ch_id_o <= tapc2tapcsync_ch_id_i;
- end
- end
-end
-
-always_ff @(posedge clk, negedge pwrup_rst_n) begin
- if (~pwrup_rst_n) begin
- tapcsync2scu_ch_sel_o <= '0;
- end else begin
- if (tck_rise_load) begin
- tapcsync2scu_ch_sel_o <= tapc2tapcsync_scu_ch_sel_i;
- end
- end
-end
-
-assign tapc2tapcsync_ch_tdo_i = tapcsync2core_ch_tdo_o;
-
-endmodule : scr1_tapc_synchronizer
-
-`endif // SCR1_DBG_EN
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_ahb.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_ahb.svh
deleted file mode 100644
index c630f6a..0000000
--- a/verilog/rtl/syntacore/scr1/src/includes/scr1_ahb.svh
+++ /dev/null
@@ -1,75 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_ahb.svh>
-/// @brief AHB header file
-///
-
-`ifndef SCR1_AHB_SVH
-`define SCR1_AHB_SVH
-
-`include "scr1_arch_description.svh"
-
-parameter SCR1_AHB_WIDTH = 32;
-
-// Encoding for HTRANS signal
-parameter logic [1:0] SCR1_HTRANS_IDLE = 2'b00;
-parameter logic [1:0] SCR1_HTRANS_NONSEQ = 2'b10;
-`ifdef SCR1_XPROP_EN
-parameter logic [1:0] SCR1_HTRANS_ERR = 'x;
-`else // SCR1_XPROP_EN
-parameter logic [1:0] SCR1_HTRANS_ERR = '0;
-`endif // SCR1_XPROP_EN
-
-// Encoding for HBURST signal
-parameter logic [2:0] SCR1_HBURST_SINGLE = 3'b000;
-`ifdef SCR1_XPROP_EN
-parameter logic [2:0] SCR1_HBURST_ERR = 'x;
-`else // SCR1_XPROP_EN
-parameter logic [1:0] SCR1_HBURST_ERR = '0;
-`endif // SCR1_XPROP_EN
-
-// Encoding for HSIZE signal
-parameter logic [2:0] SCR1_HSIZE_8B = 3'b000;
-parameter logic [2:0] SCR1_HSIZE_16B = 3'b001;
-parameter logic [2:0] SCR1_HSIZE_32B = 3'b010;
-`ifdef SCR1_XPROP_EN
-parameter logic [2:0] SCR1_HSIZE_ERR = 'x;
-`else // SCR1_XPROP_EN
-parameter logic [1:0] SCR1_HSIZE_ERR = '0;
-`endif // SCR1_XPROP_EN
-
-// Encoding HPROT signal
-// HPROT[0] : 0 - instr; 1 - data
-// HPROT[1] : 0 - user; 1 - privilege
-// HPROT[2] : 0 - not buffer; 1 - buffer
-// HPROT[3] : 0 - cacheable; 1 - cacheable
-parameter SCR1_HPROT_DATA = 0;
-parameter SCR1_HPROT_PRV = 1;
-parameter SCR1_HPROT_BUF = 2;
-parameter SCR1_HPROT_CACHE = 3;
-
-// Encoding HRESP signal
-parameter logic SCR1_HRESP_OKAY = 1'b0;
-parameter logic SCR1_HRESP_ERROR = 1'b1;
-`ifdef SCR1_XPROP_EN
-parameter logic SCR1_HRESP_ERR = 1'bx;
-`else // SCR1_XPROP_EN
-parameter logic SCR1_HRESP_ERR = 1'b0;
-`endif // SCR1_XPROP_EN
-
-`endif // SCR1_AHB_SVH
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh
deleted file mode 100644
index 2810776..0000000
--- a/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh
+++ /dev/null
@@ -1,233 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_arch_description.svh>
-/// @brief Architecture description file
-///
-
-`ifndef SCR1_ARCH_DESCRIPTION_SVH
-`define SCR1_ARCH_DESCRIPTION_SVH
-
-
-//------------------------------------------------------------------------------
-// CORE FUNDAMENTAL PARAMETERS
-//------------------------------------------------------------------------------
-
-// SCR1 core identifiers
-`define SCR1_MIMPID 32'h21051400
-`define SCR1_MVENDORID 32'h00000000
-
-// Width of main registers and buses
-`define SCR1_XLEN 32
-`define SCR1_IMEM_AWIDTH `SCR1_XLEN
-`define SCR1_IMEM_DWIDTH `SCR1_XLEN
-`define SCR1_DMEM_AWIDTH `SCR1_XLEN
-`define SCR1_DMEM_DWIDTH `SCR1_XLEN
-
-// TAP IDCODE
-`define SCR1_TAP_IDCODE 'hDEB11001
-
-
-`ifdef SCR1_ARCH_CUSTOM
-//------------------------------------------------------------------------------
-// INCLUDE SCR1_ARCH_CUSTOM.SVH
-//------------------------------------------------------------------------------
-
-// The external file scr1_arch_custom.svh is used for the open SCR1-SDK project,
-// and can also be used for any custom projects.
-
-// The file sets:
-// - target platform (FPGA/ASIC), which affects the choice of logical constructs;
-// - device build ID;
-// - address constants;
-// - could enables configuration parameters.
-
-// Possible targets:
-// `define SCR1_TRGT_FPGA_INTEL // target platform is Intel FPGAs
-// `define SCR1_TRGT_FPGA_INTEL_MAX10 // target platform is Intel MAX 10 FPGAs (used in the SCR1-SDK project)
-// `define SCR1_TRGT_FPGA_INTEL_ARRIAV // target platform is Intel Arria V FPGAs (used in the SCR1-SDK project)
-// `define SCR1_TRGT_FPGA_XILINX // target platform is Xilinx FPGAs (used in the SCR1-SDK project)
-// `define SCR1_TRGT_ASIC // target platform is ASIC
-// `define SCR1_TRGT_SIMULATION // target is simulation (enable simulation code)
-
- `include "scr1_arch_custom.svh"
-
-`endif // SCR1_ARCH_CUSTOM
-
-
-//------------------------------------------------------------------------------
-// RECOMMENDED CORE ARCHITECTURE CONFIGURATIONS
-//------------------------------------------------------------------------------
-
-// Uncomment one of these defines to set the recommended configuration:
-
-`define SCR1_CFG_RV32IMC_MAX
-//`define SCR1_CFG_RV32IC_BASE
-//`define SCR1_CFG_RV32EC_MIN
-
-// If all defines are commented, custom configuration will be used (see below)
-
-//------------------------------------------------------------------------------
-// READ-ONLY: settings for recommended configurations
-`ifdef SCR1_CFG_RV32IMC_MAX
- `define SCR1_RVI_EXT
- `define SCR1_RVM_EXT
- `define SCR1_RVC_EXT
- parameter int unsigned SCR1_MTVEC_BASE_WR_BITS = 26;
- `define SCR1_MTVEC_MODE_EN // enable writable MTVEC.mode field to allow vectored irq mode, otherwise only direct mode is possible
-// `define SCR1_FAST_MUL // enable fast one-cycle multiplication, otherwise multiplication takes 32 cycles
-//`define SCR1_MPRF_RST_EN - yosys fix, two dimensional array init not allowed
- `define SCR1_MCOUNTEN_EN // enable custom MCOUNTEN CSR for counter control
-//`define SCR1_DBG_EN // enable Debug Subsystem (TAPC, DM, SCU, HDU)
-//`define SCR1_TDU_EN // enable Trigger Debug Unit (hardware breakpoints)
-// parameter int unsigned SCR1_TDU_TRIG_NUM = 4;
-// `define SCR1_TDU_ICOUNT_EN // enable hardware triggers on instruction counter
- `define SCR1_IPIC_EN // enable Integrated Programmable Interrupt Controller
- `define SCR1_IPIC_SYNC_EN // enable IPIC synchronizer
- `define SCR1_TCM_EN
- `define SCR1_NEW_PC_REG // enable register in IFU for New_PC value
- `define SCRC1_MPRF_STAGE // enabled register at Read path of MPRF
-`elsif SCR1_CFG_RV32IC_BASE
- `define SCR1_RVI_EXT
- `define SCR1_RVC_EXT
- parameter int unsigned SCR1_MTVEC_BASE_WR_BITS = 16;
- `define SCR1_MTVEC_MODE_EN
- `define SCR1_NO_DEC_STAGE
- `define SCR1_MPRF_RST_EN
- `define SCR1_MCOUNTEN_EN
- `define SCR1_DBG_EN
- `define SCR1_TDU_EN
- parameter int unsigned SCR1_TDU_TRIG_NUM = 2;
- `define SCR1_TDU_ICOUNT_EN
- `define SCR1_IPIC_EN
- `define SCR1_IPIC_SYNC_EN
- `define SCR1_TCM_EN
-`elsif SCR1_CFG_RV32EC_MIN
- `define SCR1_RVE_EXT
- `define SCR1_RVC_EXT
- parameter int unsigned SCR1_MTVEC_BASE_WR_BITS = 0;
- `define SCR1_NO_DEC_STAGE
- `define SCR1_NO_EXE_STAGE
- `define SCR1_TCM_EN
-
-`else // begin custom configuration section
-
-
-//------------------------------------------------------------------------------
-// CUSTOM CORE ARCHITECTURE CONFIGURATION
-//------------------------------------------------------------------------------
-
-// To fine-tune custom configuration, you can change the values in this section.
-// Make sure that the defines of the recommended configurations are commented,
-// otherwise this section will be inactive.
-
-// RISC-V ISA options
-//`define SCR1_RVE_EXT // enable RV32E base integer instruction set, otherwise RV32I will be used
-`define SCR1_RVM_EXT // enable standard extension "M" for integer hardware multiplier and divider
-`define SCR1_RVC_EXT // enable standard extension "C" for compressed instructions
-parameter int unsigned SCR1_MTVEC_BASE_WR_BITS = 26; // number of writable high-order bits in MTVEC.base field
- // legal values are 0 to 26
- // read-only bits are hardwired to reset value
-`define SCR1_MTVEC_MODE_EN // enable writable MTVEC.mode field to allow vectored irq mode, otherwise only direct mode is possible
-
-`ifndef SCR1_RVE_EXT
- `define SCR1_RVI_EXT // RV32E base integer instruction set if SCR1_RVE_EXT is not enabled
-`endif // ~SCR1_RVE_EXT
-
-// Core pipeline options (power-performance-area optimization)
-`define SCR1_NO_DEC_STAGE // disable register between IFU and IDU
-`define SCR1_NO_EXE_STAGE // disable register between IDU and EXU
-`define SCR1_NEW_PC_REG // enable register in IFU for New_PC value
-`define SCR1_FAST_MUL // enable fast one-cycle multiplication, otherwise multiplication takes 32 cycles
-`define SCR1_CLKCTRL_EN // enable global clock gating
-`define SCR1_MPRF_RST_EN // enable reset for MPRF
-`define SCR1_MCOUNTEN_EN // enable custom MCOUNTEN CSR for counter control
-
-// Uncore options
-`define SCR1_DBG_EN // enable Debug Subsystem (TAPC, DM, SCU, HDU)
-`define SCR1_TDU_EN // enable Trigger Debug Unit (hardware breakpoints)
-parameter int unsigned SCR1_TDU_TRIG_NUM = 2; // number of hardware triggers
-`define SCR1_TDU_ICOUNT_EN // enable hardware triggers on instruction counter
-`define SCR1_IPIC_EN // enable Integrated Programmable Interrupt Controller
-`define SCR1_IPIC_SYNC_EN // enable IPIC synchronizer
-`define SCR1_TCM_EN // enable Tightly-Coupled Memory
-
-`endif // end custom configuration section
-
-
-//------------------------------------------------------------------------------
-// CORE INTEGRATION OPTIONS
-//------------------------------------------------------------------------------
-
-// Bypasses on AXI/AHB bridge I/O
-`define SCR1_IMEM_AHB_IN_BP // bypass instruction memory AHB bridge input register
-`define SCR1_IMEM_AHB_OUT_BP // bypass instruction memory AHB bridge output register
-`define SCR1_DMEM_AHB_IN_BP // bypass data memory AHB bridge input register
-`define SCR1_DMEM_AHB_OUT_BP // bypass data memory AHB bridge output register
-`define SCR1_IMEM_AXI_REQ_BP // bypass instruction memory AXI bridge request register
-`define SCR1_IMEM_AXI_RESP_BP // bypass instruction memory AXI bridge response register
-`define SCR1_DMEM_AXI_REQ_BP // bypass data memory AXI bridge request register
-`define SCR1_DMEM_AXI_RESP_BP // bypass data memory AXI bridge response register
-
-`ifndef SCR1_ARCH_CUSTOM
-// Default address constants (if scr1_arch_custom.svh is not used)
-parameter bit [`SCR1_XLEN-1:0] SCR1_ARCH_RST_VECTOR = 'h200; // Reset vector value (start address after reset)
-parameter bit [`SCR1_XLEN-1:0] SCR1_ARCH_MTVEC_BASE = 'h1C0; // MTVEC.base field reset value, or constant value for MTVEC.base bits that are hardwired
-
-parameter bit [`SCR1_DMEM_AWIDTH-1:0] SCR1_TCM_ADDR_MASK = 'hFFFF0000; // TCM mask and size; size in bytes is two's complement of the mask value
-parameter bit [`SCR1_DMEM_AWIDTH-1:0] SCR1_TCM_ADDR_PATTERN = 'h00480000; // TCM address match pattern
-
-parameter bit [`SCR1_DMEM_AWIDTH-1:0] SCR1_TIMER_ADDR_MASK = 'hFFFFFFE0; // Timer mask
-parameter bit [`SCR1_DMEM_AWIDTH-1:0] SCR1_TIMER_ADDR_PATTERN = 'h00490000; // Timer address match pattern
-
-// Device build ID
- `define SCR1_ARCH_BUILD_ID `SCR1_MIMPID
-
-`endif // SCR1_ARCH_CUSTOM
-
-
-//------------------------------------------------------------------------------
-// TARGET-SPECIFIC OPTIONS
-//------------------------------------------------------------------------------
-
-// RAM-based MPRF can be used for Intel FPGAs only
-`ifdef SCR1_TRGT_FPGA_INTEL
- `define SCR1_MPRF_RAM // implements MPRF with dedicated RAM blocks
-`endif
-
-// EXU_STAGE_BYPASS and MPRF_RST_EN must be disabled for RAM-based MPRF
-`ifdef SCR1_MPRF_RAM
- `undef SCR1_NO_EXE_STAGE
- `undef SCR1_MPRF_RST_EN
-`endif
-
-
-//------------------------------------------------------------------------------
-// SIMULATION OPTIONS
-//------------------------------------------------------------------------------
-
-//`define SCR1_TRGT_SIMULATION // enable simulation code (automatically defined by root makefile)
-//`define SCR1_TRACE_LOG_EN // enable tracelog
-//`define SCR1_XPROP_EN // enable X-propagation
-
-// Addresses used in testbench
-localparam [`SCR1_XLEN-1:0] SCR1_SIM_EXIT_ADDR = 32'h0000_00F8;
-localparam [`SCR1_XLEN-1:0] SCR1_SIM_PRINT_ADDR = 32'hF000_0000;
-localparam [`SCR1_XLEN-1:0] SCR1_SIM_EXT_IRQ_ADDR = 32'h3000_000C; // Bit [15:0]
-localparam [`SCR1_XLEN-1:0] SCR1_SIM_SOFT_IRQ_ADDR = 32'h3000_000C; // Bit[16]
-
-`endif // SCR1_ARCH_DESCRIPTION_SVH
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_types.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_types.svh
deleted file mode 100644
index 1b1b273..0000000
--- a/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_types.svh
+++ /dev/null
@@ -1,90 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_arch_types.svh>
-/// @brief Pipeline types description file
-///
-
-`ifndef SCR1_ARCH_TYPES_SVH
-`define SCR1_ARCH_TYPES_SVH
-
-`include "scr1_arch_description.svh"
-
-//-------------------------------------------------------------------------------
-// MPRF and CSR parameters
-//-------------------------------------------------------------------------------
-
-`ifdef SCR1_RVE_EXT
- `define SCR1_MPRF_AWIDTH 4
- `define SCR1_MPRF_SIZE 16
-`else // SCR1_RVE_EXT
- `define SCR1_MPRF_AWIDTH 5
- `define SCR1_MPRF_SIZE 32
-`endif // SCR1_RVE_EXT
-
-// Masked due to iverilog issue
-//typedef logic [`SCR1_XLEN-1:0] type_scr1_mprf_v;
-//typedef logic [`SCR1_XLEN-1:0] type_scr1_pc_v;
-
-parameter int unsigned SCR1_CSR_ADDR_WIDTH = 12;
-parameter int unsigned SCR1_CSR_MTVEC_BASE_ZERO_BITS = 6;
-parameter int unsigned SCR1_CSR_MTVEC_BASE_VAL_BITS = `SCR1_XLEN-SCR1_CSR_MTVEC_BASE_ZERO_BITS;
-parameter bit [`SCR1_XLEN-1:SCR1_CSR_MTVEC_BASE_ZERO_BITS] SCR1_CSR_MTVEC_BASE_WR_RST_VAL =
- SCR1_CSR_MTVEC_BASE_VAL_BITS'(SCR1_ARCH_MTVEC_BASE >> SCR1_CSR_MTVEC_BASE_ZERO_BITS);
-parameter int unsigned SCR1_CSR_MTVEC_BASE_RO_BITS = (`SCR1_XLEN-(SCR1_CSR_MTVEC_BASE_ZERO_BITS+SCR1_MTVEC_BASE_WR_BITS));
-
-`define SCR1_MTVAL_ILLEGAL_INSTR_EN
-
-//-------------------------------------------------------------------------------
-// Exception and IRQ codes
-//-------------------------------------------------------------------------------
-parameter int unsigned SCR1_EXC_CODE_WIDTH_E = 4;
-
-// Exceptions
-typedef enum logic [SCR1_EXC_CODE_WIDTH_E-1:0] {
- SCR1_EXC_CODE_INSTR_MISALIGN = 4'd0, // from EXU
- SCR1_EXC_CODE_INSTR_ACCESS_FAULT = 4'd1, // from IFU
- SCR1_EXC_CODE_ILLEGAL_INSTR = 4'd2, // from IDU or CSR
- SCR1_EXC_CODE_BREAKPOINT = 4'd3, // from IDU or BRKM
- SCR1_EXC_CODE_LD_ADDR_MISALIGN = 4'd4, // from LSU
- SCR1_EXC_CODE_LD_ACCESS_FAULT = 4'd5, // from LSU
- SCR1_EXC_CODE_ST_ADDR_MISALIGN = 4'd6, // from LSU
- SCR1_EXC_CODE_ST_ACCESS_FAULT = 4'd7, // from LSU
- SCR1_EXC_CODE_ECALL_M = 4'd11 // from IDU
-} type_scr1_exc_code_e;
-
-// IRQs, reset
-parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_IRQ_M_SOFTWARE = 4'd3;
-parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_IRQ_M_TIMER = 4'd7;
-parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_IRQ_M_EXTERNAL = 4'd11;
-parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_RESET = 4'd0;
-
-//-------------------------------------------------------------------------------
-// Operand width for BRKM
-//-------------------------------------------------------------------------------
-typedef enum logic [1:0] {
- SCR1_OP_WIDTH_BYTE = 2'b00,
- SCR1_OP_WIDTH_HALF = 2'b01,
- SCR1_OP_WIDTH_WORD = 2'b10
-`ifdef SCR1_XPROP_EN
- ,
- SCR1_OP_WIDTH_ERROR = 'x
-`endif // SCR1_XPROP_EN
-} type_scr1_op_width_e;
-
-`endif //SCR1_ARCH_TYPES_SVH
-
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_csr.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_csr.svh
deleted file mode 100644
index d9ee33a..0000000
--- a/verilog/rtl/syntacore/scr1/src/includes/scr1_csr.svh
+++ /dev/null
@@ -1,212 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_csr.svh>
-/// @brief CSR mapping/description file
-///
-
-`ifndef SCR1_CSR_SVH
-`define SCR1_CSR_SVH
-
-`include "scr1_arch_description.svh"
-`include "scr1_arch_types.svh"
-`include "scr1_ipic.svh"
-
-`ifdef SCR1_RVE_EXT
-`define SCR1_CSR_REDUCED_CNT
-`endif // SCR1_RVE_EXT
-
-`ifdef SCR1_CSR_REDUCED_CNT
-`undef SCR1_MCOUNTEN_EN
-`endif // SCR1_CSR_REDUCED_CNT
-
-//-------------------------------------------------------------------------------
-// CSR addresses (standard)
-//-------------------------------------------------------------------------------
-
-// Machine Information Registers (read-only)
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MVENDORID = 'hF11;
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MARCHID = 'hF12;
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MIMPID = 'hF13;
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MHARTID = 'hF14;
-
-// Machine Trap Setup (read-write)
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MSTATUS = 'h300;
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MISA = 'h301;
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MIE = 'h304;
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MTVEC = 'h305;
-
-// Machine Trap Handling (read-write)
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MSCRATCH = 'h340;
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MEPC = 'h341;
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MCAUSE = 'h342;
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MTVAL = 'h343;
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MIP = 'h344;
-
-// Machine Counters/Timers (read-write)
-`ifndef SCR1_CSR_REDUCED_CNT
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MCYCLE = 'hB00;
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MINSTRET = 'hB02;
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MCYCLEH = 'hB80;
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MINSTRETH = 'hB82;
-`endif // SCR1_CSR_REDUCED_CNT
-
-// Shadow Counters/Timers (read-only)
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TIME = 'hC01;
-`ifndef SCR1_CSR_REDUCED_CNT
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_CYCLE = 'hC00;
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_INSTRET = 'hC02;
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TIMEH = 'hC81;
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_CYCLEH = 'hC80;
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_INSTRETH = 'hC82;
-`endif // SCR1_CSR_REDUCED_CNT
-
-`ifdef SCR1_DBG_EN
-//parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_DBGC_SCRATCH = 'h7C8;
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_HDU_MBASE = 'h7B0;
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_HDU_MSPAN = 'h004; // must be power of 2
-`endif // SCR1_DBG_EN
-
-//-------------------------------------------------------------------------------
-// CSR addresses (non-standard)
-//-------------------------------------------------------------------------------
-`ifdef SCR1_MCOUNTEN_EN
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MCOUNTEN = 'h7E0;
-`endif // SCR1_MCOUNTEN_EN
-
-`ifdef SCR1_TDU_EN
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TDU_MBASE = 'h7A0;
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TDU_MSPAN = 'h008; // must be power of 2
-`endif // SCR1_TDU_EN
-
-`ifdef SCR1_IPIC_EN
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_BASE = 'hBF0;
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_CISV = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_CISV );
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_CICSR = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_CICSR);
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_IPR = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_IPR );
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_ISVR = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_ISVR );
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_EOI = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_EOI );
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_SOI = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_SOI );
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_IDX = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_IDX );
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_ICSR = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_ICSR );
-`endif // SCR1_IPIC_EN
-
-
-//-------------------------------------------------------------------------------
-// CSR definitions
-//-------------------------------------------------------------------------------
-
-// General
-parameter bit [`SCR1_XLEN-1:0] SCR1_RST_VECTOR = SCR1_ARCH_RST_VECTOR;
-
-// Reset values TBD
-parameter bit SCR1_CSR_MIE_MSIE_RST_VAL = 1'b0;
-parameter bit SCR1_CSR_MIE_MTIE_RST_VAL = 1'b0;
-parameter bit SCR1_CSR_MIE_MEIE_RST_VAL = 1'b0;
-
-parameter bit SCR1_CSR_MIP_MSIP_RST_VAL = 1'b0;
-parameter bit SCR1_CSR_MIP_MTIP_RST_VAL = 1'b0;
-parameter bit SCR1_CSR_MIP_MEIP_RST_VAL = 1'b0;
-
-parameter bit SCR1_CSR_MSTATUS_MIE_RST_VAL = 1'b0;
-parameter bit SCR1_CSR_MSTATUS_MPIE_RST_VAL = 1'b1;
-
-// MISA
-`define SCR1_RVC_ENC `SCR1_XLEN'h0004
-`define SCR1_RVE_ENC `SCR1_XLEN'h0010
-`define SCR1_RVI_ENC `SCR1_XLEN'h0100
-`define SCR1_RVM_ENC `SCR1_XLEN'h1000
-parameter bit [1:0] SCR1_MISA_MXL_32 = 2'd1;
-parameter bit [`SCR1_XLEN-1:0] SCR1_CSR_MISA = (SCR1_MISA_MXL_32 << (`SCR1_XLEN-2))
-`ifndef SCR1_RVE_EXT
- | `SCR1_RVI_ENC
-`else // SCR1_RVE_EXT
- | `SCR1_RVE_ENC
-`endif // SCR1_RVE_EXT
-`ifdef SCR1_RVC_EXT
- | `SCR1_RVC_ENC
-`endif // SCR1_RVC_EXT
-`ifdef SCR1_RVM_EXT
- | `SCR1_RVM_ENC
-`endif // SCR1_RVM_EXT
- ;
-
-// MVENDORID
-parameter bit [`SCR1_XLEN-1:0] SCR1_CSR_MVENDORID = `SCR1_MVENDORID;
-
-// MARCHID
-parameter bit [`SCR1_XLEN-1:0] SCR1_CSR_MARCHID = `SCR1_XLEN'd8;
-
-// MIMPID
-parameter bit [`SCR1_XLEN-1:0] SCR1_CSR_MIMPID = `SCR1_MIMPID;
-
-// MSTATUS
-parameter bit [1:0] SCR1_CSR_MSTATUS_MPP = 2'b11;
-parameter int unsigned SCR1_CSR_MSTATUS_MIE_OFFSET = 3;
-parameter int unsigned SCR1_CSR_MSTATUS_MPIE_OFFSET = 7;
-parameter int unsigned SCR1_CSR_MSTATUS_MPP_OFFSET = 11;
-
-// MTVEC
-// bits [5:0] are always zero
-parameter bit [`SCR1_XLEN-1:SCR1_CSR_MTVEC_BASE_ZERO_BITS] SCR1_CSR_MTVEC_BASE_RST_VAL = SCR1_CSR_MTVEC_BASE_WR_RST_VAL;
-
-parameter bit SCR1_CSR_MTVEC_MODE_DIRECT = 1'b0;
-`ifdef SCR1_MTVEC_MODE_EN
-parameter bit SCR1_CSR_MTVEC_MODE_VECTORED = 1'b1;
-`endif // SCR1_MTVEC_MODE_EN
-
-// MIE, MIP
-parameter int unsigned SCR1_CSR_MIE_MSIE_OFFSET = 3;
-parameter int unsigned SCR1_CSR_MIE_MTIE_OFFSET = 7;
-parameter int unsigned SCR1_CSR_MIE_MEIE_OFFSET = 11;
-
-`ifdef SCR1_MCOUNTEN_EN
-// MCOUNTEN
-parameter int unsigned SCR1_CSR_MCOUNTEN_CY_OFFSET = 0;
-parameter int unsigned SCR1_CSR_MCOUNTEN_IR_OFFSET = 2;
-`endif // SCR1_MCOUNTEN_EN
-
-// MCAUSE
-typedef logic [`SCR1_XLEN-2:0] type_scr1_csr_mcause_ec_v;
-
-// MCYCLE, MINSTRET
-`ifdef SCR1_CSR_REDUCED_CNT
-parameter int unsigned SCR1_CSR_COUNTERS_WIDTH = 32;
-`else // ~SCR1_CSR_REDUCED_CNT
-parameter int unsigned SCR1_CSR_COUNTERS_WIDTH = 64;
-`endif // ~SCR1_CSR_REDUCED_CNT
-
-// HPM
-parameter bit [6:0] SCR1_CSR_ADDR_HPMCOUNTER_MASK = 7'b1100000;
-parameter bit [6:0] SCR1_CSR_ADDR_HPMCOUNTERH_MASK = 7'b1100100;
-parameter bit [6:0] SCR1_CSR_ADDR_MHPMCOUNTER_MASK = 7'b1011000;
-parameter bit [6:0] SCR1_CSR_ADDR_MHPMCOUNTERH_MASK = 7'b1011100;
-parameter bit [6:0] SCR1_CSR_ADDR_MHPMEVENT_MASK = 7'b0011001;
-
-//-------------------------------------------------------------------------------
-// Types declaration
-//-------------------------------------------------------------------------------
-typedef enum logic {
- SCR1_CSR_RESP_OK,
- SCR1_CSR_RESP_ER
-`ifdef SCR1_XPROP_EN
- ,
- SCR1_CSR_RESP_ERROR = 'x
-`endif // SCR1_XPROP_EN
-} type_scr1_csr_resp_e;
-
-`endif // SCR1_CSR_SVH
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_dm.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_dm.svh
deleted file mode 100644
index 8c98684..0000000
--- a/verilog/rtl/syntacore/scr1/src/includes/scr1_dm.svh
+++ /dev/null
@@ -1,157 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_dm.svh>
-/// @brief Debug Module header file
-///
-
-`ifndef SCR1_INCLUDE_DM_DEFS
-`define SCR1_INCLUDE_DM_DEFS
-
-`include "scr1_arch_description.svh"
-`include "scr1_hdu.svh"
-`include "scr1_csr.svh"
-
-parameter SCR1_DBG_DMI_ADDR_WIDTH = 6'd7;
-parameter SCR1_DBG_DMI_DATA_WIDTH = 6'd32;
-parameter SCR1_DBG_DMI_OP_WIDTH = 2'd2;
-
-parameter SCR1_DBG_DMI_CH_ID_WIDTH = 2'd2;
-parameter SCR1_DBG_DMI_DR_DTMCS_WIDTH = 6'd32;
-parameter SCR1_DBG_DMI_DR_DMI_ACCESS_WIDTH = SCR1_DBG_DMI_OP_WIDTH +
- SCR1_DBG_DMI_DATA_WIDTH +
- SCR1_DBG_DMI_ADDR_WIDTH;
-
-// Debug Module addresses
-parameter SCR1_DBG_DATA0 = 7'h4;
-parameter SCR1_DBG_DATA1 = 7'h5;
-parameter SCR1_DBG_DMCONTROL = 7'h10;
-parameter SCR1_DBG_DMSTATUS = 7'h11;
-parameter SCR1_DBG_HARTINFO = 7'h12;
-parameter SCR1_DBG_ABSTRACTCS = 7'h16;
-parameter SCR1_DBG_COMMAND = 7'h17;
-parameter SCR1_DBG_ABSTRACTAUTO = 7'h18;
-parameter SCR1_DBG_PROGBUF0 = 7'h20;
-parameter SCR1_DBG_PROGBUF1 = 7'h21;
-parameter SCR1_DBG_PROGBUF2 = 7'h22;
-parameter SCR1_DBG_PROGBUF3 = 7'h23;
-parameter SCR1_DBG_PROGBUF4 = 7'h24;
-parameter SCR1_DBG_PROGBUF5 = 7'h25;
-parameter SCR1_DBG_HALTSUM0 = 7'h40;
-
-// DMCONTROL
-parameter SCR1_DBG_DMCONTROL_HALTREQ = 5'd31;
-parameter SCR1_DBG_DMCONTROL_RESUMEREQ = 5'd30;
-parameter SCR1_DBG_DMCONTROL_HARTRESET = 5'd29;
-parameter SCR1_DBG_DMCONTROL_ACKHAVERESET = 5'd28;
-parameter SCR1_DBG_DMCONTROL_RESERVEDB = 5'd27;
-parameter SCR1_DBG_DMCONTROL_HASEL = 5'd26;
-parameter SCR1_DBG_DMCONTROL_HARTSELLO_HI = 5'd25;
-parameter SCR1_DBG_DMCONTROL_HARTSELLO_LO = 5'd16;
-parameter SCR1_DBG_DMCONTROL_HARTSELHI_HI = 5'd15;
-parameter SCR1_DBG_DMCONTROL_HARTSELHI_LO = 5'd6;
-parameter SCR1_DBG_DMCONTROL_RESERVEDA_HI = 5'd5;
-parameter SCR1_DBG_DMCONTROL_RESERVEDA_LO = 5'd2;
-parameter SCR1_DBG_DMCONTROL_NDMRESET = 5'd1;
-parameter SCR1_DBG_DMCONTROL_DMACTIVE = 5'd0;
-
-// DMSTATUS
-parameter SCR1_DBG_DMSTATUS_RESERVEDC_HI = 5'd31;
-parameter SCR1_DBG_DMSTATUS_RESERVEDC_LO = 5'd23;
-parameter SCR1_DBG_DMSTATUS_IMPEBREAK = 5'd22;
-parameter SCR1_DBG_DMSTATUS_RESERVEDB_HI = 5'd21;
-parameter SCR1_DBG_DMSTATUS_RESERVEDB_LO = 5'd20;
-parameter SCR1_DBG_DMSTATUS_ALLHAVERESET = 5'd19;
-parameter SCR1_DBG_DMSTATUS_ANYHAVERESET = 5'd18;
-parameter SCR1_DBG_DMSTATUS_ALLRESUMEACK = 5'd17;
-parameter SCR1_DBG_DMSTATUS_ANYRESUMEACK = 5'd16;
-parameter SCR1_DBG_DMSTATUS_ALLNONEXISTENT = 5'd15;
-parameter SCR1_DBG_DMSTATUS_ANYNONEXISTENT = 5'd14;
-parameter SCR1_DBG_DMSTATUS_ALLUNAVAIL = 5'd13;
-parameter SCR1_DBG_DMSTATUS_ANYUNAVAIL = 5'd12;
-parameter SCR1_DBG_DMSTATUS_ALLRUNNING = 5'd11;
-parameter SCR1_DBG_DMSTATUS_ANYRUNNING = 5'd10;
-parameter SCR1_DBG_DMSTATUS_ALLHALTED = 5'd9;
-parameter SCR1_DBG_DMSTATUS_ANYHALTED = 5'd8;
-parameter SCR1_DBG_DMSTATUS_AUTHENTICATED = 5'd7;
-parameter SCR1_DBG_DMSTATUS_AUTHBUSY = 5'd6;
-parameter SCR1_DBG_DMSTATUS_RESERVEDA = 5'd5;
-parameter SCR1_DBG_DMSTATUS_DEVTREEVALID = 5'd4;
-parameter SCR1_DBG_DMSTATUS_VERSION_HI = 5'd3;
-parameter SCR1_DBG_DMSTATUS_VERSION_LO = 5'd0;
-
-// COMMANDS
-parameter SCR1_DBG_COMMAND_TYPE_HI = 5'd31;
-parameter SCR1_DBG_COMMAND_TYPE_LO = 5'd24;
-parameter SCR1_DBG_COMMAND_TYPE_WDTH = SCR1_DBG_COMMAND_TYPE_HI
- - SCR1_DBG_COMMAND_TYPE_LO;
-
-parameter SCR1_DBG_COMMAND_ACCESSREG_RESERVEDB = 5'd23;
-parameter SCR1_DBG_COMMAND_ACCESSREG_SIZE_HI = 5'd22;
-parameter SCR1_DBG_COMMAND_ACCESSREG_SIZE_LO = 5'd20;
-parameter SCR1_DBG_COMMAND_ACCESSREG_SIZE_WDTH = SCR1_DBG_COMMAND_ACCESSREG_SIZE_HI
- - SCR1_DBG_COMMAND_ACCESSREG_SIZE_LO;
-parameter SCR1_DBG_COMMAND_ACCESSREG_RESERVEDA = 5'd19;
-parameter SCR1_DBG_COMMAND_ACCESSREG_POSTEXEC = 5'd18;
-parameter SCR1_DBG_COMMAND_ACCESSREG_TRANSFER = 5'd17;
-parameter SCR1_DBG_COMMAND_ACCESSREG_WRITE = 5'd16;
-parameter SCR1_DBG_COMMAND_ACCESSREG_REGNO_HI = 5'd15;
-parameter SCR1_DBG_COMMAND_ACCESSREG_REGNO_LO = 5'd0;
-
-parameter SCR1_DBG_COMMAND_ACCESSMEM_AAMVIRTUAL = 5'd23;
-parameter SCR1_DBG_COMMAND_ACCESSMEM_AAMSIZE_HI = 5'd22;
-parameter SCR1_DBG_COMMAND_ACCESSMEM_AAMSIZE_LO = 5'd20;
-parameter SCR1_DBG_COMMAND_ACCESSMEM_AAMPOSTINC = 5'd19;
-parameter SCR1_DBG_COMMAND_ACCESSMEM_RESERVEDB_HI = 5'd18;
-parameter SCR1_DBG_COMMAND_ACCESSMEM_RESERVEDB_LO = 5'd17;
-parameter SCR1_DBG_COMMAND_ACCESSMEM_WRITE = 5'd16;
-parameter SCR1_DBG_COMMAND_ACCESSMEM_RESERVEDA_HI = 5'd13;
-parameter SCR1_DBG_COMMAND_ACCESSMEM_RESERVEDA_LO = 5'd0;
-
-// ABSTRACTCS
-parameter SCR1_DBG_ABSTRACTCS_RESERVEDD_HI = 5'd31;
-parameter SCR1_DBG_ABSTRACTCS_RESERVEDD_LO = 5'd29;
-parameter SCR1_DBG_ABSTRACTCS_PROGBUFSIZE_HI = 5'd28;
-parameter SCR1_DBG_ABSTRACTCS_PROGBUFSIZE_LO = 5'd24;
-parameter SCR1_DBG_ABSTRACTCS_RESERVEDC_HI = 5'd23;
-parameter SCR1_DBG_ABSTRACTCS_RESERVEDC_LO = 5'd13;
-parameter SCR1_DBG_ABSTRACTCS_BUSY = 5'd12;
-parameter SCR1_DBG_ABSTRACTCS_RESERVEDB = 5'd11;
-parameter SCR1_DBG_ABSTRACTCS_CMDERR_HI = 5'd10;
-parameter SCR1_DBG_ABSTRACTCS_CMDERR_LO = 5'd8;
-parameter SCR1_DBG_ABSTRACTCS_CMDERR_WDTH = SCR1_DBG_ABSTRACTCS_CMDERR_HI
- - SCR1_DBG_ABSTRACTCS_CMDERR_LO;
-parameter SCR1_DBG_ABSTRACTCS_RESERVEDA_HI = 5'd7;
-parameter SCR1_DBG_ABSTRACTCS_RESERVEDA_LO = 5'd4;
-parameter SCR1_DBG_ABSTRACTCS_DATACOUNT_HI = 5'd3;
-parameter SCR1_DBG_ABSTRACTCS_DATACOUNT_LO = 5'd0;
-
-// HARTINFO
-parameter SCR1_DBG_HARTINFO_RESERVEDB_HI = 5'd31;
-parameter SCR1_DBG_HARTINFO_RESERVEDB_LO = 5'd24;
-parameter SCR1_DBG_HARTINFO_NSCRATCH_HI = 5'd23;
-parameter SCR1_DBG_HARTINFO_NSCRATCH_LO = 5'd20;
-parameter SCR1_DBG_HARTINFO_RESERVEDA_HI = 5'd19;
-parameter SCR1_DBG_HARTINFO_RESERVEDA_LO = 5'd17;
-parameter SCR1_DBG_HARTINFO_DATAACCESS = 5'd16;
-parameter SCR1_DBG_HARTINFO_DATASIZE_HI = 5'd15;
-parameter SCR1_DBG_HARTINFO_DATASIZE_LO = 5'd12;
-parameter SCR1_DBG_HARTINFO_DATAADDR_HI = 5'd11;
-parameter SCR1_DBG_HARTINFO_DATAADDR_LO = 5'd0;
-
-
-`endif // SCR1_INCLUDE_DM_DEFS
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_hdu.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_hdu.svh
deleted file mode 100644
index 155792c..0000000
--- a/verilog/rtl/syntacore/scr1/src/includes/scr1_hdu.svh
+++ /dev/null
@@ -1,179 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_pipe_hdu.svh>
-/// @brief HART Debug Unit definitions file
-///
-
-`ifndef SCR1_INCLUDE_HDU_DEFS
-`define SCR1_INCLUDE_HDU_DEFS
-
-`include "scr1_arch_description.svh"
-`include "scr1_csr.svh"
-
-`ifdef SCR1_MMU_EN
- `define SCR1_HDU_FEATURE_MPRVEN
-`endif // SCR1_MMU_EN
-
-//==============================================================================
-// Parameters
-//==============================================================================
-//localparam int unsigned SCR1_HDU_DEBUGCSR_BASE_ADDR = 12'h7B0;
-localparam int unsigned SCR1_HDU_DEBUGCSR_ADDR_SPAN = 4; // YOSYS FIX
-localparam int unsigned SCR1_HDU_DEBUGCSR_ADDR_WIDTH = $clog2(SCR1_HDU_DEBUGCSR_ADDR_SPAN);
-localparam bit [3:0] SCR1_HDU_DEBUGCSR_DCSR_XDEBUGVER = 4'h4;
-localparam int unsigned SCR1_HDU_PBUF_ADDR_SPAN = 8;
-localparam int unsigned SCR1_HDU_PBUF_ADDR_WIDTH = $clog2(SCR1_HDU_PBUF_ADDR_SPAN);
-localparam int unsigned SCR1_HDU_DATA_REG_WIDTH = 32;
-localparam int unsigned SCR1_HDU_CORE_INSTR_WIDTH = 32;
-
-
-//==============================================================================
-// Types
-//==============================================================================
-
-// HART Debug States:
-typedef enum logic [1:0] {
- SCR1_HDU_DBGSTATE_RESET = 2'b00,
- SCR1_HDU_DBGSTATE_RUN = 2'b01,
- SCR1_HDU_DBGSTATE_DHALTED = 2'b10,
- SCR1_HDU_DBGSTATE_DRUN = 2'b11
-`ifdef SCR1_XPROP_EN
- ,
- SCR1_HDU_DBGSTATE_XXX = 'X
-`endif // SCR1_XPROP_EN
-} type_scr1_hdu_dbgstates_e;
-
-typedef enum logic [1:0] {
- SCR1_HDU_PBUFSTATE_IDLE = 2'b00,
- SCR1_HDU_PBUFSTATE_FETCH = 2'b01,
- SCR1_HDU_PBUFSTATE_EXCINJECT = 2'b10,
- SCR1_HDU_PBUFSTATE_WAIT4END = 2'b11
-`ifdef SCR1_XPROP_EN
- ,
- SCR1_HDU_PBUFSTATE_XXX = 'X
-`endif // SCR1_XPROP_EN
-} type_scr1_hdu_pbufstates_e;
-
-typedef enum logic {
- SCR1_HDU_HARTCMD_RESUME = 1'b0,
- SCR1_HDU_HARTCMD_HALT = 1'b1
-`ifdef SCR1_XPROP_EN
- ,
- SCR1_HDU_HARTCMD_XXX = 1'bX
-`endif // SCR1_XPROP_EN
-} type_scr1_hdu_hart_command_e;
-
-typedef enum logic {
- SCR1_HDU_FETCH_SRC_NORMAL = 1'b0,
- SCR1_HDU_FETCH_SRC_PBUF = 1'b1
-`ifdef SCR1_XPROP_EN
- ,
- SCR1_HDU_FETCH_SRC_XXX = 1'bX
-`endif // SCR1_XPROP_EN
-} type_scr1_hdu_fetch_src_e;
-
-typedef struct packed {
- //logic reset_n;
- logic except;
- logic ebreak;
- type_scr1_hdu_dbgstates_e dbg_state;
-} type_scr1_hdu_hartstatus_s;
-
-// Debug Mode Redirection control:
-typedef struct packed {
- logic sstep; // Single Step
- logic ebreak; // Redirection after EBREAK execution
-} type_scr1_hdu_redirect_s;
-
-typedef struct packed {
- logic irq_dsbl;
- type_scr1_hdu_fetch_src_e fetch_src;
- logic pc_advmt_dsbl;
- logic hwbrkpt_dsbl;
- type_scr1_hdu_redirect_s redirect;
-} type_scr1_hdu_runctrl_s;
-
-// HART Halt Status:
-typedef enum logic [2:0] {
- SCR1_HDU_HALTCAUSE_NONE = 3'b000,
- SCR1_HDU_HALTCAUSE_EBREAK = 3'b001,
- SCR1_HDU_HALTCAUSE_TMREQ = 3'b010,
- SCR1_HDU_HALTCAUSE_DMREQ = 3'b011,
- SCR1_HDU_HALTCAUSE_SSTEP = 3'b100,
- SCR1_HDU_HALTCAUSE_RSTEXIT = 3'b101
-`ifdef SCR1_XPROP_EN
- ,
- SCR1_HDU_HALTCAUSE_XXX = 'X
-`endif // SCR1_XPROP_EN
-} type_scr1_hdu_haltcause_e;
-
-typedef struct packed {
- logic except;
- type_scr1_hdu_haltcause_e cause;
-} type_scr1_hdu_haltstatus_s;
-
-
-// Debug CSR map
-localparam SCR1_HDU_DBGCSR_OFFS_DCSR = SCR1_HDU_DEBUGCSR_ADDR_WIDTH'( 'd0 );
-localparam SCR1_HDU_DBGCSR_OFFS_DPC = SCR1_HDU_DEBUGCSR_ADDR_WIDTH'( 'd1 );
-localparam SCR1_HDU_DBGCSR_OFFS_DSCRATCH0 = SCR1_HDU_DEBUGCSR_ADDR_WIDTH'( 'd2 );
-localparam SCR1_HDU_DBGCSR_OFFS_DSCRATCH1 = SCR1_HDU_DEBUGCSR_ADDR_WIDTH'( 'd3 );
-
-localparam bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_HDU_DBGCSR_ADDR_DCSR = SCR1_CSR_ADDR_HDU_MBASE + SCR1_HDU_DBGCSR_OFFS_DCSR;
-localparam bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_HDU_DBGCSR_ADDR_DPC = SCR1_CSR_ADDR_HDU_MBASE + SCR1_HDU_DBGCSR_OFFS_DPC;
-localparam bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_HDU_DBGCSR_ADDR_DSCRATCH0 = SCR1_CSR_ADDR_HDU_MBASE + SCR1_HDU_DBGCSR_OFFS_DSCRATCH0;
-localparam bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_HDU_DBGCSR_ADDR_DSCRATCH1 = SCR1_CSR_ADDR_HDU_MBASE + SCR1_HDU_DBGCSR_OFFS_DSCRATCH1;
-
-// Debug CSRs :: DCSR
-typedef enum int {
- SCR1_HDU_DCSR_PRV_BIT_R = 0,
- SCR1_HDU_DCSR_PRV_BIT_L = 1,
- SCR1_HDU_DCSR_STEP_BIT = 2,
- SCR1_HDU_DCSR_RSRV0_BIT_R = 3,
- SCR1_HDU_DCSR_RSRV0_BIT_L = 5,
- SCR1_HDU_DCSR_CAUSE_BIT_R = 6,
- SCR1_HDU_DCSR_CAUSE_BIT_L = 8,
- SCR1_HDU_DCSR_RSRV1_BIT_R = 9,
- SCR1_HDU_DCSR_RSRV1_BIT_L = 10,
- SCR1_HDU_DCSR_STEPIE_BIT = 11,
- SCR1_HDU_DCSR_RSRV2_BIT_R = 12,
- SCR1_HDU_DCSR_RSRV2_BIT_L = 14,
- SCR1_HDU_DCSR_EBREAKM_BIT = 15,
- SCR1_HDU_DCSR_RSRV3_BIT_R = 16,
- SCR1_HDU_DCSR_RSRV3_BIT_L = 27,
- SCR1_HDU_DCSR_XDEBUGVER_BIT_R = 28,
- SCR1_HDU_DCSR_XDEBUGVER_BIT_L = 31
-} type_scr1_hdu_dcsr_bits_e;
-
-//localparam int unsigned SCR1_HDU_DEBUGCSR_DCSR_PRV_WIDTH = SCR1_HDU_DCSR_PRV_BIT_L-SCR1_HDU_DCSR_PRV_BIT_R+1;
-
-typedef struct packed {
- logic [SCR1_HDU_DCSR_XDEBUGVER_BIT_L-SCR1_HDU_DCSR_XDEBUGVER_BIT_R:0] xdebugver;
- logic [SCR1_HDU_DCSR_RSRV3_BIT_L-SCR1_HDU_DCSR_RSRV3_BIT_R:0] rsrv3;
- logic ebreakm;
- logic [SCR1_HDU_DCSR_RSRV2_BIT_L-SCR1_HDU_DCSR_RSRV2_BIT_R:0] rsrv2;
- logic stepie;
- logic [SCR1_HDU_DCSR_RSRV1_BIT_L-SCR1_HDU_DCSR_RSRV1_BIT_R:0] rsrv1;
- logic [SCR1_HDU_DCSR_CAUSE_BIT_L-SCR1_HDU_DCSR_CAUSE_BIT_R:0] cause;
- logic [SCR1_HDU_DCSR_RSRV0_BIT_L-SCR1_HDU_DCSR_RSRV0_BIT_R:0] rsrv0;
- logic step;
- logic [SCR1_HDU_DCSR_PRV_BIT_L-SCR1_HDU_DCSR_PRV_BIT_R:0] prv;
-} type_scr1_hdu_dcsr_s;
-
-
-`endif // SCR1_INCLUDE_HDU_DEFS
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_ipic.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_ipic.svh
deleted file mode 100644
index 555137c..0000000
--- a/verilog/rtl/syntacore/scr1/src/includes/scr1_ipic.svh
+++ /dev/null
@@ -1,74 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_ipic.svh>
-/// @brief IPIC header file
-///
-
-`ifndef SCR1_IPIC_SVH
-`define SCR1_IPIC_SVH
-
-`include "scr1_arch_description.svh"
-
-`ifdef SCR1_IPIC_EN
-//-------------------------------------------------------------------------------
-// Parameters declaration
-//-------------------------------------------------------------------------------
-parameter SCR1_IRQ_VECT_NUM = 16; // must be power of 2 in the current implementation
-parameter SCR1_IRQ_VECT_WIDTH = $clog2(SCR1_IRQ_VECT_NUM+1);
-parameter SCR1_IRQ_LINES_NUM = SCR1_IRQ_VECT_NUM;
-parameter SCR1_IRQ_LINES_WIDTH = $clog2(SCR1_IRQ_LINES_NUM);
-parameter logic [SCR1_IRQ_VECT_WIDTH-1:0] SCR1_IRQ_VOID_VECT_NUM = SCR1_IRQ_VECT_WIDTH'(SCR1_IRQ_VECT_NUM);
-parameter SCR1_IRQ_IDX_WIDTH = $clog2(SCR1_IRQ_VECT_NUM);
-
-// Address decoding parameters
-parameter logic [2:0] SCR1_IPIC_CISV = 3'h0; // RO
-parameter logic [2:0] SCR1_IPIC_CICSR = 3'h1; // {IP, IE}
-parameter logic [2:0] SCR1_IPIC_IPR = 3'h2; // RW1C
-parameter logic [2:0] SCR1_IPIC_ISVR = 3'h3; // RO
-parameter logic [2:0] SCR1_IPIC_EOI = 3'h4; // RZW
-parameter logic [2:0] SCR1_IPIC_SOI = 3'h5; // RZW
-parameter logic [2:0] SCR1_IPIC_IDX = 3'h6; // RW
-parameter logic [2:0] SCR1_IPIC_ICSR = 3'h7; // RW
-
-parameter SCR1_IPIC_ICSR_IP = 0;
-parameter SCR1_IPIC_ICSR_IE = 1;
-parameter SCR1_IPIC_ICSR_IM = 2;
-parameter SCR1_IPIC_ICSR_INV = 3;
-parameter SCR1_IPIC_ICSR_IS = 4;
-parameter SCR1_IPIC_ICSR_PRV_LSB = 8;
-parameter SCR1_IPIC_ICSR_PRV_MSB = 9;
-parameter SCR1_IPIC_ICSR_LN_LSB = 12;
-parameter SCR1_IPIC_ICSR_LN_MSB = SCR1_IPIC_ICSR_LN_LSB
- + SCR1_IRQ_LINES_WIDTH;
-
-parameter logic [1:0] SCR1_IPIC_PRV_M = 2'b11;
-
-//-------------------------------------------------------------------------------
-// Types declaration
-//-------------------------------------------------------------------------------
-typedef enum logic {
- SCR1_CSR2IPIC_RD,
- SCR1_CSR2IPIC_WR
-`ifdef SCR1_XPROP_EN
- ,
- SCR1_CSR2IPIC_ERROR = 'x
-`endif // SCR1_XPROP_EN
-} type_scr1_csr2ipic_wr_e;
-
-`endif // SCR1_IPIC_EN
-`endif // SCR1_IPIC_SVH
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_memif.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_memif.svh
deleted file mode 100644
index 997df58..0000000
--- a/verilog/rtl/syntacore/scr1/src/includes/scr1_memif.svh
+++ /dev/null
@@ -1,65 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_memif.svh>
-/// @brief Memory interface definitions file
-///
-
-`ifndef SCR1_MEMIF_SVH
-`define SCR1_MEMIF_SVH
-
-`include "scr1_arch_description.svh"
-
-//-------------------------------------------------------------------------------
-// Memory command enum
-//-------------------------------------------------------------------------------
-//typedef enum logic {
-parameter SCR1_MEM_CMD_RD = 1'b0;
-parameter SCR1_MEM_CMD_WR = 1'b1;
-//`ifdef SCR1_XPROP_EN
-// ,
-parameter SCR1_MEM_CMD_ERROR = 'x;
-//`endif // SCR1_XPROP_EN
-//} type_scr1_mem_cmd_e;
-
-//-------------------------------------------------------------------------------
-// Memory data width enum
-//-------------------------------------------------------------------------------
-//typedef enum logic[1:0] {
-parameter SCR1_MEM_WIDTH_BYTE = 2'b00;
-parameter SCR1_MEM_WIDTH_HWORD = 2'b01;
-parameter SCR1_MEM_WIDTH_WORD = 2'b10;
-//`ifdef SCR1_XPROP_EN
-// ,
-parameter SCR1_MEM_WIDTH_ERROR = 'x;
-//`endif // SCR1_XPROP_EN
-//} type_scr1_mem_width_e;
-
-//-------------------------------------------------------------------------------
-// Memory response enum
-//-------------------------------------------------------------------------------
-//typedef enum logic[1:0] {
-parameter SCR1_MEM_RESP_NOTRDY = 2'b00;
-parameter SCR1_MEM_RESP_RDY_OK = 2'b01;
-parameter SCR1_MEM_RESP_RDY_ER = 2'b10;
-//`ifdef SCR1_XPROP_EN
-// ,
-parameter SCR1_MEM_RESP_ERROR = 'x;
-//`endif // SCR1_XPROP_EN
-//} type_scr1_mem_resp_e;
-
-`endif // SCR1_MEMIF_SVH
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_riscv_isa_decoding.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_riscv_isa_decoding.svh
deleted file mode 100644
index ff380a1..0000000
--- a/verilog/rtl/syntacore/scr1/src/includes/scr1_riscv_isa_decoding.svh
+++ /dev/null
@@ -1,201 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_riscv_isa_decoding.svh>
-/// @brief RISC-V ISA definitions file
-///
-
-`ifndef SCR1_RISCV_ISA_DECODING_SVH
-`define SCR1_RISCV_ISA_DECODING_SVH
-
-`include "scr1_arch_description.svh"
-`include "scr1_arch_types.svh"
-
-//-------------------------------------------------------------------------------
-// Instruction types
-//-------------------------------------------------------------------------------
-//typedef enum logic [1:0] {
-parameter SCR1_INSTR_RVC0 = 2'b00;
-parameter SCR1_INSTR_RVC1 = 2'b01;
-parameter SCR1_INSTR_RVC2 = 2'b10;
-parameter SCR1_INSTR_RVI = 2'b11;
-//} type_scr1_instr_type_e;
-
-//-------------------------------------------------------------------------------
-// RV32I opcodes (bits 6:2)
-//-------------------------------------------------------------------------------
-//typedef enum logic [6:2] {
-parameter SCR1_OPCODE_LOAD = 5'b00000;
-parameter SCR1_OPCODE_MISC_MEM = 5'b00011;
-parameter SCR1_OPCODE_OP_IMM = 5'b00100;
-parameter SCR1_OPCODE_AUIPC = 5'b00101;
-parameter SCR1_OPCODE_STORE = 5'b01000;
-parameter SCR1_OPCODE_OP = 5'b01100;
-parameter SCR1_OPCODE_LUI = 5'b01101;
-parameter SCR1_OPCODE_BRANCH = 5'b11000;
-parameter SCR1_OPCODE_JALR = 5'b11001;
-parameter SCR1_OPCODE_JAL = 5'b11011;
-parameter SCR1_OPCODE_SYSTEM = 5'b11100;
-//} type_scr1_rvi_opcode_e;
-
-
-//-------------------------------------------------------------------------------
-// IALU main operands
-//-------------------------------------------------------------------------------
-localparam SCR1_IALU_OP_ALL_NUM_E = 2;
-localparam SCR1_IALU_OP_WIDTH_E = $clog2(SCR1_IALU_OP_ALL_NUM_E);
-typedef enum logic [SCR1_IALU_OP_WIDTH_E-1:0] {
- SCR1_IALU_OP_REG_IMM, // op1 = rs1; op2 = imm
- SCR1_IALU_OP_REG_REG // op1 = rs1; op2 = rs2
-} type_scr1_ialu_op_sel_e;
-
-//-------------------------------------------------------------------------------
-// IALU main commands
-//-------------------------------------------------------------------------------
-`ifdef SCR1_RVM_EXT
-localparam SCR1_IALU_CMD_ALL_NUM_E = 23;
-`else // ~SCR1_RVM_EXT
-localparam SCR1_IALU_CMD_ALL_NUM_E = 15;
-`endif // ~SCR1_RVM_EXT
-localparam SCR1_IALU_CMD_WIDTH_E = $clog2(SCR1_IALU_CMD_ALL_NUM_E);
-typedef enum logic [SCR1_IALU_CMD_WIDTH_E-1:0] {
- SCR1_IALU_CMD_NONE = '0, // IALU disable
- SCR1_IALU_CMD_AND, // op1 & op2
- SCR1_IALU_CMD_OR, // op1 | op2
- SCR1_IALU_CMD_XOR, // op1 ^ op2
- SCR1_IALU_CMD_ADD, // op1 + op2
- SCR1_IALU_CMD_SUB, // op1 - op2
- SCR1_IALU_CMD_SUB_LT, // op1 < op2
- SCR1_IALU_CMD_SUB_LTU, // op1 u< op2
- SCR1_IALU_CMD_SUB_EQ, // op1 = op2
- SCR1_IALU_CMD_SUB_NE, // op1 != op2
- SCR1_IALU_CMD_SUB_GE, // op1 >= op2
- SCR1_IALU_CMD_SUB_GEU, // op1 u>= op2
- SCR1_IALU_CMD_SLL, // op1 << op2
- SCR1_IALU_CMD_SRL, // op1 >> op2
- SCR1_IALU_CMD_SRA // op1 >>> op2
-`ifdef SCR1_RVM_EXT
- ,
- SCR1_IALU_CMD_MUL, // low(unsig(op1) * unsig(op2))
- SCR1_IALU_CMD_MULHU, // high(unsig(op1) * unsig(op2))
- SCR1_IALU_CMD_MULHSU, // high(op1 * unsig(op2))
- SCR1_IALU_CMD_MULH, // high(op1 * op2)
- SCR1_IALU_CMD_DIV, // op1 / op2
- SCR1_IALU_CMD_DIVU, // op1 u/ op2
- SCR1_IALU_CMD_REM, // op1 % op2
- SCR1_IALU_CMD_REMU // op1 u% op2
-`endif // SCR1_RVM_EXT
-} type_scr1_ialu_cmd_sel_e;
-
-//-------------------------------------------------------------------------------
-// IALU SUM2 operands (result is JUMP/BRANCH target, LOAD/STORE address)
-//-------------------------------------------------------------------------------
-localparam SCR1_SUM2_OP_ALL_NUM_E = 2;
-localparam SCR1_SUM2_OP_WIDTH_E = $clog2(SCR1_SUM2_OP_ALL_NUM_E);
-typedef enum logic [SCR1_SUM2_OP_WIDTH_E-1:0] {
- SCR1_SUM2_OP_PC_IMM, // op1 = curr_pc; op2 = imm (AUIPC, target new_pc for JAL and branches)
- SCR1_SUM2_OP_REG_IMM // op1 = rs1; op2 = imm (target new_pc for JALR, LOAD/STORE address)
-`ifdef SCR1_XPROP_EN
- ,
- SCR1_SUM2_OP_ERROR = 'x
-`endif // SCR1_XPROP_EN
-} type_scr1_ialu_sum2_op_sel_e;
-
-//-------------------------------------------------------------------------------
-// LSU commands
-//-------------------------------------------------------------------------------
-localparam SCR1_LSU_CMD_ALL_NUM_E = 9;
-localparam SCR1_LSU_CMD_WIDTH_E = $clog2(SCR1_LSU_CMD_ALL_NUM_E);
-typedef enum logic [SCR1_LSU_CMD_WIDTH_E-1:0] {
- SCR1_LSU_CMD_NONE = '0,
- SCR1_LSU_CMD_LB,
- SCR1_LSU_CMD_LH,
- SCR1_LSU_CMD_LW,
- SCR1_LSU_CMD_LBU,
- SCR1_LSU_CMD_LHU,
- SCR1_LSU_CMD_SB,
- SCR1_LSU_CMD_SH,
- SCR1_LSU_CMD_SW
-} type_scr1_lsu_cmd_sel_e;
-
-//-------------------------------------------------------------------------------
-// CSR operands
-//-------------------------------------------------------------------------------
-localparam SCR1_CSR_OP_ALL_NUM_E = 2;
-localparam SCR1_CSR_OP_WIDTH_E = $clog2(SCR1_CSR_OP_ALL_NUM_E);
-typedef enum logic [SCR1_CSR_OP_WIDTH_E-1:0] {
- SCR1_CSR_OP_IMM,
- SCR1_CSR_OP_REG
-} type_scr1_csr_op_sel_e;
-
-//-------------------------------------------------------------------------------
-// CSR commands
-//-------------------------------------------------------------------------------
-localparam SCR1_CSR_CMD_ALL_NUM_E = 4;
-localparam SCR1_CSR_CMD_WIDTH_E = $clog2(SCR1_CSR_CMD_ALL_NUM_E);
-typedef enum logic [SCR1_CSR_CMD_WIDTH_E-1:0] {
- SCR1_CSR_CMD_NONE = '0,
- SCR1_CSR_CMD_WRITE,
- SCR1_CSR_CMD_SET,
- SCR1_CSR_CMD_CLEAR
-} type_scr1_csr_cmd_sel_e;
-
-//-------------------------------------------------------------------------------
-// MPRF rd writeback source
-//-------------------------------------------------------------------------------
-localparam SCR1_RD_WB_ALL_NUM_E = 7;
-localparam SCR1_RD_WB_WIDTH_E = $clog2(SCR1_RD_WB_ALL_NUM_E);
-typedef enum logic [SCR1_RD_WB_WIDTH_E-1:0] {
- SCR1_RD_WB_NONE = '0,
- SCR1_RD_WB_IALU, // IALU main result
- SCR1_RD_WB_SUM2, // IALU SUM2 result (AUIPC)
- SCR1_RD_WB_IMM, // LUI
- SCR1_RD_WB_INC_PC, // JAL(R)
- SCR1_RD_WB_LSU, // Load from DMEM
- SCR1_RD_WB_CSR // Read CSR
-} type_scr1_rd_wb_sel_e;
-
-//-------------------------------------------------------------------------------
-// IDU to EXU full command structure
-//-------------------------------------------------------------------------------
-localparam SCR1_GPR_FIELD_WIDTH = 5;
-
-typedef struct packed {
- logic instr_rvc; // used with a different meaning for IFU access fault exception
- type_scr1_ialu_op_sel_e ialu_op;
- type_scr1_ialu_cmd_sel_e ialu_cmd;
- type_scr1_ialu_sum2_op_sel_e sum2_op;
- type_scr1_lsu_cmd_sel_e lsu_cmd;
- type_scr1_csr_op_sel_e csr_op;
- type_scr1_csr_cmd_sel_e csr_cmd;
- type_scr1_rd_wb_sel_e rd_wb_sel;
- logic jump_req;
- logic branch_req;
- logic mret_req;
- logic fencei_req;
- logic wfi_req;
- logic [SCR1_GPR_FIELD_WIDTH-1:0] rs1_addr; // also used as zimm for CSRRxI instructions
- logic [SCR1_GPR_FIELD_WIDTH-1:0] rs2_addr;
- logic [SCR1_GPR_FIELD_WIDTH-1:0] rd_addr;
- logic [`SCR1_XLEN-1:0] imm; // used as {funct3, CSR address} for CSR instructions
- // used as instruction field for illegal instruction exception
- logic exc_req;
- type_scr1_exc_code_e exc_code;
-} type_scr1_exu_cmd_s;
-
-`endif // SCR1_RISCV_ISA_DECODING_SVH
-
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_scu.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_scu.svh
deleted file mode 100644
index 2c8f5df..0000000
--- a/verilog/rtl/syntacore/scr1/src/includes/scr1_scu.svh
+++ /dev/null
@@ -1,102 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_scu.svh>
-/// @brief SCU header file
-///
-
-`ifndef SCR1_INCLUDE_SCU_DEFS
-`define SCR1_INCLUDE_SCU_DEFS
-
-//`include "scr1_arch_description.svh"
-
-`ifdef SCR1_DBG_EN
-
-//==============================================================================
-// Parameters
-//==============================================================================
-localparam int unsigned SCR1_SCU_DR_SYSCTRL_OP_WIDTH = 2;
-localparam int unsigned SCR1_SCU_DR_SYSCTRL_ADDR_WIDTH = 2;
-localparam int unsigned SCR1_SCU_DR_SYSCTRL_DATA_WIDTH = 4;
-localparam int unsigned SCR1_SCU_DR_SYSCTRL_WIDTH = SCR1_SCU_DR_SYSCTRL_OP_WIDTH+SCR1_SCU_DR_SYSCTRL_ADDR_WIDTH+SCR1_SCU_DR_SYSCTRL_DATA_WIDTH; // cp.3
-
-//==============================================================================
-// Types
-//==============================================================================
-typedef enum logic [SCR1_SCU_DR_SYSCTRL_OP_WIDTH-1:0] {
- SCR1_SCU_SYSCTRL_OP_WRITE = 2'h0,
- SCR1_SCU_SYSCTRL_OP_READ = 2'h1,
- SCR1_SCU_SYSCTRL_OP_SETBITS = 2'h2,
- SCR1_SCU_SYSCTRL_OP_CLRBITS = 2'h3
-`ifdef SCR1_XPROP_EN
- ,
- SCR1_SCU_SYSCTRL_OP_XXX = 'X
-`endif // SCR1_XPROP_EN
-} type_scr1_scu_sysctrl_op_e;
-
-typedef enum logic [SCR1_SCU_DR_SYSCTRL_ADDR_WIDTH-1:0] {
- SCR1_SCU_SYSCTRL_ADDR_CONTROL = 2'h0,
- SCR1_SCU_SYSCTRL_ADDR_MODE = 2'h1,
- SCR1_SCU_SYSCTRL_ADDR_STATUS = 2'h2,
- SCR1_SCU_SYSCTRL_ADDR_STICKY = 2'h3
-`ifdef SCR1_XPROP_EN
- ,
- SCR1_SCU_SYSCTRL_ADDR_XXX = 'X
-`endif // SCR1_XPROP_EN
-} type_scr1_scu_sysctrl_addr_e;
-
-typedef struct packed {
- logic [SCR1_SCU_DR_SYSCTRL_DATA_WIDTH-1:0] data;
- logic [SCR1_SCU_DR_SYSCTRL_ADDR_WIDTH-1:0] addr;
- logic [SCR1_SCU_DR_SYSCTRL_OP_WIDTH-1:0] op;
-} type_scr1_scu_sysctrl_dr_s;
-
-typedef enum int unsigned {
- SCR1_SCU_DR_SYSCTRL_OP_BIT_R = 'h0,
- SCR1_SCU_DR_SYSCTRL_OP_BIT_L = SCR1_SCU_DR_SYSCTRL_OP_WIDTH-1,
- SCR1_SCU_DR_SYSCTRL_ADDR_BIT_R = SCR1_SCU_DR_SYSCTRL_OP_WIDTH,
- SCR1_SCU_DR_SYSCTRL_ADDR_BIT_L = SCR1_SCU_DR_SYSCTRL_OP_WIDTH +
- SCR1_SCU_DR_SYSCTRL_ADDR_WIDTH - 1,
- SCR1_SCU_DR_SYSCTRL_DATA_BIT_R = SCR1_SCU_DR_SYSCTRL_OP_WIDTH +
- SCR1_SCU_DR_SYSCTRL_ADDR_WIDTH,
- SCR1_SCU_DR_SYSCTRL_DATA_BIT_L = SCR1_SCU_DR_SYSCTRL_OP_WIDTH +
- SCR1_SCU_DR_SYSCTRL_ADDR_WIDTH +
- SCR1_SCU_DR_SYSCTRL_DATA_WIDTH - 1
-} type_scr1_scu_sysctrl_dr_bits_e;
-
-typedef struct packed {
- logic [1:0] rsrv;
- logic core_reset;
- logic sys_reset;
-} type_scr1_scu_sysctrl_control_reg_s;
-
-typedef struct packed {
- logic [1:0] rsrv;
- logic hdu_rst_bhv;
- logic dm_rst_bhv;
-} type_scr1_scu_sysctrl_mode_reg_s;
-
-localparam bit [31:0] SCR1_SCU_SYSCTRL_STATUS_REG_WIDTH = 4; // cp.3
-typedef struct packed {
- logic hdu_reset;
- logic dm_reset;
- logic core_reset;
- logic sys_reset;
-} type_scr1_scu_sysctrl_status_reg_s;
-
-`endif // SCR1_DBG_EN
-`endif // SCR1_INCLUDE_SCU_DEFS
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_search_ms1.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_search_ms1.svh
deleted file mode 100644
index 5532c59..0000000
--- a/verilog/rtl/syntacore/scr1/src/includes/scr1_search_ms1.svh
+++ /dev/null
@@ -1,111 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_search_ms1.svh>
-/// @brief Most significant one search function
-///
-
-`ifndef SCR1_SEARCH_MS1_SVH
-`define SCR1_SEARCH_MS1_SVH
-
-//-------------------------------------------------------------------------------
-// Local types declaration
-//-------------------------------------------------------------------------------
-typedef struct packed {
- logic vd;
- logic idx;
-} type_scr1_search_one_2_s;
-
-typedef struct packed {
- logic vd;
- logic [4:0] idx;
-} type_scr1_search_one_32_s;
-
-//-------------------------------------------------------------------------------
-// Leading Zeros Count Function
-//-------------------------------------------------------------------------------
-function automatic type_scr1_search_one_2_s scr1_lead_zeros_cnt_2(
- input logic [1:0] din
-);
- type_scr1_search_one_2_s tmp;
-begin
- tmp.vd = |din;
- tmp.idx = ~din[1];
- scr1_lead_zeros_cnt_2 = tmp;
-end
-endfunction
-
-function automatic logic [4:0] scr1_lead_zeros_cnt_32(
- input logic [31:0] din
-);
-begin
- logic [15:0] stage1_vd;
- logic [7:0] stage2_vd;
- logic [3:0] stage3_vd;
- logic [1:0] stage4_vd;
-
- logic stage1_idx [15:0];
- logic [1:0] stage2_idx [7:0];
- logic [2:0] stage3_idx [3:0];
- logic [3:0] stage4_idx [1:0];
- type_scr1_search_one_32_s tmp;
- logic [4:0] res;
- integer i;
-
- // Stage 1
- for (i=0; i<16; i=i+1) begin // cp.4
- type_scr1_search_one_2_s tmp;
- tmp = scr1_lead_zeros_cnt_2(din[(i+1)*2-1-:2]);
- stage1_vd[i] = tmp.vd;
- stage1_idx[i] = tmp.idx;
- end
-
- // Stage 2
- for (i=0; i<8;i=i+1) begin // cp.4
- type_scr1_search_one_2_s tmp;
- tmp = scr1_lead_zeros_cnt_2(stage1_vd[(i+1)*2-1-:2]);
- stage2_vd[i] = tmp.vd;
- stage2_idx[i] = (tmp.idx) ? {tmp.idx, stage1_idx[2*i]} : {tmp.idx, stage1_idx[2*i+1]};
- end
-
- // Stage 3
- for (i=0; i<4; i=i+1) begin // cp.4
- type_scr1_search_one_2_s tmp;
- tmp = scr1_lead_zeros_cnt_2(stage2_vd[(i+1)*2-1-:2]);
- stage3_vd[i] = tmp.vd;
- stage3_idx[i] = (tmp.idx) ? {tmp.idx, stage2_idx[2*i]} : {tmp.idx, stage2_idx[2*i+1]};
- end
-
- // Stage 4
- for (i=0; i<2; i=i+1) begin // cp.4
- type_scr1_search_one_2_s tmp;
- tmp = scr1_lead_zeros_cnt_2(stage3_vd[(i+1)*2-1-:2]);
- stage4_vd[i] = tmp.vd;
- stage4_idx[i] = (tmp.idx) ? {tmp.idx, stage3_idx[2*i]} : {tmp.idx, stage3_idx[2*i+1]};
- end
-
- // Stage 5
- tmp.vd = |stage4_vd;
- tmp.idx = (stage4_vd[1]) ? {1'b0, stage4_idx[1]} : {1'b1, stage4_idx[0]};
-
- res = tmp.idx;
-
- scr1_lead_zeros_cnt_32 = res;
-end
-endfunction
-
-`endif // SCR1_SEARCH_MS1_SVH
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_tapc.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_tapc.svh
deleted file mode 100644
index cdf5068..0000000
--- a/verilog/rtl/syntacore/scr1/src/includes/scr1_tapc.svh
+++ /dev/null
@@ -1,82 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_tapc.svh>
-/// @brief TAPC header file
-///
-
-`ifndef SCR1_INCLUDE_TAPC_DEFS
-`define SCR1_INCLUDE_TAPC_DEFS
-
-`include "scr1_arch_description.svh"
-
-`ifdef SCR1_DBG_EN
-
-//==============================================================================
-// Parameters
-//==============================================================================
-localparam int unsigned SCR1_TAP_STATE_WIDTH = 4;
-localparam int unsigned SCR1_TAP_INSTRUCTION_WIDTH = 5;
-localparam int unsigned SCR1_TAP_DR_IDCODE_WIDTH = 32;
-localparam int unsigned SCR1_TAP_DR_BLD_ID_WIDTH = 32;
-localparam int unsigned SCR1_TAP_DR_BYPASS_WIDTH = 1;
-//localparam bit [SCR1_TAP_DR_IDCODE_WIDTH-1:0] SCR1_TAP_IDCODE_RISCV_SC = `SCR1_TAP_IDCODE;
-localparam bit [SCR1_TAP_DR_BLD_ID_WIDTH-1:0] SCR1_TAP_BLD_ID_VALUE = `SCR1_MIMPID;
-
-//==============================================================================
-// Types
-//==============================================================================
-typedef enum logic [SCR1_TAP_STATE_WIDTH-1:0] {
- SCR1_TAP_STATE_RESET,
- SCR1_TAP_STATE_IDLE,
- SCR1_TAP_STATE_DR_SEL_SCAN,
- SCR1_TAP_STATE_DR_CAPTURE,
- SCR1_TAP_STATE_DR_SHIFT,
- SCR1_TAP_STATE_DR_EXIT1,
- SCR1_TAP_STATE_DR_PAUSE,
- SCR1_TAP_STATE_DR_EXIT2,
- SCR1_TAP_STATE_DR_UPDATE,
- SCR1_TAP_STATE_IR_SEL_SCAN,
- SCR1_TAP_STATE_IR_CAPTURE,
- SCR1_TAP_STATE_IR_SHIFT,
- SCR1_TAP_STATE_IR_EXIT1,
- SCR1_TAP_STATE_IR_PAUSE,
- SCR1_TAP_STATE_IR_EXIT2,
- SCR1_TAP_STATE_IR_UPDATE
-`ifdef SCR1_XPROP_EN
- ,
- SCR1_TAP_STATE_XXX = 'X
-`endif // SCR1_XPROP_EN
-} type_scr1_tap_state_e;
-
-typedef enum logic [SCR1_TAP_INSTRUCTION_WIDTH - 1:0] {
- SCR1_TAP_INSTR_IDCODE = 5'h01,
- SCR1_TAP_INSTR_BLD_ID = 5'h04,
- SCR1_TAP_INSTR_SCU_ACCESS = 5'h09,
-
- SCR1_TAP_INSTR_DTMCS = 5'h10,
- SCR1_TAP_INSTR_DMI_ACCESS = 5'h11,
-
- SCR1_TAP_INSTR_BYPASS = 5'h1F
-`ifdef SCR1_XPROP_EN
- ,
- SCR1_TAP_INSTR_XXX = 'X
-`endif // SCR1_XPROP_EN
-} type_scr1_tap_instr_e;
-
-`endif // SCR1_DBG_EN
-`endif // SCR1_INCLUDE_TAPC_DEFS
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_tdu.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_tdu.svh
deleted file mode 100644
index fda1616..0000000
--- a/verilog/rtl/syntacore/scr1/src/includes/scr1_tdu.svh
+++ /dev/null
@@ -1,137 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_tdu.svh>
-/// @brief Trigger Debug Module header
-///
-
-`ifndef SCR1_INCLUDE_TDU_DEFS
-`define SCR1_INCLUDE_TDU_DEFS
-
-//`include "scr1_arch_description.svh"
-
-`ifdef SCR1_TDU_EN
-//`include "scr1_csr.svh"
-
-`include "scr1_arch_description.svh"
-//`include "scr1_arch_types.svh"
-`include "scr1_csr.svh"
-
-parameter int unsigned SCR1_TDU_MTRIG_NUM = SCR1_TDU_TRIG_NUM;
-`ifdef SCR1_TDU_ICOUNT_EN
-parameter int unsigned SCR1_TDU_ALLTRIG_NUM = SCR1_TDU_MTRIG_NUM + 1'b1;
-`else
-parameter int unsigned SCR1_TDU_ALLTRIG_NUM = SCR1_TDU_MTRIG_NUM;
-`endif
-
-parameter int unsigned SCR1_TDU_ADDR_W = `SCR1_XLEN;
-parameter int unsigned SCR1_TDU_DATA_W = `SCR1_XLEN;
-
-// Register map
-parameter SCR1_CSR_ADDR_TDU_OFFS_W = 3;
-parameter bit [SCR1_CSR_ADDR_TDU_OFFS_W-1:0] SCR1_CSR_ADDR_TDU_OFFS_TSELECT = 'h0;
-parameter bit [SCR1_CSR_ADDR_TDU_OFFS_W-1:0] SCR1_CSR_ADDR_TDU_OFFS_TDATA1 = 'h1;
-parameter bit [SCR1_CSR_ADDR_TDU_OFFS_W-1:0] SCR1_CSR_ADDR_TDU_OFFS_TDATA2 = 'h2;
-parameter bit [SCR1_CSR_ADDR_TDU_OFFS_W-1:0] SCR1_CSR_ADDR_TDU_OFFS_TINFO = 'h4;
-
-
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TDU_TSELECT = SCR1_CSR_ADDR_TDU_MBASE + SCR1_CSR_ADDR_TDU_OFFS_TSELECT;
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TDU_TDATA1 = SCR1_CSR_ADDR_TDU_MBASE + SCR1_CSR_ADDR_TDU_OFFS_TDATA1;
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TDU_TDATA2 = SCR1_CSR_ADDR_TDU_MBASE + SCR1_CSR_ADDR_TDU_OFFS_TDATA2;
-parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TDU_TINFO = SCR1_CSR_ADDR_TDU_MBASE + SCR1_CSR_ADDR_TDU_OFFS_TINFO;
-
-// TDATA1
-parameter int unsigned SCR1_TDU_TDATA1_TYPE_HI = `SCR1_XLEN-1;
-parameter int unsigned SCR1_TDU_TDATA1_TYPE_LO = `SCR1_XLEN-4;
-parameter int unsigned SCR1_TDU_TDATA1_DMODE = `SCR1_XLEN-5;
-
-// TDATA1: constant bits values
-parameter bit SCR1_TDU_TDATA1_DMODE_VAL = 1'b0;
-
-// MCONTROL: bits number
-parameter int unsigned SCR1_TDU_MCONTROL_MASKMAX_HI = `SCR1_XLEN-6;
-parameter int unsigned SCR1_TDU_MCONTROL_MASKMAX_LO = `SCR1_XLEN-11;
-parameter int unsigned SCR1_TDU_MCONTROL_RESERVEDB_HI = `SCR1_XLEN-12;
-parameter int unsigned SCR1_TDU_MCONTROL_RESERVEDB_LO = 21;
-parameter int unsigned SCR1_TDU_MCONTROL_HIT = 20;
-parameter int unsigned SCR1_TDU_MCONTROL_SELECT = 19;
-parameter int unsigned SCR1_TDU_MCONTROL_TIMING = 18;
-parameter int unsigned SCR1_TDU_MCONTROL_ACTION_HI = 17;
-parameter int unsigned SCR1_TDU_MCONTROL_ACTION_LO = 12;
-parameter int unsigned SCR1_TDU_MCONTROL_CHAIN = 11;
-parameter int unsigned SCR1_TDU_MCONTROL_MATCH_HI = 10;
-parameter int unsigned SCR1_TDU_MCONTROL_MATCH_LO = 7;
-parameter int unsigned SCR1_TDU_MCONTROL_M = 6;
-parameter int unsigned SCR1_TDU_MCONTROL_RESERVEDA = 5;
-parameter int unsigned SCR1_TDU_MCONTROL_S = 4;
-parameter int unsigned SCR1_TDU_MCONTROL_U = 3;
-parameter int unsigned SCR1_TDU_MCONTROL_EXECUTE = 2;
-parameter int unsigned SCR1_TDU_MCONTROL_STORE = 1;
-parameter int unsigned SCR1_TDU_MCONTROL_LOAD = 0;
-
-// MCONTROL: constant bits values
-parameter bit [SCR1_TDU_TDATA1_TYPE_HI-SCR1_TDU_TDATA1_TYPE_LO:0]
- SCR1_TDU_MCONTROL_TYPE_VAL = 2'd2;
-
-parameter bit SCR1_TDU_MCONTROL_SELECT_VAL = 1'b0;
-parameter bit SCR1_TDU_MCONTROL_TIMING_VAL = 1'b0;
-
-parameter bit [SCR1_TDU_MCONTROL_MASKMAX_HI-SCR1_TDU_MCONTROL_MASKMAX_LO:0]
- SCR1_TDU_MCONTROL_MASKMAX_VAL = 1'b0;
-
-parameter bit SCR1_TDU_MCONTROL_RESERVEDA_VAL = 1'b0;
-
-// ICOUNT: bits number
-parameter int unsigned SCR1_TDU_ICOUNT_DMODE = `SCR1_XLEN-5;
-parameter int unsigned SCR1_TDU_ICOUNT_RESERVEDB_HI = `SCR1_XLEN-6;
-parameter int unsigned SCR1_TDU_ICOUNT_RESERVEDB_LO = 25;
-parameter int unsigned SCR1_TDU_ICOUNT_HIT = 24;
-parameter int unsigned SCR1_TDU_ICOUNT_COUNT_HI = 23;
-parameter int unsigned SCR1_TDU_ICOUNT_COUNT_LO = 10;
-parameter int unsigned SCR1_TDU_ICOUNT_M = 9;
-parameter int unsigned SCR1_TDU_ICOUNT_RESERVEDA = 8;
-parameter int unsigned SCR1_TDU_ICOUNT_S = 7;
-parameter int unsigned SCR1_TDU_ICOUNT_U = 6;
-parameter int unsigned SCR1_TDU_ICOUNT_ACTION_HI = 5;
-parameter int unsigned SCR1_TDU_ICOUNT_ACTION_LO = 0;
-
-// ICOUNT: constant bits values
-parameter bit [SCR1_TDU_TDATA1_TYPE_HI-SCR1_TDU_TDATA1_TYPE_LO:0]
- SCR1_TDU_ICOUNT_TYPE_VAL = 2'd3;
-
-parameter bit [SCR1_TDU_ICOUNT_RESERVEDB_HI-SCR1_TDU_ICOUNT_RESERVEDB_LO:0]
- SCR1_TDU_ICOUNT_RESERVEDB_VAL = 1'b0;
-
-parameter bit SCR1_TDU_ICOUNT_RESERVEDA_VAL = 1'b0;
-
-// CPU pipeline monitors
-typedef struct packed {
- logic vd;
- logic req;
- logic [`SCR1_XLEN-1:0] addr;
-} type_scr1_brkm_instr_mon_s;
-
-typedef struct packed {
- logic vd;
- logic load;
- logic store;
- logic [`SCR1_XLEN-1:0] addr;
-} type_scr1_brkm_lsu_mon_s;
-
-`endif // SCR1_TDU_EN
-
-`endif // SCR1_INCLUDE_TDU_DEFS
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_wb.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_wb.svh
deleted file mode 100644
index c061103..0000000
--- a/verilog/rtl/syntacore/scr1/src/includes/scr1_wb.svh
+++ /dev/null
@@ -1,84 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: 2021, Dinesh Annayya
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
-// //////////////////////////////////////////////////////////////////////////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// yifive Wishbone define for syntacore ////
-//// ////
-//// This file is part of the yifive cores project ////
-//// https://github.com/dineshannayya/yifive_r0.git ////
-//// http://www.opencores.org/cores/yifive/ ////
-//// ////
-//// Description: ////
-//// integrated wishbone i/f to Syntacore,scr1 core ////
-//// ////
-//// To Do: ////
-//// nothing ////
-//// ////
-//// Author(s): ////
-//// - Dinesh Annayya, dinesha@opencores.org ////
-//// ////
-//// Revision : ////
-//// v0: June 7, 2021, Dinesh A ////
-//// wishbone define added ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-// Orginal owner Details ////
-//////////////////////////////////////////////////////////////////////
-/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details///
-/// @file <scr1_ahb.svh> ///
-/// @brief WB header file ///
-/////////////////////////////////////////////////////////////////////
-
-`ifndef SCR1_WB_SVH
-`define SCR1_WB_SVH
-
-`include "scr1_arch_description.svh"
-
-parameter SCR1_WB_WIDTH = 32;
-
-// Encoding for DATA SIZE
-parameter logic [2:0] SCR1_DSIZE_8B = 3'b000;
-parameter logic [2:0] SCR1_DSIZE_16B = 3'b001;
-parameter logic [2:0] SCR1_DSIZE_32B = 3'b010;
-
-`endif // SCR1_WB_SVH
diff --git a/verilog/rtl/syntacore/scr1/src/run_modemsim b/verilog/rtl/syntacore/scr1/src/run_modemsim
deleted file mode 100755
index 51910e9..0000000
--- a/verilog/rtl/syntacore/scr1/src/run_modemsim
+++ /dev/null
@@ -1,19 +0,0 @@
-# //////////////////////////////////////////////////////////////////////////////
-# // SPDX-FileCopyrightText: 2021, Dinesh Annayya
-# //
-# // Licensed under the Apache License, Version 2.0 (the "License");
-# // you may not use this file except in compliance with the License.
-# // You may obtain a copy of the License at
-# //
-# // http://www.apache.org/licenses/LICENSE-2.0
-# //
-# // Unless required by applicable law or agreed to in writing, software
-# // distributed under the License is distributed on an "AS IS" BASIS,
-# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# // See the License for the specific language governing permissions and
-# // limitations under the License.
-# // SPDX-License-Identifier: Apache-2.0
-# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
-# // //////////////////////////////////////////////////////////////////////////
-vlib work
-vlog -f wb_top.files -f core.files +incdir+includes -sv
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_ahb.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_ahb.sv
deleted file mode 100644
index 43958b1..0000000
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_ahb.sv
+++ /dev/null
@@ -1,482 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_dmem_ahb.sv>
-/// @brief Data memory AHB bridge
-///
-
-`include "scr1_ahb.svh"
-`include "scr1_memif.svh"
-
-module scr1_dmem_ahb (
- // Control Signals
- input logic rst_n,
- input logic clk,
-
- // Core Interface
- output logic dmem_req_ack,
- input logic dmem_req,
- input logic dmem_cmd,
- input logic [1:0] dmem_width,
- input logic [SCR1_AHB_WIDTH-1:0] dmem_addr,
- input logic [SCR1_AHB_WIDTH-1:0] dmem_wdata,
- output logic [SCR1_AHB_WIDTH-1:0] dmem_rdata,
- output logic [1:0] dmem_resp,
-
- // AHB Interface
- output logic [3:0] hprot,
- output logic [2:0] hburst,
- output logic [2:0] hsize,
- output logic [1:0] htrans,
- output logic hmastlock,
- output logic [SCR1_AHB_WIDTH-1:0] haddr,
- output logic hwrite,
- output logic [SCR1_AHB_WIDTH-1:0] hwdata,
- input logic hready,
- input logic [SCR1_AHB_WIDTH-1:0] hrdata,
- input logic hresp
-
-);
-
-//-------------------------------------------------------------------------------
-// Local Parameters
-//-------------------------------------------------------------------------------
-`ifndef SCR1_DMEM_AHB_OUT_BP
-localparam SCR1_FIFO_WIDTH = 2;
-localparam SCR1_FIFO_CNT_WIDTH = $clog2(SCR1_FIFO_WIDTH+1);
-`endif // SCR1_DMEM_AHB_OUT_BP
-
-//-------------------------------------------------------------------------------
-// Local type declaration
-//-------------------------------------------------------------------------------
-typedef enum logic {
- SCR1_FSM_ADDR = 1'b0,
- SCR1_FSM_DATA = 1'b1,
- SCR1_FSM_ERR = 1'bx
-} type_scr1_fsm_e;
-
-typedef struct packed {
- logic hwrite;
- logic [2:0] hwidth;
- logic [SCR1_AHB_WIDTH-1:0] haddr;
- logic [SCR1_AHB_WIDTH-1:0] hwdata;
-} type_scr1_req_fifo_s;
-
-typedef struct packed {
- logic hwrite;
- logic [2:0] hwidth;
- logic [1:0] haddr;
- logic [SCR1_AHB_WIDTH-1:0] hwdata;
-} type_scr1_data_fifo_s;
-
-typedef struct packed {
- logic hresp;
- logic [2:0] hwidth;
- logic [1:0] haddr;
- logic [SCR1_AHB_WIDTH-1:0] hrdata;
-} type_scr1_resp_fifo_s;
-
-//-------------------------------------------------------------------------------
-// Local functions
-//-------------------------------------------------------------------------------
-function automatic logic [2:0] scr1_conv_mem2ahb_width (
- input logic [1:0] dmem_width
-);
- logic [2:0] tmp;
-begin
- case (dmem_width)
- SCR1_MEM_WIDTH_BYTE : begin
- tmp = SCR1_HSIZE_8B;
- end
- SCR1_MEM_WIDTH_HWORD : begin
- tmp = SCR1_HSIZE_16B;
- end
- SCR1_MEM_WIDTH_WORD : begin
- tmp = SCR1_HSIZE_32B;
- end
- default : begin
- tmp = SCR1_HSIZE_ERR;
- end
- endcase
- scr1_conv_mem2ahb_width = tmp; // cp.11
-end
-endfunction
-
-function automatic logic[SCR1_AHB_WIDTH-1:0] scr1_conv_mem2ahb_wdata (
- input logic [1:0] dmem_addr,
- input logic [1:0] dmem_width,
- input logic [SCR1_AHB_WIDTH-1:0] dmem_wdata
-);
- logic [SCR1_AHB_WIDTH-1:0] tmp;
-begin
- tmp = 'x;
- case (dmem_width)
- SCR1_MEM_WIDTH_BYTE : begin
- case (dmem_addr)
- 2'b00 : begin
- tmp[7:0] = dmem_wdata[7:0];
- end
- 2'b01 : begin
- tmp[15:8] = dmem_wdata[7:0];
- end
- 2'b10 : begin
- tmp[23:16] = dmem_wdata[7:0];
- end
- 2'b11 : begin
- tmp[31:24] = dmem_wdata[7:0];
- end
- default : begin
- end
- endcase
- end
- SCR1_MEM_WIDTH_HWORD : begin
- case (dmem_addr[1])
- 1'b0 : begin
- tmp[15:0] = dmem_wdata[15:0];
- end
- 1'b1 : begin
- tmp[31:16] = dmem_wdata[15:0];
- end
- default : begin
- end
- endcase
- end
- SCR1_MEM_WIDTH_WORD : begin
- tmp = dmem_wdata;
- end
- default : begin
- end
- endcase
- scr1_conv_mem2ahb_wdata = tmp;
-end
-endfunction
-
-function automatic logic[SCR1_AHB_WIDTH-1:0] scr1_conv_ahb2mem_rdata (
- input logic [2:0] hwidth,
- input logic [1:0] haddr,
- input logic [SCR1_AHB_WIDTH-1:0] hrdata
-);
- logic [SCR1_AHB_WIDTH-1:0] tmp;
-begin
- tmp = 'x;
- case (hwidth)
- SCR1_HSIZE_8B : begin
- case (haddr)
- 2'b00 : tmp[7:0] = hrdata[7:0];
- 2'b01 : tmp[7:0] = hrdata[15:8];
- 2'b10 : tmp[7:0] = hrdata[23:16];
- 2'b11 : tmp[7:0] = hrdata[31:24];
- default : begin
- end
- endcase
- end
- SCR1_HSIZE_16B : begin
- case (haddr[1])
- 1'b0 : tmp[15:0] = hrdata[15:0];
- 1'b1 : tmp[15:0] = hrdata[31:16];
- default : begin
- end
- endcase
- end
- SCR1_HSIZE_32B : begin
- tmp = hrdata;
- end
- default : begin
- end
- endcase
- scr1_conv_ahb2mem_rdata = tmp;
-end
-endfunction
-
-//-------------------------------------------------------------------------------
-// Local signal declaration
-//-------------------------------------------------------------------------------
-type_scr1_fsm_e fsm;
-logic req_fifo_rd;
-logic req_fifo_wr;
-logic req_fifo_up;
-`ifdef SCR1_DMEM_AHB_OUT_BP
-type_scr1_req_fifo_s req_fifo_new;
-type_scr1_req_fifo_s req_fifo_r;
-type_scr1_req_fifo_s [0:0] req_fifo;
-`else // SCR1_DMEM_AHB_OUT_BP
-type_scr1_req_fifo_s [0:SCR1_FIFO_WIDTH-1] req_fifo;
-type_scr1_req_fifo_s [0:SCR1_FIFO_WIDTH-1] req_fifo_new;
-logic [SCR1_FIFO_CNT_WIDTH-1:0] req_fifo_cnt;
-logic [SCR1_FIFO_CNT_WIDTH-1:0] req_fifo_cnt_new;
-`endif // SCR1_DMEM_AHB_OUT_BP
-logic req_fifo_empty;
-logic req_fifo_full;
-
-type_scr1_data_fifo_s data_fifo;
-type_scr1_resp_fifo_s resp_fifo;
-logic resp_fifo_hready;
-
-//-------------------------------------------------------------------------------
-// Interface to Core
-//-------------------------------------------------------------------------------
-assign dmem_req_ack = ~req_fifo_full;
-assign req_fifo_wr = ~req_fifo_full & dmem_req;
-
-assign dmem_rdata = scr1_conv_ahb2mem_rdata(resp_fifo.hwidth, resp_fifo.haddr, resp_fifo.hrdata);
-
-assign dmem_resp = (resp_fifo_hready)
- ? (resp_fifo.hresp == SCR1_HRESP_OKAY)
- ? SCR1_MEM_RESP_RDY_OK
- : SCR1_MEM_RESP_RDY_ER
- : SCR1_MEM_RESP_NOTRDY ;
-
-//-------------------------------------------------------------------------------
-// REQ_FIFO
-//-------------------------------------------------------------------------------
-`ifdef SCR1_DMEM_AHB_OUT_BP
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- req_fifo_full <= 1'b0;
- end else begin
- if (~req_fifo_full) begin
- req_fifo_full <= dmem_req & ~req_fifo_rd;
- end else begin
- req_fifo_full <= ~req_fifo_rd;
- end
- end
-end
-assign req_fifo_empty = ~(req_fifo_full | dmem_req);
-
-assign req_fifo_up = ~req_fifo_rd & req_fifo_wr;
-always_ff @(posedge clk) begin
- if (req_fifo_up) begin
- req_fifo_r <= req_fifo_new;
- end
-end
-
-assign req_fifo_new.hwrite = dmem_req ? (dmem_cmd == SCR1_MEM_CMD_WR) : 1'b0;
-assign req_fifo_new.hwidth = dmem_req ? scr1_conv_mem2ahb_width(dmem_width) : '0;
-assign req_fifo_new.haddr = dmem_req ? dmem_addr : '0;
-assign req_fifo_new.hwdata = (dmem_req & (dmem_cmd == SCR1_MEM_CMD_WR))
- ? scr1_conv_mem2ahb_wdata(dmem_addr[1:0], dmem_width, dmem_wdata)
- : '0;
-assign req_fifo[0] = (req_fifo_full) ? req_fifo_r: req_fifo_new;
-
-`else // SCR1_DMEM_AHB_OUT_BP
-always_comb begin
- req_fifo_up = 1'b0;
- req_fifo_cnt_new = req_fifo_cnt;
- req_fifo_new = req_fifo;
- case ({req_fifo_rd, req_fifo_wr})
- 2'b00 : begin
- // nothing todo
- end
- 2'b01: begin
- // FIFO write
- req_fifo_up = 1'b1;
- req_fifo_new[req_fifo_cnt].hwrite = (dmem_cmd == SCR1_MEM_CMD_WR);
- req_fifo_new[req_fifo_cnt].hwidth = scr1_conv_mem2ahb_width(dmem_width);
- req_fifo_new[req_fifo_cnt].haddr = dmem_addr;
- req_fifo_new[req_fifo_cnt].hwdata = scr1_conv_mem2ahb_wdata(dmem_addr[1:0], dmem_width, dmem_wdata);
- req_fifo_cnt_new = req_fifo_cnt + 1'b1;
- end
- 2'b10 : begin
- // FIFO read
- req_fifo_up = 1'b1;
- req_fifo_new[0] = req_fifo_new[1];
- req_fifo_new[1].hwrite = 1'b0;
- req_fifo_new[1].hwidth = SCR1_HSIZE_32B;
- req_fifo_new[1].haddr = 'x;
- req_fifo_new[1].hwdata = 'x;
- req_fifo_cnt_new = req_fifo_cnt - 1'b1;
- end
- 2'b11 : begin
- // Read and Write FIFO. It is possible only when fifo_cnt = 1
- req_fifo_up = 1'b1;
- req_fifo_new[0].hwrite = (dmem_cmd == SCR1_MEM_CMD_WR);
- req_fifo_new[0].hwidth = scr1_conv_mem2ahb_width(dmem_width);
- req_fifo_new[0].haddr = dmem_addr;
- req_fifo_new[0].hwdata = scr1_conv_mem2ahb_wdata(dmem_addr[1:0], dmem_width, dmem_wdata);
- end
- default : begin
- req_fifo_up = 'x;
- req_fifo_cnt_new = 'x;
- req_fifo_new = 'x;
- end
- endcase
-end
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- req_fifo_cnt <= '0;
- end else begin
- if (req_fifo_up) begin
- req_fifo_cnt <= req_fifo_cnt_new;
- end
- end
-end
-assign req_fifo_full = (req_fifo_cnt == SCR1_FIFO_WIDTH);
-assign req_fifo_empty = ~(|req_fifo_cnt);
-
-always_ff @(posedge clk) begin
- if (req_fifo_up) begin
- req_fifo <= req_fifo_new;
- end
-end
-`endif // SCR1_DMEM_AHB_OUT_BP
-//-------------------------------------------------------------------------------
-// FSM
-//-------------------------------------------------------------------------------
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- fsm <= SCR1_FSM_ADDR;
- end else begin
- case (fsm)
- SCR1_FSM_ADDR : begin
- if (hready) begin
- fsm <= (req_fifo_empty) ? SCR1_FSM_ADDR : SCR1_FSM_DATA;
- end
- end
- SCR1_FSM_DATA : begin
- if (hready) begin
- if (hresp == SCR1_HRESP_OKAY) begin
- fsm <= (req_fifo_empty) ? SCR1_FSM_ADDR : SCR1_FSM_DATA;
- end else begin
- fsm <= SCR1_FSM_ADDR;
- end
- end
- end
- default : begin
- fsm <= SCR1_FSM_ERR;
- end
- endcase
- end
-end
-
-always_comb begin
- req_fifo_rd = 1'b0;
- case (fsm)
- SCR1_FSM_ADDR : begin
- if (hready) begin
- req_fifo_rd = ~req_fifo_empty;
- end
- end
- SCR1_FSM_DATA : begin
- if (hready) begin
- req_fifo_rd = ~req_fifo_empty & (hresp == SCR1_HRESP_OKAY);
- end
- end
- default : begin
- req_fifo_rd = 1'bx;
- end
- endcase
-end
-
-//-------------------------------------------------------------------------------
-// FIFO data
-//-------------------------------------------------------------------------------
-always_ff @(posedge clk) begin
- case (fsm)
- SCR1_FSM_ADDR : begin
- if (~req_fifo_empty) begin
- data_fifo.hwrite <= req_fifo[0].hwrite;
- data_fifo.hwidth <= req_fifo[0].hwidth;
- data_fifo.haddr <= req_fifo[0].haddr[1:0];
- data_fifo.hwdata <= req_fifo[0].hwdata;
- end
- end
- SCR1_FSM_DATA : begin
- if (hready) begin
- if (hresp == SCR1_HRESP_OKAY) begin
- if (~req_fifo_empty) begin
- data_fifo.hwrite <= req_fifo[0].hwrite;
- data_fifo.hwidth <= req_fifo[0].hwidth;
- data_fifo.haddr <= req_fifo[0].haddr[1:0];
- data_fifo.hwdata <= req_fifo[0].hwdata;
- end
- end
- end
- end
- default : begin
- end
- endcase
-end
-
-//-------------------------------------------------------------------------------
-// FIFO response
-//-------------------------------------------------------------------------------
-`ifdef SCR1_DMEM_AHB_IN_BP
-assign resp_fifo_hready = (fsm == SCR1_FSM_DATA) ? hready : 1'b0;
-assign resp_fifo.hresp = hresp;
-assign resp_fifo.hwidth = data_fifo.hwidth;
-assign resp_fifo.haddr = data_fifo.haddr;
-assign resp_fifo.hrdata = hrdata;
-`else // SCR1_DMEM_AHB_IN_BP
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- resp_fifo_hready <= 1'b0;
- end else begin
- resp_fifo_hready <= (fsm == SCR1_FSM_DATA) ? hready : 1'b0;
- end
-end
-
-always_ff @(posedge clk) begin
- if (hready & (fsm == SCR1_FSM_DATA)) begin
- resp_fifo.hresp <= hresp;
- resp_fifo.hwidth <= data_fifo.hwidth;
- resp_fifo.haddr <= data_fifo.haddr;
- resp_fifo.hrdata <= hrdata;
- end
-end
-`endif // SCR1_DMEM_AHB_IN_BP
-
-//-------------------------------------------------------------------------------
-// Interface to AHB
-//-------------------------------------------------------------------------------
-assign hprot[SCR1_HPROT_DATA] = 1'b1;
-assign hprot[SCR1_HPROT_PRV] = 1'b0;
-assign hprot[SCR1_HPROT_BUF] = 1'b0;
-assign hprot[SCR1_HPROT_CACHE] = 1'b0;
-
-assign hburst = SCR1_HBURST_SINGLE;
-assign hsize = req_fifo[0].hwidth;
-assign hmastlock = 1'b0;
-
-always_comb begin
- htrans = SCR1_HTRANS_IDLE;
- case (fsm)
- SCR1_FSM_ADDR : begin
- if (~req_fifo_empty) begin
- htrans = SCR1_HTRANS_NONSEQ;
- end
- end
- SCR1_FSM_DATA : begin
- if (hready) begin
- if (hresp == SCR1_HRESP_OKAY) begin
- if (~req_fifo_empty) begin
- htrans = SCR1_HTRANS_NONSEQ;
- end
- end
- end
- end
- default : begin
- htrans = SCR1_HTRANS_ERR;
- end
- endcase
-end
-
-assign haddr = req_fifo[0].haddr;
-assign hwrite = req_fifo[0].hwrite;
-assign hwdata = data_fifo.hwdata;
-
-endmodule : scr1_dmem_ahb
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_router.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_router.sv
deleted file mode 100644
index 749085a..0000000
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_router.sv
+++ /dev/null
@@ -1,294 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_dmem_router.sv>
-/// @brief Data memory router
-///
-`include "scr1_memif.svh"
-`include "scr1_arch_description.svh"
-
-module scr1_dmem_router
-#(
- parameter SCR1_PORT1_ADDR_MASK = `SCR1_DMEM_AWIDTH'hFFFF0000,
- parameter SCR1_PORT1_ADDR_PATTERN = `SCR1_DMEM_AWIDTH'h00010000,
- parameter SCR1_PORT2_ADDR_MASK = `SCR1_DMEM_AWIDTH'hFFFF0000,
- parameter SCR1_PORT2_ADDR_PATTERN = `SCR1_DMEM_AWIDTH'h00020000
-)
-(
- // Control signals
- input logic rst_n,
- input logic clk,
-
- // Core interface
- output logic dmem_req_ack,
- input logic dmem_req,
- input logic dmem_cmd,
- input logic [1:0] dmem_width,
- input logic [`SCR1_DMEM_AWIDTH-1:0] dmem_addr,
- input logic [`SCR1_DMEM_DWIDTH-1:0] dmem_wdata,
- output logic [`SCR1_DMEM_DWIDTH-1:0] dmem_rdata,
- output logic [1:0] dmem_resp,
-
- // PORT0 interface
- input logic port0_req_ack,
- output logic port0_req,
- output logic port0_cmd,
- output logic [1:0] port0_width,
- output logic [`SCR1_DMEM_AWIDTH-1:0] port0_addr,
- output logic [`SCR1_DMEM_DWIDTH-1:0] port0_wdata,
- input logic [`SCR1_DMEM_DWIDTH-1:0] port0_rdata,
- input logic [1:0] port0_resp,
-
- // PORT1 interface
- input logic port1_req_ack,
- output logic port1_req,
- output logic port1_cmd,
- output logic [1:0] port1_width,
- output logic [`SCR1_DMEM_AWIDTH-1:0] port1_addr,
- output logic [`SCR1_DMEM_DWIDTH-1:0] port1_wdata,
- input logic [`SCR1_DMEM_DWIDTH-1:0] port1_rdata,
- input logic [1:0] port1_resp,
-
- // PORT2 interface
- input logic port2_req_ack,
- output logic port2_req,
- output logic port2_cmd,
- output logic [1:0] port2_width,
- output logic [`SCR1_DMEM_AWIDTH-1:0] port2_addr,
- output logic [`SCR1_DMEM_DWIDTH-1:0] port2_wdata,
- input logic [`SCR1_DMEM_DWIDTH-1:0] port2_rdata,
- input logic [1:0] port2_resp
-);
-
-//-------------------------------------------------------------------------------
-// Local types declaration
-//-------------------------------------------------------------------------------
-typedef enum logic {
- SCR1_FSM_ADDR,
- SCR1_FSM_DATA
-} type_scr1_fsm_e;
-
-typedef enum logic [1:0] {
- SCR1_SEL_PORT0,
- SCR1_SEL_PORT1,
- SCR1_SEL_PORT2
-} type_scr1_sel_e;
-
-//-------------------------------------------------------------------------------
-// Local signal declaration
-//-------------------------------------------------------------------------------
-type_scr1_fsm_e fsm;
-type_scr1_sel_e port_sel;
-type_scr1_sel_e port_sel_r;
-logic [`SCR1_DMEM_DWIDTH-1:0] sel_rdata;
-logic [1:0] sel_resp;
-logic sel_req_ack;
-
-//-------------------------------------------------------------------------------
-// FSM
-//-------------------------------------------------------------------------------
-always_comb begin
- port_sel = SCR1_SEL_PORT0;
- if ((dmem_addr & SCR1_PORT1_ADDR_MASK) == SCR1_PORT1_ADDR_PATTERN) begin
- port_sel = SCR1_SEL_PORT1;
- end else if ((dmem_addr & SCR1_PORT2_ADDR_MASK) == SCR1_PORT2_ADDR_PATTERN) begin
- port_sel = SCR1_SEL_PORT2;
- end
-end
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- fsm <= SCR1_FSM_ADDR;
- port_sel_r <= SCR1_SEL_PORT0;
- end else begin
- case (fsm)
- SCR1_FSM_ADDR : begin
- if (dmem_req & sel_req_ack) begin
- fsm <= SCR1_FSM_DATA;
- port_sel_r <= port_sel;
- end
- end
- SCR1_FSM_DATA : begin
- case (sel_resp)
- SCR1_MEM_RESP_RDY_OK : begin
- if (dmem_req & sel_req_ack) begin
- fsm <= SCR1_FSM_DATA;
- port_sel_r <= port_sel;
- end else begin
- fsm <= SCR1_FSM_ADDR;
- end
- end
- SCR1_MEM_RESP_RDY_ER : begin
- fsm <= SCR1_FSM_ADDR;
- end
- default : begin
- end
- endcase
- end
- default : begin
- end
- endcase
- end
-end
-
-always_comb begin
- if ((fsm == SCR1_FSM_ADDR) | ((fsm == SCR1_FSM_DATA) & (sel_resp == SCR1_MEM_RESP_RDY_OK))) begin
- case (port_sel)
- SCR1_SEL_PORT0 : sel_req_ack = port0_req_ack;
- SCR1_SEL_PORT1 : sel_req_ack = port1_req_ack;
- SCR1_SEL_PORT2 : sel_req_ack = port2_req_ack;
- default : sel_req_ack = 1'b0;
- endcase
- end else begin
- sel_req_ack = 1'b0;
- end
-end
-
-always_comb begin
- case (port_sel_r)
- SCR1_SEL_PORT0 : begin
- sel_rdata = port0_rdata;
- sel_resp = port0_resp;
- end
- SCR1_SEL_PORT1 : begin
- sel_rdata = port1_rdata;
- sel_resp = port1_resp;
- end
- SCR1_SEL_PORT2 : begin
- sel_rdata = port2_rdata;
- sel_resp = port2_resp;
- end
- default : begin
- sel_rdata = '0;
- sel_resp = SCR1_MEM_RESP_RDY_ER;
- end
- endcase
-end
-
-//-------------------------------------------------------------------------------
-// Interface to core
-//-------------------------------------------------------------------------------
-assign dmem_req_ack = sel_req_ack;
-assign dmem_rdata = sel_rdata;
-assign dmem_resp = sel_resp;
-
-//-------------------------------------------------------------------------------
-// Interface to PORT0
-//-------------------------------------------------------------------------------
-always_comb begin
- port0_req = 1'b0;
- case (fsm)
- SCR1_FSM_ADDR : begin
- port0_req = dmem_req & (port_sel == SCR1_SEL_PORT0);
- end
- SCR1_FSM_DATA : begin
- if (sel_resp == SCR1_MEM_RESP_RDY_OK) begin
- port0_req = dmem_req & (port_sel == SCR1_SEL_PORT0);
- end
- end
- default : begin
- end
- endcase
-end
-
-`ifdef SCR1_XPROP_EN
-assign port0_cmd = (port_sel == SCR1_SEL_PORT0) ? dmem_cmd : SCR1_MEM_CMD_ERROR;
-assign port0_width = (port_sel == SCR1_SEL_PORT0) ? dmem_width : SCR1_MEM_WIDTH_ERROR;
-assign port0_addr = (port_sel == SCR1_SEL_PORT0) ? dmem_addr : 'x;
-assign port0_wdata = (port_sel == SCR1_SEL_PORT0) ? dmem_wdata : 'x;
-`else // SCR1_XPROP_EN
-assign port0_cmd = dmem_cmd ;
-assign port0_width = dmem_width;
-assign port0_addr = dmem_addr ;
-assign port0_wdata = dmem_wdata;
-`endif // SCR1_XPROP_EN
-
-//-------------------------------------------------------------------------------
-// Interface to PORT1
-//-------------------------------------------------------------------------------
-always_comb begin
- port1_req = 1'b0;
- case (fsm)
- SCR1_FSM_ADDR : begin
- port1_req = dmem_req & (port_sel == SCR1_SEL_PORT1);
- end
- SCR1_FSM_DATA : begin
- if (sel_resp == SCR1_MEM_RESP_RDY_OK) begin
- port1_req = dmem_req & (port_sel == SCR1_SEL_PORT1);
- end
- end
- default : begin
- end
- endcase
-end
-
-`ifdef SCR1_XPROP_EN
-assign port1_cmd = (port_sel == SCR1_SEL_PORT1) ? dmem_cmd : SCR1_MEM_CMD_ERROR;
-assign port1_width = (port_sel == SCR1_SEL_PORT1) ? dmem_width : SCR1_MEM_WIDTH_ERROR;
-assign port1_addr = (port_sel == SCR1_SEL_PORT1) ? dmem_addr : 'x;
-assign port1_wdata = (port_sel == SCR1_SEL_PORT1) ? dmem_wdata : 'x;
-`else // SCR1_XPROP_EN
-assign port1_cmd = dmem_cmd ;
-assign port1_width = dmem_width;
-assign port1_addr = dmem_addr ;
-assign port1_wdata = dmem_wdata;
-`endif // SCR1_XPROP_EN
-
-//-------------------------------------------------------------------------------
-// Interface to PORT2
-//-------------------------------------------------------------------------------
-always_comb begin
- port2_req = 1'b0;
- case (fsm)
- SCR1_FSM_ADDR : begin
- port2_req = dmem_req & (port_sel == SCR1_SEL_PORT2);
- end
- SCR1_FSM_DATA : begin
- if (sel_resp == SCR1_MEM_RESP_RDY_OK) begin
- port2_req = dmem_req & (port_sel == SCR1_SEL_PORT2);
- end
- end
- default : begin
- end
- endcase
-end
-
-`ifdef SCR1_XPROP_EN
-assign port2_cmd = (port_sel == SCR1_SEL_PORT2) ? dmem_cmd : SCR1_MEM_CMD_ERROR;
-assign port2_width = (port_sel == SCR1_SEL_PORT2) ? dmem_width : SCR1_MEM_WIDTH_ERROR;
-assign port2_addr = (port_sel == SCR1_SEL_PORT2) ? dmem_addr : 'x;
-assign port2_wdata = (port_sel == SCR1_SEL_PORT2) ? dmem_wdata : 'x;
-`else // SCR1_XPROP_EN
-assign port2_cmd = dmem_cmd ;
-assign port2_width = dmem_width;
-assign port2_addr = dmem_addr ;
-assign port2_wdata = dmem_wdata;
-`endif // SCR1_XPROP_EN
-
-`ifdef SCR1_TRGT_SIMULATION
-//-------------------------------------------------------------------------------
-// Assertion
-//-------------------------------------------------------------------------------
-
-SCR1_SVA_DMEM_RT_XCHECK : assert property (
- @(negedge clk) disable iff (~rst_n)
- dmem_req |-> !$isunknown({port_sel, dmem_cmd, dmem_width})
- ) else $error("DMEM router Error: unknown values");
-
-`endif // SCR1_TRGT_SIMULATION
-
-endmodule : scr1_dmem_router
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv
deleted file mode 100644
index f839edd..0000000
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv
+++ /dev/null
@@ -1,400 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: 2021, Dinesh Annayya
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
-// //////////////////////////////////////////////////////////////////////////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// yifive Wishbone interface for Data memory ////
-//// ////
-//// This file is part of the yifive cores project ////
-//// https://github.com/dineshannayya/yifive_r0.git ////
-//// http://www.opencores.org/cores/yifive/ ////
-//// ////
-//// Description: ////
-//// integrated wishbone i/f to data memory ////
-//// ////
-//// To Do: ////
-//// nothing ////
-//// ////
-//// Author(s): ////
-//// - Dinesh Annayya, dinesha@opencores.org ////
-//// ////
-//// Revision : ////
-//// v0: June 7, 2021, Dinesh A ////
-//// wishbone integration ////
-//// v1: June 9, 2021, Dinesh A ////
-//// On power up, wishbone output are unkown as it ////
-//// driven from fifo output. To avoid unknown ////
-//// propgation, we are driving 'h0 when fifo empty ////
-//// v2: June 18, 2021, Dinesh A ////
-//// core and wishbone is made async and async fifo ////
-//// added to take care of domain cross-over ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-// Orginal owner Details ////
-//////////////////////////////////////////////////////////////////////
-/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details///
-/// @file <scr1_dmem_wb.sv> ///
-/// @brief Data memory WB bridge ///
-/////////////////////////////////////////////////////////////////////
-
-`include "scr1_wb.svh"
-`include "scr1_memif.svh"
-
-module scr1_dmem_wb (
- // Control Signals
- input logic core_rst_n, // core reset
- input logic core_clk, // Core clock
-
- // Core Interface
- output logic dmem_req_ack,
- input logic dmem_req,
- input logic dmem_cmd,
- input logic [1:0] dmem_width,
- input logic [SCR1_WB_WIDTH-1:0] dmem_addr,
- input logic [SCR1_WB_WIDTH-1:0] dmem_wdata,
- output logic [SCR1_WB_WIDTH-1:0] dmem_rdata,
- output logic [1:0] dmem_resp,
-
- // WB Interface
- input logic wb_rst_n, // wishbone reset
- input logic wb_clk, // wishbone clock
- output logic wbd_stb_o, // strobe/request
- output logic [SCR1_WB_WIDTH-1:0] wbd_adr_o, // address
- output logic wbd_we_o, // write
- output logic [SCR1_WB_WIDTH-1:0] wbd_dat_o, // data output
- output logic [3:0] wbd_sel_o, // byte enable
- input logic [SCR1_WB_WIDTH-1:0] wbd_dat_i, // data input
- input logic wbd_ack_i, // acknowlegement
- input logic wbd_err_i // error
-
-);
-
-//-------------------------------------------------------------------------------
-// Local Parameters
-//-------------------------------------------------------------------------------
-
-//-------------------------------------------------------------------------------
-// Local type declaration
-//-------------------------------------------------------------------------------
-
-typedef struct packed {
- logic [3:0] hbel;
- logic hwrite;
- logic [2:0] hwidth;
- logic [SCR1_WB_WIDTH-1:0] haddr;
- logic [SCR1_WB_WIDTH-1:0] hwdata;
-} type_scr1_req_fifo_s;
-
-
-typedef struct packed {
- logic hresp;
- logic [2:0] hwidth;
- logic [1:0] haddr;
- logic [SCR1_WB_WIDTH-1:0] hrdata;
-} type_scr1_resp_fifo_s;
-
-//-------------------------------------------------------------------------------
-// Local functions
-//-------------------------------------------------------------------------------
-function automatic logic [2:0] scr1_conv_mem2wb_width (
- input logic [1:0] dmem_width
-);
- logic [2:0] tmp;
-begin
- case (dmem_width)
- SCR1_MEM_WIDTH_BYTE : begin
- tmp = SCR1_DSIZE_8B;
- end
- SCR1_MEM_WIDTH_HWORD : begin
- tmp = SCR1_DSIZE_16B;
- end
- SCR1_MEM_WIDTH_WORD : begin
- tmp = SCR1_DSIZE_32B;
- end
- default : begin
- tmp = SCR1_DSIZE_32B;
- end
- endcase
- scr1_conv_mem2wb_width = tmp; // cp.11
-end
-endfunction
-
-function automatic logic[SCR1_WB_WIDTH-1:0] scr1_conv_mem2wb_wdata (
- input logic [1:0] dmem_addr,
- input logic [1:0] dmem_width,
- input logic [SCR1_WB_WIDTH-1:0] dmem_wdata
-);
- logic [SCR1_WB_WIDTH-1:0] tmp;
-begin
- tmp = 'x;
- case (dmem_width)
- SCR1_MEM_WIDTH_BYTE : begin
- case (dmem_addr)
- 2'b00 : begin
- tmp[7:0] = dmem_wdata[7:0];
- end
- 2'b01 : begin
- tmp[15:8] = dmem_wdata[7:0];
- end
- 2'b10 : begin
- tmp[23:16] = dmem_wdata[7:0];
- end
- 2'b11 : begin
- tmp[31:24] = dmem_wdata[7:0];
- end
- default : begin
- end
- endcase
- end
- SCR1_MEM_WIDTH_HWORD : begin
- case (dmem_addr[1])
- 1'b0 : begin
- tmp[15:0] = dmem_wdata[15:0];
- end
- 1'b1 : begin
- tmp[31:16] = dmem_wdata[15:0];
- end
- default : begin
- end
- endcase
- end
- SCR1_MEM_WIDTH_WORD : begin
- tmp = dmem_wdata;
- end
- default : begin
- end
- endcase
- scr1_conv_mem2wb_wdata = tmp;
-end
-endfunction
-
-function automatic logic[SCR1_WB_WIDTH-1:0] scr1_conv_wb2mem_rdata (
- input logic [2:0] hwidth,
- input logic [1:0] haddr,
- input logic [SCR1_WB_WIDTH-1:0] hrdata
-);
- logic [SCR1_WB_WIDTH-1:0] tmp;
-begin
- tmp = 'x;
- case (hwidth)
- SCR1_DSIZE_8B : begin
- case (haddr)
- 2'b00 : tmp[7:0] = hrdata[7:0];
- 2'b01 : tmp[7:0] = hrdata[15:8];
- 2'b10 : tmp[7:0] = hrdata[23:16];
- 2'b11 : tmp[7:0] = hrdata[31:24];
- default : begin
- end
- endcase
- end
- SCR1_DSIZE_16B : begin
- case (haddr[1])
- 1'b0 : tmp[15:0] = hrdata[15:0];
- 1'b1 : tmp[15:0] = hrdata[31:16];
- default : begin
- end
- endcase
- end
- SCR1_DSIZE_32B : begin
- tmp = hrdata;
- end
- default : begin
- end
- endcase
- scr1_conv_wb2mem_rdata = tmp;
-end
-endfunction
-
-//-------------------------------------------------------------------------------
-// Local signal declaration
-//-------------------------------------------------------------------------------
-logic req_fifo_rd;
-logic req_fifo_wr;
-logic req_fifo_empty;
-logic req_fifo_full;
-
-
-logic resp_fifo_rd;
-logic resp_fifo_empty;
-logic resp_fifo_full;
-
-
-//-------------------------------------------------------------------------------
-// REQ_FIFO (CORE to WB)
-//-------------------------------------------------------------------------------
-wire hwrite_in = (dmem_cmd == SCR1_MEM_CMD_WR);
-wire [2:0] hwidth_in = scr1_conv_mem2wb_width(dmem_width);
-wire [SCR1_WB_WIDTH-1:0] haddr_in = dmem_addr;
-wire [SCR1_WB_WIDTH-1:0] hwdata_in = scr1_conv_mem2wb_wdata(dmem_addr[1:0], dmem_width, dmem_wdata);
-
-reg [3:0] hbel_in; // byte select
-always_comb begin
- hbel_in = 0;
- case (hwidth_in)
- SCR1_DSIZE_8B : begin
- hbel_in = 4'b0001 << haddr_in[1:0];
- end
- SCR1_DSIZE_16B : begin
- hbel_in = 4'b0011 << haddr_in[1:0];
- end
- SCR1_DSIZE_32B : begin
- hbel_in = 4'b1111;
- end
- endcase
-end
-
-
-//-------------------------------------------------------------------------------
-// REQ_FIFO (WB to CORE)
-//-------------------------------------------------------------------------------
-type_scr1_req_fifo_s req_fifo_din;
-type_scr1_req_fifo_s req_fifo_dout;
-
-
-assign dmem_req_ack = ~req_fifo_full;
-assign req_fifo_wr = ~req_fifo_full & dmem_req;
-
-//pack data in
-assign req_fifo_din.hbel = hbel_in;
-assign req_fifo_din.hwrite = hwrite_in;
-assign req_fifo_din.hwidth = hwidth_in;
-assign req_fifo_din.haddr = haddr_in;
-assign req_fifo_din.hwdata = hwdata_in;
-
-
- async_fifo #(
- .W(SCR1_WB_WIDTH+SCR1_WB_WIDTH+3+1+4), // Data Width
- .DP(4), // FIFO DEPTH
- .WR_FAST(1), // We need FF'ed Full
- .RD_FAST(1) // We need FF'ed Empty
- ) u_req_fifo(
- // Writc Clock
- .wr_clk (core_clk ),
- .wr_reset_n (core_rst_n ),
- .wr_en (req_fifo_wr ),
- .wr_data (req_fifo_din ),
- .full (req_fifo_full ),
- .afull ( ),
-
- // RD Clock
- .rd_clk (wb_clk ),
- .rd_reset_n (wb_rst_n ),
- .rd_en (req_fifo_rd ),
- .empty (req_fifo_empty ),
- .aempty ( ),
- .rd_data (req_fifo_dout )
- );
-
-
-always_comb begin
- req_fifo_rd = 1'b0;
- if (wbd_ack_i) begin
- req_fifo_rd = ~req_fifo_empty;
- end
-end
-
-
-assign wbd_stb_o = ~req_fifo_empty;
-
-// To avoid unknown progating the design, driven zero when fifo is empty
-assign wbd_adr_o = (req_fifo_empty) ? 'h0 : req_fifo_dout.haddr;
-assign wbd_we_o = (req_fifo_empty) ? 'h0 : req_fifo_dout.hwrite;
-assign wbd_dat_o = (req_fifo_empty) ? 'h0 : req_fifo_dout.hwdata;
-assign wbd_sel_o = (req_fifo_empty) ? 'h0 : req_fifo_dout.hbel;
-
-
-//-------------------------------------------------------------------------------
-// Response path - Used by Read path logic
-//-------------------------------------------------------------------------------
-type_scr1_resp_fifo_s resp_fifo_din;
-type_scr1_resp_fifo_s resp_fifo_dout;
-
-
-assign resp_fifo_din.hresp = (wbd_err_i) ? 1'b0 : 1'b1;
-assign resp_fifo_din.hwidth = req_fifo_dout.hwidth;
-assign resp_fifo_din.haddr = req_fifo_dout.haddr[1:0];
-assign resp_fifo_din.hrdata = (wbd_we_o) ? 'h0: wbd_dat_i;
-
- async_fifo #(
- .W(SCR1_WB_WIDTH+2+3+1), // Data Width
- .DP(4), // FIFO DEPTH
- .WR_FAST(1), // We need FF'ed Full
- .RD_FAST(1) // We need FF'ed Empty
- ) u_res_fifo(
- // Writc Clock
- .wr_clk (wb_clk ),
- .wr_reset_n (wb_rst_n ),
- .wr_en (wbd_ack_i ),
- .wr_data (resp_fifo_din ),
- .full ( ), // Assmed FIFO will never be full as it's Response a Single Request
- .afull ( ),
-
- // RD Clock
- .rd_clk (core_clk ),
- .rd_reset_n (core_rst_n ),
- .rd_en (resp_fifo_rd ),
- .empty (resp_fifo_empty ),
- .aempty ( ),
- .rd_data (resp_fifo_dout )
- );
-
-assign resp_fifo_rd = !resp_fifo_empty;
-
-// Added FF to improve timing
-always_ff @(posedge core_clk, negedge core_rst_n) begin
- if(core_rst_n == 0) begin
- dmem_rdata <= '0;
- dmem_resp <= '0;
- end else begin
- dmem_rdata <= (resp_fifo_rd) ? scr1_conv_wb2mem_rdata(resp_fifo_dout.hwidth, resp_fifo_dout.haddr, resp_fifo_dout.hrdata) : 'h0;
- dmem_resp <= (resp_fifo_rd)
- ? (resp_fifo_dout.hresp == 1'b1)
- ? SCR1_MEM_RESP_RDY_OK
- : SCR1_MEM_RESP_RDY_ER
- : SCR1_MEM_RESP_NOTRDY ;
- end
-end
-
-
-
-
-endmodule : scr1_dmem_wb
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_dp_memory.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_dp_memory.sv
deleted file mode 100644
index 00a2281..0000000
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_dp_memory.sv
+++ /dev/null
@@ -1,127 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_dp_memory.sv>
-/// @brief Dual-port synchronous memory with byte enable inputs
-///
-
-`include "scr1_arch_description.svh"
-
-`ifdef SCR1_TCM_EN
-module scr1_dp_memory
-#(
- parameter SCR1_WIDTH = 32,
- parameter SCR1_SIZE = `SCR1_IMEM_AWIDTH'h00010000,
- parameter SCR1_NBYTES = SCR1_WIDTH / 8
-)
-(
- input logic clk,
- // Port A
- input logic rena,
- input logic [$clog2(SCR1_SIZE)-1:2] addra,
- output logic [SCR1_WIDTH-1:0] qa,
- // Port B
- input logic renb,
- input logic wenb,
- input logic [SCR1_NBYTES-1:0] webb,
- input logic [$clog2(SCR1_SIZE)-1:2] addrb,
- input logic [SCR1_WIDTH-1:0] datab,
- output logic [SCR1_WIDTH-1:0] qb
-);
-
-`ifdef SCR1_TRGT_FPGA_INTEL
-//-------------------------------------------------------------------------------
-// Local signal declaration
-//-------------------------------------------------------------------------------
- `ifdef SCR1_TRGT_FPGA_INTEL_MAX10
-(* ramstyle = "M9K" *) logic [SCR1_NBYTES-1:0][7:0] memory_array [0:(SCR1_SIZE/SCR1_NBYTES)-1];
- `elsif SCR1_TRGT_FPGA_INTEL_ARRIAV
-(* ramstyle = "M10K" *) logic [SCR1_NBYTES-1:0][7:0] memory_array [0:(SCR1_SIZE/SCR1_NBYTES)-1];
- `endif
-logic [3:0] wenbb;
-//-------------------------------------------------------------------------------
-// Port B memory behavioral description
-//-------------------------------------------------------------------------------
-assign wenbb = {4{wenb}} & webb;
-always_ff @(posedge clk) begin
- if (wenb) begin
- if (wenbb[0]) begin
- memory_array[addrb][0] <= datab[0+:8];
- end
- if (wenbb[1]) begin
- memory_array[addrb][1] <= datab[8+:8];
- end
- if (wenbb[2]) begin
- memory_array[addrb][2] <= datab[16+:8];
- end
- if (wenbb[3]) begin
- memory_array[addrb][3] <= datab[24+:8];
- end
- end
- qb <= memory_array[addrb];
-end
-//-------------------------------------------------------------------------------
-// Port A memory behavioral description
-//-------------------------------------------------------------------------------
-always_ff @(posedge clk) begin
- qa <= memory_array[addra];
-end
-
-`else // SCR1_TRGT_FPGA_INTEL
-
-// CASE: OTHERS - SCR1_TRGT_FPGA_XILINX, SIMULATION, ASIC etc
-
-localparam int unsigned RAM_SIZE_WORDS = SCR1_SIZE/SCR1_NBYTES;
-
-//-------------------------------------------------------------------------------
-// Local signal declaration
-//-------------------------------------------------------------------------------
- `ifdef SCR1_TRGT_FPGA_XILINX
-(* ram_style = "block" *) logic [SCR1_WIDTH-1:0] ram_block [RAM_SIZE_WORDS-1:0];
- `else // ASIC or SIMULATION
-logic [SCR1_WIDTH-1:0] ram_block [RAM_SIZE_WORDS-1:0];
- `endif
-//-------------------------------------------------------------------------------
-// Port A memory behavioral description
-//-------------------------------------------------------------------------------
-always_ff @(posedge clk) begin
- if (rena) begin
- qa <= ram_block[addra];
- end
-end
-
-//-------------------------------------------------------------------------------
-// Port B memory behavioral description
-//-------------------------------------------------------------------------------
-always_ff @(posedge clk) begin
- if (wenb) begin
- for (int i=0; i<SCR1_NBYTES; i++) begin
- if (webb[i]) begin
- ram_block[addrb][i*8 +: 8] <= datab[i*8 +: 8];
- end
- end
- end
- if (renb) begin
- qb <= ram_block[addrb];
- end
-end
-
-`endif // SCR1_TRGT_FPGA_INTEL
-
-endmodule : scr1_dp_memory
-
-`endif // SCR1_TCM_EN
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_imem_ahb.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_imem_ahb.sv
deleted file mode 100644
index 764f0d3..0000000
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_imem_ahb.sv
+++ /dev/null
@@ -1,335 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_imem_ahb.sv>
-/// @brief Instruction memory AHB bridge
-///
-
-`include "scr1_ahb.svh"
-`include "scr1_memif.svh"
-
-module scr1_imem_ahb (
- // Control Signals
- input logic rst_n,
- input logic clk,
-
- // Core Interface
- output logic imem_req_ack,
- input logic imem_req,
- input logic [SCR1_AHB_WIDTH-1:0] imem_addr,
- output logic [SCR1_AHB_WIDTH-1:0] imem_rdata,
- output logic [1:0] imem_resp,
-
- // AHB Interface
- output logic [3:0] hprot,
- output logic [2:0] hburst,
- output logic [2:0] hsize,
- output logic [1:0] htrans,
- output logic hmastlock,
- output logic [SCR1_AHB_WIDTH-1:0] haddr,
- input logic hready,
- input logic [SCR1_AHB_WIDTH-1:0] hrdata,
- input logic hresp
-
-);
-
-//-------------------------------------------------------------------------------
-// Local parameters declaration
-//-------------------------------------------------------------------------------
-`ifndef SCR1_IMEM_AHB_OUT_BP
-localparam SCR1_FIFO_WIDTH = 2;
-localparam SCR1_FIFO_CNT_WIDTH = $clog2(SCR1_FIFO_WIDTH+1);
-`endif // SCR1_IMEM_AHB_OUT_BP
-
-//-------------------------------------------------------------------------------
-// Local types declaration
-//-------------------------------------------------------------------------------
-typedef enum logic {
- SCR1_FSM_ADDR = 1'b0,
- SCR1_FSM_DATA = 1'b1,
- SCR1_FSM_ERR = 1'bx
-} type_scr1_fsm_e;
-
-typedef struct packed {
- logic [SCR1_AHB_WIDTH-1:0] haddr;
-} type_scr1_req_fifo_s;
-
-typedef struct packed {
- logic hresp;
- logic [SCR1_AHB_WIDTH-1:0] hrdata;
-} type_scr1_resp_fifo_s;
-
-//-------------------------------------------------------------------------------
-// Local signal declaration
-//-------------------------------------------------------------------------------
-type_scr1_fsm_e fsm;
-logic req_fifo_rd;
-logic req_fifo_wr;
-logic req_fifo_up;
-`ifdef SCR1_IMEM_AHB_OUT_BP
-type_scr1_req_fifo_s req_fifo_r;
-type_scr1_req_fifo_s [0:0] req_fifo;
-`else // SCR1_IMEM_AHB_OUT_BP
-type_scr1_req_fifo_s [0:SCR1_FIFO_WIDTH-1] req_fifo;
-type_scr1_req_fifo_s [0:SCR1_FIFO_WIDTH-1] req_fifo_new;
-logic [SCR1_FIFO_CNT_WIDTH-1:0] req_fifo_cnt;
-logic [SCR1_FIFO_CNT_WIDTH-1:0] req_fifo_cnt_new;
-`endif // SCR1_IMEM_AHB_OUT_BP
-logic req_fifo_empty;
-logic req_fifo_full;
-
-type_scr1_resp_fifo_s resp_fifo;
-logic resp_fifo_hready;
-
-//-------------------------------------------------------------------------------
-// Interface to Core
-//-------------------------------------------------------------------------------
-assign imem_req_ack = ~req_fifo_full;
-assign req_fifo_wr = ~req_fifo_full & imem_req;
-
-assign imem_rdata = resp_fifo.hrdata;
-
-assign imem_resp = (resp_fifo_hready)
- ? (resp_fifo.hresp == SCR1_HRESP_OKAY)
- ? SCR1_MEM_RESP_RDY_OK
- : SCR1_MEM_RESP_RDY_ER
- : SCR1_MEM_RESP_NOTRDY;
-
-//-------------------------------------------------------------------------------
-// REQ_FIFO
-//-------------------------------------------------------------------------------
-`ifdef SCR1_IMEM_AHB_OUT_BP
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- req_fifo_full <= 1'b0;
- end else begin
- if (~req_fifo_full) begin
- req_fifo_full <= imem_req & ~req_fifo_rd;
- end else begin
- req_fifo_full <= ~req_fifo_rd;
- end
- end
-end
-assign req_fifo_empty = ~(req_fifo_full | imem_req);
-
-assign req_fifo_up = ~req_fifo_rd & req_fifo_wr;
-always_ff @(posedge clk) begin
- if (req_fifo_up) begin
- req_fifo_r.haddr <= imem_addr;
- end
-end
-
-assign req_fifo[0] = (req_fifo_full) ? req_fifo_r : imem_addr;
-
-`else // SCR1_IMEM_AHB_OUT_BP
-always_comb begin
- req_fifo_up = 1'b0;
- req_fifo_cnt_new = req_fifo_cnt;
- req_fifo_new = req_fifo;
- case ({req_fifo_rd, req_fifo_wr})
- 2'b00 : begin
- // nothing todo
- end
- 2'b01: begin
- // FIFO write
- req_fifo_up = 1'b1;
- req_fifo_new[req_fifo_cnt].haddr = imem_addr;
- req_fifo_cnt_new = req_fifo_cnt + 1'b1;
- end
- 2'b10 : begin
- // FIFO read
- req_fifo_up = 1'b1;
- req_fifo_new[0] = req_fifo_new[1];
- req_fifo_new[1].haddr = 'x;
- req_fifo_cnt_new = req_fifo_cnt - 1'b1;
- end
- 2'b11 : begin
- // Read and Write FIFO. It is possible only when fifo_cnt = 1
- req_fifo_up = 1'b1;
- req_fifo_new[0].haddr = imem_addr;
- end
- default : begin
- req_fifo_up = 'x;
- req_fifo_cnt_new = 'x;
- req_fifo_new = 'x;
- end
- endcase
-end
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- req_fifo_cnt <= '0;
- end else begin
- if (req_fifo_up) begin
- req_fifo_cnt <= req_fifo_cnt_new;
- end
- end
-end
-assign req_fifo_full = (req_fifo_cnt == SCR1_FIFO_WIDTH);
-assign req_fifo_empty = ~(|req_fifo_cnt);
-
-always_ff @(posedge clk) begin
- if (req_fifo_up) begin
- req_fifo <= req_fifo_new;
- end
-end
-`endif // SCR1_IMEM_AHB_OUT_BP
-
-//-------------------------------------------------------------------------------
-// FSM
-//-------------------------------------------------------------------------------
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- fsm <= SCR1_FSM_ADDR;
- end else begin
- case (fsm)
- SCR1_FSM_ADDR : begin
- if (hready) begin
- fsm <= (req_fifo_empty) ? SCR1_FSM_ADDR : SCR1_FSM_DATA;
- end
- end
- SCR1_FSM_DATA : begin
- if (hready) begin
- if (hresp == SCR1_HRESP_OKAY) begin
- fsm <= (req_fifo_empty) ? SCR1_FSM_ADDR : SCR1_FSM_DATA;
- end else begin
- fsm <= SCR1_FSM_ADDR;
- end
- end
- end
- default : begin
- fsm <= SCR1_FSM_ERR;
- end
- endcase
- end
-end
-
-always_comb begin
- req_fifo_rd = 1'b0;
- case (fsm)
- SCR1_FSM_ADDR : begin
- if (hready) begin
- req_fifo_rd = ~req_fifo_empty;
- end
- end
- SCR1_FSM_DATA : begin
- if (hready) begin
- req_fifo_rd = ~req_fifo_empty & (hresp == SCR1_HRESP_OKAY);
- end
- end
- default : begin
- req_fifo_rd = 1'bx;
- end
- endcase
-end
-
-//-------------------------------------------------------------------------------
-// FIFO response
-//-------------------------------------------------------------------------------
-`ifdef SCR1_IMEM_AHB_IN_BP
-assign resp_fifo_hready = (fsm == SCR1_FSM_DATA) ? hready : 1'b0;
-assign resp_fifo.hresp = hresp;
-assign resp_fifo.hrdata = hrdata;
-`else // SCR1_IMEM_AHB_IN_BP
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- resp_fifo_hready <= 1'b0;
- end else begin
- resp_fifo_hready <= (fsm == SCR1_FSM_DATA) ? hready : 1'b0;
- end
-end
-
-always_ff @(posedge clk) begin
- if (hready & (fsm == SCR1_FSM_DATA)) begin
- resp_fifo.hresp <= hresp;
- resp_fifo.hrdata <= hrdata;
- end
-end
-`endif // SCR1_IMEM_AHB_IN_BP
-
-//-------------------------------------------------------------------------------
-// Interface to AHB
-//-------------------------------------------------------------------------------
-assign hprot[SCR1_HPROT_DATA] = 1'b0;
-assign hprot[SCR1_HPROT_PRV] = 1'b0;
-assign hprot[SCR1_HPROT_BUF] = 1'b0;
-assign hprot[SCR1_HPROT_CACHE] = 1'b0;
-
-assign hburst = SCR1_HBURST_SINGLE;
-assign hsize = SCR1_HSIZE_32B;
-assign hmastlock = 1'b0;
-
-always_comb begin
- htrans = SCR1_HTRANS_IDLE;
- case (fsm)
- SCR1_FSM_ADDR : begin
- if (~req_fifo_empty) begin
- htrans = SCR1_HTRANS_NONSEQ;
- end
- end
- SCR1_FSM_DATA : begin
- if (hready) begin
- if (hresp == SCR1_HRESP_OKAY) begin
- if (~req_fifo_empty) begin
- htrans = SCR1_HTRANS_NONSEQ;
- end
- end
- end
- end
- default : begin
- htrans = SCR1_HTRANS_ERR;
- end
- endcase
-end
-
-assign haddr = req_fifo[0].haddr;
-
-`ifdef SCR1_TRGT_SIMULATION
-//-------------------------------------------------------------------------------
-// Assertion
-//-------------------------------------------------------------------------------
-
-// Check Core interface
-SCR1_SVA_IMEM_AHB_BRIDGE_REQ_XCHECK : assert property (
- @(negedge clk) disable iff (~rst_n)
- !$isunknown(imem_req)
- ) else $error("IMEM AHB bridge Error: imem_req has unknown values");
-
-SCR1_IMEM_AHB_BRIDGE_ADDR_XCHECK : assert property (
- @(negedge clk) disable iff (~rst_n)
- imem_req |-> !$isunknown(imem_addr)
- ) else $error("IMEM AHB bridge Error: imem_addr has unknown values");
-
-SCR1_IMEM_AHB_BRIDGE_ADDR_ALLIGN : assert property (
- @(negedge clk) disable iff (~rst_n)
- imem_req |-> (imem_addr[1:0] == '0)
- ) else $error("IMEM AHB bridge Error: imem_addr has unalign values");
-
-// Check AHB interface
-SCR1_IMEM_AHB_BRIDGE_HREADY_XCHECK : assert property (
- @(negedge clk) disable iff (~rst_n)
- !$isunknown(hready)
- ) else $error("IMEM AHB bridge Error: hready has unknown values");
-
-SCR1_IMEM_AHB_BRIDGE_HRESP_XCHECK : assert property (
- @(negedge clk) disable iff (~rst_n)
- !$isunknown(hresp)
- ) else $error("IMEM AHB bridge Error: hresp has unknown values");
-
-`endif // SCR1_TRGT_SIMULATION
-
-endmodule : scr1_imem_ahb
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_imem_router.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_imem_router.sv
deleted file mode 100644
index 72554f1..0000000
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_imem_router.sv
+++ /dev/null
@@ -1,201 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_imem_router.sv>
-/// @brief Instruction memory router
-///
-`include "scr1_memif.svh"
-`include "scr1_arch_description.svh"
-
-module scr1_imem_router
-#(
- parameter SCR1_ADDR_MASK = `SCR1_IMEM_AWIDTH'hFFFF0000,
- parameter SCR1_ADDR_PATTERN = `SCR1_IMEM_AWIDTH'h00010000
-)
-(
- // Control signals
- input logic rst_n,
- input logic clk,
-
- // Core interface
- output logic imem_req_ack,
- input logic imem_req,
- input logic imem_cmd,
- input logic [`SCR1_IMEM_AWIDTH-1:0] imem_addr,
- output logic [`SCR1_IMEM_DWIDTH-1:0] imem_rdata,
- output logic [1:0] imem_resp,
-
- // PORT0 interface
- input logic port0_req_ack,
- output logic port0_req,
- output logic port0_cmd,
- output logic [`SCR1_IMEM_AWIDTH-1:0] port0_addr,
- input logic [`SCR1_IMEM_DWIDTH-1:0] port0_rdata,
- input logic [1:0] port0_resp,
-
- // PORT1 interface
- input logic port1_req_ack,
- output logic port1_req,
- output logic port1_cmd,
- output logic [`SCR1_IMEM_AWIDTH-1:0] port1_addr,
- input logic [`SCR1_IMEM_DWIDTH-1:0] port1_rdata,
- input logic [1:0] port1_resp
-);
-
-//-------------------------------------------------------------------------------
-// Local types declaration
-//-------------------------------------------------------------------------------
-typedef enum logic {
- SCR1_FSM_ADDR,
- SCR1_FSM_DATA
-} type_scr1_fsm_e;
-
-//-------------------------------------------------------------------------------
-// Local signal declaration
-//-------------------------------------------------------------------------------
-type_scr1_fsm_e fsm;
-logic port_sel;
-logic port_sel_r;
-logic [`SCR1_IMEM_DWIDTH-1:0] sel_rdata;
-logic [1:0] sel_resp;
-logic sel_req_ack;
-
-//-------------------------------------------------------------------------------
-// FSM
-//-------------------------------------------------------------------------------
-assign port_sel = ((imem_addr & SCR1_ADDR_MASK) == SCR1_ADDR_PATTERN);
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- fsm <= SCR1_FSM_ADDR;
- port_sel_r <= 1'b0;
- end else begin
- case (fsm)
- SCR1_FSM_ADDR : begin
- if (imem_req & sel_req_ack) begin
- fsm <= SCR1_FSM_DATA;
- port_sel_r <= port_sel;
- end
- end
- SCR1_FSM_DATA : begin
- case (sel_resp)
- SCR1_MEM_RESP_RDY_OK : begin
- if (imem_req & sel_req_ack) begin
- fsm <= SCR1_FSM_DATA;
- port_sel_r <= port_sel;
- end else begin
- fsm <= SCR1_FSM_ADDR;
- end
- end
- SCR1_MEM_RESP_RDY_ER : begin
- fsm <= SCR1_FSM_ADDR;
- end
- default : begin
- end
- endcase
- end
- default : begin
- end
- endcase
- end
-end
-
-always_comb begin
- if ((fsm == SCR1_FSM_ADDR) | ((fsm == SCR1_FSM_DATA) & (sel_resp == SCR1_MEM_RESP_RDY_OK))) begin
- sel_req_ack = (port_sel) ? port1_req_ack : port0_req_ack;
- end else begin
- sel_req_ack = 1'b0;
- end
-end
-
-assign sel_rdata = (port_sel_r) ? port1_rdata : port0_rdata;
-assign sel_resp = (port_sel_r) ? port1_resp : port0_resp;
-
-//-------------------------------------------------------------------------------
-// Interface to core
-//-------------------------------------------------------------------------------
-assign imem_req_ack = sel_req_ack;
-assign imem_rdata = sel_rdata;
-assign imem_resp = sel_resp;
-
-//-------------------------------------------------------------------------------
-// Interface to PORT0
-//-------------------------------------------------------------------------------
-always_comb begin
- port0_req = 1'b0;
- case (fsm)
- SCR1_FSM_ADDR : begin
- port0_req = imem_req & ~port_sel;
- end
- SCR1_FSM_DATA : begin
- if (sel_resp == SCR1_MEM_RESP_RDY_OK) begin
- port0_req = imem_req & ~port_sel;
- end
- end
- default : begin
- end
- endcase
-end
-
-`ifdef SCR1_XPROP_EN
-assign port0_cmd = (~port_sel) ? imem_cmd : SCR1_MEM_CMD_ERROR;
-assign port0_addr = (~port_sel) ? imem_addr : 'x;
-`else // SCR1_XPROP_EN
-assign port0_cmd = imem_cmd ;
-assign port0_addr = imem_addr;
-`endif // SCR1_XPROP_EN
-
-//-------------------------------------------------------------------------------
-// Interface to PORT1
-//-------------------------------------------------------------------------------
-always_comb begin
- port1_req = 1'b0;
- case (fsm)
- SCR1_FSM_ADDR : begin
- port1_req = imem_req & port_sel;
- end
- SCR1_FSM_DATA : begin
- if (sel_resp == SCR1_MEM_RESP_RDY_OK) begin
- port1_req = imem_req & port_sel;
- end
- end
- default : begin
- end
- endcase
-end
-
-`ifdef SCR1_XPROP_EN
-assign port1_cmd = (port_sel) ? imem_cmd : SCR1_MEM_CMD_ERROR;
-assign port1_addr = (port_sel) ? imem_addr : 'x;
-`else // SCR1_XPROP_EN
-assign port1_cmd = imem_cmd ;
-assign port1_addr = imem_addr;
-`endif // SCR1_XPROP_EN
-
-`ifdef SCR1_TRGT_SIMULATION
-//-------------------------------------------------------------------------------
-// Assertion
-//-------------------------------------------------------------------------------
-
-SCR1_SVA_IMEM_RT_XCHECK : assert property (
- @(negedge clk) disable iff (~rst_n)
- imem_req |-> !$isunknown({port_sel, imem_cmd})
- ) else $error("IMEM router Error: unknown values");
-
-`endif // SCR1_TRGT_SIMULATION
-
-endmodule : scr1_imem_router
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv
deleted file mode 100644
index 65a6abb..0000000
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv
+++ /dev/null
@@ -1,271 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: 2021, Dinesh Annayya
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
-// //////////////////////////////////////////////////////////////////////////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// yifive Wishbone interface for Instruction memory ////
-//// ////
-//// This file is part of the yifive cores project ////
-//// https://github.com/dineshannayya/yifive_r0.git ////
-//// http://www.opencores.org/cores/yifive/ ////
-//// ////
-//// Description: ////
-//// integrated wishbone i/f to instruction memory ////
-//// ////
-//// To Do: ////
-//// nothing ////
-//// ////
-//// Author(s): ////
-//// - Dinesh Annayya, dinesha@opencores.org ////
-//// ////
-//// Revision : ////
-//// v0: June 7, 2021, Dinesh A ////
-//// wishbone integration ////
-//// v1: June 9, 2021, Dinesh A ////
-//// On power up, wishbone output are unkown as it ////
-//// driven from fifo output. To avoid unknown ////
-//// propgation, we are driving 'h0 when fifo empty ////
-//// v2: June 18, 2021, Dinesh A ////
-//// core and wishbone is made async and async fifo ////
-//// added to take care of domain cross-over ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-// Orginal owner Details ////
-//////////////////////////////////////////////////////////////////////
-/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details///
-/// @file <scr1_imem_wb.sv> ///
-/// @brief Instruction memory AHB bridge ///
-//////////////////////////////////////////////////////////////////////
-
-`include "scr1_wb.svh"
-`include "scr1_memif.svh"
-
-module scr1_imem_wb (
- // Control Signals
- input logic core_rst_n, // core reset
- input logic core_clk, // Core clock
-
- // Core Interface
- output logic imem_req_ack,
- input logic imem_req,
- input logic [SCR1_WB_WIDTH-1:0] imem_addr,
- output logic [SCR1_WB_WIDTH-1:0] imem_rdata,
- output logic [1:0] imem_resp,
-
- // WB Interface
- input logic wb_rst_n, // wishbone reset
- input logic wb_clk, // wishbone clock
- output logic wbd_stb_o, // strobe/request
- output logic [SCR1_WB_WIDTH-1:0] wbd_adr_o, // address
- output logic wbd_we_o, // write
- output logic [SCR1_WB_WIDTH-1:0] wbd_dat_o, // data output
- output logic [3:0] wbd_sel_o, // byte enable
- input logic [SCR1_WB_WIDTH-1:0] wbd_dat_i, // data input
- input logic wbd_ack_i, // acknowlegement
- input logic wbd_err_i // error
-
-);
-
-//-------------------------------------------------------------------------------
-// Local parameters declaration
-//-------------------------------------------------------------------------------
-
-//-------------------------------------------------------------------------------
-// Local types declaration
-//-------------------------------------------------------------------------------
-
-typedef struct packed {
- logic [SCR1_WB_WIDTH-1:0] haddr;
-} type_scr1_req_fifo_s;
-
-typedef struct packed {
- logic hresp;
- logic [SCR1_WB_WIDTH-1:0] hrdata;
-} type_scr1_resp_fifo_s;
-
-//-------------------------------------------------------------------------------
-// Local signal declaration
-//-------------------------------------------------------------------------------
-
-//-------------------------------------------------------------------------------
-// Request FIFO
-// ------------------------------------------------------------------------------
-logic req_fifo_rd;
-logic req_fifo_wr;
-logic req_fifo_empty;
-logic req_fifo_full;
-
-
-//-----------------------------------------------------
-// Response FIFO (READ PATH
-// ----------------------------------------------------
-logic resp_fifo_empty;
-logic resp_fifo_rd;
-
-
-
-//-------------------------------------------------------------------------------
-// REQ_FIFO
-//-------------------------------------------------------------------------------
-type_scr1_req_fifo_s req_fifo_din;
-type_scr1_req_fifo_s req_fifo_dout;
-
-assign req_fifo_wr = ~req_fifo_full & imem_req;
-assign imem_req_ack = ~req_fifo_full;
-
-assign req_fifo_din.haddr = imem_addr;
-
- async_fifo #(
- .W(SCR1_WB_WIDTH), // Data Width
- .DP(4), // FIFO DEPTH
- .WR_FAST(1), // We need FF'ed Full
- .RD_FAST(1) // We need FF'ed Empty
- ) u_req_fifo(
- // Writc Clock
- .wr_clk (core_clk ),
- .wr_reset_n (core_rst_n ),
- .wr_en (req_fifo_wr ),
- .wr_data (req_fifo_din ),
- .full (req_fifo_full ),
- .afull ( ),
-
- // RD Clock
- .rd_clk (wb_clk ),
- .rd_reset_n (wb_rst_n ),
- .rd_en (req_fifo_rd ),
- .empty (req_fifo_empty ),
- .aempty ( ),
- .rd_data (req_fifo_dout )
- );
-
-
-always_comb begin
- req_fifo_rd = 1'b0;
- if (wbd_ack_i) begin
- req_fifo_rd = ~req_fifo_empty;
- end
-end
-
-assign wbd_stb_o = ~req_fifo_empty;
-// On Power, to avoid unknow propgating the value
-assign wbd_adr_o = (req_fifo_empty) ? 'h0 : req_fifo_dout.haddr;
-assign wbd_we_o = 0; // Only Read supported
-assign wbd_dat_o = 32'h0; // No Write
-assign wbd_sel_o = 4'b1111; // Only Read allowed in imem i/f
-//-------------------------------------------------------------------------------
-// Response path - Used by Read path logic
-//-------------------------------------------------------------------------------
-type_scr1_resp_fifo_s resp_fifo_din;
-type_scr1_resp_fifo_s resp_fifo_dout;
-
-assign resp_fifo_din.hresp = (wbd_err_i) ? 1'b0 : 1'b1;
-assign resp_fifo_din.hrdata = wbd_dat_i;
-
- async_fifo #(
- .W(SCR1_WB_WIDTH+1), // Data Width
- .DP(4), // FIFO DEPTH
- .WR_FAST(1), // We need FF'ed Full
- .RD_FAST(1) // We need FF'ed Empty
- ) u_res_fifo(
- // Writc Clock
- .wr_clk (wb_clk ),
- .wr_reset_n (wb_rst_n ),
- .wr_en (wbd_ack_i ),
- .wr_data (resp_fifo_din ),
- .full ( ), // Assmed FIFO will never be full as it's Response a Single Request
- .afull ( ),
-
- // RD Clock
- .rd_clk (core_clk ),
- .rd_reset_n (core_rst_n ),
- .rd_en (resp_fifo_rd ),
- .empty (resp_fifo_empty ),
- .aempty ( ),
- .rd_data (resp_fifo_dout )
- );
-
-
-assign resp_fifo_rd = !resp_fifo_empty;
-assign imem_rdata = resp_fifo_dout.hrdata;
-
-assign imem_resp = (resp_fifo_rd)
- ? (resp_fifo_dout.hresp == 1'b1)
- ? SCR1_MEM_RESP_RDY_OK
- : SCR1_MEM_RESP_RDY_ER
- : SCR1_MEM_RESP_NOTRDY ;
-
-
-`ifdef SCR1_TRGT_SIMULATION
-//-------------------------------------------------------------------------------
-// Assertion
-//-------------------------------------------------------------------------------
-
-// Check Core interface
-SCR1_SVA_IMEM_WB_BRIDGE_REQ_XCHECK : assert property (
- @(negedge core_clk) disable iff (~core_rst_n)
- !$isunknown(imem_req)
- ) else $error("IMEM WB bridge Error: imem_req has unknown values");
-
-SCR1_IMEM_WB_BRIDGE_ADDR_XCHECK : assert property (
- @(negedge core_clk) disable iff (~core_rst_n)
- imem_req |-> !$isunknown(imem_addr)
- ) else $error("IMEM WB bridge Error: imem_addr has unknown values");
-
-SCR1_IMEM_WB_BRIDGE_ADDR_ALLIGN : assert property (
- @(negedge core_clk) disable iff (~core_rst_n)
- imem_req |-> (imem_addr[1:0] == '0)
- ) else $error("IMEM WB bridge Error: imem_addr has unalign values");
-
-// Check WB interface
-SCR1_IMEM_WB_BRIDGE_HREADY_XCHECK : assert property (
- @(negedge core_clk) disable iff (~core_rst_n)
- !$isunknown(imem_req_ack)
- ) else $error("IMEM WB bridge Error: imem_req_ack has unknown values");
-
-SCR1_IMEM_WB_BRIDGE_HRESP_XCHECK : assert property (
- @(negedge core_clk) disable iff (~core_rst_n)
- !$isunknown(imem_resp)
- ) else $error("IMEM WB bridge Error: imem_resp has unknown values");
-
-`endif // SCR1_TRGT_SIMULATION
-
-endmodule : scr1_imem_wb
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_intf.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_intf.sv
deleted file mode 100644
index b1a5a05..0000000
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_intf.sv
+++ /dev/null
@@ -1,554 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: 2021, Dinesh Annayya
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
-// //////////////////////////////////////////////////////////////////////////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// syntacore interface block ////
-//// ////
-//// This file is part of the yifive cores project ////
-//// https://github.com/dineshannayya/yifive_r0.git ////
-//// http://www.opencores.org/cores/yifive/ ////
-//// ////
-//// Description: ////
-//// Holds interface block and timer & reset sync logic ////
-//// ////
-//// To Do: ////
-//// nothing ////
-//// ////
-//// Author(s): ////
-//// - Dinesh Annayya, dinesha@opencores.org ////
-//// ////
-//// Revision : ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-`include "scr1_arch_description.svh"
-`include "scr1_memif.svh"
-`include "scr1_wb.svh"
-`ifdef SCR1_IPIC_EN
-`include "scr1_ipic.svh"
-`endif // SCR1_IPIC_EN
-
-`ifdef SCR1_TCM_EN
- `define SCR1_IMEM_ROUTER_EN
-`endif // SCR1_TCM_EN
-
-module scr1_intf (
- // Control
- input logic pwrup_rst_n, // Power-Up Reset
- input logic rst_n, // Regular Reset signal
- input logic cpu_rst_n, // CPU Reset (Core Reset)
- input logic core_clk, // Core clock
- input logic rtc_clk, // Real-time clock
- output logic [63:0] riscv_debug,
-
-`ifdef SCR1_DBG_EN
- // -- JTAG I/F
- input logic trst_n,
-`endif // SCR1_DBG_EN
-
-`ifndef SCR1_TCM_MEM
- // SRAM-0 PORT-0
- output logic sram0_clk0,
- output logic sram0_csb0,
- output logic sram0_web0,
- output logic [8:0] sram0_addr0,
- output logic [3:0] sram0_wmask0,
- output logic [31:0] sram0_din0,
- input logic [31:0] sram0_dout0,
-
- // SRAM-0 PORT-1
- output logic sram0_clk1,
- output logic sram0_csb1,
- output logic [8:0] sram0_addr1,
- input logic [31:0] sram0_dout1,
-
- // SRAM-1 PORT-0
- output logic sram1_clk0,
- output logic sram1_csb0,
- output logic sram1_web0,
- output logic [8:0] sram1_addr0,
- output logic [3:0] sram1_wmask0,
- output logic [31:0] sram1_din0,
- input logic [31:0] sram1_dout0,
-
- // SRAM-1 PORT-1
- output logic sram1_clk1,
- output logic sram1_csb1,
- output logic [8:0] sram1_addr1,
- input logic [31:0] sram1_dout1,
-`endif
-
- input logic wb_rst_n, // Wish bone reset
- input logic wb_clk, // wish bone clock
- // Instruction Memory Interface
- output logic wbd_imem_stb_o, // strobe/request
- output logic [SCR1_WB_WIDTH-1:0] wbd_imem_adr_o, // address
- output logic wbd_imem_we_o, // write
- output logic [SCR1_WB_WIDTH-1:0] wbd_imem_dat_o, // data output
- output logic [3:0] wbd_imem_sel_o, // byte enable
- input logic [SCR1_WB_WIDTH-1:0] wbd_imem_dat_i, // data input
- input logic wbd_imem_ack_i, // acknowlegement
- input logic wbd_imem_err_i, // error
-
- // Data Memory Interface
- output logic wbd_dmem_stb_o, // strobe/request
- output logic [SCR1_WB_WIDTH-1:0] wbd_dmem_adr_o, // address
- output logic wbd_dmem_we_o, // write
- output logic [SCR1_WB_WIDTH-1:0] wbd_dmem_dat_o, // data output
- output logic [3:0] wbd_dmem_sel_o, // byte enable
- input logic [SCR1_WB_WIDTH-1:0] wbd_dmem_dat_i, // data input
- input logic wbd_dmem_ack_i, // acknowlegement
- input logic wbd_dmem_err_i, // error
-
- // Common
- output logic pwrup_rst_n_sync, // Power-Up reset
- output logic rst_n_sync, // Regular reset
- output logic cpu_rst_n_sync, // CPU reset
- output logic test_mode, // DFT Test Mode
- output logic test_rst_n, // DFT Test Reset
- input logic core_rst_n_local, // Core reset
- input logic [48:0] core_debug ,
-`ifdef SCR1_DBG_EN
- // Debug Interface
- output logic tapc_trst_n, // Test Reset (TRSTn)
-`endif
- // Memory-mapped external timer
- output logic [63:0] timer_val, // Machine timer value
- output logic timer_irq,
- // Instruction Memory Interface
- output logic core_imem_req_ack, // IMEM request acknowledge
- input logic core_imem_req, // IMEM request
- input logic core_imem_cmd, // IMEM command
- input logic [`SCR1_IMEM_AWIDTH-1:0] core_imem_addr, // IMEM address
- output logic [`SCR1_IMEM_DWIDTH-1:0] core_imem_rdata, // IMEM read data
- output logic [1:0] core_imem_resp, // IMEM response
-
- // Data Memory Interface
- output logic core_dmem_req_ack, // DMEM request acknowledge
- input logic core_dmem_req, // DMEM request
- input logic core_dmem_cmd, // DMEM command
- input logic[1:0] core_dmem_width, // DMEM data width
- input logic [`SCR1_DMEM_AWIDTH-1:0] core_dmem_addr, // DMEM address
- input logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_wdata, // DMEM write data
- output logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_rdata, // DMEM read data
- output logic [1:0] core_dmem_resp // DMEM response
-
-);
-//-------------------------------------------------------------------------------
-// Local parameters
-//-------------------------------------------------------------------------------
-localparam int unsigned SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM = 2;
-
-//-------------------------------------------------------------------------------
-// Local signal declaration
-//-------------------------------------------------------------------------------
-
-// Instruction memory interface from router to WB bridge
-logic wb_imem_req_ack;
-logic wb_imem_req;
-logic wb_imem_cmd;
-logic [`SCR1_IMEM_AWIDTH-1:0] wb_imem_addr;
-logic [`SCR1_IMEM_DWIDTH-1:0] wb_imem_rdata;
-logic [1:0] wb_imem_resp;
-
-// Data memory interface from router to WB bridge
-logic wb_dmem_req_ack;
-logic wb_dmem_req;
-logic wb_dmem_cmd;
-logic [1:0] wb_dmem_width;
-logic [`SCR1_DMEM_AWIDTH-1:0] wb_dmem_addr;
-logic [`SCR1_DMEM_DWIDTH-1:0] wb_dmem_wdata;
-logic [`SCR1_DMEM_DWIDTH-1:0] wb_dmem_rdata;
-logic [1:0] wb_dmem_resp;
-
-`ifdef SCR1_TCM_EN
-// Instruction memory interface from router to TCM
-logic tcm_imem_req_ack;
-logic tcm_imem_req;
-logic tcm_imem_cmd;
-logic [`SCR1_IMEM_AWIDTH-1:0] tcm_imem_addr;
-logic [`SCR1_IMEM_DWIDTH-1:0] tcm_imem_rdata;
-logic [1:0] tcm_imem_resp;
-
-// Data memory interface from router to TCM
-logic tcm_dmem_req_ack;
-logic tcm_dmem_req;
-logic tcm_dmem_cmd;
-logic [1:0] tcm_dmem_width;
-logic [`SCR1_DMEM_AWIDTH-1:0] tcm_dmem_addr;
-logic [`SCR1_DMEM_DWIDTH-1:0] tcm_dmem_wdata;
-logic [`SCR1_DMEM_DWIDTH-1:0] tcm_dmem_rdata;
-logic [1:0] tcm_dmem_resp;
-`endif // SCR1_TCM_EN
-
-// Data memory interface from router to memory-mapped timer
-logic timer_dmem_req_ack;
-logic timer_dmem_req;
-logic timer_dmem_cmd;
-logic [1:0] timer_dmem_width;
-logic [`SCR1_DMEM_AWIDTH-1:0] timer_dmem_addr;
-logic [`SCR1_DMEM_DWIDTH-1:0] timer_dmem_wdata;
-logic [`SCR1_DMEM_DWIDTH-1:0] timer_dmem_rdata;
-logic [1:0] timer_dmem_resp;
-
-
-
-//---------------------------------------------------------------------------------
-// To avoid core level power hook up, we have brought this signal inside, to
-// avoid any cell at digital core level
-// --------------------------------------------------------------------------------
-assign test_mode = 1'b0;
-assign test_rst_n = 1'b0;
-
-assign riscv_debug = {core_imem_req_ack,core_imem_req,core_imem_cmd,core_imem_resp[1:0],
- core_dmem_req_ack,core_dmem_req,core_dmem_cmd,core_dmem_resp[1:0],
- wb_imem_req,wb_dmem_req,wb_imem_cmd,wb_imem_resp[1:0], core_debug };
-//-------------------------------------------------------------------------------
-// Reset logic
-//-------------------------------------------------------------------------------
-// Power-Up Reset synchronizer
-scr1_reset_sync_cell #(
- .STAGES_AMOUNT (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
-) i_pwrup_rstn_reset_sync (
- .rst_n (pwrup_rst_n ),
- .clk (core_clk ),
- .test_rst_n (test_rst_n ),
- .test_mode (test_mode ),
- .rst_n_in (1'b1 ),
- .rst_n_out (pwrup_rst_n_sync)
-);
-
-// Regular Reset synchronizer
-scr1_reset_sync_cell #(
- .STAGES_AMOUNT (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
-) i_rstn_reset_sync (
- .rst_n (pwrup_rst_n ),
- .clk (core_clk ),
- .test_rst_n (test_rst_n ),
- .test_mode (test_mode ),
- .rst_n_in (rst_n ),
- .rst_n_out (rst_n_sync )
-);
-
-// CPU Reset synchronizer
-scr1_reset_sync_cell #(
- .STAGES_AMOUNT (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
-) i_cpu_rstn_reset_sync (
- .rst_n (pwrup_rst_n ),
- .clk (core_clk ),
- .test_rst_n (test_rst_n ),
- .test_mode (test_mode ),
- .rst_n_in (cpu_rst_n ),
- .rst_n_out (cpu_rst_n_sync )
-);
-
-`ifdef SCR1_DBG_EN
-// TAPC Reset
-scr1_reset_and2_cell i_tapc_rstn_and2_cell (
- .rst_n_in ({trst_n, pwrup_rst_n}),
- .test_rst_n (test_rst_n ),
- .test_mode (test_mode ),
- .rst_n_out (tapc_trst_n )
-);
-`endif // SCR1_DBG_EN
-
-`ifdef SCR1_TCM_EN
-//-------------------------------------------------------------------------------
-// TCM instance
-//-------------------------------------------------------------------------------
-scr1_tcm #(
- .SCR1_TCM_SIZE (`SCR1_DMEM_AWIDTH'(~SCR1_TCM_ADDR_MASK + 1'b1))
-) i_tcm (
- .clk (core_clk ),
- .rst_n (core_rst_n_local),
-
-`ifndef SCR1_TCM_MEM
- // SRAM-0 PORT-0
- .sram0_clk0 (sram0_clk0),
- .sram0_csb0 (sram0_csb0),
- .sram0_web0 (sram0_web0),
- .sram0_addr0 (sram0_addr0),
- .sram0_wmask0 (sram0_wmask0),
- .sram0_din0 (sram0_din0),
- .sram0_dout0 (sram0_dout0),
-
- // SRAM-0 PORT-1
- .sram0_clk1 (sram0_clk1),
- .sram0_csb1 (sram0_csb1),
- .sram0_addr1 (sram0_addr1),
- .sram0_dout1 (sram0_dout1),
-
- // SRAM-1 PORT-0
- .sram1_clk0 (sram1_clk0),
- .sram1_csb0 (sram1_csb0),
- .sram1_web0 (sram1_web0),
- .sram1_addr0 (sram1_addr0),
- .sram1_wmask0 (sram1_wmask0),
- .sram1_din0 (sram1_din0),
- .sram1_dout0 (sram1_dout0),
-
- // SRAM-1 PORT-1
- .sram1_clk1 (sram1_clk1),
- .sram1_csb1 (sram1_csb1),
- .sram1_addr1 (sram1_addr1),
- .sram1_dout1 (sram1_dout1),
-
-`endif
-
-
- // Instruction interface to TCM
- .imem_req_ack (tcm_imem_req_ack),
- .imem_req (tcm_imem_req ),
- .imem_addr (tcm_imem_addr ),
- .imem_rdata (tcm_imem_rdata ),
- .imem_resp (tcm_imem_resp ),
-
- // Data interface to TCM
- .dmem_req_ack (tcm_dmem_req_ack),
- .dmem_req (tcm_dmem_req ),
- .dmem_cmd (tcm_dmem_cmd ),
- .dmem_width (tcm_dmem_width ),
- .dmem_addr (tcm_dmem_addr ),
- .dmem_wdata (tcm_dmem_wdata ),
- .dmem_rdata (tcm_dmem_rdata ),
- .dmem_resp (tcm_dmem_resp )
-);
-`endif // SCR1_TCM_EN
-
-
-//-------------------------------------------------------------------------------
-// Memory-mapped timer instance
-//-------------------------------------------------------------------------------
-scr1_timer i_timer (
- // Common
- .rst_n (core_rst_n_local ),
- .clk (core_clk ),
- .rtc_clk (rtc_clk ),
-
- // Memory interface
- .dmem_req (timer_dmem_req ),
- .dmem_cmd (timer_dmem_cmd ),
- .dmem_width (timer_dmem_width ),
- .dmem_addr (timer_dmem_addr ),
- .dmem_wdata (timer_dmem_wdata ),
- .dmem_req_ack (timer_dmem_req_ack),
- .dmem_rdata (timer_dmem_rdata ),
- .dmem_resp (timer_dmem_resp ),
-
- // Timer interface
- .timer_val (timer_val ),
- .timer_irq (timer_irq )
-);
-
-
-`ifdef SCR1_IMEM_ROUTER_EN
-//-------------------------------------------------------------------------------
-// Instruction memory router
-//-------------------------------------------------------------------------------
-scr1_imem_router #(
- `ifdef SCR1_TCM_EN
- .SCR1_ADDR_MASK (SCR1_TCM_ADDR_MASK),
- .SCR1_ADDR_PATTERN (SCR1_TCM_ADDR_PATTERN)
- `endif // SCR1_TCM_EN
-) i_imem_router (
- .rst_n (core_rst_n_local ),
- .clk (core_clk ),
- // Interface to core
- .imem_req_ack (core_imem_req_ack),
- .imem_req (core_imem_req ),
- .imem_cmd (core_imem_cmd ),
- .imem_addr (core_imem_addr ),
- .imem_rdata (core_imem_rdata ),
- .imem_resp (core_imem_resp ),
- // Interface to WB bridge
- .port0_req_ack (wb_imem_req_ack ),
- .port0_req (wb_imem_req ),
- .port0_cmd (wb_imem_cmd ),
- .port0_addr (wb_imem_addr ),
- .port0_rdata (wb_imem_rdata ),
- .port0_resp (wb_imem_resp ),
- `ifdef SCR1_TCM_EN
- // Interface to TCM
- .port1_req_ack (tcm_imem_req_ack ),
- .port1_req (tcm_imem_req ),
- .port1_cmd (tcm_imem_cmd ),
- .port1_addr (tcm_imem_addr ),
- .port1_rdata (tcm_imem_rdata ),
- .port1_resp (tcm_imem_resp )
- `endif // SCR1_TCM_EN
-);
-
-`else // SCR1_IMEM_ROUTER_EN
-
-assign wb_imem_req = core_imem_req;
-assign wb_imem_cmd = core_imem_cmd;
-assign wb_imem_addr = core_imem_addr;
-assign core_imem_req_ack = wb_imem_req_ack;
-assign core_imem_resp = wb_imem_resp;
-assign core_imem_rdata = wb_imem_rdata;
-
-`endif // SCR1_IMEM_ROUTER_EN
-
-//-------------------------------------------------------------------------------
-// Data memory router
-//-------------------------------------------------------------------------------
-scr1_dmem_router #(
-
-`ifdef SCR1_TCM_EN
- .SCR1_PORT1_ADDR_MASK (SCR1_TCM_ADDR_MASK),
- .SCR1_PORT1_ADDR_PATTERN (SCR1_TCM_ADDR_PATTERN),
-`else // SCR1_TCM_EN
- .SCR1_PORT1_ADDR_MASK (32'h00000000),
- .SCR1_PORT1_ADDR_PATTERN (32'hFFFFFFFF),
-`endif // SCR1_TCM_EN
-
- .SCR1_PORT2_ADDR_MASK (SCR1_TIMER_ADDR_MASK),
- .SCR1_PORT2_ADDR_PATTERN (SCR1_TIMER_ADDR_PATTERN)
-
-) i_dmem_router (
- .rst_n (core_rst_n_local ),
- .clk (core_clk ),
- // Interface to core
- .dmem_req_ack (core_dmem_req_ack ),
- .dmem_req (core_dmem_req ),
- .dmem_cmd (core_dmem_cmd ),
- .dmem_width (core_dmem_width ),
- .dmem_addr (core_dmem_addr ),
- .dmem_wdata (core_dmem_wdata ),
- .dmem_rdata (core_dmem_rdata ),
- .dmem_resp (core_dmem_resp ),
-`ifdef SCR1_TCM_EN
- // Interface to TCM
- .port1_req_ack (tcm_dmem_req_ack ),
- .port1_req (tcm_dmem_req ),
- .port1_cmd (tcm_dmem_cmd ),
- .port1_width (tcm_dmem_width ),
- .port1_addr (tcm_dmem_addr ),
- .port1_wdata (tcm_dmem_wdata ),
- .port1_rdata (tcm_dmem_rdata ),
- .port1_resp (tcm_dmem_resp ),
-`else // SCR1_TCM_EN
- .port1_req_ack (1'b0),
- .port1_req ( ),
- .port1_cmd ( ),
- .port1_width ( ),
- .port1_addr ( ),
- .port1_wdata ( ),
- .port1_rdata (32'h0 ),
- .port1_resp (SCR1_MEM_RESP_RDY_ER),
-`endif // SCR1_TCM_EN
- // Interface to memory-mapped timer
- .port2_req_ack (timer_dmem_req_ack ),
- .port2_req (timer_dmem_req ),
- .port2_cmd (timer_dmem_cmd ),
- .port2_width (timer_dmem_width ),
- .port2_addr (timer_dmem_addr ),
- .port2_wdata (timer_dmem_wdata ),
- .port2_rdata (timer_dmem_rdata ),
- .port2_resp (timer_dmem_resp ),
- // Interface to WB bridge
- .port0_req_ack (wb_dmem_req_ack ),
- .port0_req (wb_dmem_req ),
- .port0_cmd (wb_dmem_cmd ),
- .port0_width (wb_dmem_width ),
- .port0_addr (wb_dmem_addr ),
- .port0_wdata (wb_dmem_wdata ),
- .port0_rdata (wb_dmem_rdata ),
- .port0_resp (wb_dmem_resp )
-);
-
-
-//-------------------------------------------------------------------------------
-// Instruction memory WB bridge
-//-------------------------------------------------------------------------------
-scr1_imem_wb i_imem_wb (
- .core_rst_n (core_rst_n_local ),
- .core_clk (core_clk ),
- // Interface to imem router
- .imem_req_ack (wb_imem_req_ack ),
- .imem_req (wb_imem_req ),
- .imem_addr (wb_imem_addr ),
- .imem_rdata (wb_imem_rdata ),
- .imem_resp (wb_imem_resp ),
- // WB interface
- .wb_rst_n (wb_rst_n ),
- .wb_clk (wb_clk ),
- .wbd_stb_o (wbd_imem_stb_o ),
- .wbd_adr_o (wbd_imem_adr_o ),
- .wbd_we_o (wbd_imem_we_o ),
- .wbd_dat_o (wbd_imem_dat_o ),
- .wbd_sel_o (wbd_imem_sel_o ),
- .wbd_dat_i (wbd_imem_dat_i ),
- .wbd_ack_i (wbd_imem_ack_i ),
- .wbd_err_i (wbd_imem_err_i )
-);
-
-
-//-------------------------------------------------------------------------------
-// Data memory WB bridge
-//-------------------------------------------------------------------------------
-scr1_dmem_wb i_dmem_wb (
- .core_rst_n (core_rst_n_local ),
- .core_clk (core_clk ),
- // Interface to dmem router
- .dmem_req_ack (wb_dmem_req_ack ),
- .dmem_req (wb_dmem_req ),
- .dmem_cmd (wb_dmem_cmd ),
- .dmem_width (wb_dmem_width ),
- .dmem_addr (wb_dmem_addr ),
- .dmem_wdata (wb_dmem_wdata ),
- .dmem_rdata (wb_dmem_rdata ),
- .dmem_resp (wb_dmem_resp ),
- // WB interface
- .wb_rst_n (wb_rst_n ),
- .wb_clk (wb_clk ),
- .wbd_stb_o (wbd_dmem_stb_o ),
- .wbd_adr_o (wbd_dmem_adr_o ),
- .wbd_we_o (wbd_dmem_we_o ),
- .wbd_dat_o (wbd_dmem_dat_o ),
- .wbd_sel_o (wbd_dmem_sel_o ),
- .wbd_dat_i (wbd_dmem_dat_i ),
- .wbd_ack_i (wbd_dmem_ack_i ),
- .wbd_err_i (wbd_dmem_err_i )
-);
-
-endmodule : scr1_intf
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_mem_axi.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_mem_axi.sv
deleted file mode 100644
index cad4658..0000000
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_mem_axi.sv
+++ /dev/null
@@ -1,404 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_mem_axi.sv>
-/// @brief Memory AXI bridge
-///
-
-`include "scr1_memif.svh"
-`include "scr1_arch_description.svh"
-
-module scr1_mem_axi
-#(
- parameter SCR1_REQ_BUF_SIZE = 2, // Power of 2 value
- parameter SCR1_AXI_IDWIDTH = 4,
- parameter SCR1_ADDR_WIDTH = 32,
- parameter SCR1_AXI_REQ_BP = 1,
- parameter SCR1_AXI_RESP_BP = 1
-)
-(
- // Clock and Reset
- input logic clk,
- input logic rst_n,
- input logic axi_reinit,
- // Core Interface
- output logic core_idle,
- output logic core_req_ack,
- input logic core_req,
- input logic core_cmd,
- input logic [1:0] core_width,
- input logic [SCR1_ADDR_WIDTH-1:0] core_addr,
- input logic [31:0] core_wdata,
- output logic [31:0] core_rdata,
- output logic [1:0] core_resp,
-
- // AXI
- output logic [SCR1_AXI_IDWIDTH-1:0] awid,
- output logic [SCR1_ADDR_WIDTH-1:0] awaddr,
- output logic [ 7:0] awlen,
- output logic [ 2:0] awsize,
- output logic [ 1:0] awburst,
- output logic awlock,
- output logic [ 3:0] awcache,
- output logic [ 2:0] awprot,
- output logic [ 3:0] awregion,
- output logic [ 3:0] awuser,
- output logic [ 3:0] awqos,
- output logic awvalid,
- input logic awready,
- output logic [31:0] wdata,
- output logic [3:0] wstrb,
- output logic wlast,
- output logic [3:0] wuser,
- output logic wvalid,
- input logic wready,
- input logic [SCR1_AXI_IDWIDTH-1:0] bid,
- input logic [ 1:0] bresp,
- input logic bvalid,
- input logic [ 3:0] buser,
- output logic bready,
- output logic [SCR1_AXI_IDWIDTH-1:0] arid,
- output logic [SCR1_ADDR_WIDTH-1:0] araddr,
- output logic [ 7:0] arlen,
- output logic [ 2:0] arsize,
- output logic [ 1:0] arburst,
- output logic arlock,
- output logic [ 3:0] arcache,
- output logic [ 2:0] arprot,
- output logic [ 3:0] arregion,
- output logic [ 3:0] aruser,
- output logic [ 3:0] arqos,
- output logic arvalid,
- input logic arready,
- input logic [SCR1_AXI_IDWIDTH-1:0] rid,
- input logic [31:0] rdata,
- input logic [ 1:0] rresp,
- input logic rlast,
- input logic [ 3:0] ruser,
- input logic rvalid,
- output logic rready
-);
-
-
-// Local functions
-function automatic logic [2:0] width2axsize (
- input logic [1:0] width );
- logic [2:0] axsize;
-begin
- case (width)
- SCR1_MEM_WIDTH_BYTE : axsize = 3'b000;
- SCR1_MEM_WIDTH_HWORD: axsize = 3'b001;
- SCR1_MEM_WIDTH_WORD : axsize = 3'b010;
- default: axsize = 'x;
- endcase
-
- width2axsize = axsize; // cp.11
-end
-endfunction
-
-typedef struct packed {
- logic [1:0] axi_width;
- logic [SCR1_ADDR_WIDTH-1:0] axi_addr;
- logic [31:0] axi_wdata;
-} type_scr1_request_s;
-
-typedef struct packed {
- logic req_write;
- logic req_addr;
- logic req_data;
- logic req_resp;
-} type_scr1_req_status_s;
-
-
-//type_scr1_request_s [SCR1_REQ_BUF_SIZE-1:0] req_fifo;
-logic [1:0] req_fifo_axi_width[SCR1_REQ_BUF_SIZE-1:0];
-logic [SCR1_ADDR_WIDTH-1:0] req_fifo_axi_addr [SCR1_REQ_BUF_SIZE-1:0];
-logic [31:0] req_fifo_axi_wdata [SCR1_REQ_BUF_SIZE-1:0];
-//type_scr1_req_status_s [SCR1_REQ_BUF_SIZE-1:0] req_status;
-logic [SCR1_REQ_BUF_SIZE-1:0] req_status_req_write ;
-logic [SCR1_REQ_BUF_SIZE-1:0] req_status_req_addr ;
-logic [SCR1_REQ_BUF_SIZE-1:0] req_status_req_data ;
-logic [SCR1_REQ_BUF_SIZE-1:0] req_status_req_resp ;
-//type_scr1_req_status_s [SCR1_REQ_BUF_SIZE-1:0] req_status_new;
-logic [SCR1_REQ_BUF_SIZE-1:0] req_status_new_req_write ;
-logic [SCR1_REQ_BUF_SIZE-1:0] req_status_new_req_addr ;
-logic [SCR1_REQ_BUF_SIZE-1:0] req_status_new_req_data ;
-logic [SCR1_REQ_BUF_SIZE-1:0] req_status_new_req_resp ;
-
-logic [SCR1_REQ_BUF_SIZE-1:0] req_status_en;
-logic [$clog2(SCR1_REQ_BUF_SIZE)-1:0] req_aval_ptr;
-logic [$clog2(SCR1_REQ_BUF_SIZE)-1:0] req_proc_ptr;
-logic [$clog2(SCR1_REQ_BUF_SIZE)-1:0] req_done_ptr;
-logic rresp_err;
-logic [31:0] rcvd_rdata;
-logic [1:0] rcvd_resp;
-logic force_read;
-logic force_write;
-
-
-
-assign core_req_ack = ~axi_reinit &
- ~req_status_req_resp[req_aval_ptr] &
- core_resp!=SCR1_MEM_RESP_RDY_ER;
-
-
-assign rready = ~req_status_req_write[req_done_ptr];
-assign bready = req_status_req_write[req_done_ptr];
-
-
-assign force_read = SCR1_AXI_REQ_BP & core_req & core_req_ack & req_aval_ptr==req_proc_ptr & core_cmd==SCR1_MEM_CMD_RD;
-assign force_write = SCR1_AXI_REQ_BP & core_req & core_req_ack & req_aval_ptr==req_proc_ptr & core_cmd==SCR1_MEM_CMD_WR;
-
-integer i;
-always_comb begin: idle_status
- core_idle = 1'b1;
- for (i=0; i<SCR1_REQ_BUF_SIZE; i=i+1) begin
- core_idle &= req_status_req_resp[i]==1'b0;
- end
-end
-
-always_ff @(posedge clk) begin
- if (core_req & core_req_ack) begin
- req_fifo_axi_width[req_aval_ptr] <= core_width;
- req_fifo_axi_addr[req_aval_ptr] <= core_addr;
- req_fifo_axi_wdata[req_aval_ptr] <= core_wdata;
- end
-end
-
-// Request Status Queue
-// It is used for holding control info of processing requests
-
-// Combinational logic of Request Status Queue
-always_comb begin
- // Default
- req_status_en = '0; // No update
- req_status_new_req_write = req_status_req_write; // Hold request info
- req_status_new_req_addr = req_status_req_addr; // Hold request info
- req_status_new_req_data = req_status_req_data; // Hold request info
- req_status_new_req_resp = req_status_req_resp; // Hold request info
-
- // Update status on new core request
- if( core_req & core_req_ack ) begin
- req_status_en[req_aval_ptr] = 1'd1;
-
- req_status_new_req_resp[req_aval_ptr] = 1'd1;
- req_status_new_req_write[req_aval_ptr] = core_cmd == SCR1_MEM_CMD_WR;
-
- req_status_new_req_addr[req_aval_ptr] = ~( (force_read & arready) |
- (force_write & awready) );
-
- req_status_new_req_data[req_aval_ptr] = ~( (force_write & wready & awlen == 8'd0) |
- (~force_write & core_cmd == SCR1_MEM_CMD_RD) );
- end
-
- // Update status on AXI address phase
- if ( (awvalid & awready) | (arvalid & arready) ) begin
- req_status_en[req_proc_ptr] = 1'd1;
- req_status_new_req_addr[req_proc_ptr] = 1'd0;
- end
-
- // Update status on AXI data phase
- if ( wvalid & wready & wlast ) begin
- req_status_en[req_proc_ptr] = 1'd1;
- req_status_new_req_data[req_proc_ptr] = 1'd0;
- end
-
- // Update status when AXI finish transaction
- if ( (bvalid & bready) | (rvalid & rready & rlast) ) begin
- req_status_en[req_done_ptr] = 1'd1;
- req_status_new_req_resp[req_done_ptr] = 1'd0;
- end
-end
-
-// Request Status Queue register
-integer j;
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- req_status_req_write <= '0;
- req_status_req_addr <= '0;
- req_status_req_data <= '0;
- req_status_req_resp <= '0;
- end else begin
- for (j = 0; j < SCR1_REQ_BUF_SIZE; j = j+1) begin // cp.4
- if ( req_status_en[j] ) begin
- req_status_req_write[j] <= req_status_new_req_write[j];
- req_status_req_addr[j] <= req_status_new_req_addr[j];
- req_status_req_data[j] <= req_status_new_req_data[j];
- req_status_req_resp[j] <= req_status_new_req_resp[j];
- end
- end
- end
-end
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) req_aval_ptr <= '0;
- else if (core_req & core_req_ack) req_aval_ptr <= req_aval_ptr + 1'b1;
-end
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- req_proc_ptr <= '0;
- end else begin
- if (( awvalid & awready & wvalid & wready & wlast) |
- (~force_write & ~req_status_req_data[req_proc_ptr] & awvalid & awready ) |
- (~force_write & ~req_status_req_addr[req_proc_ptr] & wvalid & wready & wlast) |
- ( ~req_status_req_data[req_proc_ptr] & arvalid & arready ) ) begin
-
- req_proc_ptr <= req_proc_ptr + 1'b1;
- end
- end
-end
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- req_done_ptr <= '0;
- end else begin
- if ((bvalid & bready | rvalid & rready & rlast) & req_status_req_resp[req_done_ptr]) begin
-
- req_done_ptr <= req_done_ptr + 1'b1;
- end
- end
-end
-
-
-
-assign arvalid = req_status_req_addr[req_proc_ptr] & ~req_status_req_write[req_proc_ptr] | force_read;
-assign awvalid = req_status_req_addr[req_proc_ptr] & req_status_req_write[req_proc_ptr] | force_write;
-assign wvalid = req_status_req_data[req_proc_ptr] & req_status_req_write[req_proc_ptr] | force_write;
-
-assign araddr = (~force_read )? req_fifo_axi_addr[req_proc_ptr] : core_addr;
-assign awaddr = (~force_write)? req_fifo_axi_addr[req_proc_ptr] : core_addr;
-
-always_comb begin
- if (bvalid & bready & req_status_req_resp[req_done_ptr]) begin
- rcvd_resp = (bresp==2'b00)? SCR1_MEM_RESP_RDY_OK :
- SCR1_MEM_RESP_RDY_ER;
- end else begin
- if (rvalid & rready & rlast & req_status_req_resp[req_done_ptr]) begin
- rcvd_resp = (rresp==2'b00)? SCR1_MEM_RESP_RDY_OK :
- SCR1_MEM_RESP_RDY_ER;
- end else begin
- rcvd_resp = SCR1_MEM_RESP_NOTRDY;
- end
- end
-end
-
-
-wire [SCR1_ADDR_WIDTH-1:0] CurAddr1 = req_fifo_axi_addr[req_proc_ptr];
-wire [1:0] bShift1 = CurAddr1[1:0];
-
-// Write data signals adaptation
-always_comb begin
- if (force_write)
- case (core_width)
- SCR1_MEM_WIDTH_BYTE : wstrb = 4'h1 << core_addr[1:0];
- SCR1_MEM_WIDTH_HWORD: wstrb = 4'h3 << core_addr[1:0];
- SCR1_MEM_WIDTH_WORD : wstrb = 4'hf << core_addr[1:0];
- default: wstrb = 'x;
- endcase
- else
- case (req_fifo_axi_width[req_proc_ptr])
- SCR1_MEM_WIDTH_BYTE : wstrb = 4'h1 << bShift1;
- SCR1_MEM_WIDTH_HWORD: wstrb = 4'h3 << bShift1;
- SCR1_MEM_WIDTH_WORD : wstrb = 4'hf << bShift1;
- default: wstrb = 'x;
- endcase
-end
-
-
-
-assign wdata = (force_write)? core_wdata << (8* core_addr[1:0]) :
- req_fifo_axi_wdata[req_proc_ptr] << (8* bShift1);
-
-wire [SCR1_ADDR_WIDTH-1:0] CurAddr2 = req_fifo_axi_addr[req_done_ptr];
-wire [1:0] bShift2 = CurAddr2[1:0];
-
-// Read data adaptation
-always_comb begin
- case (req_fifo_axi_width[req_done_ptr])
- SCR1_MEM_WIDTH_BYTE : rcvd_rdata = rdata >> (8*bShift2);
- SCR1_MEM_WIDTH_HWORD: rcvd_rdata = rdata >> (8*bShift2);
- SCR1_MEM_WIDTH_WORD : rcvd_rdata = rdata >> (8*bShift2);
- default: rcvd_rdata = 'x;
- endcase
-end
-
-
-generate
- if (SCR1_AXI_RESP_BP == 1) begin : axi_resp_bp
- assign core_rdata = (rvalid & rready & rlast) ? rcvd_rdata : '0;
- assign core_resp = (axi_reinit) ? SCR1_MEM_RESP_NOTRDY : rcvd_resp;
- end else begin : axi_resp_no_bp
- always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) core_resp <= SCR1_MEM_RESP_NOTRDY;
- else core_resp <= (axi_reinit) ? SCR1_MEM_RESP_NOTRDY : rcvd_resp;
- end
- always_ff @(posedge clk) begin
- if (rvalid & rready & rlast) core_rdata <= rcvd_rdata;
- end
- end
-endgenerate
-
-
-
-// AXI interface assignments
-assign awid = SCR1_AXI_IDWIDTH'(1);
-assign awlen = 8'd0;
-assign awsize = (force_write) ? width2axsize(core_width) : width2axsize(req_fifo_axi_width[req_proc_ptr]);
-assign awburst = 2'd1;
-assign awcache = 4'd2;
-assign awlock = '0;
-assign awprot = '0;
-assign awregion = '0;
-assign awuser = '0;
-assign awqos = '0;
-
-assign arid = SCR1_AXI_IDWIDTH'(0);
-assign arlen = 8'd0;
-assign arsize = (force_read) ? width2axsize(core_width) : width2axsize(req_fifo_axi_width[req_proc_ptr]);
-assign arburst = 2'd1;
-assign arcache = 4'd2;
-assign arprot = '0;
-assign arregion = '0;
-assign arlock = '0;
-assign arqos = '0;
-assign aruser = '0;
-
-assign wlast = 1'd1;
-assign wuser = '0;
-
-
-`ifdef SCR1_TRGT_SIMULATION
-//-------------------------------------------------------------------------------
-// Assertion
-//-------------------------------------------------------------------------------
-
-// X checks
-SCR1_SVA_AXI_X_CHECK0 : assert property (@(negedge clk) disable iff (~rst_n) !$isunknown({core_req, awready, wready, bvalid, arready, rvalid}) )
- else $error("AXI bridge: X state on input");
-SCR1_SVA_AXI_X_CHECK1 : assert property (@(negedge clk) disable iff (~rst_n) core_req |->
- !$isunknown({core_cmd, core_width, core_addr}) )
- else $error("AXI bridge: X state on input");
-SCR1_SVA_AXI_X_CHECK2 : assert property (@(negedge clk) disable iff (~rst_n) bvalid |->
- !$isunknown({bid, bresp}) )
- else $error("AXI bridge: X state on input");
-SCR1_SVA_AXI_X_CHECK3 : assert property (@(negedge clk) disable iff (~rst_n) rvalid |->
- !$isunknown({rid, rresp}) )
- else $error("AXI bridge: X state on input");
-`endif // SCR1_TRGT_SIMULATION
-
-endmodule : scr1_mem_axi
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv
deleted file mode 100644
index db8174e..0000000
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv
+++ /dev/null
@@ -1,212 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_tcm.sv>
-/// @brief Tightly-Coupled Memory (TCM)
-///
-
-`include "scr1_memif.svh"
-`include "scr1_arch_description.svh"
-
-`ifdef SCR1_TCM_EN
-module scr1_tcm
-#(
- parameter SCR1_TCM_SIZE = `SCR1_IMEM_AWIDTH'h00010000
-)
-(
- // Control signals
- input logic clk,
- input logic rst_n,
-
-`ifndef SCR1_TCM_MEM
- // SRAM0 PORT-0
- output logic sram0_clk0,
- output logic sram0_csb0,
- output logic sram0_web0,
- output logic [8:0] sram0_addr0,
- output logic [3:0] sram0_wmask0,
- output logic [31:0] sram0_din0,
- input logic [31:0] sram0_dout0,
-
- // SRAM-0 PORT-1
- output logic sram0_clk1,
- output logic sram0_csb1,
- output logic [8:0] sram0_addr1,
- input logic [31:0] sram0_dout1,
-
- // SRAM1 PORT-0
- output logic sram1_clk0,
- output logic sram1_csb0,
- output logic sram1_web0,
- output logic [8:0] sram1_addr0,
- output logic [3:0] sram1_wmask0,
- output logic [31:0] sram1_din0,
- input logic [31:0] sram1_dout0,
-
- // SRAM-1 PORT-1
- output logic sram1_clk1,
- output logic sram1_csb1,
- output logic [8:0] sram1_addr1,
- input logic [31:0] sram1_dout1,
-
-`endif
-
- // Core instruction interface
- output logic imem_req_ack,
- input logic imem_req,
- input logic [`SCR1_IMEM_AWIDTH-1:0] imem_addr,
- output logic [`SCR1_IMEM_DWIDTH-1:0] imem_rdata,
- output logic [1:0] imem_resp,
-
- // Core data interface
- output logic dmem_req_ack,
- input logic dmem_req,
- input logic dmem_cmd,
- input logic [1:0] dmem_width,
- input logic [`SCR1_DMEM_AWIDTH-1:0] dmem_addr,
- input logic [`SCR1_DMEM_DWIDTH-1:0] dmem_wdata,
- output logic [`SCR1_DMEM_DWIDTH-1:0] dmem_rdata,
- output logic [1:0] dmem_resp
-);
-
-//-------------------------------------------------------------------------------
-// Local signal declaration
-//-------------------------------------------------------------------------------
-logic imem_req_en;
-logic dmem_req_en;
-logic imem_rd;
-logic dmem_rd;
-logic dmem_wr;
-logic [`SCR1_DMEM_DWIDTH-1:0] dmem_writedata;
-logic [`SCR1_DMEM_DWIDTH-1:0] dmem_rdata_local;
-logic [3:0] dmem_byteen;
-logic [1:0] dmem_rdata_shift_reg;
-//-------------------------------------------------------------------------------
-// Core interface
-//-------------------------------------------------------------------------------
-assign imem_req_en = (imem_resp == SCR1_MEM_RESP_RDY_OK) ^ imem_req;
-assign dmem_req_en = (dmem_resp == SCR1_MEM_RESP_RDY_OK) ^ dmem_req;
-
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- imem_resp <= SCR1_MEM_RESP_NOTRDY;
- end else if (imem_req_en) begin
- imem_resp <= imem_req ? SCR1_MEM_RESP_RDY_OK : SCR1_MEM_RESP_NOTRDY;
- end
-end
-
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- dmem_resp <= SCR1_MEM_RESP_NOTRDY;
- end else if (dmem_req_en) begin
- dmem_resp <= dmem_req ? SCR1_MEM_RESP_RDY_OK : SCR1_MEM_RESP_NOTRDY;
- end
-end
-
-assign imem_req_ack = 1'b1;
-assign dmem_req_ack = 1'b1;
-//-------------------------------------------------------------------------------
-// Memory data composing
-//-------------------------------------------------------------------------------
-`ifndef SCR1_TCM_MEM
-// connect the TCM memory to SRAM-0
-assign sram0_clk1 = clk;
-assign sram0_csb1 =!(imem_req & imem_addr[11] == 1'b0);
-assign sram0_addr1 = imem_addr[10:2];
-
-// connect the TCM memory to SRAM-1
-assign sram1_clk1 = clk;
-assign sram1_csb1 =!(imem_req & imem_addr[11] == 1'b1);
-assign sram1_addr1 = imem_addr[10:2];
-
-// IMEM Read Data Selection Based on Address bit[11]
-assign imem_rdata = (imem_addr[11] == 1'b0) ? sram0_dout1: sram1_dout1;
-
-// SRAM-0 Port 0 Control Generation
-assign sram0_clk0 = clk;
-assign sram0_csb0 = !(dmem_req & (dmem_addr[11] == 1'b0) & ((dmem_cmd == SCR1_MEM_CMD_RD) | (dmem_cmd == SCR1_MEM_CMD_WR)));
-assign sram0_web0 = !(dmem_req & (dmem_cmd == SCR1_MEM_CMD_WR));
-assign sram0_addr0 = dmem_addr[10:2];
-assign sram0_wmask0 = dmem_byteen;
-assign sram0_din0 = dmem_writedata;
-
-// SRAM-1 Port 0 Control Generation
-assign sram1_clk0 = clk;
-assign sram1_csb0 = !(dmem_req & (dmem_addr[11] == 1'b1) & ((dmem_cmd == SCR1_MEM_CMD_RD) | (dmem_cmd == SCR1_MEM_CMD_WR)));
-assign sram1_web0 = !(dmem_req & (dmem_cmd == SCR1_MEM_CMD_WR));
-assign sram1_addr0 = dmem_addr[10:2];
-assign sram1_wmask0 = dmem_byteen;
-assign sram1_din0 = dmem_writedata;
-
-
-// DMEM Read Data Selection Based on Address bit[11]
-assign dmem_rdata_local = (dmem_addr[11] == 1'b0) ? sram0_dout0: sram1_dout0;
-
-`endif
-
-//------------------------------
-always_comb begin
- dmem_writedata = dmem_wdata;
- dmem_byteen = 4'b1111;
- case ( dmem_width )
- SCR1_MEM_WIDTH_BYTE : begin
- dmem_writedata = {(`SCR1_DMEM_DWIDTH / 8){dmem_wdata[7:0]}};
- dmem_byteen = 4'b0001 << dmem_addr[1:0];
- end
- SCR1_MEM_WIDTH_HWORD : begin
- dmem_writedata = {(`SCR1_DMEM_DWIDTH / 16){dmem_wdata[15:0]}};
- dmem_byteen = 4'b0011 << {dmem_addr[1], 1'b0};
- end
- default : begin
- end
- endcase
-end
-//-------------------------------------------------------------------------------
-// Memory instantiation
-//-------------------------------------------------------------------------------
-`ifdef SCR1_TCM_MEM
-scr1_dp_memory #(
- .SCR1_WIDTH ( 32 ),
- .SCR1_SIZE ( SCR1_TCM_SIZE )
-) i_dp_memory (
- .clk ( clk ),
- // Instruction port
- // Port A
- .rena ( imem_rd ),
- .addra ( imem_addr[$clog2(SCR1_TCM_SIZE)-1:2] ),
- .qa ( imem_rdata ),
- // Data port
- // Port B
- .renb ( dmem_rd ),
- .wenb ( dmem_wr ),
- .webb ( dmem_byteen ),
- .addrb ( dmem_addr[$clog2(SCR1_TCM_SIZE)-1:2] ),
- .qb ( dmem_rdata_local ),
- .datab ( dmem_writedata )
-);
-`endif
-
-//-------------------------------------------------------------------------------
-// Data memory output generation
-//-------------------------------------------------------------------------------
-
-assign dmem_rdata_shift_reg = dmem_addr[1:0];
-assign dmem_rdata = dmem_rdata_local >> ( 8 * dmem_rdata_shift_reg );
-
-endmodule : scr1_tcm
-
-`endif // SCR1_TCM_EN
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_timer.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_timer.sv
deleted file mode 100644
index 63d5d7c..0000000
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_timer.sv
+++ /dev/null
@@ -1,301 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_timer.sv>
-/// @brief Memory-mapped Timer
-/// Version 1.0 - 18 - July 2021 - Dinesh A Project: yifive
-/// 1.To break the timing path, input and output path are registered
-/// 2.Spilt the 64 bit adder into two 32 bit adder with taking care of
-/// overflow
-////////////////////////////////////////////////////////////////////////////////
-
-`include "scr1_arch_description.svh"
-`include "scr1_memif.svh"
-
-module scr1_timer (
- // Common
- input logic rst_n,
- input logic clk,
- input logic rtc_clk,
-
- // Memory interface
- input logic dmem_req,
- input logic dmem_cmd,
- input logic [1:0] dmem_width,
- input logic [`SCR1_DMEM_AWIDTH-1:0] dmem_addr,
- input logic [`SCR1_DMEM_DWIDTH-1:0] dmem_wdata,
- output logic dmem_req_ack,
- output logic [`SCR1_DMEM_DWIDTH-1:0] dmem_rdata,
- output logic [1:0] dmem_resp,
-
- // Timer interface
- output logic [63:0] timer_val,
- output logic timer_irq
-);
-
-//-------------------------------------------------------------------------------
-// Local parameters declaration
-//-------------------------------------------------------------------------------
-localparam int unsigned SCR1_TIMER_ADDR_WIDTH = 5;
-localparam logic [SCR1_TIMER_ADDR_WIDTH-1:0] SCR1_TIMER_CONTROL = 5'h0;
-localparam logic [SCR1_TIMER_ADDR_WIDTH-1:0] SCR1_TIMER_DIVIDER = 5'h4;
-localparam logic [SCR1_TIMER_ADDR_WIDTH-1:0] SCR1_TIMER_MTIMELO = 5'h8;
-localparam logic [SCR1_TIMER_ADDR_WIDTH-1:0] SCR1_TIMER_MTIMEHI = 5'hC;
-localparam logic [SCR1_TIMER_ADDR_WIDTH-1:0] SCR1_TIMER_MTIMECMPLO = 5'h10;
-localparam logic [SCR1_TIMER_ADDR_WIDTH-1:0] SCR1_TIMER_MTIMECMPHI = 5'h14;
-
-localparam int unsigned SCR1_TIMER_CONTROL_EN_OFFSET = 0;
-localparam int unsigned SCR1_TIMER_CONTROL_CLKSRC_OFFSET = 1;
-localparam int unsigned SCR1_TIMER_DIVIDER_WIDTH = 10;
-
-//-------------------------------------------------------------------------------
-// Local signals declaration
-//-------------------------------------------------------------------------------
-logic [63:0] mtime_reg;
-logic mtime_32b_ovr; // Indicate 32b Ovr flow
-logic [63:0] mtime_new;
-logic [63:0] mtimecmp_reg;
-logic [63:0] mtimecmp_new;
-logic timer_en;
-logic timer_clksrc_rtc;
-logic [SCR1_TIMER_DIVIDER_WIDTH-1:0] timer_div;
-
-logic control_up;
-logic divider_up;
-logic mtimelo_up;
-logic mtimehi_up;
-logic mtimecmplo_up;
-logic mtimecmphi_up;
-
-logic dmem_req_valid;
-
-logic [3:0] rtc_sync;
-logic rtc_ext_pulse;
-logic [SCR1_TIMER_DIVIDER_WIDTH-1:0] timeclk_cnt;
-logic timeclk_cnt_en;
-logic time_posedge;
-logic time_cmp_flag;
-
-//-------------------------------------------------------------------------------
-// Registers
-//-------------------------------------------------------------------------------
-
-// CONTROL
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- timer_en <= 1'b1;
- timer_clksrc_rtc <= 1'b0;
- end else begin
- if (control_up) begin
- timer_en <= dmem_wdata[SCR1_TIMER_CONTROL_EN_OFFSET];
- timer_clksrc_rtc <= dmem_wdata[SCR1_TIMER_CONTROL_CLKSRC_OFFSET];
- end
- end
-end
-
-// DIVIDER
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- timer_div <= '0;
- end else begin
- if (divider_up) begin
- timer_div <= dmem_wdata[SCR1_TIMER_DIVIDER_WIDTH-1:0];
- end
- end
-end
-
-// MTIME
-assign time_posedge = (timeclk_cnt_en & (timeclk_cnt == 0));
-
-always_comb begin
- mtime_new = mtime_reg;
- if (time_posedge) begin
- mtime_new[31:0] = mtime_reg[31:0] + 1'b1;
- mtime_new[63:32] = mtime_32b_ovr ? (mtime_new[63:32] + 1'b1) : mtime_new[63:32];
- end else if (mtimelo_up) begin
- mtime_new[31:0] = dmem_wdata;
- end else if (mtimehi_up) begin
- mtime_new[63:32] = dmem_wdata;
- end
-end
-
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- mtime_reg <= '0;
- mtime_32b_ovr <= '0;
- end else begin
- if (time_posedge | mtimelo_up | mtimehi_up) begin
- mtime_reg <= mtime_new;
- mtime_32b_ovr <= &mtime_new; // Indicate 32B Overflow in next increment by check all one
- end
- end
-end
-
-// MTIMECMP
-always_comb begin
- mtimecmp_new = mtimecmp_reg;
- if (mtimecmplo_up) begin
- mtimecmp_new[31:0] = dmem_wdata;
- end
- if (mtimecmphi_up) begin
- mtimecmp_new[63:32] = dmem_wdata;
- end
-end
-
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- mtimecmp_reg <= '0;
- end else begin
- if (mtimecmplo_up | mtimecmphi_up) begin
- mtimecmp_reg <= mtimecmp_new;
- end
- end
-end
-
-//-------------------------------------------------------------------------------
-// Interrupt pending
-//-------------------------------------------------------------------------------
-assign time_cmp_flag = (mtime_reg >= ((mtimecmplo_up | mtimecmphi_up) ? mtimecmp_new : mtimecmp_reg));
-
-always_ff @(posedge clk, negedge rst_n) begin
- if (~rst_n) begin
- timer_irq <= 1'b0;
- end else begin
- if (~timer_irq) begin
- timer_irq <= time_cmp_flag;
- end else begin // 1'b1
- if (mtimecmplo_up | mtimecmphi_up) begin
- timer_irq <= time_cmp_flag;
- end
- end
- end
-end
-
-//-------------------------------------------------------------------------------
-// Timer divider
-//-------------------------------------------------------------------------------
-assign timeclk_cnt_en = (~timer_clksrc_rtc ? 1'b1 : rtc_ext_pulse) & timer_en;
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- timeclk_cnt <= '0;
- end else begin
- case (1'b1)
- divider_up : timeclk_cnt <= dmem_wdata[SCR1_TIMER_DIVIDER_WIDTH-1:0];
- time_posedge : timeclk_cnt <= timer_div;
- timeclk_cnt_en : timeclk_cnt <= timeclk_cnt - 1'b1;
- default : begin end
- endcase
- end
-end
-
-//-------------------------------------------------------------------------------
-// RTC synchronization
-//-------------------------------------------------------------------------------
-assign rtc_ext_pulse = rtc_sync[3] ^ rtc_sync[2];
-
-always_ff @(negedge rst_n, posedge rtc_clk) begin
- if (~rst_n) begin
- rtc_sync[0] <= 1'b0;
- end else begin
- if (timer_clksrc_rtc) begin
- rtc_sync[0] <= ~rtc_sync[0];
- end
- end
-end
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- rtc_sync[3:1] <= '0;
- end else begin
- if (timer_clksrc_rtc) begin
- rtc_sync[3:1] <= rtc_sync[2:0];
- end
- end
-end
-
-//-------------------------------------------------------------------------------
-// Memory interface
-//-------------------------------------------------------------------------------
-logic dmem_cmd_ff;
-logic [SCR1_TIMER_ADDR_WIDTH-1:0] dmem_addr_ff;
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- dmem_req_valid <= '0;
- dmem_req_ack <= '0;
- dmem_cmd_ff <= '0;
- dmem_addr_ff <= '0;
- end else begin
- dmem_req_valid <= (dmem_req) && (dmem_req_ack == 0) && (dmem_width == SCR1_MEM_WIDTH_WORD) & (~|dmem_addr[1:0]) &
- (dmem_addr[SCR1_TIMER_ADDR_WIDTH-1:2] <= SCR1_TIMER_MTIMECMPHI[SCR1_TIMER_ADDR_WIDTH-1:2]);
- dmem_req_ack <= dmem_req & (dmem_req_ack ==0);
- dmem_cmd_ff <= dmem_cmd;
- dmem_addr_ff <= dmem_addr[SCR1_TIMER_ADDR_WIDTH-1:0];
- end
-end
-
-always_ff @(negedge rst_n, posedge clk) begin
- if (~rst_n) begin
- dmem_resp <= SCR1_MEM_RESP_NOTRDY;
- dmem_rdata <= '0;
- end else begin
- if (dmem_req_valid) begin
- dmem_resp <= SCR1_MEM_RESP_RDY_OK;
- if (dmem_cmd_ff == SCR1_MEM_CMD_RD) begin
- case (dmem_addr_ff)
- SCR1_TIMER_CONTROL : dmem_rdata <= `SCR1_DMEM_DWIDTH'({timer_clksrc_rtc, timer_en});
- SCR1_TIMER_DIVIDER : dmem_rdata <= `SCR1_DMEM_DWIDTH'(timer_div);
- SCR1_TIMER_MTIMELO : dmem_rdata <= mtime_reg[31:0];
- SCR1_TIMER_MTIMEHI : dmem_rdata <= mtime_reg[63:32];
- SCR1_TIMER_MTIMECMPLO : dmem_rdata <= mtimecmp_reg[31:0];
- SCR1_TIMER_MTIMECMPHI : dmem_rdata <= mtimecmp_reg[63:32];
- default : begin end
- endcase
- end
- end else begin
- dmem_resp <= SCR1_MEM_RESP_NOTRDY;
- dmem_rdata <= '0;
- end
- end
-end
-
-always_comb begin
- control_up = 1'b0;
- divider_up = 1'b0;
- mtimelo_up = 1'b0;
- mtimehi_up = 1'b0;
- mtimecmplo_up = 1'b0;
- mtimecmphi_up = 1'b0;
- if (dmem_req_valid & (dmem_cmd_ff == SCR1_MEM_CMD_WR)) begin
- case (dmem_addr_ff)
- SCR1_TIMER_CONTROL : control_up = 1'b1;
- SCR1_TIMER_DIVIDER : divider_up = 1'b1;
- SCR1_TIMER_MTIMELO : mtimelo_up = 1'b1;
- SCR1_TIMER_MTIMEHI : mtimehi_up = 1'b1;
- SCR1_TIMER_MTIMECMPLO : mtimecmplo_up = 1'b1;
- SCR1_TIMER_MTIMECMPHI : mtimecmphi_up = 1'b1;
- default : begin end
- endcase
- end
-end
-
-//-------------------------------------------------------------------------------
-// Timer interface
-//-------------------------------------------------------------------------------
-assign timer_val = mtime_reg;
-
-endmodule : scr1_timer
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_top_ahb.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_top_ahb.sv
deleted file mode 100644
index 7856118..0000000
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_top_ahb.sv
+++ /dev/null
@@ -1,529 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_top_ahb.sv>
-/// @brief SCR1 AHB top
-///
-
-`include "scr1_arch_description.svh"
-`include "scr1_memif.svh"
-`include "scr1_ahb.svh"
-`ifdef SCR1_IPIC_EN
-`include "scr1_ipic.svh"
-`endif // SCR1_IPIC_EN
-
-`ifdef SCR1_TCM_EN
- `define SCR1_IMEM_ROUTER_EN
-`endif // SCR1_TCM_EN
-
-module scr1_top_ahb (
- // Control
- input logic pwrup_rst_n, // Power-Up Reset
- input logic rst_n, // Regular Reset signal
- input logic cpu_rst_n, // CPU Reset (Core Reset)
- input logic test_mode, // Test mode
- input logic test_rst_n, // Test mode's reset
- input logic clk, // System clock
- input logic rtc_clk, // Real-time clock
-`ifdef SCR1_DBG_EN
- output logic sys_rst_n_o, // External System Reset output
- // (for the processor cluster's components or
- // external SOC (could be useful in small
- // SCR-core-centric SOCs))
- output logic sys_rdc_qlfy_o, // System-to-External SOC Reset Domain Crossing Qualifier
-`endif // SCR1_DBG_EN
-
- // Fuses
- input logic [`SCR1_XLEN-1:0] fuse_mhartid, // Hart ID
-`ifdef SCR1_DBG_EN
- input logic [31:0] fuse_idcode, // TAPC IDCODE
-`endif // SCR1_DBG_EN
-
- // IRQ
-`ifdef SCR1_IPIC_EN
- input logic [SCR1_IRQ_LINES_NUM-1:0] irq_lines, // IRQ lines to IPIC
-`else // SCR1_IPIC_EN
- input logic ext_irq, // External IRQ input
-`endif // SCR1_IPIC_EN
- input logic soft_irq, // Software IRQ input
-
-`ifdef SCR1_DBG_EN
- // -- JTAG I/F
- input logic trst_n,
- input logic tck,
- input logic tms,
- input logic tdi,
- output logic tdo,
- output logic tdo_en,
-`endif // SCR1_DBG_EN
-
- // Instruction Memory Interface
- output logic [3:0] imem_hprot,
- output logic [2:0] imem_hburst,
- output logic [2:0] imem_hsize,
- output logic [1:0] imem_htrans,
- output logic imem_hmastlock,
- output logic [SCR1_AHB_WIDTH-1:0] imem_haddr,
- input logic imem_hready,
- input logic [SCR1_AHB_WIDTH-1:0] imem_hrdata,
- input logic imem_hresp,
-
- // Data Memory Interface
- output logic [3:0] dmem_hprot,
- output logic [2:0] dmem_hburst,
- output logic [2:0] dmem_hsize,
- output logic [1:0] dmem_htrans,
- output logic dmem_hmastlock,
- output logic [SCR1_AHB_WIDTH-1:0] dmem_haddr,
- output logic dmem_hwrite,
- output logic [SCR1_AHB_WIDTH-1:0] dmem_hwdata,
- input logic dmem_hready,
- input logic [SCR1_AHB_WIDTH-1:0] dmem_hrdata,
- input logic dmem_hresp
-);
-
-//-------------------------------------------------------------------------------
-// Local parameters
-//-------------------------------------------------------------------------------
-localparam int unsigned SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM = 2;
-
-//-------------------------------------------------------------------------------
-// Local signal declaration
-//-------------------------------------------------------------------------------
-// Reset logic
-logic pwrup_rst_n_sync;
-logic rst_n_sync;
-logic cpu_rst_n_sync;
-logic core_rst_n_local;
-`ifdef SCR1_DBG_EN
-logic tapc_trst_n;
-`endif // SCR1_DBG_EN
-
-// Instruction memory interface from core to router
-logic core_imem_req_ack;
-logic core_imem_req;
-logic core_imem_cmd;
-logic [`SCR1_IMEM_AWIDTH-1:0] core_imem_addr;
-logic [`SCR1_IMEM_DWIDTH-1:0] core_imem_rdata;
-logic [1:0] core_imem_resp;
-
-// Data memory interface from core to router
-logic core_dmem_req_ack;
-logic core_dmem_req;
-logic core_dmem_cmd;
-logic [1:0] core_dmem_width;
-logic [`SCR1_DMEM_AWIDTH-1:0] core_dmem_addr;
-logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_wdata;
-logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_rdata;
-logic [1:0] core_dmem_resp;
-
-// Instruction memory interface from router to AHB bridge
-logic ahb_imem_req_ack;
-logic ahb_imem_req;
-logic ahb_imem_cmd;
-logic [`SCR1_IMEM_AWIDTH-1:0] ahb_imem_addr;
-logic [`SCR1_IMEM_DWIDTH-1:0] ahb_imem_rdata;
-logic [1:0] ahb_imem_resp;
-
-// Data memory interface from router to AHB bridge
-logic ahb_dmem_req_ack;
-logic ahb_dmem_req;
-logic ahb_dmem_cmd;
-logic [1:0] ahb_dmem_width;
-logic [`SCR1_DMEM_AWIDTH-1:0] ahb_dmem_addr;
-logic [`SCR1_DMEM_DWIDTH-1:0] ahb_dmem_wdata;
-logic [`SCR1_DMEM_DWIDTH-1:0] ahb_dmem_rdata;
-logic [1:0] ahb_dmem_resp;
-
-`ifdef SCR1_TCM_EN
-// Instruction memory interface from router to TCM
-logic tcm_imem_req_ack;
-logic tcm_imem_req;
-logic tcm_imem_cmd;
-logic [`SCR1_IMEM_AWIDTH-1:0] tcm_imem_addr;
-logic [`SCR1_IMEM_DWIDTH-1:0] tcm_imem_rdata;
-logic [1:0] tcm_imem_resp;
-
-// Data memory interface from router to TCM
-logic tcm_dmem_req_ack;
-logic tcm_dmem_req;
-logic tcm_dmem_cmd;
-logic [1:0] tcm_dmem_width;
-logic [`SCR1_DMEM_AWIDTH-1:0] tcm_dmem_addr;
-logic [`SCR1_DMEM_DWIDTH-1:0] tcm_dmem_wdata;
-logic [`SCR1_DMEM_DWIDTH-1:0] tcm_dmem_rdata;
-logic [1:0] tcm_dmem_resp;
-`endif // SCR1_TCM_EN
-
-// Data memory interface from router to memory-mapped timer
-logic timer_dmem_req_ack;
-logic timer_dmem_req;
-logic timer_dmem_cmd;
-logic [1:0] timer_dmem_width;
-logic [`SCR1_DMEM_AWIDTH-1:0] timer_dmem_addr;
-logic [`SCR1_DMEM_DWIDTH-1:0] timer_dmem_wdata;
-logic [`SCR1_DMEM_DWIDTH-1:0] timer_dmem_rdata;
-logic [1:0] timer_dmem_resp;
-
-logic timer_irq;
-logic [63:0] timer_val;
-
-
-//-------------------------------------------------------------------------------
-// Reset logic
-//-------------------------------------------------------------------------------
-// Power-Up Reset synchronizer
-scr1_reset_sync_cell #(
- .STAGES_AMOUNT (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
-) i_pwrup_rstn_reset_sync (
- .rst_n (pwrup_rst_n ),
- .clk (clk ),
- .test_rst_n (test_rst_n ),
- .test_mode (test_mode ),
- .rst_n_in (1'b1 ),
- .rst_n_out (pwrup_rst_n_sync)
-);
-
-// Regular Reset synchronizer
-scr1_reset_sync_cell #(
- .STAGES_AMOUNT (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
-) i_rstn_reset_sync (
- .rst_n (pwrup_rst_n ),
- .clk (clk ),
- .test_rst_n (test_rst_n ),
- .test_mode (test_mode ),
- .rst_n_in (rst_n ),
- .rst_n_out (rst_n_sync )
-);
-
-// CPU Reset synchronizer
-scr1_reset_sync_cell #(
- .STAGES_AMOUNT (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
-) i_cpu_rstn_reset_sync (
- .rst_n (pwrup_rst_n ),
- .clk (clk ),
- .test_rst_n (test_rst_n ),
- .test_mode (test_mode ),
- .rst_n_in (cpu_rst_n ),
- .rst_n_out (cpu_rst_n_sync )
-);
-
-`ifdef SCR1_DBG_EN
-// TAPC Reset
-scr1_reset_and2_cell i_tapc_rstn_and2_cell (
- .rst_n_in ({trst_n, pwrup_rst_n}),
- .test_rst_n (test_rst_n ),
- .test_mode (test_mode ),
- .rst_n_out (tapc_trst_n )
-);
-`endif // SCR1_DBG_EN
-
-//-------------------------------------------------------------------------------
-// SCR1 core instance
-//-------------------------------------------------------------------------------
-scr1_core_top i_core_top (
- // Common
- .pwrup_rst_n (pwrup_rst_n_sync ),
- .rst_n (rst_n_sync ),
- .cpu_rst_n (cpu_rst_n_sync ),
- .test_mode (test_mode ),
- .test_rst_n (test_rst_n ),
- .clk (clk ),
- .core_rst_n_o (core_rst_n_local ),
- .core_rdc_qlfy_o ( ),
-`ifdef SCR1_DBG_EN
- .sys_rst_n_o (sys_rst_n_o ),
- .sys_rdc_qlfy_o (sys_rdc_qlfy_o ),
-`endif // SCR1_DBG_EN
-
- // Fuses
- .core_fuse_mhartid_i (fuse_mhartid ),
-`ifdef SCR1_DBG_EN
- .tapc_fuse_idcode_i (fuse_idcode ),
-`endif // SCR1_DBG_EN
-
- // IRQ
-`ifdef SCR1_IPIC_EN
- .core_irq_lines_i (irq_lines ),
-`else // SCR1_IPIC_EN
- .core_irq_ext_i (ext_irq ),
-`endif // SCR1_IPIC_EN
- .core_irq_soft_i (soft_irq ),
- .core_irq_mtimer_i (timer_irq ),
-
- // Memory-mapped external timer
- .core_mtimer_val_i (timer_val ),
-
-`ifdef SCR1_DBG_EN
- // Debug interface
- .tapc_trst_n (tapc_trst_n ),
- .tapc_tck (tck ),
- .tapc_tms (tms ),
- .tapc_tdi (tdi ),
- .tapc_tdo (tdo ),
- .tapc_tdo_en (tdo_en ),
-`endif // SCR1_DBG_EN
-
- // Instruction memory interface
- .imem2core_req_ack_i (core_imem_req_ack),
- .core2imem_req_o (core_imem_req ),
- .core2imem_cmd_o (core_imem_cmd ),
- .core2imem_addr_o (core_imem_addr ),
- .imem2core_rdata_i (core_imem_rdata ),
- .imem2core_resp_i (core_imem_resp ),
-
- // Data memory interface
- .dmem2core_req_ack_i (core_dmem_req_ack),
- .core2dmem_req_o (core_dmem_req ),
- .core2dmem_cmd_o (core_dmem_cmd ),
- .core2dmem_width_o (core_dmem_width ),
- .core2dmem_addr_o (core_dmem_addr ),
- .core2dmem_wdata_o (core_dmem_wdata ),
- .dmem2core_rdata_i (core_dmem_rdata ),
- .dmem2core_resp_i (core_dmem_resp )
-);
-
-
-`ifdef SCR1_TCM_EN
-//-------------------------------------------------------------------------------
-// TCM instance
-//-------------------------------------------------------------------------------
-scr1_tcm #(
- .SCR1_TCM_SIZE (`SCR1_DMEM_AWIDTH'(~SCR1_TCM_ADDR_MASK + 1'b1))
-) i_tcm (
- .clk (clk ),
- .rst_n (core_rst_n_local),
-
- // Instruction interface to TCM
- .imem_req_ack (tcm_imem_req_ack),
- .imem_req (tcm_imem_req ),
- .imem_addr (tcm_imem_addr ),
- .imem_rdata (tcm_imem_rdata ),
- .imem_resp (tcm_imem_resp ),
-
- // Data interface to TCM
- .dmem_req_ack (tcm_dmem_req_ack),
- .dmem_req (tcm_dmem_req ),
- .dmem_cmd (tcm_dmem_cmd ),
- .dmem_width (tcm_dmem_width ),
- .dmem_addr (tcm_dmem_addr ),
- .dmem_wdata (tcm_dmem_wdata ),
- .dmem_rdata (tcm_dmem_rdata ),
- .dmem_resp (tcm_dmem_resp )
-);
-`endif // SCR1_TCM_EN
-
-
-//-------------------------------------------------------------------------------
-// Memory-mapped timer instance
-//-------------------------------------------------------------------------------
-scr1_timer i_timer (
- // Common
- .rst_n (core_rst_n_local ),
- .clk (clk ),
- .rtc_clk (rtc_clk ),
-
- // Memory interface
- .dmem_req (timer_dmem_req ),
- .dmem_cmd (timer_dmem_cmd ),
- .dmem_width (timer_dmem_width ),
- .dmem_addr (timer_dmem_addr ),
- .dmem_wdata (timer_dmem_wdata ),
- .dmem_req_ack (timer_dmem_req_ack),
- .dmem_rdata (timer_dmem_rdata ),
- .dmem_resp (timer_dmem_resp ),
-
- // Timer interface
- .timer_val (timer_val ),
- .timer_irq (timer_irq )
-);
-
-
-`ifdef SCR1_IMEM_ROUTER_EN
-//-------------------------------------------------------------------------------
-// Instruction memory router
-//-------------------------------------------------------------------------------
-scr1_imem_router #(
- `ifdef SCR1_TCM_EN
- .SCR1_ADDR_MASK (SCR1_TCM_ADDR_MASK),
- .SCR1_ADDR_PATTERN (SCR1_TCM_ADDR_PATTERN)
- `endif // SCR1_TCM_EN
-) i_imem_router (
- .rst_n (core_rst_n_local ),
- .clk (clk ),
- // Interface to core
- .imem_req_ack (core_imem_req_ack),
- .imem_req (core_imem_req ),
- .imem_cmd (core_imem_cmd ),
- .imem_addr (core_imem_addr ),
- .imem_rdata (core_imem_rdata ),
- .imem_resp (core_imem_resp ),
- // Interface to AHB bridge
- .port0_req_ack (ahb_imem_req_ack ),
- .port0_req (ahb_imem_req ),
- .port0_cmd (ahb_imem_cmd ),
- .port0_addr (ahb_imem_addr ),
- .port0_rdata (ahb_imem_rdata ),
- .port0_resp (ahb_imem_resp ),
- `ifdef SCR1_TCM_EN
- // Interface to TCM
- .port1_req_ack (tcm_imem_req_ack ),
- .port1_req (tcm_imem_req ),
- .port1_cmd (tcm_imem_cmd ),
- .port1_addr (tcm_imem_addr ),
- .port1_rdata (tcm_imem_rdata ),
- .port1_resp (tcm_imem_resp )
- `endif // SCR1_TCM_EN
-);
-
-`else // SCR1_IMEM_ROUTER_EN
-
-assign ahb_imem_req = core_imem_req;
-assign ahb_imem_cmd = core_imem_cmd;
-assign ahb_imem_addr = core_imem_addr;
-assign core_imem_req_ack = ahb_imem_req_ack;
-assign core_imem_resp = ahb_imem_resp;
-assign core_imem_rdata = ahb_imem_rdata;
-
-`endif // SCR1_IMEM_ROUTER_EN
-
-//-------------------------------------------------------------------------------
-// Data memory router
-//-------------------------------------------------------------------------------
-scr1_dmem_router #(
-
-`ifdef SCR1_TCM_EN
- .SCR1_PORT1_ADDR_MASK (SCR1_TCM_ADDR_MASK),
- .SCR1_PORT1_ADDR_PATTERN (SCR1_TCM_ADDR_PATTERN),
-`else // SCR1_TCM_EN
- .SCR1_PORT1_ADDR_MASK (32'h00000000),
- .SCR1_PORT1_ADDR_PATTERN (32'hFFFFFFFF),
-`endif // SCR1_TCM_EN
-
- .SCR1_PORT2_ADDR_MASK (SCR1_TIMER_ADDR_MASK),
- .SCR1_PORT2_ADDR_PATTERN (SCR1_TIMER_ADDR_PATTERN)
-
-) i_dmem_router (
- .rst_n (core_rst_n_local ),
- .clk (clk ),
- // Interface to core
- .dmem_req_ack (core_dmem_req_ack ),
- .dmem_req (core_dmem_req ),
- .dmem_cmd (core_dmem_cmd ),
- .dmem_width (core_dmem_width ),
- .dmem_addr (core_dmem_addr ),
- .dmem_wdata (core_dmem_wdata ),
- .dmem_rdata (core_dmem_rdata ),
- .dmem_resp (core_dmem_resp ),
-`ifdef SCR1_TCM_EN
- // Interface to TCM
- .port1_req_ack (tcm_dmem_req_ack ),
- .port1_req (tcm_dmem_req ),
- .port1_cmd (tcm_dmem_cmd ),
- .port1_width (tcm_dmem_width ),
- .port1_addr (tcm_dmem_addr ),
- .port1_wdata (tcm_dmem_wdata ),
- .port1_rdata (tcm_dmem_rdata ),
- .port1_resp (tcm_dmem_resp ),
-`else // SCR1_TCM_EN
- .port1_req_ack (1'b0),
- .port1_req ( ),
- .port1_cmd ( ),
- .port1_width ( ),
- .port1_addr ( ),
- .port1_wdata ( ),
- .port1_rdata ('0 ),
- .port1_resp (SCR1_MEM_RESP_RDY_ER),
-`endif // SCR1_TCM_EN
- // Interface to memory-mapped timer
- .port2_req_ack (timer_dmem_req_ack ),
- .port2_req (timer_dmem_req ),
- .port2_cmd (timer_dmem_cmd ),
- .port2_width (timer_dmem_width ),
- .port2_addr (timer_dmem_addr ),
- .port2_wdata (timer_dmem_wdata ),
- .port2_rdata (timer_dmem_rdata ),
- .port2_resp (timer_dmem_resp ),
- // Interface to AHB bridge
- .port0_req_ack (ahb_dmem_req_ack ),
- .port0_req (ahb_dmem_req ),
- .port0_cmd (ahb_dmem_cmd ),
- .port0_width (ahb_dmem_width ),
- .port0_addr (ahb_dmem_addr ),
- .port0_wdata (ahb_dmem_wdata ),
- .port0_rdata (ahb_dmem_rdata ),
- .port0_resp (ahb_dmem_resp )
-);
-
-
-//-------------------------------------------------------------------------------
-// Instruction memory AHB bridge
-//-------------------------------------------------------------------------------
-scr1_imem_ahb i_imem_ahb (
- .rst_n (core_rst_n_local ),
- .clk (clk ),
- // Interface to imem router
- .imem_req_ack (ahb_imem_req_ack ),
- .imem_req (ahb_imem_req ),
- .imem_addr (ahb_imem_addr ),
- .imem_rdata (ahb_imem_rdata ),
- .imem_resp (ahb_imem_resp ),
- // AHB interface
- .hprot (imem_hprot ),
- .hburst (imem_hburst ),
- .hsize (imem_hsize ),
- .htrans (imem_htrans ),
- .hmastlock (imem_hmastlock ),
- .haddr (imem_haddr ),
- .hready (imem_hready ),
- .hrdata (imem_hrdata ),
- .hresp (imem_hresp )
-);
-
-
-//-------------------------------------------------------------------------------
-// Data memory AHB bridge
-//-------------------------------------------------------------------------------
-scr1_dmem_ahb i_dmem_ahb (
- .rst_n (core_rst_n_local ),
- .clk (clk ),
- // Interface to dmem router
- .dmem_req_ack (ahb_dmem_req_ack ),
- .dmem_req (ahb_dmem_req ),
- .dmem_cmd (ahb_dmem_cmd ),
- .dmem_width (ahb_dmem_width ),
- .dmem_addr (ahb_dmem_addr ),
- .dmem_wdata (ahb_dmem_wdata ),
- .dmem_rdata (ahb_dmem_rdata ),
- .dmem_resp (ahb_dmem_resp ),
- // AHB interface
- .hprot (dmem_hprot ),
- .hburst (dmem_hburst ),
- .hsize (dmem_hsize ),
- .htrans (dmem_htrans ),
- .hmastlock (dmem_hmastlock ),
- .haddr (dmem_haddr ),
- .hwrite (dmem_hwrite ),
- .hwdata (dmem_hwdata ),
- .hready (dmem_hready ),
- .hrdata (dmem_hrdata ),
- .hresp (dmem_hresp )
-);
-
-endmodule : scr1_top_ahb
-
-
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_top_axi.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_top_axi.sv
deleted file mode 100644
index f7e4962..0000000
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_top_axi.sv
+++ /dev/null
@@ -1,717 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Syntacore LLC
-// //////////////////////////////////////////////////////////////////////////
-/// @file <scr1_top_axi.sv>
-/// @brief SCR1 AXI top
-///
-
-`include "scr1_arch_description.svh"
-`include "scr1_memif.svh"
-`ifdef SCR1_IPIC_EN
-`include "scr1_ipic.svh"
-`endif // SCR1_IPIC_EN
-
-`ifdef SCR1_TCM_EN
- `define SCR1_IMEM_ROUTER_EN
-`endif // SCR1_TCM_EN
-
-module scr1_top_axi (
- // Control
- input logic pwrup_rst_n, // Power-Up Reset
- input logic rst_n, // Regular Reset signal
- input logic cpu_rst_n, // CPU Reset (Core Reset)
- input logic test_mode, // Test mode
- input logic test_rst_n, // Test mode's reset
- input logic clk, // System clock
- input logic rtc_clk, // Real-time clock
-`ifdef SCR1_DBG_EN
- output logic sys_rst_n_o, // External System Reset output
- // (for the processor cluster's components or
- // external SOC (could be useful in small
- // SCR-core-centric SOCs))
- output logic sys_rdc_qlfy_o, // System-to-External SOC Reset Domain Crossing Qualifier
-`endif // SCR1_DBG_EN
-
- // Fuses
- input logic [`SCR1_XLEN-1:0] fuse_mhartid, // Hart ID
-`ifdef SCR1_DBG_EN
- input logic [31:0] fuse_idcode, // TAPC IDCODE
-`endif // SCR1_DBG_EN
-
- // IRQ
-`ifdef SCR1_IPIC_EN
- input logic [SCR1_IRQ_LINES_NUM-1:0] irq_lines, // IRQ lines to IPIC
-`else // SCR1_IPIC_EN
- input logic ext_irq, // External IRQ input
-`endif // SCR1_IPIC_EN
- input logic soft_irq, // Software IRQ input
-
-`ifdef SCR1_DBG_EN
- // -- JTAG I/F
- input logic trst_n,
- input logic tck,
- input logic tms,
- input logic tdi,
- output logic tdo,
- output logic tdo_en,
-`endif // SCR1_DBG_EN
-
- // Instruction Memory Interface
- output logic [3:0] io_axi_imem_awid,
- output logic [31:0] io_axi_imem_awaddr,
- output logic [7:0] io_axi_imem_awlen,
- output logic [2:0] io_axi_imem_awsize,
- output logic [1:0] io_axi_imem_awburst,
- output logic io_axi_imem_awlock,
- output logic [3:0] io_axi_imem_awcache,
- output logic [2:0] io_axi_imem_awprot,
- output logic [3:0] io_axi_imem_awregion,
- output logic [3:0] io_axi_imem_awuser,
- output logic [3:0] io_axi_imem_awqos,
- output logic io_axi_imem_awvalid,
- input logic io_axi_imem_awready,
- output logic [31:0] io_axi_imem_wdata,
- output logic [3:0] io_axi_imem_wstrb,
- output logic io_axi_imem_wlast,
- output logic [3:0] io_axi_imem_wuser,
- output logic io_axi_imem_wvalid,
- input logic io_axi_imem_wready,
- input logic [3:0] io_axi_imem_bid,
- input logic [1:0] io_axi_imem_bresp,
- input logic io_axi_imem_bvalid,
- input logic [3:0] io_axi_imem_buser,
- output logic io_axi_imem_bready,
- output logic [3:0] io_axi_imem_arid,
- output logic [31:0] io_axi_imem_araddr,
- output logic [7:0] io_axi_imem_arlen,
- output logic [2:0] io_axi_imem_arsize,
- output logic [1:0] io_axi_imem_arburst,
- output logic io_axi_imem_arlock,
- output logic [3:0] io_axi_imem_arcache,
- output logic [2:0] io_axi_imem_arprot,
- output logic [3:0] io_axi_imem_arregion,
- output logic [3:0] io_axi_imem_aruser,
- output logic [3:0] io_axi_imem_arqos,
- output logic io_axi_imem_arvalid,
- input logic io_axi_imem_arready,
- input logic [3:0] io_axi_imem_rid,
- input logic [31:0] io_axi_imem_rdata,
- input logic [1:0] io_axi_imem_rresp,
- input logic io_axi_imem_rlast,
- input logic [3:0] io_axi_imem_ruser,
- input logic io_axi_imem_rvalid,
- output logic io_axi_imem_rready,
-
- // Data Memory Interface
- output logic [3:0] io_axi_dmem_awid,
- output logic [31:0] io_axi_dmem_awaddr,
- output logic [7:0] io_axi_dmem_awlen,
- output logic [2:0] io_axi_dmem_awsize,
- output logic [1:0] io_axi_dmem_awburst,
- output logic io_axi_dmem_awlock,
- output logic [3:0] io_axi_dmem_awcache,
- output logic [2:0] io_axi_dmem_awprot,
- output logic [3:0] io_axi_dmem_awregion,
- output logic [3:0] io_axi_dmem_awuser,
- output logic [3:0] io_axi_dmem_awqos,
- output logic io_axi_dmem_awvalid,
- input logic io_axi_dmem_awready,
- output logic [31:0] io_axi_dmem_wdata,
- output logic [3:0] io_axi_dmem_wstrb,
- output logic io_axi_dmem_wlast,
- output logic [3:0] io_axi_dmem_wuser,
- output logic io_axi_dmem_wvalid,
- input logic io_axi_dmem_wready,
- input logic [3:0] io_axi_dmem_bid,
- input logic [1:0] io_axi_dmem_bresp,
- input logic io_axi_dmem_bvalid,
- input logic [3:0] io_axi_dmem_buser,
- output logic io_axi_dmem_bready,
- output logic [3:0] io_axi_dmem_arid,
- output logic [31:0] io_axi_dmem_araddr,
- output logic [7:0] io_axi_dmem_arlen,
- output logic [2:0] io_axi_dmem_arsize,
- output logic [1:0] io_axi_dmem_arburst,
- output logic io_axi_dmem_arlock,
- output logic [3:0] io_axi_dmem_arcache,
- output logic [2:0] io_axi_dmem_arprot,
- output logic [3:0] io_axi_dmem_arregion,
- output logic [3:0] io_axi_dmem_aruser,
- output logic [3:0] io_axi_dmem_arqos,
- output logic io_axi_dmem_arvalid,
- input logic io_axi_dmem_arready,
- input logic [3:0] io_axi_dmem_rid,
- input logic [31:0] io_axi_dmem_rdata,
- input logic [1:0] io_axi_dmem_rresp,
- input logic io_axi_dmem_rlast,
- input logic [3:0] io_axi_dmem_ruser,
- input logic io_axi_dmem_rvalid,
- output logic io_axi_dmem_rready
-);
-
-//-------------------------------------------------------------------------------
-// Local parameters
-//-------------------------------------------------------------------------------
-localparam int unsigned SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM = 2;
-
-//-------------------------------------------------------------------------------
-// Local signal declaration
-//-------------------------------------------------------------------------------
-// Reset logic
-logic pwrup_rst_n_sync;
-logic rst_n_sync;
-logic cpu_rst_n_sync;
-logic core_rst_n_local;
-logic axi_rst_n;
-`ifdef SCR1_DBG_EN
-logic tapc_trst_n;
-`endif // SCR1_DBG_EN
-
-// Instruction memory interface from core to router
-logic core_imem_req_ack;
-logic core_imem_req;
-logic core_imem_cmd;
-logic [`SCR1_IMEM_AWIDTH-1:0] core_imem_addr;
-logic [`SCR1_IMEM_DWIDTH-1:0] core_imem_rdata;
-logic [1:0] core_imem_resp;
-
-// Data memory interface from core to router
-logic core_dmem_req_ack;
-logic core_dmem_req;
-logic core_dmem_cmd;
-logic [1:0] core_dmem_width;
-logic [`SCR1_DMEM_AWIDTH-1:0] core_dmem_addr;
-logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_wdata;
-logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_rdata;
-logic [1:0] core_dmem_resp;
-
-// Instruction memory interface from router to AXI bridge
-logic axi_imem_req_ack;
-logic axi_imem_req;
-logic axi_imem_cmd;
-logic [`SCR1_IMEM_AWIDTH-1:0] axi_imem_addr;
-logic [`SCR1_IMEM_DWIDTH-1:0] axi_imem_rdata;
-logic [1:0] axi_imem_resp;
-
-// Data memory interface from router to AXI bridge
-logic axi_dmem_req_ack;
-logic axi_dmem_req;
-logic axi_dmem_cmd;
-logic [1:0] axi_dmem_width;
-logic [`SCR1_DMEM_AWIDTH-1:0] axi_dmem_addr;
-logic [`SCR1_DMEM_DWIDTH-1:0] axi_dmem_wdata;
-logic [`SCR1_DMEM_DWIDTH-1:0] axi_dmem_rdata;
-logic [1:0] axi_dmem_resp;
-
-`ifdef SCR1_TCM_EN
-// Instruction memory interface from router to TCM
-logic tcm_imem_req_ack;
-logic tcm_imem_req;
-logic tcm_imem_cmd;
-logic [`SCR1_IMEM_AWIDTH-1:0] tcm_imem_addr;
-logic [`SCR1_IMEM_DWIDTH-1:0] tcm_imem_rdata;
-logic [1:0] tcm_imem_resp;
-
-// Data memory interface from router to TCM
-logic tcm_dmem_req_ack;
-logic tcm_dmem_req;
-logic tcm_dmem_cmd;
-logic [1:0] tcm_dmem_width;
-logic [`SCR1_DMEM_AWIDTH-1:0] tcm_dmem_addr;
-logic [`SCR1_DMEM_DWIDTH-1:0] tcm_dmem_wdata;
-logic [`SCR1_DMEM_DWIDTH-1:0] tcm_dmem_rdata;
-logic [1:0] tcm_dmem_resp;
-`endif // SCR1_TCM_EN
-
-// Data memory interface from router to memory-mapped timer
-logic timer_dmem_req_ack;
-logic timer_dmem_req;
-logic timer_dmem_cmd;
-logic [1:0] timer_dmem_width;
-logic [`SCR1_DMEM_AWIDTH-1:0] timer_dmem_addr;
-logic [`SCR1_DMEM_DWIDTH-1:0] timer_dmem_wdata;
-logic [`SCR1_DMEM_DWIDTH-1:0] timer_dmem_rdata;
-logic [1:0] timer_dmem_resp;
-
-// Misc
-logic timer_irq;
-logic [63:0] timer_val;
-logic axi_reinit;
-logic axi_imem_idle;
-logic axi_dmem_idle;
-
-//-------------------------------------------------------------------------------
-// Reset logic
-//-------------------------------------------------------------------------------
-// Power-Up Reset synchronizer
-scr1_reset_sync_cell #(
- .STAGES_AMOUNT (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
-) i_pwrup_rstn_reset_sync (
- .rst_n (pwrup_rst_n ),
- .clk (clk ),
- .test_rst_n (test_rst_n ),
- .test_mode (test_mode ),
- .rst_n_in (1'b1 ),
- .rst_n_out (pwrup_rst_n_sync)
-);
-
-// Regular Reset synchronizer
-scr1_reset_sync_cell #(
- .STAGES_AMOUNT (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
-) i_rstn_reset_sync (
- .rst_n (pwrup_rst_n ),
- .clk (clk ),
- .test_rst_n (test_rst_n ),
- .test_mode (test_mode ),
- .rst_n_in (rst_n ),
- .rst_n_out (rst_n_sync )
-);
-
-// CPU Reset synchronizer
-scr1_reset_sync_cell #(
- .STAGES_AMOUNT (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
-) i_cpu_rstn_reset_sync (
- .rst_n (pwrup_rst_n ),
- .clk (clk ),
- .test_rst_n (test_rst_n ),
- .test_mode (test_mode ),
- .rst_n_in (cpu_rst_n ),
- .rst_n_out (cpu_rst_n_sync )
-);
-
-`ifdef SCR1_DBG_EN
-// TAPC Reset
-scr1_reset_and2_cell i_tapc_rstn_and2_cell (
- .rst_n_in ({trst_n, pwrup_rst_n}),
- .test_rst_n (test_rst_n ),
- .test_mode (test_mode ),
- .rst_n_out (tapc_trst_n )
-);
-`endif // SCR1_DBG_EN
-
-`ifdef SCR1_DBG_EN
-assign axi_rst_n = sys_rst_n_o;
-`else // SCR1_DBG_EN
-assign axi_rst_n = rst_n_sync;
-`endif // SCR1_DBG_EN
-
-//-------------------------------------------------------------------------------
-// SCR1 core instance
-//-------------------------------------------------------------------------------
-scr1_core_top i_core_top (
- // Common
- .pwrup_rst_n (pwrup_rst_n_sync ),
- .rst_n (rst_n_sync ),
- .cpu_rst_n (cpu_rst_n_sync ),
- .test_mode (test_mode ),
- .test_rst_n (test_rst_n ),
- .clk (clk ),
- .core_rst_n_o (core_rst_n_local ),
- .core_rdc_qlfy_o ( ),
-`ifdef SCR1_DBG_EN
- .sys_rst_n_o (sys_rst_n_o ),
- .sys_rdc_qlfy_o (sys_rdc_qlfy_o ),
-`endif // SCR1_DBG_EN
-
- // Fuses
- .core_fuse_mhartid_i (fuse_mhartid ),
-`ifdef SCR1_DBG_EN
- .tapc_fuse_idcode_i (fuse_idcode ),
-`endif // SCR1_DBG_EN
-
- // IRQ
-`ifdef SCR1_IPIC_EN
- .core_irq_lines_i (irq_lines ),
-`else // SCR1_IPIC_EN
- .core_irq_ext_i (ext_irq ),
-`endif // SCR1_IPIC_EN
- .core_irq_soft_i (soft_irq ),
- .core_irq_mtimer_i (timer_irq ),
-
- // Memory-mapped external timer
- .core_mtimer_val_i (timer_val ),
-
-`ifdef SCR1_DBG_EN
- // Debug interface
- .tapc_trst_n (tapc_trst_n ),
- .tapc_tck (tck ),
- .tapc_tms (tms ),
- .tapc_tdi (tdi ),
- .tapc_tdo (tdo ),
- .tapc_tdo_en (tdo_en ),
-`endif // SCR1_DBG_EN
-
- // Instruction memory interface
- .imem2core_req_ack_i (core_imem_req_ack),
- .core2imem_req_o (core_imem_req ),
- .core2imem_cmd_o (core_imem_cmd ),
- .core2imem_addr_o (core_imem_addr ),
- .imem2core_rdata_i (core_imem_rdata ),
- .imem2core_resp_i (core_imem_resp ),
-
- // Data memory interface
- .dmem2core_req_ack_i (core_dmem_req_ack),
- .core2dmem_req_o (core_dmem_req ),
- .core2dmem_cmd_o (core_dmem_cmd ),
- .core2dmem_width_o (core_dmem_width ),
- .core2dmem_addr_o (core_dmem_addr ),
- .core2dmem_wdata_o (core_dmem_wdata ),
- .dmem2core_rdata_i (core_dmem_rdata ),
- .dmem2core_resp_i (core_dmem_resp )
-);
-
-
-`ifdef SCR1_TCM_EN
-//-------------------------------------------------------------------------------
-// TCM instance
-//-------------------------------------------------------------------------------
-scr1_tcm #(
- .SCR1_TCM_SIZE (`SCR1_DMEM_AWIDTH'(~SCR1_TCM_ADDR_MASK + 1'b1))
-) i_tcm (
- .clk (clk ),
- .rst_n (core_rst_n_local),
-
- // Instruction interface to TCM
- .imem_req_ack (tcm_imem_req_ack),
- .imem_req (tcm_imem_req ),
- .imem_addr (tcm_imem_addr ),
- .imem_rdata (tcm_imem_rdata ),
- .imem_resp (tcm_imem_resp ),
-
- // Data interface to TCM
- .dmem_req_ack (tcm_dmem_req_ack),
- .dmem_req (tcm_dmem_req ),
- .dmem_cmd (tcm_dmem_cmd ),
- .dmem_width (tcm_dmem_width ),
- .dmem_addr (tcm_dmem_addr ),
- .dmem_wdata (tcm_dmem_wdata ),
- .dmem_rdata (tcm_dmem_rdata ),
- .dmem_resp (tcm_dmem_resp )
-);
-`endif // SCR1_TCM_EN
-
-
-//-------------------------------------------------------------------------------
-// Memory-mapped timer instance
-//-------------------------------------------------------------------------------
-scr1_timer i_timer (
- // Common
- .rst_n (core_rst_n_local ),
- .clk (clk ),
- .rtc_clk (rtc_clk ),
-
- // Memory interface
- .dmem_req (timer_dmem_req ),
- .dmem_cmd (timer_dmem_cmd ),
- .dmem_width (timer_dmem_width ),
- .dmem_addr (timer_dmem_addr ),
- .dmem_wdata (timer_dmem_wdata ),
- .dmem_req_ack (timer_dmem_req_ack),
- .dmem_rdata (timer_dmem_rdata ),
- .dmem_resp (timer_dmem_resp ),
-
- // Timer interface
- .timer_val (timer_val ),
- .timer_irq (timer_irq )
-);
-
-
-`ifdef SCR1_IMEM_ROUTER_EN
-//-------------------------------------------------------------------------------
-// Instruction memory router
-//-------------------------------------------------------------------------------
-scr1_imem_router #(
- .SCR1_ADDR_MASK (SCR1_TCM_ADDR_MASK),
- .SCR1_ADDR_PATTERN (SCR1_TCM_ADDR_PATTERN)
-) i_imem_router (
- .rst_n (core_rst_n_local ),
- .clk (clk ),
-
- // Interface to core
- .imem_req_ack (core_imem_req_ack),
- .imem_req (core_imem_req ),
- .imem_cmd (core_imem_cmd ),
- .imem_addr (core_imem_addr ),
- .imem_rdata (core_imem_rdata ),
- .imem_resp (core_imem_resp ),
-
- // Interface to AXI bridge
- .port0_req_ack (axi_imem_req_ack ),
- .port0_req (axi_imem_req ),
- .port0_cmd (axi_imem_cmd ),
- .port0_addr (axi_imem_addr ),
- .port0_rdata (axi_imem_rdata ),
- .port0_resp (axi_imem_resp ),
-
- // Interface to TCM
- .port1_req_ack (tcm_imem_req_ack ),
- .port1_req (tcm_imem_req ),
- .port1_cmd (tcm_imem_cmd ),
- .port1_addr (tcm_imem_addr ),
- .port1_rdata (tcm_imem_rdata ),
- .port1_resp (tcm_imem_resp )
-);
-
-`else // SCR1_IMEM_ROUTER_EN
-
-assign axi_imem_req = core_imem_req;
-assign axi_imem_cmd = core_imem_cmd;
-assign axi_imem_addr = core_imem_addr;
-assign core_imem_req_ack = axi_imem_req_ack;
-assign core_imem_resp = axi_imem_resp;
-assign core_imem_rdata = axi_imem_rdata;
-
-`endif // SCR1_IMEM_ROUTER_EN
-
-
-//-------------------------------------------------------------------------------
-// Data memory router
-//-------------------------------------------------------------------------------
-scr1_dmem_router #(
-
-`ifdef SCR1_TCM_EN
- .SCR1_PORT1_ADDR_MASK (SCR1_TCM_ADDR_MASK),
- .SCR1_PORT1_ADDR_PATTERN (SCR1_TCM_ADDR_PATTERN),
-`else // SCR1_TCM_EN
- .SCR1_PORT1_ADDR_MASK (32'h00000000),
- .SCR1_PORT1_ADDR_PATTERN (32'hFFFFFFFF),
-`endif // SCR1_TCM_EN
-
- .SCR1_PORT2_ADDR_MASK (SCR1_TIMER_ADDR_MASK),
- .SCR1_PORT2_ADDR_PATTERN (SCR1_TIMER_ADDR_PATTERN)
-
-) i_dmem_router (
- .rst_n (core_rst_n_local ),
- .clk (clk ),
-
- // Interface to core
- .dmem_req_ack (core_dmem_req_ack ),
- .dmem_req (core_dmem_req ),
- .dmem_cmd (core_dmem_cmd ),
- .dmem_width (core_dmem_width ),
- .dmem_addr (core_dmem_addr ),
- .dmem_wdata (core_dmem_wdata ),
- .dmem_rdata (core_dmem_rdata ),
- .dmem_resp (core_dmem_resp ),
-
-`ifdef SCR1_TCM_EN
- // Interface to TCM
- .port1_req_ack (tcm_dmem_req_ack ),
- .port1_req (tcm_dmem_req ),
- .port1_cmd (tcm_dmem_cmd ),
- .port1_width (tcm_dmem_width ),
- .port1_addr (tcm_dmem_addr ),
- .port1_wdata (tcm_dmem_wdata ),
- .port1_rdata (tcm_dmem_rdata ),
- .port1_resp (tcm_dmem_resp ),
-`else // SCR1_TCM_EN
- .port1_req_ack (1'b0 ),
- .port1_req ( ),
- .port1_cmd ( ),
- .port1_width ( ),
- .port1_addr ( ),
- .port1_wdata ( ),
- .port1_rdata ('0 ),
- .port1_resp (SCR1_MEM_RESP_RDY_ER),
-`endif // SCR1_TCM_EN
-
- // Interface to memory-mapped timer
- .port2_req_ack (timer_dmem_req_ack ),
- .port2_req (timer_dmem_req ),
- .port2_cmd (timer_dmem_cmd ),
- .port2_width (timer_dmem_width ),
- .port2_addr (timer_dmem_addr ),
- .port2_wdata (timer_dmem_wdata ),
- .port2_rdata (timer_dmem_rdata ),
- .port2_resp (timer_dmem_resp ),
-
- // Interface to AXI bridge
- .port0_req_ack (axi_dmem_req_ack ),
- .port0_req (axi_dmem_req ),
- .port0_cmd (axi_dmem_cmd ),
- .port0_width (axi_dmem_width ),
- .port0_addr (axi_dmem_addr ),
- .port0_wdata (axi_dmem_wdata ),
- .port0_rdata (axi_dmem_rdata ),
- .port0_resp (axi_dmem_resp )
-);
-
-
-//-------------------------------------------------------------------------------
-// Instruction memory AXI bridge
-//-------------------------------------------------------------------------------
-scr1_mem_axi #(
-`ifdef SCR1_IMEM_AXI_REQ_BP
- .SCR1_AXI_REQ_BP (1),
-`else // SCR1_IMEM_AXI_REQ_BP
- .SCR1_AXI_REQ_BP (0),
-`endif // SCR1_IMEM_AXI_REQ_BP
-`ifdef SCR1_IMEM_AXI_RESP_BP
- .SCR1_AXI_RESP_BP (1)
-`else // SCR1_IMEM_AXI_RESP_BP
- .SCR1_AXI_RESP_BP (0)
-`endif // SCR1_IMEM_AXI_RESP_BP
-) i_imem_axi (
- .clk (clk ),
- .rst_n (axi_rst_n ),
- .axi_reinit (axi_reinit ),
-
- // Interface to core
- .core_idle (axi_imem_idle ),
- .core_req_ack (axi_imem_req_ack ),
- .core_req (axi_imem_req ),
- .core_cmd (axi_imem_cmd ),
- .core_width (SCR1_MEM_WIDTH_WORD ),
- .core_addr (axi_imem_addr ),
- .core_wdata ('0 ),
- .core_rdata (axi_imem_rdata ),
- .core_resp (axi_imem_resp ),
-
- // AXI I/O
- .awid (io_axi_imem_awid ),
- .awaddr (io_axi_imem_awaddr ),
- .awlen (io_axi_imem_awlen ),
- .awsize (io_axi_imem_awsize ),
- .awburst (io_axi_imem_awburst ),
- .awlock (io_axi_imem_awlock ),
- .awcache (io_axi_imem_awcache ),
- .awprot (io_axi_imem_awprot ),
- .awregion (io_axi_imem_awregion ),
- .awuser (io_axi_imem_awuser ),
- .awqos (io_axi_imem_awqos ),
- .awvalid (io_axi_imem_awvalid ),
- .awready (io_axi_imem_awready ),
- .wdata (io_axi_imem_wdata ),
- .wstrb (io_axi_imem_wstrb ),
- .wlast (io_axi_imem_wlast ),
- .wuser (io_axi_imem_wuser ),
- .wvalid (io_axi_imem_wvalid ),
- .wready (io_axi_imem_wready ),
- .bid (io_axi_imem_bid ),
- .bresp (io_axi_imem_bresp ),
- .bvalid (io_axi_imem_bvalid ),
- .buser (io_axi_imem_buser ),
- .bready (io_axi_imem_bready ),
- .arid (io_axi_imem_arid ),
- .araddr (io_axi_imem_araddr ),
- .arlen (io_axi_imem_arlen ),
- .arsize (io_axi_imem_arsize ),
- .arburst (io_axi_imem_arburst ),
- .arlock (io_axi_imem_arlock ),
- .arcache (io_axi_imem_arcache ),
- .arprot (io_axi_imem_arprot ),
- .arregion (io_axi_imem_arregion ),
- .aruser (io_axi_imem_aruser ),
- .arqos (io_axi_imem_arqos ),
- .arvalid (io_axi_imem_arvalid ),
- .arready (io_axi_imem_arready ),
- .rid (io_axi_imem_rid ),
- .rdata (io_axi_imem_rdata ),
- .rresp (io_axi_imem_rresp ),
- .rlast (io_axi_imem_rlast ),
- .ruser (io_axi_imem_ruser ),
- .rvalid (io_axi_imem_rvalid ),
- .rready (io_axi_imem_rready )
-);
-
-
-//-------------------------------------------------------------------------------
-// Data memory AXI bridge
-//-------------------------------------------------------------------------------
-scr1_mem_axi #(
-`ifdef SCR1_DMEM_AXI_REQ_BP
- .SCR1_AXI_REQ_BP (1),
-`else // SCR1_DMEM_AXI_REQ_BP
- .SCR1_AXI_REQ_BP (0),
-`endif // SCR1_DMEM_AXI_REQ_BP
-`ifdef SCR1_DMEM_AXI_RESP_BP
- .SCR1_AXI_RESP_BP (1)
-`else // SCR1_DMEM_AXI_RESP_BP
- .SCR1_AXI_RESP_BP (0)
-`endif // SCR1_DMEM_AXI_RESP_BP
-) i_dmem_axi (
- .clk (clk ),
- .rst_n (axi_rst_n ),
- .axi_reinit (axi_reinit ),
-
- // Interface to core
- .core_idle (axi_dmem_idle ),
- .core_req_ack (axi_dmem_req_ack ),
- .core_req (axi_dmem_req ),
- .core_cmd (axi_dmem_cmd ),
- .core_width (axi_dmem_width ),
- .core_addr (axi_dmem_addr ),
- .core_wdata (axi_dmem_wdata ),
- .core_rdata (axi_dmem_rdata ),
- .core_resp (axi_dmem_resp ),
-
- // AXI I/O
- .awid (io_axi_dmem_awid ),
- .awaddr (io_axi_dmem_awaddr ),
- .awlen (io_axi_dmem_awlen ),
- .awsize (io_axi_dmem_awsize ),
- .awburst (io_axi_dmem_awburst ),
- .awlock (io_axi_dmem_awlock ),
- .awcache (io_axi_dmem_awcache ),
- .awprot (io_axi_dmem_awprot ),
- .awregion (io_axi_dmem_awregion ),
- .awuser (io_axi_dmem_awuser ),
- .awqos (io_axi_dmem_awqos ),
- .awvalid (io_axi_dmem_awvalid ),
- .awready (io_axi_dmem_awready ),
- .wdata (io_axi_dmem_wdata ),
- .wstrb (io_axi_dmem_wstrb ),
- .wlast (io_axi_dmem_wlast ),
- .wuser (io_axi_dmem_wuser ),
- .wvalid (io_axi_dmem_wvalid ),
- .wready (io_axi_dmem_wready ),
- .bid (io_axi_dmem_bid ),
- .bresp (io_axi_dmem_bresp ),
- .bvalid (io_axi_dmem_bvalid ),
- .buser (io_axi_dmem_buser ),
- .bready (io_axi_dmem_bready ),
- .arid (io_axi_dmem_arid ),
- .araddr (io_axi_dmem_araddr ),
- .arlen (io_axi_dmem_arlen ),
- .arsize (io_axi_dmem_arsize ),
- .arburst (io_axi_dmem_arburst ),
- .arlock (io_axi_dmem_arlock ),
- .arcache (io_axi_dmem_arcache ),
- .arprot (io_axi_dmem_arprot ),
- .arregion (io_axi_dmem_arregion ),
- .aruser (io_axi_dmem_aruser ),
- .arqos (io_axi_dmem_arqos ),
- .arvalid (io_axi_dmem_arvalid ),
- .arready (io_axi_dmem_arready ),
- .rid (io_axi_dmem_rid ),
- .rdata (io_axi_dmem_rdata ),
- .rresp (io_axi_dmem_rresp ),
- .rlast (io_axi_dmem_rlast ),
- .ruser (io_axi_dmem_ruser ),
- .rvalid (io_axi_dmem_rvalid ),
- .rready (io_axi_dmem_rready )
-);
-
-//-------------------------------------------------------------------------------
-// AXI reinit logic
-//-------------------------------------------------------------------------------
-always_ff @(negedge core_rst_n_local, posedge clk) begin
- if (~core_rst_n_local) axi_reinit <= 1'b1;
- else if (axi_imem_idle & axi_dmem_idle) axi_reinit <= 1'b0;
-end
-
-endmodule : scr1_top_axi
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
deleted file mode 100644
index 60e055c..0000000
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
+++ /dev/null
@@ -1,477 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: 2021, Dinesh Annayya
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
-// //////////////////////////////////////////////////////////////////////////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// yifive Wishbone interface for syntacore ////
-//// ////
-//// This file is part of the yifive cores project ////
-//// https://github.com/dineshannayya/yifive_r0.git ////
-//// http://www.opencores.org/cores/yifive/ ////
-//// ////
-//// Description: ////
-//// integrated wishbone i/f to instruction/data memory ////
-//// ////
-//// To Do: ////
-//// nothing ////
-//// ////
-//// Author(s): ////
-//// - Dinesh Annayya, dinesha@opencores.org ////
-//// ////
-//// Revision : ////
-//// v0: June 7, 2021, Dinesh A ////
-//// wishbone integration ////
-//// v1: June 17, 2021, Dinesh A ////
-//// core and wishbone clock domain are seperated ////
-//// Async fifo added in imem and dmem path ////
-//// v2: July 7, 2021, Dinesh A ////
-//// 64bit debug signal added ////
-//// v3: Aug 23, 2021, Dinesh A ////
-//// timer_irq connective bug fix ////
-//// v3: Nov 12, 2021, Dinesh A ////
-//// 2KB SRAM Integrated at TCM Interface ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-// Orginal owner Details ////
-//////////////////////////////////////////////////////////////////////
-/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details///
-/// @file <scr1_top_wb.sv> ///
-/// @brief SCR1 AHB top ///
-//////////////////////////////////////////////////////////////////////
-
-`include "scr1_arch_description.svh"
-`include "scr1_memif.svh"
-`include "scr1_wb.svh"
-`ifdef SCR1_IPIC_EN
-`include "scr1_ipic.svh"
-`endif // SCR1_IPIC_EN
-
-`ifdef SCR1_TCM_EN
- `define SCR1_IMEM_ROUTER_EN
-`endif // SCR1_TCM_EN
-
-module scr1_top_wb (
-
-`ifdef USE_POWER_PINS
- input logic vccd1, // User area 1 1.8V supply
- input logic vssd1, // User area 1 digital ground
-`endif
- input logic [3:0] cfg_cska_riscv,
- input logic wbd_clk_int,
- output logic wbd_clk_riscv,
-
- // Control
- input logic pwrup_rst_n, // Power-Up Reset
- input logic rst_n, // Regular Reset signal
- input logic cpu_rst_n, // CPU Reset (Core Reset)
- // input logic test_mode, // Test mode - unused
- // input logic test_rst_n, // Test mode's reset - unused
- input logic core_clk, // Core clock
- input logic rtc_clk, // Real-time clock
- output logic [63:0] riscv_debug,
-`ifdef SCR1_DBG_EN
- output logic sys_rst_n_o, // External System Reset output
- // (for the processor cluster's components or
- // external SOC (could be useful in small
- // SCR-core-centric SOCs))
- output logic sys_rdc_qlfy_o, // System-to-External SOC Reset Domain Crossing Qualifier
-`endif // SCR1_DBG_EN
-
- // Fuses
- input logic [`SCR1_XLEN-1:0] fuse_mhartid, // Hart ID
-`ifdef SCR1_DBG_EN
- input logic [31:0] fuse_idcode, // TAPC IDCODE
-`endif // SCR1_DBG_EN
-
- // IRQ
-`ifdef SCR1_IPIC_EN
- input logic [SCR1_IRQ_LINES_NUM-1:0] irq_lines, // IRQ lines to IPIC
-`else // SCR1_IPIC_EN
- input logic ext_irq, // External IRQ input
-`endif // SCR1_IPIC_EN
- input logic soft_irq, // Software IRQ input
-
-`ifdef SCR1_DBG_EN
- // -- JTAG I/F
- input logic trst_n,
- input logic tck,
- input logic tms,
- input logic tdi,
- output logic tdo,
- output logic tdo_en,
-`endif // SCR1_DBG_EN
-
-`ifndef SCR1_TCM_MEM
- // SRAM-0 PORT-0
- output logic sram0_clk0,
- output logic sram0_csb0,
- output logic sram0_web0,
- output logic [8:0] sram0_addr0,
- output logic [3:0] sram0_wmask0,
- output logic [31:0] sram0_din0,
- input logic [31:0] sram0_dout0,
-
- // SRAM-0 PORT-1
- output logic sram0_clk1,
- output logic sram0_csb1,
- output logic [8:0] sram0_addr1,
- input logic [31:0] sram0_dout1,
-
- // SRAM-1 PORT-0
- output logic sram1_clk0,
- output logic sram1_csb0,
- output logic sram1_web0,
- output logic [8:0] sram1_addr0,
- output logic [3:0] sram1_wmask0,
- output logic [31:0] sram1_din0,
- input logic [31:0] sram1_dout0,
-
- // SRAM-1 PORT-1
- output logic sram1_clk1,
- output logic sram1_csb1,
- output logic [8:0] sram1_addr1,
- input logic [31:0] sram1_dout1,
-`endif
-
-
- input logic wb_rst_n, // Wish bone reset
- input logic wb_clk, // wish bone clock
- // Instruction Memory Interface
- output logic wbd_imem_stb_o, // strobe/request
- output logic [SCR1_WB_WIDTH-1:0] wbd_imem_adr_o, // address
- output logic wbd_imem_we_o, // write
- output logic [SCR1_WB_WIDTH-1:0] wbd_imem_dat_o, // data output
- output logic [3:0] wbd_imem_sel_o, // byte enable
- input logic [SCR1_WB_WIDTH-1:0] wbd_imem_dat_i, // data input
- input logic wbd_imem_ack_i, // acknowlegement
- input logic wbd_imem_err_i, // error
-
- // Data Memory Interface
- output logic wbd_dmem_stb_o, // strobe/request
- output logic [SCR1_WB_WIDTH-1:0] wbd_dmem_adr_o, // address
- output logic wbd_dmem_we_o, // write
- output logic [SCR1_WB_WIDTH-1:0] wbd_dmem_dat_o, // data output
- output logic [3:0] wbd_dmem_sel_o, // byte enable
- input logic [SCR1_WB_WIDTH-1:0] wbd_dmem_dat_i, // data input
- input logic wbd_dmem_ack_i, // acknowlegement
- input logic wbd_dmem_err_i // error
-);
-
-//-------------------------------------------------------------------------------
-// Local parameters
-//-------------------------------------------------------------------------------
-localparam int unsigned SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM = 2;
-
-//-------------------------------------------------------------------------------
-// Local signal declaration
-//-------------------------------------------------------------------------------
-// Reset logic
-logic test_mode; // Test mode - unused
-logic test_rst_n; // Test mode's reset - unused
-logic pwrup_rst_n_sync;
-logic rst_n_sync;
-logic cpu_rst_n_sync;
-logic core_rst_n_local;
-`ifdef SCR1_DBG_EN
-logic tapc_trst_n;
-`endif // SCR1_DBG_EN
-
-// Instruction memory interface from core to router
-logic core_imem_req_ack;
-logic core_imem_req;
-logic core_imem_cmd;
-logic [`SCR1_IMEM_AWIDTH-1:0] core_imem_addr;
-logic [`SCR1_IMEM_DWIDTH-1:0] core_imem_rdata;
-logic [1:0] core_imem_resp;
-
-// Data memory interface from core to router
-logic core_dmem_req_ack;
-logic core_dmem_req;
-logic core_dmem_cmd;
-logic [1:0] core_dmem_width;
-logic [`SCR1_DMEM_AWIDTH-1:0] core_dmem_addr;
-logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_wdata;
-logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_rdata;
-logic [1:0] core_dmem_resp;
-
-// Instruction memory interface from router to WB bridge
-logic wb_imem_req_ack;
-logic wb_imem_req;
-logic wb_imem_cmd;
-logic [`SCR1_IMEM_AWIDTH-1:0] wb_imem_addr;
-logic [`SCR1_IMEM_DWIDTH-1:0] wb_imem_rdata;
-logic [1:0] wb_imem_resp;
-
-// Data memory interface from router to WB bridge
-logic wb_dmem_req_ack;
-logic wb_dmem_req;
-logic wb_dmem_cmd;
-logic [1:0] wb_dmem_width;
-logic [`SCR1_DMEM_AWIDTH-1:0] wb_dmem_addr;
-logic [`SCR1_DMEM_DWIDTH-1:0] wb_dmem_wdata;
-logic [`SCR1_DMEM_DWIDTH-1:0] wb_dmem_rdata;
-logic [1:0] wb_dmem_resp;
-
-`ifdef SCR1_TCM_EN
-// Instruction memory interface from router to TCM
-logic tcm_imem_req_ack;
-logic tcm_imem_req;
-logic tcm_imem_cmd;
-logic [`SCR1_IMEM_AWIDTH-1:0] tcm_imem_addr;
-logic [`SCR1_IMEM_DWIDTH-1:0] tcm_imem_rdata;
-logic [1:0] tcm_imem_resp;
-
-// Data memory interface from router to TCM
-logic tcm_dmem_req_ack;
-logic tcm_dmem_req;
-logic tcm_dmem_cmd;
-logic [1:0] tcm_dmem_width;
-logic [`SCR1_DMEM_AWIDTH-1:0] tcm_dmem_addr;
-logic [`SCR1_DMEM_DWIDTH-1:0] tcm_dmem_wdata;
-logic [`SCR1_DMEM_DWIDTH-1:0] tcm_dmem_rdata;
-logic [1:0] tcm_dmem_resp;
-`endif // SCR1_TCM_EN
-
-// Data memory interface from router to memory-mapped timer
-logic timer_dmem_req_ack;
-logic timer_dmem_req;
-logic timer_dmem_cmd;
-logic [1:0] timer_dmem_width;
-logic [`SCR1_DMEM_AWIDTH-1:0] timer_dmem_addr;
-logic [`SCR1_DMEM_DWIDTH-1:0] timer_dmem_wdata;
-logic [`SCR1_DMEM_DWIDTH-1:0] timer_dmem_rdata;
-logic [1:0] timer_dmem_resp;
-
-logic timer_irq;
-logic [63:0] timer_val;
-logic [48:0] core_debug;
-
-// riscv clock skew control
-clk_skew_adjust u_skew_riscv
- (
-`ifdef USE_POWER_PINS
- .vccd1 (vccd1 ),// User area 1 1.8V supply
- .vssd1 (vssd1 ),// User area 1 digital ground
-`endif
- .clk_in (wbd_clk_int ),
- .sel (cfg_cska_riscv ),
- .clk_out (wbd_clk_riscv )
- );
-//-------------------------------------------------------------------------------
-// SCR1 Intf instance
-//-------------------------------------------------------------------------------
-scr1_intf u_intf (
- // Control
- .pwrup_rst_n (pwrup_rst_n), // Power-Up Reset
- .rst_n (rst_n), // Regular Reset signal
- .cpu_rst_n (cpu_rst_n), // CPU Reset (Core Reset)
- .core_clk (core_clk), // Core clock
- .rtc_clk (rtc_clk), // Real-time clock
- .riscv_debug (riscv_debug),
-
-`ifdef SCR1_DBG_EN
- // -- JTAG I/F
- .trst_n (trst_n),
-`endif // SCR1_DBG_EN
-
-`ifndef SCR1_TCM_MEM
- // SRAM-0 PORT-0
- .sram0_clk0 (sram0_clk0),
- .sram0_csb0 (sram0_csb0),
- .sram0_web0 (sram0_web0),
- .sram0_addr0 (sram0_addr0),
- .sram0_wmask0 (sram0_wmask0),
- .sram0_din0 (sram0_din0),
- .sram0_dout0 (sram0_dout0),
-
- // SRAM-0 PORT-1
- .sram0_clk1 (sram0_clk1),
- .sram0_csb1 (sram0_csb1),
- .sram0_addr1 (sram0_addr1),
- .sram0_dout1 (sram0_dout1),
-
- // SRAM-1 PORT-0
- .sram1_clk0 (sram1_clk0),
- .sram1_csb0 (sram1_csb0),
- .sram1_web0 (sram1_web0),
- .sram1_addr0 (sram1_addr0),
- .sram1_wmask0 (sram1_wmask0),
- .sram1_din0 (sram1_din0),
- .sram1_dout0 (sram1_dout0),
-
- // SRAM-1 PORT-1
- .sram1_clk1 (sram1_clk1),
- .sram1_csb1 (sram1_csb1),
- .sram1_addr1 (sram1_addr1),
- .sram1_dout1 (sram1_dout1),
-`endif
-
- .wb_rst_n (wb_rst_n), // Wish bone reset
- .wb_clk (wb_clk), // wish bone clock
-
- // Instruction Memory Interface
- .wbd_imem_stb_o (wbd_imem_stb_o), // strobe/request
- .wbd_imem_adr_o (wbd_imem_adr_o), // address
- .wbd_imem_we_o (wbd_imem_we_o), // write
- .wbd_imem_dat_o (wbd_imem_dat_o), // data output
- .wbd_imem_sel_o (wbd_imem_sel_o), // byte enable
- .wbd_imem_dat_i (wbd_imem_dat_i), // data input
- .wbd_imem_ack_i (wbd_imem_ack_i), // acknowlegement
- .wbd_imem_err_i (wbd_imem_err_i), // error
-
- // Data Memory Interface
- .wbd_dmem_stb_o (wbd_dmem_stb_o), // strobe/request
- .wbd_dmem_adr_o (wbd_dmem_adr_o), // address
- .wbd_dmem_we_o (wbd_dmem_we_o), // write
- .wbd_dmem_dat_o (wbd_dmem_dat_o), // data output
- .wbd_dmem_sel_o (wbd_dmem_sel_o), // byte enable
- .wbd_dmem_dat_i (wbd_dmem_dat_i), // data input
- .wbd_dmem_ack_i (wbd_dmem_ack_i), // acknowlegement
- .wbd_dmem_err_i (wbd_dmem_err_i), // error
-
- // Common
- .pwrup_rst_n_sync (pwrup_rst_n_sync), // Power-Up reset
- .rst_n_sync (rst_n_sync), // Regular reset
- .cpu_rst_n_sync (cpu_rst_n_sync), // CPU reset
- .test_mode (test_mode), // DFT Test Mode
- .test_rst_n (test_rst_n), // DFT Test Reset
- .core_rst_n_local (core_rst_n_local), // Core reset
- .core_debug (core_debug ),
-`ifdef SCR1_DBG_EN
- // Debug Interface
- .tapc_trst_n (tapc_trst_n), // Test Reset (TRSTn)
-`endif
- // Memory-mapped external timer
- .timer_val (timer_val), // Machine timer value
- .timer_irq (timer_irq), // Machine timer value
- // Instruction Memory Interface
- .core_imem_req_ack (core_imem_req_ack), // IMEM request acknowledge
- .core_imem_req (core_imem_req), // IMEM request
- .core_imem_cmd (core_imem_cmd), // IMEM command
- .core_imem_addr (core_imem_addr), // IMEM address
- .core_imem_rdata (core_imem_rdata), // IMEM read data
- .core_imem_resp (core_imem_resp), // IMEM response
-
- // Data Memory Interface
- .core_dmem_req_ack (core_dmem_req_ack), // DMEM request acknowledge
- .core_dmem_req (core_dmem_req), // DMEM request
- .core_dmem_cmd (core_dmem_cmd), // DMEM command
- .core_dmem_width (core_dmem_width), // DMEM data width
- .core_dmem_addr (core_dmem_addr), // DMEM address
- .core_dmem_wdata (core_dmem_wdata), // DMEM write data
- .core_dmem_rdata (core_dmem_rdata), // DMEM read data
- .core_dmem_resp (core_dmem_resp) // DMEM response
-
-);
-
-
-//-------------------------------------------------------------------------------
-// SCR1 core instance
-//-------------------------------------------------------------------------------
-scr1_core_top i_core_top (
- // Common
- .pwrup_rst_n (pwrup_rst_n_sync ),
- .rst_n (rst_n_sync ),
- .cpu_rst_n (cpu_rst_n_sync ),
- .test_mode (test_mode ),
- .test_rst_n (test_rst_n ),
- .clk (core_clk ),
- .core_rst_n_o (core_rst_n_local ),
- .core_rdc_qlfy_o ( ),
- .core_debug (core_debug ),
-`ifdef SCR1_DBG_EN
- .sys_rst_n_o (sys_rst_n_o ),
- .sys_rdc_qlfy_o (sys_rdc_qlfy_o ),
-`endif // SCR1_DBG_EN
-
- // Fuses
- .core_fuse_mhartid_i (fuse_mhartid ),
-`ifdef SCR1_DBG_EN
- .tapc_fuse_idcode_i (fuse_idcode ),
-`endif // SCR1_DBG_EN
-
- // IRQ
-`ifdef SCR1_IPIC_EN
- .core_irq_lines_i (irq_lines ),
-`else // SCR1_IPIC_EN
- .core_irq_ext_i (ext_irq ),
-`endif // SCR1_IPIC_EN
- .core_irq_soft_i (soft_irq ),
- .core_irq_mtimer_i (timer_irq ),
-
- // Memory-mapped external timer
- .core_mtimer_val_i (timer_val ),
-
-`ifdef SCR1_DBG_EN
- // Debug interface
- .tapc_trst_n (tapc_trst_n ),
- .tapc_tck (tck ),
- .tapc_tms (tms ),
- .tapc_tdi (tdi ),
- .tapc_tdo (tdo ),
- .tapc_tdo_en (tdo_en ),
-`endif // SCR1_DBG_EN
-
- // Instruction memory interface
- .imem2core_req_ack_i (core_imem_req_ack),
- .core2imem_req_o (core_imem_req ),
- .core2imem_cmd_o (core_imem_cmd ),
- .core2imem_addr_o (core_imem_addr ),
- .imem2core_rdata_i (core_imem_rdata ),
- .imem2core_resp_i (core_imem_resp ),
-
- // Data memory interface
- .dmem2core_req_ack_i (core_dmem_req_ack),
- .core2dmem_req_o (core_dmem_req ),
- .core2dmem_cmd_o (core_dmem_cmd ),
- .core2dmem_width_o (core_dmem_width ),
- .core2dmem_addr_o (core_dmem_addr ),
- .core2dmem_wdata_o (core_dmem_wdata ),
- .dmem2core_rdata_i (core_dmem_rdata ),
- .dmem2core_resp_i (core_dmem_resp )
-);
-
-
-
-endmodule : scr1_top_wb
-
-
diff --git a/verilog/rtl/syntacore/scr1/src/wb_top.files b/verilog/rtl/syntacore/scr1/src/wb_top.files
deleted file mode 100644
index 1d67b0c..0000000
--- a/verilog/rtl/syntacore/scr1/src/wb_top.files
+++ /dev/null
@@ -1,26 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: 2021, Dinesh Annayya
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
-// //////////////////////////////////////////////////////////////////////////
-top/scr1_dmem_router.sv
-top/scr1_dp_memory.sv
-top/scr1_tcm.sv
-top/scr1_timer.sv
-top/scr1_dmem_wb.sv
-top/scr1_imem_wb.sv
-top/scr1_top_wb.sv
-top/scr1_intf.sv
-../../../lib/sync_fifo.sv
diff --git a/verilog/rtl/syntacore/scr1/synth/Makefile b/verilog/rtl/syntacore/scr1/synth/Makefile
deleted file mode 100644
index f8cd450..0000000
--- a/verilog/rtl/syntacore/scr1/synth/Makefile
+++ /dev/null
@@ -1,91 +0,0 @@
-# //////////////////////////////////////////////////////////////////////////////
-# // SPDX-FileCopyrightText: 2021, Dinesh Annayya
-# //
-# // Licensed under the Apache License, Version 2.0 (the "License");
-# // you may not use this file except in compliance with the License.
-# // You may obtain a copy of the License at
-# //
-# // http://www.apache.org/licenses/LICENSE-2.0
-# //
-# // Unless required by applicable law or agreed to in writing, software
-# // distributed under the License is distributed on an "AS IS" BASIS,
-# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# // See the License for the specific language governing permissions and
-# // limitations under the License.
-# // SPDX-License-Identifier: Apache-2.0
-# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
-# // //////////////////////////////////////////////////////////////////////////
-#------------------------------------------------------------------------------
-# Makefile for Synthesis
-#------------------------------------------------------------------------------
-
-# Paths
-export ROOT_DIR := $(shell pwd)
-export DESIGN_FILE := $(ROOT_DIR)/syntacore.sv
-export SYNTH_LOG := $(ROOT_DIR)/synth.log
-export REPORT_DIR := $(ROOT_DIR)/reports
-export NETLIST_DIR := $(ROOT_DIR)/netlist
-export TMP_DIR := $(ROOT_DIR)/tmp
-
-
-# Targets
-.PHONY: clean create merge synth
-
-default: clean create merge synth
-
-synth: clean create merge
- yosys -g -c synth.tcl -l synth.log
-
-create:
- mkdir -p ./tmp/synthesis;
- mkdir -p ./reports;
- mkdir -p ./netlist;
- $(OPENLANE_ROOT)/scripts/libtrim.pl $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib $(PDK_ROOT)/sky130A/libs.tech/openlane/sky130_fd_sc_hd/no_synth.cells > ./tmp/trimmed.lib
- #create No PG Pin library for hand instantiated cells
- sed '/pg_pin.*/a \ direction : "inout";' $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib > ./tmp/sky130_fd_sc_hd__tt_025C_1v80.no_pg.lib
- sed -i 's/pg_pin/pin/' ./tmp/sky130_fd_sc_hd__tt_025C_1v80.no_pg.lib
-
-merge:
- ################################################
- # yosys has issue in propgating the golbal parameter from one file to other file
- # to fix this issue, we have concatinated all the rtl file into single file before starting synthesis
- # only memory are exclded from this list
- # ################################################
- cat ../src/core/pipeline/scr1_pipe_top.sv > syntacore.sv;
- cat ../src/core/scr1_core_top.sv >> syntacore.sv;
- cat ../src/core/scr1_dm.sv >> syntacore.sv;
- cat ../src/core/scr1_tapc_synchronizer.sv >> syntacore.sv;
- cat ../src/core/scr1_clk_ctrl.sv >> syntacore.sv;
- cat ../src/core/scr1_scu.sv >> syntacore.sv;
- cat ../src/core/scr1_tapc.sv >> syntacore.sv;
- cat ../src/core/scr1_tapc_shift_reg.sv >> syntacore.sv;
- cat ../src/core/scr1_dmi.sv >> syntacore.sv;
- cat ../src/core/primitives/scr1_reset_cells.sv >> syntacore.sv;
- cat ../src/core/pipeline/scr1_pipe_ifu.sv >> syntacore.sv;
- cat ../src/core/pipeline/scr1_pipe_idu.sv >> syntacore.sv;
- cat ../src/core/pipeline/scr1_pipe_exu.sv >> syntacore.sv;
- cat ../src/core/pipeline/scr1_pipe_mprf.sv >> syntacore.sv;
- cat ../src/core/pipeline/scr1_pipe_csr.sv >> syntacore.sv;
- cat ../src/core/pipeline/scr1_pipe_ialu.sv >> syntacore.sv;
- cat ../src/core/pipeline/scr1_pipe_lsu.sv >> syntacore.sv;
- cat ../src/core/pipeline/scr1_pipe_hdu.sv >> syntacore.sv;
- cat ../src/core/pipeline/scr1_pipe_tdu.sv >> syntacore.sv;
- cat ../src/core/pipeline/scr1_ipic.sv >> syntacore.sv;
- cat ../src/top/scr1_dmem_router.sv >> syntacore.sv;
- cat ../src/top/scr1_imem_router.sv >> syntacore.sv;
- #cat ../src/top/scr1_dp_memory.sv >> syntacore.sv;
- cat ../src/top/scr1_tcm.sv >> syntacore.sv;
- cat ../src/top/scr1_timer.sv >> syntacore.sv;
- #cat ../src/top/scr1_dmem_ahb.sv >> syntacore.sv;
- #cat ../src/top/scr1_imem_ahb.sv >> syntacore.sv;
- cat ../src/top/scr1_top_axi.sv >> syntacore.sv;
- cat ../src/top/scr1_mem_axi.sv>> syntacore.sv;
-
-
-
-clean:
- $(RM) $(DESIGN_FILE)
- $(RM) $(SYNTH_LOG)
- $(RM) -R $(REPORT_DIR)
- $(RM) -R $(NETLIST_DIR)
- $(RM) -R $(TMP_DIR)
diff --git a/verilog/rtl/syntacore/scr1/synth/base.sdc b/verilog/rtl/syntacore/scr1/synth/base.sdc
deleted file mode 100644
index e47298c..0000000
--- a/verilog/rtl/syntacore/scr1/synth/base.sdc
+++ /dev/null
@@ -1,89 +0,0 @@
-# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-
-set_units -time ns
-#Wishbone Clock
-set ::env(WB_CLOCK_PERIOD) "10"
-set ::env(WB_CLOCK_PORT) "wb_clk"
-set ::env(WB_CLOCK_NAME) "wb_clk"
-
-#Risc Core Clock
-set ::env(CORE_CLOCK_PERIOD) "20"
-set ::env(CORE_CLOCK_PORT) "core_clk"
-set ::env(CORE_CLOCK_NAME) "core_clk"
-
-#RTC Core Clock
-set ::env(RTC_CLOCK_PERIOD) "40"
-set ::env(RTC_CLOCK_PORT) "rtc_clk"
-set ::env(RTC_CLOCK_NAME) "rtc_clk"
-
-######################################
-# CORE Clock domain input output
-######################################
-create_clock [get_ports $::env(CORE_CLOCK_PORT)] -name $::env(CORE_CLOCK_NAME) -period $::env(CORE_CLOCK_PERIOD)
-set core_input_delay_value [expr $::env(CORE_CLOCK_PERIOD) * 0.6]
-set core_output_delay_value [expr $::env(CORE_CLOCK_PERIOD) * 0.6]
-puts "\[INFO\]: Setting core output delay to: $core_output_delay_value"
-puts "\[INFO\]: Setting core input delay to: $core_input_delay_value"
-set core_clk_indx [lsearch [all_inputs] [get_port $::env(CORE_CLOCK_NAME)]]
-set core_rst_indx [lsearch [all_inputs] [get_port cpu_rst_n]]
-set all_inputs_wo_core_clk_rst [lreplace [all_inputs] $core_clk_indx $core_rst_indx]
-set all_outputs_core [all_outputs]
-
-set_input_delay $core_input_delay_value -clock [get_clocks $::env(CORE_CLOCK_NAME)] $all_inputs_wo_core_clk_rst
-set_input_delay 5.0 -clock [get_clocks $::env(CORE_CLOCK_NAME)] {cpu_rst_n}
-set_output_delay $core_output_delay_value -clock [get_clocks $::env(CORE_CLOCK_NAME)] $all_outputs_core
-
-create_clock [get_ports $::env(RTC_CLOCK_PORT)] -name $::env(RTC_CLOCK_NAME) -period $::env(RTC_CLOCK_PERIOD)
-
-######################################
-# WB Clock domain input output
-######################################
-create_clock [get_ports $::env(WB_CLOCK_PORT)] -name $::env(WB_CLOCK_NAME) -period $::env(WB_CLOCK_PERIOD)
-set wb_input_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
-set wb_output_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
-puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
-puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
-set wb_clk_indx [lsearch [all_inputs] [get_port $::env(WB_CLOCK_NAME)]]
-set wb_rst_indx [lsearch [all_inputs] [get_port wb_rst_n]]
-set all_inputs_wo_wb_clk_rst [lreplace [all_inputs] $wb_clk_indx $wb_rst_indx]
-set all_outputs_wb [all_outputs]
-
-set_false_path -to riscv_debug*
-set_false_path -from soft_irq
-
-set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_NAME)] $all_inputs_wo_wb_clk_rst
-set_input_delay 5.0 -clock [get_clocks $::env(WB_CLOCK_NAME)] {wb_rst_n}
-set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_NAME)] $all_outputs_wb
-
-#### Clock Async Defination
-set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks $::env(WB_CLOCK_NAME)] -group [get_clocks $::env(CORE_CLOCK_NAME)] -group [get_clocks $::env(RTC_CLOCK_NAME)]
-
-set_clock_uncertainty -from $::env(WB_CLOCK_NAME) -to $::env(WB_CLOCK_NAME) -setup 0.400
-set_clock_uncertainty -from $::env(CORE_CLOCK_NAME) -to $::env(CORE_CLOCK_NAME) -setup 0.400
-set_clock_uncertainty -from $::env(RTC_CLOCK_NAME) -to $::env(RTC_CLOCK_NAME) -setup 0.400
-
-set_clock_uncertainty -from $::env(WB_CLOCK_NAME) -to $::env(WB_CLOCK_NAME) -hold 0.050
-set_clock_uncertainty -from $::env(CORE_CLOCK_NAME) -to $::env(CORE_CLOCK_NAME) -hold 0.050
-set_clock_uncertainty -from $::env(RTC_CLOCK_NAME) -to $::env(RTC_CLOCK_NAME) -hold 0.050
-
-
-# TODO set this as parameter
-set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
-set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
-puts "\[INFO\]: Setting load to: $cap_load"
-set_load $cap_load [all_outputs]
diff --git a/verilog/rtl/syntacore/scr1/synth/run_synth b/verilog/rtl/syntacore/scr1/synth/run_synth
deleted file mode 100755
index d549ad4..0000000
--- a/verilog/rtl/syntacore/scr1/synth/run_synth
+++ /dev/null
@@ -1,66 +0,0 @@
-# //////////////////////////////////////////////////////////////////////////////
-# // SPDX-FileCopyrightText: 2021, Dinesh Annayya
-# //
-# // Licensed under the Apache License, Version 2.0 (the "License");
-# // you may not use this file except in compliance with the License.
-# // You may obtain a copy of the License at
-# //
-# // http://www.apache.org/licenses/LICENSE-2.0
-# //
-# // Unless required by applicable law or agreed to in writing, software
-# // distributed under the License is distributed on an "AS IS" BASIS,
-# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# // See the License for the specific language governing permissions and
-# // limitations under the License.
-# // SPDX-License-Identifier: Apache-2.0
-# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
-# // //////////////////////////////////////////////////////////////////////////
-#####################################################
-# Clean up old file and freshly create the directory
-####################################################
-\rm -rf pyfive.sv
-\rm -rf ./tmp
-\rm -rf ./reports
-\rm -rf ./netlist
-mkdir -p ./tmp/synthesis
-mkdir -p ./reports
-mkdir -p ./netlist
-
-################################################
-# yosys has issue in propgating the golbal parameter from one file to other file
-# to fix this issue, we have concatinated all the rtl file into single file before starting synthesis
-# only memory are exclded from this list
-################################################
-
-cat ../src/core/pipeline/scr1_pipe_top.sv > pyfive.sv
-cat ../src/core/scr1_core_top.sv >> pyfive.sv
-cat ../src/core/scr1_dm.sv >> pyfive.sv
-cat ../src/core/scr1_tapc_synchronizer.sv >> pyfive.sv
-cat ../src/core/scr1_clk_ctrl.sv >> pyfive.sv
-cat ../src/core/scr1_scu.sv >> pyfive.sv
-cat ../src/core/scr1_tapc.sv >> pyfive.sv
-cat ../src/core/scr1_tapc_shift_reg.sv >> pyfive.sv
-cat ../src/core/scr1_dmi.sv >> pyfive.sv
-cat ../src/core/primitives/scr1_reset_cells.sv >> pyfive.sv
-cat ../src/core/pipeline/scr1_pipe_ifu.sv >> pyfive.sv
-cat ../src/core/pipeline/scr1_pipe_idu.sv >> pyfive.sv
-cat ../src/core/pipeline/scr1_pipe_exu.sv >> pyfive.sv
-cat ../src/core/pipeline/scr1_pipe_mprf.sv >> pyfive.sv
-cat ../src/core/pipeline/scr1_pipe_csr.sv >> pyfive.sv
-cat ../src/core/pipeline/scr1_pipe_ialu.sv >> pyfive.sv
-cat ../src/core/pipeline/scr1_pipe_lsu.sv >> pyfive.sv
-cat ../src/core/pipeline/scr1_pipe_hdu.sv >> pyfive.sv
-cat ../src/core/pipeline/scr1_pipe_tdu.sv >> pyfive.sv
-cat ../src/core/pipeline/scr1_ipic.sv >> pyfive.sv
-cat ../src/top/scr1_dmem_router.sv >> pyfive.sv
-cat ../src/top/scr1_imem_router.sv >> pyfive.sv
-#cat ../src/top/scr1_dp_memory.sv >> pyfive.sv
-cat ../src/top/scr1_tcm.sv >> pyfive.sv
-cat ../src/top/scr1_timer.sv >> pyfive.sv
-cat ../src/top/scr1_dmem_ahb.sv >> pyfive.sv
-cat ../src/top/scr1_imem_ahb.sv >> pyfive.sv
-cat ../src/top/scr1_top_axi.sv >> pyfive.sv
-cat ../src/top/scr1_mem_axi.sv>> pyfive.sv
-
-yosys -g -c synth.tcl -l synth.log
-
diff --git a/verilog/rtl/syntacore/scr1/synth/sta.tcl b/verilog/rtl/syntacore/scr1/synth/sta.tcl
deleted file mode 100644
index bddbb8d..0000000
--- a/verilog/rtl/syntacore/scr1/synth/sta.tcl
+++ /dev/null
@@ -1,54 +0,0 @@
-# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
-set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
-set ::env(CURRENT_NETLIST) netlist/scr1_top_wb.gv
-set ::env(DESIGN_NAME) "scr1_top_wb"
-set ::env(BASE_SDC_FILE) "base.sdc"
-set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
-set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
-set ::env(SYNTH_CAP_LOAD) "17.65"
-set ::env(WIRE_RC_LAYER) "met1"
-
-
-set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
-read_liberty -min $::env(LIB_FASTEST)
-read_liberty -max $::env(LIB_SLOWEST)
-read_verilog $::env(CURRENT_NETLIST)
-link_design $::env(DESIGN_NAME)
-
-
-read_sdc -echo $::env(BASE_SDC_FILE)
-
-# check for missing constraints
-check_setup -verbose > unconstraints.rpt
-
-set_operating_conditions -analysis_type single
-# Propgate the clock
-set_propagated_clock [all_clocks]
-
-report_tns
-report_wns
-report_power
-report_checks -unique -slack_max -0.0 -group_count 100
-report_checks -unique -slack_min -0.0 -group_count 100
-report_checks -path_delay min_max
-report_checks -group_count 100 -slack_max -0.01 > timing.rpt
-
-report_checks -group_count 100 -slack_min -0.01 >> timing.rpt
-
-
diff --git a/verilog/rtl/syntacore/scr1/synth/synth.tcl b/verilog/rtl/syntacore/scr1/synth/synth.tcl
deleted file mode 100755
index 1a30503..0000000
--- a/verilog/rtl/syntacore/scr1/synth/synth.tcl
+++ /dev/null
@@ -1,424 +0,0 @@
-# ////////////////////////////////////////////////////////////////////////////
-# // SPDX-FileCopyrightText: 2021 , Dinesh Annayya
-# //
-# // Licensed under the Apache License, Version 2.0 (the "License");
-# // you may not use this file except in compliance with the License.
-# // You may obtain a copy of the License at
-# //
-# // http://www.apache.org/licenses/LICENSE-2.0
-# //
-# // Unless required by applicable law or agreed to in writing, software
-# // distributed under the License is distributed on an "AS IS" BASIS,
-# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# // See the License for the specific language governing permissions and
-# // limitations under the License.
-# // SPDX-License-Identifier: Apache-2.0
-# // SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-########### config.tcl ##################
-# User config
-
-# User config
-set ::env(DESIGN_DIR) ../
-
-set ::env(PROJ_DIR) ../../../../
-
-# User config
-set ::env(DESIGN_NAME) scr1_top_wb
-
-# Change if needed
-set ::env(VERILOG_FILES) [glob \
- ../src/core/pipeline/scr1_pipe_top.sv \
- ../src/core/scr1_core_top.sv \
- ../src/core/scr1_dm.sv \
- ../src/core/scr1_tapc_synchronizer.sv \
- ../src/core/scr1_clk_ctrl.sv \
- ../src/core/scr1_scu.sv \
- ../src/core/scr1_tapc.sv \
- ../src/core/scr1_tapc_shift_reg.sv \
- ../src/core/scr1_dmi.sv \
- ../src/core/primitives/scr1_reset_cells.sv \
- ../src/core/pipeline/scr1_pipe_ifu.sv \
- ../src/core/pipeline/scr1_pipe_idu.sv \
- ../src/core/pipeline/scr1_pipe_exu.sv \
- ../src/core/pipeline/scr1_pipe_mprf.sv \
- ../src/core/pipeline/scr1_pipe_csr.sv \
- ../src/core/pipeline/scr1_pipe_ialu.sv \
- ../src/core/pipeline/scr1_pipe_mul.sv \
- ../src/core/pipeline/scr1_pipe_div.sv \
- ../src/core/pipeline/scr1_pipe_lsu.sv \
- ../src/core/pipeline/scr1_pipe_hdu.sv \
- ../src/core/pipeline/scr1_pipe_tdu.sv \
- ../src/core/pipeline/scr1_ipic.sv \
- ../src/top/scr1_dmem_router.sv \
- ../src/top/scr1_imem_router.sv \
- ../src/top/scr1_tcm.sv \
- ../src/top/scr1_timer.sv \
- ../src/top/scr1_intf.sv \
- ../src/top/scr1_top_wb.sv \
- ../src/top/scr1_dmem_wb.sv \
- ../src/top/scr1_imem_wb.sv \
- ../../../lib/clk_skew_adjust.gv \
- ../../../lib/ctech_cells.sv \
- ../../../lib/async_fifo.sv ]
-
-#set ::env(VERILOG_FILES_BLACKBOX) [glob \
-# $::env(DESIGN_DIR)/src/top/scr1_dp_memory.sv ]
-
-set ::env(VERILOG_INCLUDE_DIRS) [glob $::env(DESIGN_DIR)/src/includes]
-
-set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-#set ::env(SYNTH_DEFINES) [list SCR1_DBG_EN SCR1_MPRF_RAM ]
-
-set ::env(SYNTH_READ_BLACKBOX_LIB) 1
-
-set ::env(LIB_SYNTH) ./tmp/trimmed.lib
-set ::env(LIB_SYNTH_COMPLETE_NO_PG) ./tmp/sky130_fd_sc_hd__tt_025C_1v80.no_pg.lib
-
-
-set ::env(SDC_FILE) "base.sdc"
-
-# Fill this
-set ::env(CLOCK_PERIOD) "10"
-set ::env(CLOCK_PORT) "wb_clk core_clk rtc_clk"
-set ::env(CLOCK_TREE_SYNTH) 0
-
-set ::env(SYNTH_BUFFERING) 1
-set ::env(SYNTH_SIZING) 1
-
-set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
-set ::env(SYNTH_CAP_LOAD) "17.65"
-set ::env(SYNTH_MAX_TRAN) "[expr {0.1*10.0}]"
-
-set ::env(SYNTH_MAX_FANOUT) 6
-
-set ::env(SYNTH_NO_FLAT) "1"
-
-
-set ::env(SYNTH_STRATEGY) "AREA 0"
-set ::env(SYNTH_TIELO_PORT) "sky130_fd_sc_hd__conb_1 LO"
-set ::env(SYNTH_TIEHI_PORT) "sky130_fd_sc_hd__conb_1 HI"
-set ::env(SYNTH_MIN_BUF_PORT) "sky130_fd_sc_hd__buf_2 A X"
-
-
-set ::env(CLOCK_NET) $::env(CLOCK_PORT)
-
-
-
-set ::env(yosys_tmp_file_tag) "./tmp/"
-set ::env(TMP_DIR) "./tmp/"
-set ::env(yosys_netlist_dir) "./netlist"
-set ::env(yosys_report_file_tag) "./reports/yosys"
-set ::env(yosys_result_file_tag) "./reports/yosys.synthesis"
-
-set ::env(SAVE_NETLIST) $::env(yosys_netlist_dir)/$::env(DESIGN_NAME).gv
-
-
-
-########### End of config.tcl
-set buffering $::env(SYNTH_BUFFERING)
-set sizing $::env(SYNTH_SIZING)
-
-yosys -import
-
-set vtop $::env(DESIGN_NAME)
-set sdc_file $::env(SDC_FILE)
-set sclib $::env(LIB_SYNTH)
-
-if { [info exists ::env(SYNTH_DEFINES) ] } {
- foreach define $::env(SYNTH_DEFINES) {
- log "Defining $define"
- verilog_defines -D$define
- }
-}
-
-set vIdirsArgs ""
-if {[info exist ::env(VERILOG_INCLUDE_DIRS)]} {
- foreach dir $::env(VERILOG_INCLUDE_DIRS) {
- log "Adding include file -I$dir "
- lappend vIdirsArgs "-I$dir"
- }
- set vIdirsArgs [join $vIdirsArgs]
-}
-
-if { $::env(SYNTH_READ_BLACKBOX_LIB) } {
- log "Reading $::env(LIB_SYNTH_COMPLETE_NO_PG) as a blackbox"
- read_liberty -lib -ignore_miss_dir -setattr blackbox $::env(LIB_SYNTH_COMPLETE_NO_PG)
-}
-
-
-if { [info exists ::env(EXTRA_LIBS) ] } {
- foreach lib $::env(EXTRA_LIBS) {
- read_liberty {*}$vIdirsArgs -lib -ignore_miss_dir -setattr blackbox $lib
- }
-}
-
-
-
-# ns expected (in sdc as well)
-set clock_period [expr {$::env(CLOCK_PERIOD)*1000}]
-
-set driver $::env(SYNTH_DRIVING_CELL)
-set cload $::env(SYNTH_CAP_LOAD)
-# input pin cap of IN_3VX8
-set max_FO $::env(SYNTH_MAX_FANOUT)
-if {![info exist ::env(SYNTH_MAX_TRAN)]} {
- set ::env(SYNTH_MAX_TRAN) [expr {0.1*$clock_period}]
-} else {
- set ::env(SYNTH_MAX_TRAN) [expr {$::env(SYNTH_MAX_TRAN) * 1000}]
-}
-set max_Tran $::env(SYNTH_MAX_TRAN)
-
-
-# Mapping parameters
-set A_factor 0.00
-set B_factor 0.88
-set F_factor 0.00
-
-# Don't change these unless you know what you are doing
-set stat_ext ".stat.rpt"
-set chk_ext ".chk.rpt"
-set gl_ext ".gl.v"
-set constr_ext ".$clock_period.constr"
-set timing_ext ".timing.txt"
-set abc_ext ".abc"
-
-
-# get old sdc, add library specific stuff for abc scripts
-#set sdc_file $::env(yosys_tmp_file_tag).sdc
-#set outfile [open ${sdc_file} w]
-#puts $outfile $sdc_data
-#puts $outfile "set_driving_cell ${driver}"
-#puts $outfile "set_load ${cload}"
-#close $outfile
-
-
-# ABC Scrips
-set abc_rs_K "resub,-K,"
-set abc_rs "resub"
-set abc_rsz "resub,-z"
-set abc_rw_K "rewrite,-K,"
-set abc_rw "rewrite"
-set abc_rwz "rewrite,-z"
-set abc_rf "refactor"
-set abc_rfz "refactor,-z"
-set abc_b "balance"
-
-set abc_resyn2 "${abc_b}; ${abc_rw}; ${abc_rf}; ${abc_b}; ${abc_rw}; ${abc_rwz}; ${abc_b}; ${abc_rfz}; ${abc_rwz}; ${abc_b}"
-set abc_share "strash; multi,-m; ${abc_resyn2}"
-set abc_resyn2a "${abc_b};${abc_rw};${abc_b};${abc_rw};${abc_rwz};${abc_b};${abc_rwz};${abc_b}"
-set abc_resyn3 "balance;resub;resub,-K,6;balance;resub,-z;resub,-z,-K,6;balance;resub,-z,-K,5;balance"
-set abc_resyn2rs "${abc_b};${abc_rs_K},6;${abc_rw};${abc_rs_K},6,-N,2;${abc_rf};${abc_rs_K},8;${abc_rw};${abc_rs_K},10;${abc_rwz};${abc_rs_K},10,-N,2;${abc_b},${abc_rs_K},12;${abc_rfz};${abc_rs_K},12,-N,2;${abc_rwz};${abc_b}"
-
-set abc_choice "fraig_store; ${abc_resyn2}; fraig_store; ${abc_resyn2}; fraig_store; fraig_restore"
-set abc_choice2 "fraig_store; balance; fraig_store; ${abc_resyn2}; fraig_store; ${abc_resyn2}; fraig_store; ${abc_resyn2}; fraig_store; fraig_restore"
-
-set abc_map_old_cnt "map,-p,-a,-B,0.2,-A,0.9,-M,0"
-set abc_map_old_dly "map,-p,-B,0.2,-A,0.9,-M,0"
-set abc_retime_area "retime,-D,{D},-M,5"
-set abc_retime_dly "retime,-D,{D},-M,6"
-set abc_map_new_area "amap,-m,-Q,0.1,-F,20,-A,20,-C,5000"
-
-set abc_area_recovery_1 "${abc_choice}; map;"
-set abc_area_recovery_2 "${abc_choice2}; map;"
-
-set map_old_cnt "map,-p,-a,-B,0.2,-A,0.9,-M,0"
-set map_old_dly "map,-p,-B,0.2,-A,0.9,-M,0"
-set abc_retime_area "retime,-D,{D},-M,5"
-set abc_retime_dly "retime,-D,{D},-M,6"
-set abc_map_new_area "amap,-m,-Q,0.1,-F,20,-A,20,-C,5000"
-
-if {$buffering==1} {
- set abc_fine_tune "buffer,-N,${max_FO},-S,${max_Tran};upsize,{D};dnsize,{D}"
-} elseif {$sizing} {
- set abc_fine_tune "upsize,{D};dnsize,{D}"
-} else {
- set abc_fine_tune ""
-}
-
-
-set delay_scripts [list \
- "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_dly}; scleanup;${abc_map_old_dly};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
- \
- "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_dly}; scleanup;${abc_choice2};${abc_map_old_dly};${abc_area_recovery_2}; retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
- \
- "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_dly}; scleanup;${abc_choice};${abc_map_old_dly};${abc_area_recovery_1}; retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
- \
- "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_old_dly};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
- ]
-
-set area_scripts [list \
- "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
- \
- "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_new_area};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
- \
- "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_choice2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_new_area};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
- ]
-
-set all_scripts [list {*}$delay_scripts {*}$area_scripts]
-
-set strategy_parts [split $::env(SYNTH_STRATEGY)]
-
-proc synth_strategy_format_err { } {
- upvar area_scripts area_scripts
- upvar delay_scripts delay_scripts
- log -stderr "\[ERROR] Misformatted SYNTH_STRATEGY (\"$::env(SYNTH_STRATEGY)\")."
- log -stderr "\[ERROR] Correct format is \"DELAY|AREA 0-[expr [llength $delay_scripts]-1]|0-[expr [llength $area_scripts]-1]\"."
- exit 1
-}
-
-if { [llength $strategy_parts] != 2 } {
- synth_strategy_format_err
-}
-
-set strategy_type [lindex $strategy_parts 0]
-set strategy_type_idx [lindex $strategy_parts 1]
-
-if { $strategy_type != "AREA" && $strategy_type != "DELAY" } {
- log -stderr "\[ERROR] AREA|DELAY tokens not found. ($strategy_type)"
- synth_strategy_format_err
-}
-
-if { $strategy_type == "DELAY" && $strategy_type_idx >= [llength $delay_scripts] } {
- log -stderr "\[ERROR] strategy index ($strategy_type_idx) is too high."
- synth_strategy_format_err
-}
-
-if { $strategy_type == "AREA" && $strategy_type_idx >= [llength $area_scripts] } {
- log -stderr "\[ERROR] strategy index ($strategy_type_idx) is too high."
- synth_strategy_format_err
-}
-
-if { $strategy_type == "DELAY" } {
- set strategy $strategy_type_idx
-} else {
- set strategy [expr {[llength $delay_scripts]+$strategy_type_idx}]
-}
-
-
-for { set i 0 } { $i < [llength $::env(VERILOG_FILES)] } { incr i } {
- read_verilog -sv {*}$vIdirsArgs [lindex $::env(VERILOG_FILES) $i]
-}
-
-if { [info exists ::env(VERILOG_FILES_BLACKBOX)] } {
- foreach verilog_file $::env(VERILOG_FILES_BLACKBOX) {
- read_verilog -sv {*}$vIdirsArgs -lib $verilog_file
- }
-}
-select -module $vtop
-show -format dot -prefix $::env(TMP_DIR)/synthesis/hierarchy
-select -clear
-
-hierarchy -check -top $vtop
-
-# Infer tri-state buffers.
-set tbuf_map false
-if { [info exists ::env(TRISTATE_BUFFER_MAP)] } {
- if { [file exists $::env(TRISTATE_BUFFER_MAP)] } {
- set tbuf_map true
- tribuf
- } else {
- log "WARNING: TRISTATE_BUFFER_MAP is defined but could not be found: $::env(TRISTATE_BUFFER_MAP)"
- }
-}
-
-if { $::env(SYNTH_NO_FLAT) } {
- synth -top $vtop
-} else {
- synth -top $vtop -flatten
-}
-
-share -aggressive
-opt
-opt_clean -purge
-
-tee -o "$::env(yosys_report_file_tag)_pre.stat" stat
-
-# Map tri-state buffers.
-if { $tbuf_map } {
- log {mapping tbuf}
- techmap -map $::env(TRISTATE_BUFFER_MAP)
- simplemap
-}
-
-# handle technology mapping of 4-MUX, and tell Yosys to infer 4-muxes
-if { [info exists ::env(SYNTH_MUX4_MAP)] && [file exists $::env(SYNTH_MUX4_MAP)] } {
- muxcover -mux4
- techmap -map $::env(SYNTH_MUX4_MAP)
- simplemap
-}
-
-# handle technology mapping of 2-MUX
-if { [info exists ::env(SYNTH_MUX_MAP)] && [file exists $::env(SYNTH_MUX_MAP)] } {
- techmap -map $::env(SYNTH_MUX_MAP)
- simplemap
-}
-
-# handle technology mapping of latches
-if { [info exists ::env(SYNTH_LATCH_MAP)] && [file exists $::env(SYNTH_LATCH_MAP)] } {
- techmap -map $::env(SYNTH_LATCH_MAP)
- simplemap
-}
-
-dfflibmap -liberty $sclib
-tee -o "$::env(yosys_report_file_tag)_dff.stat" stat
-
-if { [info exists ::env(SYNTH_EXPLORE)] && $::env(SYNTH_EXPLORE) } {
- design -save myDesign
-
- for { set index 0 } { $index < [llength $all_scripts] } { incr index } {
- log "\[INFO\]: ABC: WireLoad : S_$index"
- design -load myDesign
-
- abc -D $clock_period \
- -constr "$sdc_file" \
- -liberty $sclib \
- -script [lindex $all_scripts $index]
-
- setundef -zero
-
- hilomap -hicell {*}$::env(SYNTH_TIEHI_PORT) -locell {*}$::env(SYNTH_TIELO_PORT)
-
- # get rid of the assignments that make verilog2def fail
- splitnets
- opt_clean -purge
- insbuf -buf {*}$::env(SYNTH_MIN_BUF_PORT)
-
- tee -o "$::env(yosys_report_file_tag)_$index$chk_ext" check
- write_verilog -noattr -noexpr -nohex -nodec -defparam "$::env(yosys_result_file_tag)_$index.v"
- design -reset
- }
-} else {
-
- log "\[INFO\]: ABC: WireLoad : S_$strategy"
-
- abc -D $clock_period \
- -constr "$sdc_file" \
- -liberty $sclib \
- -script [lindex $all_scripts $strategy] \
- -showtmp;
-
- setundef -zero
-
- hilomap -hicell {*}$::env(SYNTH_TIEHI_PORT) -locell {*}$::env(SYNTH_TIELO_PORT)
-
- # get rid of the assignments that make verilog2def fail
- splitnets
- opt_clean -purge
- insbuf -buf {*}$::env(SYNTH_MIN_BUF_PORT)
-
- tee -o "$::env(yosys_report_file_tag)_$strategy$chk_ext" check
- write_verilog -noattr -noexpr -nohex -nodec -defparam "$::env(SAVE_NETLIST)"
-}
-
-#if { $::env(SYNTH_NO_FLAT) } {
-# design -reset
-# file copy -force $::env(SAVE_NETLIST) $::env(yosys_tmp_file_tag)_unflat.v
-# read_verilog -sv $::env(SAVE_NETLIST)
-# synth -top $vtop -flatten
-# splitnets
-# opt_clean -purge
-# insbuf -buf {*}$::env(SYNTH_MIN_BUF_PORT)
-# write_verilog -noattr -noexpr -nohex -nodec -defparam "$::env(SAVE_NETLIST)"
-# tee -o "$::env(yosys_report_file_tag)_$strategy$chk_ext" check
-#}
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 1b7e48c..b9fc454 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -30,7 +30,7 @@
`include "uart_i2cm.v"
`include "wb_interconnect.v"
`include "user_project_wrapper.v"
- `include "syntacore.v"
+ `include "yifive.v"
`include "wb_host.v"
`include "clk_skew_adjust.v"
`include "clk_buf.v"
@@ -110,39 +110,39 @@
`include "wb_interconnect/src/wb_interconnect.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_ipic.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_mul.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_div.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv"
- `include "syntacore/scr1/src/core/primitives/scr1_reset_cells.sv"
- `include "syntacore/scr1/src/core/primitives/scr1_cg.sv"
- `include "syntacore/scr1/src/core/scr1_clk_ctrl.sv"
- `include "syntacore/scr1/src/core/scr1_tapc_shift_reg.sv"
- `include "syntacore/scr1/src/core/scr1_tapc.sv"
- `include "syntacore/scr1/src/core/scr1_tapc_synchronizer.sv"
- `include "syntacore/scr1/src/core/scr1_core_top.sv"
- `include "syntacore/scr1/src/core/scr1_dm.sv"
- `include "syntacore/scr1/src/core/scr1_dmi.sv"
- `include "syntacore/scr1/src/core/scr1_scu.sv"
+ `include "yifive/ycr1/src/core/pipeline/ycr1_pipe_hdu.sv"
+ `include "yifive/ycr1/src/core/pipeline/ycr1_pipe_tdu.sv"
+ `include "yifive/ycr1/src/core/pipeline/ycr1_ipic.sv"
+ `include "yifive/ycr1/src/core/pipeline/ycr1_pipe_csr.sv"
+ `include "yifive/ycr1/src/core/pipeline/ycr1_pipe_exu.sv"
+ `include "yifive/ycr1/src/core/pipeline/ycr1_pipe_ialu.sv"
+ `include "yifive/ycr1/src/core/pipeline/ycr1_pipe_idu.sv"
+ `include "yifive/ycr1/src/core/pipeline/ycr1_pipe_ifu.sv"
+ `include "yifive/ycr1/src/core/pipeline/ycr1_pipe_lsu.sv"
+ `include "yifive/ycr1/src/core/pipeline/ycr1_pipe_mprf.sv"
+ `include "yifive/ycr1/src/core/pipeline/ycr1_pipe_mul.sv"
+ `include "yifive/ycr1/src/core/pipeline/ycr1_pipe_div.sv"
+ `include "yifive/ycr1/src/core/pipeline/ycr1_pipe_top.sv"
+ `include "yifive/ycr1/src/core/primitives/ycr1_reset_cells.sv"
+ `include "yifive/ycr1/src/core/primitives/ycr1_cg.sv"
+ `include "yifive/ycr1/src/core/ycr1_clk_ctrl.sv"
+ `include "yifive/ycr1/src/core/ycr1_tapc_shift_reg.sv"
+ `include "yifive/ycr1/src/core/ycr1_tapc.sv"
+ `include "yifive/ycr1/src/core/ycr1_tapc_synchronizer.sv"
+ `include "yifive/ycr1/src/core/ycr1_core_top.sv"
+ `include "yifive/ycr1/src/core/ycr1_dm.sv"
+ `include "yifive/ycr1/src/core/ycr1_dmi.sv"
+ `include "yifive/ycr1/src/core/ycr1_scu.sv"
- `include "syntacore/scr1/src/top/scr1_imem_router.sv"
- `include "syntacore/scr1/src/top/scr1_dmem_router.sv"
- `include "syntacore/scr1/src/top/scr1_dp_memory.sv"
- `include "syntacore/scr1/src/top/scr1_tcm.sv"
- `include "syntacore/scr1/src/top/scr1_timer.sv"
- `include "syntacore/scr1/src/top/scr1_dmem_wb.sv"
- `include "syntacore/scr1/src/top/scr1_imem_wb.sv"
- `include "syntacore/scr1/src/top/scr1_intf.sv"
- `include "syntacore/scr1/src/top/scr1_top_wb.sv"
+ `include "yifive/ycr1/src/top/ycr1_imem_router.sv"
+ `include "yifive/ycr1/src/top/ycr1_dmem_router.sv"
+ `include "yifive/ycr1/src/top/ycr1_dp_memory.sv"
+ `include "yifive/ycr1/src/top/ycr1_tcm.sv"
+ `include "yifive/ycr1/src/top/ycr1_timer.sv"
+ `include "yifive/ycr1/src/top/ycr1_dmem_wb.sv"
+ `include "yifive/ycr1/src/top/ycr1_imem_wb.sv"
+ `include "yifive/ycr1/src/top/ycr1_intf.sv"
+ `include "yifive/ycr1/src/top/ycr1_top_wb.sv"
`include "lib/sync_fifo.sv"
`include "mbist/src/core/mbist_addr_gen.sv"
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 0a00b92..7b39611 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -147,6 +147,9 @@
//// TCM RAM Bug fix inside syntacore ////
//// 2.6 Jan 08, 2022, Dinesh A ////
//// Pinmux Interrupt Logic change ////
+//// 3.0 Jan 14, 2022, Dinesh A ////
+//// Moving from riscv core from syntacore/scr1 to ////
+//// yfive/ycr1 on sankranti 2022 (A Hindu New Year) ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
@@ -673,7 +676,7 @@
//------------------------------------------------------------------------------
// RISC V Core instance
//------------------------------------------------------------------------------
-scr1_top_wb u_riscv_top (
+ycr1_top_wb u_riscv_top (
`ifdef USE_POWER_PINS
.vccd1 (vccd1 ),// User area 1 1.8V supply
.vssd1 (vssd1 ),// User area 1 digital ground
diff --git a/verilog/rtl/yifive/ycr1 b/verilog/rtl/yifive/ycr1
new file mode 160000
index 0000000..f7438dc
--- /dev/null
+++ b/verilog/rtl/yifive/ycr1
@@ -0,0 +1 @@
+Subproject commit f7438dc651a838e2e922f6dc1753949329e7b5a9
