sdram ctrl bug fix tRAS violation, changed the define to ASIC
diff --git a/verilog/rtl/sdram_ctrl/src/core/sdrc_bank_fsm.v b/verilog/rtl/sdram_ctrl/src/core/sdrc_bank_fsm.v
index d566f6f..2ce60d3 100755
--- a/verilog/rtl/sdram_ctrl/src/core/sdrc_bank_fsm.v
+++ b/verilog/rtl/sdram_ctrl/src/core/sdrc_bank_fsm.v
@@ -34,6 +34,11 @@
Author(s):
- Dinesh Annayya, dinesha@opencores.org
Version : 1.0 - 8th Jan 2012
+ Version : 1.1 - 27th Aug 2021
+ Disabling the `TARGET_DESIGN with FPGA, Breaking timing path creating functional issue
+ Recommnended to use onlt in ASIC Mode. In FPGA mode, tRAS violation are noticed and design
+ has corner case between Active to Pre-charge
+ ERROR: tRAS violation during Precharge all bank
diff --git a/verilog/rtl/sdram_ctrl/src/defs/sdrc_define.v b/verilog/rtl/sdram_ctrl/src/defs/sdrc_define.v
index 2430831..018c683 100755
--- a/verilog/rtl/sdram_ctrl/src/defs/sdrc_define.v
+++ b/verilog/rtl/sdram_ctrl/src/defs/sdrc_define.v
@@ -41,8 +41,10 @@
`define SDR_MODE 4'b0000
`define ASIC 1'b1
-`define FPGA 1'b0
-`define TARGET_DESIGN `FPGA
+`define FPGA 1'b0
+// Don't Enable FPGA mode, there is functional bug in handling Active to
+// Precharge timing
+`define TARGET_DESIGN `ASIC
// 12 bit subtractor is not feasibile for FPGA, so changed to 6 bits
`define REQ_BW (`TARGET_DESIGN == `FPGA) ? 6 : 12 // Request Width
diff --git a/verilog/rtl/sdram_ctrl/src/top/sdrc_top.v b/verilog/rtl/sdram_ctrl/src/top/sdrc_top.v
index c845d02..cff5e76 100755
--- a/verilog/rtl/sdram_ctrl/src/top/sdrc_top.v
+++ b/verilog/rtl/sdram_ctrl/src/top/sdrc_top.v
@@ -59,7 +59,11 @@
Wishbone Stagging FF added to break timing path
0.6 - 6th July 2021, Dinesh A
32 bit debug port added
-
+ 0.7 - 27th Aug 2021, Dinesh A
+ Disabling the `TARGET_DESIGN with FPGA define , Breaking timing path creating functional issue
+ Recommnended to use onlt in ASIC Mode. In FPGA mode, tRAS violation are noticed and design
+ has corner case between Active to Pre-charge
+ ERROR: tRAS violation during Precharge all bank
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