updated database
diff --git a/openlane/glbl_cfg/config.tcl b/openlane/glbl_cfg/config.tcl
index 7040413..3dbd66b 100755
--- a/openlane/glbl_cfg/config.tcl
+++ b/openlane/glbl_cfg/config.tcl
@@ -4,9 +4,7 @@
set script_dir [file dirname [file normalize [info script]]]
# Name
set ::env(DESIGN_NAME) glbl_cfg
-set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
-#set ::env(SYNTH_READ_BLACKBOX_LIB) 1
# Timing configuration
set ::env(CLOCK_PERIOD) "10"
@@ -43,25 +41,18 @@
set ::env(DIE_AREA) "0 0 300 400"
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
-set ::env(FP_PDN_VPITCH) 50
#set ::env(PDN_CFG) $script_dir/pdn.tcl
-set ::env(FP_VERTICAL_HALO) 6
-set ::env(PL_TARGET_DENSITY) 0.52
-set ::env(PL_TARGET_DENSITY_CELLS) 0.38
-set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 1
-set ::env(CELL_PAD) 4
-set ::env(GLB_RT_ADJUSTMENT) 0
-set ::env(GLB_RT_L2_ADJUSTMENT) 0.2
-set ::env(GLB_RT_L3_ADJUSTMENT) 0.25
-set ::env(GLB_RT_L4_ADJUSTMENT) 0.2
-set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
-set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
-set ::env(GLB_RT_TILES) 14
-set ::env(GLB_RT_MAXLAYER) 5
+set ::env(PL_ROUTABILITY_DRIVEN) 1
-set ::env(DIODE_INSERTION_STRATEGY) 4
+set ::env(FP_IO_VEXTEND) 4
+set ::env(FP_IO_HEXTEND) 4
+set ::env(GLB_RT_MAXLAYER) 4
+set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+
diff --git a/openlane/sdram/config.tcl b/openlane/sdram/config.tcl
index 6d25773..45febad 100755
--- a/openlane/sdram/config.tcl
+++ b/openlane/sdram/config.tcl
@@ -47,25 +47,18 @@
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
-set ::env(FP_PDN_VPITCH) 50
#set ::env(PDN_CFG) $script_dir/pdn.tcl
-set ::env(FP_VERTICAL_HALO) 6
-set ::env(PL_TARGET_DENSITY) 0.52
-set ::env(PL_TARGET_DENSITY_CELLS) 0.38
-set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 1
-set ::env(CELL_PAD) 4
-set ::env(GLB_RT_ADJUSTMENT) 0
-set ::env(GLB_RT_L2_ADJUSTMENT) 0.2
-set ::env(GLB_RT_L3_ADJUSTMENT) 0.25
-set ::env(GLB_RT_L4_ADJUSTMENT) 0.2
-set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
-set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
-set ::env(GLB_RT_TILES) 14
-set ::env(GLB_RT_MAXLAYER) 5
+set ::env(PL_ROUTABILITY_DRIVEN) 1
-set ::env(DIODE_INSERTION_STRATEGY) 4
+set ::env(FP_IO_VEXTEND) 4
+set ::env(FP_IO_HEXTEND) 4
+set ::env(GLB_RT_MAXLAYER) 4
+set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+
diff --git a/openlane/spi_master/config.tcl b/openlane/spi_master/config.tcl
index c7cb2cb..2e9aa93 100755
--- a/openlane/spi_master/config.tcl
+++ b/openlane/spi_master/config.tcl
@@ -42,25 +42,18 @@
set ::env(DIE_AREA) "0 0 400 600"
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
-set ::env(FP_PDN_VPITCH) 50
#set ::env(PDN_CFG) $script_dir/pdn.tcl
-set ::env(FP_VERTICAL_HALO) 6
-set ::env(PL_TARGET_DENSITY) 0.52
-set ::env(PL_TARGET_DENSITY_CELLS) 0.38
-set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 1
-set ::env(CELL_PAD) 4
-set ::env(GLB_RT_ADJUSTMENT) 0
-set ::env(GLB_RT_L2_ADJUSTMENT) 0.2
-set ::env(GLB_RT_L3_ADJUSTMENT) 0.25
-set ::env(GLB_RT_L4_ADJUSTMENT) 0.2
-set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
-set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
-set ::env(GLB_RT_TILES) 14
-set ::env(GLB_RT_MAXLAYER) 5
+set ::env(PL_ROUTABILITY_DRIVEN) 1
-set ::env(DIODE_INSERTION_STRATEGY) 4
+set ::env(FP_IO_VEXTEND) 4
+set ::env(FP_IO_HEXTEND) 4
+set ::env(GLB_RT_MAXLAYER) 4
+set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+
diff --git a/openlane/syntacore/config.tcl b/openlane/syntacore/config.tcl
index 1b4c673..568494b 100755
--- a/openlane/syntacore/config.tcl
+++ b/openlane/syntacore/config.tcl
@@ -5,7 +5,6 @@
# Name
set ::env(DESIGN_NAME) scr1_top_wb
-set ::env(SYNTH_READ_BLACKBOX_LIB) 1
# Timing configuration
set ::env(CLOCK_PERIOD) "10"
@@ -63,32 +62,25 @@
# Floorplanning
# -------------
-#set ::env(FP_DEF_TEMPLATE) $script_dir/floorplan.def
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) [list 0.0 0.0 1500.0 1200.0]
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
-set ::env(FP_PDN_VPITCH) 50
#set ::env(PDN_CFG) $script_dir/pdn.tcl
-set ::env(FP_VERTICAL_HALO) 6
-set ::env(PL_TARGET_DENSITY) 0.52
-set ::env(PL_TARGET_DENSITY_CELLS) 0.38
-set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 1
-set ::env(CELL_PAD) 4
-set ::env(GLB_RT_ADJUSTMENT) 0
-set ::env(GLB_RT_L2_ADJUSTMENT) 0.2
-set ::env(GLB_RT_L3_ADJUSTMENT) 0.25
-set ::env(GLB_RT_L4_ADJUSTMENT) 0.2
-set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
-set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
-set ::env(GLB_RT_TILES) 14
+set ::env(PL_ROUTABILITY_DRIVEN) 1
+#set ::env(PL_BASIC_PLACEMENT) "1"
+
+set ::env(FP_IO_VEXTEND) 4
+set ::env(FP_IO_HEXTEND) 4
+
+
set ::env(GLB_RT_MAXLAYER) 5
-
-set ::env(DIODE_INSERTION_STRATEGY) 4
-
+set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
diff --git a/openlane/uart/config.tcl b/openlane/uart/config.tcl
index b0d2b84..b43cb74 100644
--- a/openlane/uart/config.tcl
+++ b/openlane/uart/config.tcl
@@ -48,25 +48,18 @@
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
-set ::env(FP_PDN_VPITCH) 50
#set ::env(PDN_CFG) $script_dir/pdn.tcl
-set ::env(FP_VERTICAL_HALO) 6
-set ::env(PL_TARGET_DENSITY) 0.52
-set ::env(PL_TARGET_DENSITY_CELLS) 0.38
-set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 1
-set ::env(CELL_PAD) 4
-set ::env(GLB_RT_ADJUSTMENT) 0
-set ::env(GLB_RT_L2_ADJUSTMENT) 0.2
-set ::env(GLB_RT_L3_ADJUSTMENT) 0.25
-set ::env(GLB_RT_L4_ADJUSTMENT) 0.2
-set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
-set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
-set ::env(GLB_RT_TILES) 14
-set ::env(GLB_RT_MAXLAYER) 5
+set ::env(PL_ROUTABILITY_DRIVEN) 1
-set ::env(DIODE_INSERTION_STRATEGY) 4
+set ::env(FP_IO_VEXTEND) 4
+set ::env(FP_IO_HEXTEND) 4
+set ::env(GLB_RT_MAXLAYER) 4
+set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index eee22e7..3908fab 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -83,10 +83,12 @@
set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore/scr1/src/includes $script_dir/../../verilog/rtl/sdram_ctrl/src/defs ]
-set ::env(GLB_RT_MAXLAYER) 4
+set ::env(GLB_RT_MAXLAYER) 5
set ::env(FP_PDN_CHECK_NODES) 0
+set ::env(RUN_KLAYOUT_DRC) 0
+
set ::env(VDD_PIN) [list {vccd1}]
set ::env(GND_PIN) [list {vssd1}]
@@ -106,3 +108,52 @@
set ::env(CLOCK_TREE_SYNTH) 0
set ::env(PL_DIAMOND_SEARCH_HEIGHT) "250"
+
+set ::env(GLB_RT_OBS) " \
+ met1 300.000000 2700.000000 700.000000 3300.000000, \
+ met2 300.000000 2700.000000 700.000000 3300.000000, \
+ met3 300.000000 2700.000000 700.000000 3300.000000, \
+ met4 300.000000 2700.000000 700.000000 3300.000000, \
+ met5 300.000000 2700.000000 700.000000 3300.000000, \
+ met1 1000.000000 2700.000000 1700.000000 3200.000000, \
+ met2 1000.000000 2700.000000 1700.000000 3200.000000, \
+ met3 1000.000000 2700.000000 1700.000000 3200.000000, \
+ met4 1000.000000 2700.000000 1700.000000 3200.000000, \
+ met5 1000.000000 2700.000000 1700.000000 3200.000000, \
+ met1 2000.000000 2700.000000 2300.000000 3100.000000, \
+ met2 2000.000000 2700.000000 2300.000000 3100.000000, \
+ met3 2000.000000 2700.000000 2300.000000 3100.000000, \
+ met4 2000.000000 2700.000000 2300.000000 3100.000000, \
+ met5 2000.000000 2700.000000 2300.000000 3100.000000, \
+ met1 300.000000 800.000000 1800.000000 2000.000000, \
+ met2 300.000000 800.000000 1800.000000 2000.000000, \
+ met3 300.000000 800.000000 1800.000000 2000.000000, \
+ met4 300.000000 800.000000 1800.000000 2000.000000, \
+ met5 300.000000 800.000000 1800.000000 2000.000000, \
+ met1 2000.000000 1600.000000 2300.000000 2000.000000, \
+ met2 2000.000000 1600.000000 2300.000000 2000.000000, \
+ met3 2000.000000 1600.000000 2300.000000 2000.000000, \
+ met4 2000.000000 1600.000000 2300.000000 2000.000000, \
+ met5 2000.000000 1600.000000 2300.000000 2000.000000, \
+ met1 300.0000 450.0000 650.0000 500.0000, \
+ met2 300.0000 450.0000 650.0000 500.0000, \
+ met3 300.0000 450.0000 650.0000 500.0000, \
+ met4 300.0000 450.0000 650.0000 500.0000, \
+ met5 300.0000 450.0000 650.0000 500.0000, \
+ met1 300.0000 1000.0000 650.0000 1100.0000, \
+ met2 300.0000 1000.0000 650.0000 1100.0000, \
+ met3 300.0000 1000.0000 650.0000 1100.0000, \
+ met4 300.0000 1000.0000 650.0000 1100.0000, \
+ met5 300.0000 1000.0000 650.0000 1100.0000, \
+ met1 300.0000 1700.0000 350.0000 1750.0000, \
+ met2 300.0000 1700.0000 350.0000 1750.0000, \
+ met3 300.0000 1700.0000 350.0000 1750.0000, \
+ met4 300.0000 1700.0000 350.0000 1750.0000, \
+ met5 300.0000 1700.0000 350.0000 1750.0000, \
+ met1 300.0000 3150.0000 350.0000 3200.0000, \
+ met2 300.0000 3150.0000 350.0000 3200.0000, \
+ met3 300.0000 3150.0000 350.0000 3200.0000, \
+ met4 300.0000 3150.0000 350.0000 3200.0000, \
+ met5 300.0000 3150.0000 350.0000 3200.0000 \
+ "
+
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
index dcf2828..6706f2a 100755
--- a/openlane/wb_host/config.tcl
+++ b/openlane/wb_host/config.tcl
@@ -40,19 +40,18 @@
set ::env(DIE_AREA) "0 0 1000 200"
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
-set ::env(FP_PDN_VPITCH) 50
#set ::env(PDN_CFG) $script_dir/pdn.tcl
-#set ::env(FP_VERTICAL_HALO) 6
-set ::env(PL_TARGET_DENSITY) 0.62
-set ::env(PL_TARGET_DENSITY_CELLS) 0.5
-set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 1
-#set ::env(CELL_PAD) 4
-set ::env(GLB_RT_TILES) 14
-set ::env(GLB_RT_MAXLAYER) 5
+set ::env(PL_ROUTABILITY_DRIVEN) 1
-set ::env(DIODE_INSERTION_STRATEGY) 4
+set ::env(FP_IO_VEXTEND) 4
+set ::env(FP_IO_HEXTEND) 4
+set ::env(GLB_RT_MAXLAYER) 4
+set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+
diff --git a/signoff/glbl_cfg/final_summary_report.csv b/signoff/glbl_cfg/final_summary_report.csv
index f364c36..f301c47 100644
--- a/signoff/glbl_cfg/final_summary_report.csv
+++ b/signoff/glbl_cfg/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/glbl_cfg,glbl_cfg,glbl_cfg,Flow_completed,0h4m54s,0h2m58s,47033.33333333334,0.12,23516.66666666667,42,525.0,2822,0,0,0,0,0,0,0,3,0,0,0,164082,23983,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,130105462,0.0,39.84,44.17,6.3,5.77,-1,2676,2872,476,672,0,0,0,2822,1,0,3,9,474,0,3,571,588,548,10,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,50,153.18,0.52,0,sky130_fd_sc_hd,4,4
+0,/project/openlane/glbl_cfg,glbl_cfg,glbl_cfg,Flow_completed,0h4m50s,0h3m3s,47033.33333333334,0.12,23516.66666666667,37,549.19,2822,0,0,0,0,0,0,0,1,0,-1,0,141778,20879,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,114388749,0.0,22.5,30.02,0.23,-1,-1,2676,2872,476,672,0,0,0,2822,1,0,3,9,474,0,3,571,588,548,10,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
diff --git a/signoff/sdram/final_summary_report.csv b/signoff/sdram/final_summary_report.csv
index 7679060..9bc481d 100644
--- a/signoff/sdram/final_summary_report.csv
+++ b/signoff/sdram/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/sdram,sdrc_top,sdram,Flow_completed,0h9m0s,0h4m10s,37194.28571428572,0.35,18597.14285714286,29,615.55,6509,0,0,0,0,0,0,0,1,0,0,0,317021,52641,-3.59,-3.59,-3.59,-3.59,-4.69,-3.59,-3.59,-3.59,-3.59,-4.69,248911505,0.0,35.34,22.72,5.59,0.95,-1,6444,6672,1140,1368,0,0,0,6509,132,107,80,108,350,212,30,2197,1189,1088,29,350,4248,0,4598,68.07351940095302,14.690000000000001,10,AREA 0,5,50,1,50,153.18,0.52,0,sky130_fd_sc_hd,4,4
+0,/project/openlane/sdram,sdrc_top,sdram,Flow_completed,0h9m21s,0h5m21s,37194.28571428572,0.35,18597.14285714286,25,636.34,6509,0,0,0,0,0,0,0,10,0,-1,0,288514,47774,-3.59,-3.59,-3.59,-3.59,-4.29,-3.59,-3.59,-3.59,-3.59,-4.29,227214856,0.0,19.78,15.07,1.47,-1,-1,6444,6672,1140,1368,0,0,0,6509,132,107,80,108,350,212,30,2197,1189,1088,29,350,4248,0,4598,69.97900629811058,14.29,10,AREA 0,5,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
diff --git a/signoff/spi_master/final_summary_report.csv b/signoff/spi_master/final_summary_report.csv
index 4cb3b80..5e8e8e6 100644
--- a/signoff/spi_master/final_summary_report.csv
+++ b/signoff/spi_master/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/spi_master,spim_top,spi_master,Flow_completed,0h6m23s,0h3m50s,25416.66666666667,0.24,12708.333333333336,22,570.17,3050,0,0,0,0,0,0,0,1,0,0,0,180296,28569,-1.48,-1.48,-1.98,-1.98,-2.67,-86.69,-86.69,-451.23,-451.23,-670.86,140719500,0.0,19.19,26.08,0.87,7.44,-1,3016,3128,433,545,0,0,0,3050,83,0,92,79,1118,89,19,920,527,458,28,424,2889,0,3313,78.92659826361484,12.67,10,AREA 0,4,50,1,50,153.18,0.52,0,sky130_fd_sc_hd,4,4
+0,/project/openlane/spi_master,spim_top,spi_master,Flow_completed,0h9m29s,0h6m55s,25416.66666666667,0.24,12708.333333333336,19,587.51,3050,0,0,0,0,0,0,0,5,0,-1,0,162786,26689,-1.48,-1.48,-1.55,-1.55,-2.28,-86.69,-86.69,-158.7,-158.7,-255.68,121954058,0.0,9.59,19.86,0.04,-1,-1,3016,3128,433,545,0,0,0,3050,83,0,92,79,1118,89,19,920,527,458,28,424,2889,0,3313,81.43322475570034,12.28,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
diff --git a/signoff/syntacore/final_summary_report.csv b/signoff/syntacore/final_summary_report.csv
index e34d613..7830877 100644
--- a/signoff/syntacore/final_summary_report.csv
+++ b/signoff/syntacore/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/syntacore,scr1_top_wb,syntacore,Flow_completed,0h51m0s,0h23m39s,34493.333333333336,1.8,17246.666666666668,25,1236.48,31044,0,0,0,0,0,0,0,7,2,0,0,1867015,273721,-0.26,-0.26,-0.42,-0.42,-0.49,-9.62,-9.62,-26.28,-26.28,-27.81,1569371612,0.0,34.83,24.33,13.44,3.98,-1,30930,31168,2806,3044,0,0,0,31044,619,0,692,2060,4036,2095,1327,7433,2838,2786,95,866,22836,0,23702,95.32888465204957,10.49,10,AREA 0,4,50,1,50,153.18,0.52,0,sky130_fd_sc_hd,4,4
+0,/project/openlane/syntacore,scr1_top_wb,syntacore,Flow_completed,0h55m24s,0h32m1s,34420.0,1.8,17210.0,23,1196.24,30978,0,0,0,0,0,0,0,84,2,-1,0,1618669,250632,-0.3,-0.3,-0.44,-0.44,-0.73,-12.11,-12.11,-18.83,-18.83,-29.4,1353757569,0.0,19.59,15.78,4.41,0.64,-1,30864,31102,2807,3045,0,0,0,30978,631,0,685,2044,4015,2105,1318,7432,2838,2786,94,866,22836,0,23702,93.19664492078284,10.73,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
diff --git a/signoff/uart/final_summary_report.csv b/signoff/uart/final_summary_report.csv
index d32ec61..6d20ca0 100644
--- a/signoff/uart/final_summary_report.csv
+++ b/signoff/uart/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/uart,uart_core,uart,Flow_completed,0h5m14s,0h3m20s,43433.333333333336,0.12,21716.666666666668,35,511.72,2606,0,0,0,0,0,0,0,0,0,0,0,95298,20096,-0.57,-0.57,-0.5,-0.5,-0.71,-40.55,-40.55,-33.82,-33.82,-56.54,70681058,0.0,25.01,28.03,0.33,2.03,-1,2605,2625,454,474,0,0,0,2606,59,0,30,41,182,125,26,685,435,396,16,278,1410,0,1688,93.37068160597572,10.71,10,AREA 0,5,50,1,50,153.18,0.52,0,sky130_fd_sc_hd,4,4
+0,/project/openlane/uart,uart_core,uart,Flow_completed,0h5m17s,0h3m27s,43433.333333333336,0.12,21716.666666666668,32,525.34,2606,0,0,0,0,0,0,0,0,0,-1,0,82639,18254,-0.57,-0.57,-0.5,-0.5,-0.67,-40.55,-40.55,-39.96,-39.96,-45.73,60185370,0.0,13.32,18.01,0.0,-1,-1,2605,2625,454,474,0,0,0,2606,59,0,30,41,182,125,26,685,435,396,16,278,1410,0,1688,93.72071227741331,10.67,10,AREA 0,5,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv
index 1116b1b..d8a99da 100644
--- a/signoff/wb_host/final_summary_report.csv
+++ b/signoff/wb_host/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_host,wb_host,wb_host,Flow_completed,0h6m30s,0h3m47s,35490.0,0.2,17745.0,28,592.36,3549,0,0,0,0,0,0,0,3,0,0,0,315592,33452,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,261952954,0.0,48.32,13.08,26.98,0.0,-1,3270,3912,529,1171,0,0,0,3549,85,0,5,9,30,27,13,915,660,813,16,130,2343,0,2473,100.0,10.0,10,AREA 0,4,50,1,50,153.18,0.62,0,sky130_fd_sc_hd,4,4
+0,/project/openlane/wb_host,wb_host,wb_host,Flow_completed,0h7m33s,0h4m35s,35490.0,0.2,17745.0,24,610.75,3549,0,0,0,0,0,0,0,22,0,-1,0,305549,29594,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,264347444,0.0,37.57,10.91,25.23,-1,-1,3270,3912,529,1171,0,0,0,3549,85,0,5,9,30,27,13,915,660,813,16,130,2343,137,2610,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
diff --git a/verilog/dv/user_uart/uprj_netlists.v b/verilog/dv/user_uart/uprj_netlists.v
index 1668caa..5e42730 100644
--- a/verilog/dv/user_uart/uprj_netlists.v
+++ b/verilog/dv/user_uart/uprj_netlists.v
@@ -23,48 +23,16 @@
`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
- `include "digital_core/src/digital_core.sv"
`include "glbl_cfg.v"
`include "sdram.v"
`include "spi_master.v"
`include "uart.v"
`include "wb_interconnect.v"
+ `include "user_project_wrapper.v"
- `include "wb_host/src/wb_host.sv"
- `include "lib/async_wb.sv"
- `include "lib/registers.v"
+ `include "syntacore.v"
+ `include "wb_host.v"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_ipic.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv"
- `include "syntacore/scr1/src/core/primitives/scr1_reset_cells.sv"
- `include "syntacore/scr1/src/core/primitives/scr1_cg.sv"
- `include "syntacore/scr1/src/core/scr1_clk_ctrl.sv"
- `include "syntacore/scr1/src/core/scr1_tapc_shift_reg.sv"
- `include "syntacore/scr1/src/core/scr1_tapc.sv"
- `include "syntacore/scr1/src/core/scr1_tapc_synchronizer.sv"
- `include "syntacore/scr1/src/core/scr1_core_top.sv"
- `include "syntacore/scr1/src/core/scr1_dm.sv"
- `include "syntacore/scr1/src/core/scr1_dmi.sv"
- `include "syntacore/scr1/src/core/scr1_scu.sv"
-
- `include "syntacore/scr1/src/top/scr1_dmem_router.sv"
- `include "syntacore/scr1/src/top/scr1_dp_memory.sv"
- `include "syntacore/scr1/src/top/scr1_tcm.sv"
- `include "syntacore/scr1/src/top/scr1_timer.sv"
- `include "syntacore/scr1/src/top/scr1_dmem_wb.sv"
- `include "syntacore/scr1/src/top/scr1_imem_wb.sv"
- `include "syntacore/scr1/src/top/scr1_top_wb.sv"
- `include "lib/sync_fifo.sv"
- `include "lib/async_fifo.sv"
`else
`include "spi_master/src/spim_top.sv"
`include "spi_master/src/spim_regs.sv"
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index 5a647ba..b1faa2f 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -132,8 +132,10 @@
`ifdef WFDUMP
initial begin
$dumpfile("risc_boot.vcd");
- $dumpvars(2, user_uart_tb);
- $dumpvars(4, user_uart_tb.u_top.u_core);
+ $dumpvars(4, user_uart_tb);
+
+ #1000;
+ $finish;
end
`endif
@@ -423,7 +425,7 @@
-
+/**
`ifdef GL
//-----------------------------------------------------------------------------
// RISC IMEM amd DMEM Monitoring TASK
@@ -441,5 +443,6 @@
end
`endif
+**/
endmodule
`default_nettype wire
