Test bench cleanup
diff --git a/Makefile b/Makefile
index 2b4cb64..3b4be48 100644
--- a/Makefile
+++ b/Makefile
@@ -71,10 +71,8 @@
PDK_PATH=${PDK_ROOT}/sky130A
VERIFY_COMMAND="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} DUMP=${DUMP} && make"
$(DV_PATTERNS): verify-% : ./verilog/dv/% check-coremark_repo check-riscv_comp_repo check-riscv_test_repo
- docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_PATH}:${PDK_PATH} \
- -v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
- -e TARGET_PATH=${TARGET_PATH} -e PDK_PATH=${PDK_PATH} \
- -e CARAVEL_ROOT=${CARAVEL_ROOT} \
+ docker run -v ${TARGET_PATH}:${TARGET_PATH} \
+ -e TARGET_PATH=${TARGET_PATH} \
-u $(id -u $$USER):$(id -g $$USER) dineshannayya/dv_setup:mpw5 \
sh -c $(VERIFY_COMMAND)
diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v
index bc4db63..2d0d7d5 100644
--- a/verilog/dv/risc_boot/risc_boot_tb.v
+++ b/verilog/dv/risc_boot/risc_boot_tb.v
@@ -71,6 +71,8 @@
`timescale 1 ns / 1 ps
+`define FULL_CHIP_SIM
+
`include "s25fl256s.sv"
`include "uprj_netlists.v"
`include "caravel_netlists.v"
diff --git a/verilog/dv/uart_master/uart_master_tb.v b/verilog/dv/uart_master/uart_master_tb.v
index 8a7f66e..4636dce 100644
--- a/verilog/dv/uart_master/uart_master_tb.v
+++ b/verilog/dv/uart_master/uart_master_tb.v
@@ -17,6 +17,8 @@
`timescale 1 ns / 1 ps
+`define FULL_CHIP_SIM
+
`include "uprj_netlists.v"
`include "caravel_netlists.v"
`include "spiflash.v"
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile
index a19be6a..c135403 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/wb_port/Makefile
@@ -82,7 +82,7 @@
%.vcd: %.vvp
vvp $<
-%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env
+%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s
${GCC64_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
%.hex: %.elf
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v
index 88e8bee..1d8eec5 100644
--- a/verilog/dv/wb_port/wb_port_tb.v
+++ b/verilog/dv/wb_port/wb_port_tb.v
@@ -17,6 +17,8 @@
`timescale 1 ns / 1 ps
+`define FULL_CHIP_SIM
+
`include "uprj_netlists.v"
`include "caravel_netlists.v"
`include "spiflash.v"
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 0652188..95c770a 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -148,7 +148,11 @@
`include "lib/sync_fifo.sv"
- `include "DFFRAM/DFFRAM.v"
+ // During Full Chip Sim, DFFRAM file already available in caravel file
+ // list
+ `ifndef FULL_CHIP_SIM
+ `include "DFFRAM/DFFRAM.v"
+ `endif
`include "uart2wb/src/uart2wb.sv"
`include "uart2wb/src/uart2_core.sv"
diff --git a/verilog/rtl/yifive/ycr1c b/verilog/rtl/yifive/ycr1c
index e61495a..2bab521 160000
--- a/verilog/rtl/yifive/ycr1c
+++ b/verilog/rtl/yifive/ycr1c
@@ -1 +1 @@
-Subproject commit e61495abf5c9236e00da7d2ef1f39a7b3451a087
+Subproject commit 2bab521595455a42acee88f7e0fd3747f1806581
