commit 3a14cafce74a908c0c79e62d52d80290b9287075
author dineshannayya <dinesh.annayya@gmail.com> Mon Aug 01 13:26:12 2022 +0530
committer dineshannayya <dinesh.annayya@gmail.com> Mon Aug 01 13:26:12 2022 +0530
tree 56a16fd5f10738a044e346456e679579c918e1ed
parent 919060200e743838a51f20b463e2a851cac6b39f

doc update

README.md

diff --git a/README.md b/README.md
index 2953916..47c8a4f 100644
--- a/README.md
+++ b/README.md
@@ -86,6 +86,9 @@
   <tr>
     <td  align="center"><img src="./docs/source/_static/Riscduino-derivatives.png" ></td>
   </tr>
+  <tr>
+    <td  align="center"><img src="./docs/source/_static/Riscduino_Series_placement.png" ></td>
+  </tr>
 
 </table>
 
@@ -127,7 +130,7 @@
   <tr>
     <td  align="center"> MPW-5 </td> 
     <td  align="center"> 21-Mar-2022  </td>
-    <td  align="center"> Riscduino-SCORE</td>
+    <td  align="center"> Riscduino-SCORE (S0)</td>
     <td  align="center"> Single 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar</td>
     <td  align="center"> <a href="https://github.com/dineshannayya/riscduino">Link</a></td>
     <td  align="center"> <a href="https://platform.efabless.com/projects/670">Link</a></td>
@@ -135,7 +138,7 @@
   <tr>
     <td  align="center"> MPW-5 </td> 
     <td  align="center"> 21-Mar-2022  </td>
-    <td  align="center"> Riscduino-DCORE</td>
+    <td  align="center"> Riscduino-DCORE (D0)</td>
     <td  align="center"> Dual 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar</td>
     <td  align="center"> <a href="https://github.com/dineshannayya/riscduino_dcore">Link</a></td>
     <td  align="center"> <a href="https://platform.efabless.com/projects/718">Link</a></td>
@@ -143,11 +146,35 @@
   <tr>
     <td  align="center"> MPW-5 </td> 
     <td  align="center"> 21-Mar-2022  </td>
-    <td  align="center"> Riscduino-QCORE</td>
+    <td  align="center"> Riscduino-QCORE (Q0)</td>
     <td  align="center"> Quad 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar</td>
     <td  align="center"> <a href="https://github.com/dineshannayya/riscduino_qcore">Link</a></td>
     <td  align="center"> <a href="https://platform.efabless.com/projects/782">Link</a></td>
   </tr>
+  <tr>
+    <td  align="center"> MPW-6 </td> 
+    <td  align="center"> 07-June-2022  </td>
+    <td  align="center"> Riscduino-SCORE (S3)</td>
+    <td  align="center"> Single 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar</td>
+    <td  align="center"> <a href="https://github.com/dineshannayya/riscduino">Link</a></td>
+    <td  align="center"> <a href="https://platform.efabless.com/projects/1047">Link</a></td>
+  </tr>
+  <tr>
+    <td  align="center"> MPW-6 </td> 
+    <td  align="center"> 07-June-2022  </td>
+    <td  align="center"> Riscduino-DCORE (D1)</td>
+    <td  align="center"> Dual 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar</td>
+    <td  align="center"> <a href="https://github.com/dineshannayya/riscduino_dcore">Link</a></td>
+    <td  align="center"> <a href="https://platform.efabless.com/projects/838">Link</a></td>
+  </tr>
+  <tr>
+    <td  align="center"> MPW-6 </td> 
+    <td  align="center"> 07-June-2022 </td>
+    <td  align="center"> Riscduino-QCORE (Q1)</td>
+    <td  align="center"> Quad 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar</td>
+    <td  align="center"> <a href="https://github.com/dineshannayya/riscduino_qcore">Link</a></td>
+    <td  align="center"> <a href="https://platform.efabless.com/projects/839">Link</a></td>
+  </tr>
 </table>
 
 # SOC Pin Mapping

docs/source/_static/Riscduino_Series_placement.png

diff --git a/docs/source/_static/Riscduino_Series_placement.png b/docs/source/_static/Riscduino_Series_placement.png
new file mode 100644
index 0000000..bbe5005
--- /dev/null
+++ b/docs/source/_static/Riscduino_Series_placement.png
Binary files differ