Riscv Unalign access fix and sdr ctrl 8 bit address mode fix
diff --git a/signoff/sdram/OPENLANE_VERSION b/signoff/sdram/OPENLANE_VERSION
index ad796aa..bab6e84 100644
--- a/signoff/sdram/OPENLANE_VERSION
+++ b/signoff/sdram/OPENLANE_VERSION
@@ -1 +1 @@
-openlane v0.21-6-gbc3b032
+openlane v0.21-9-g94fe743
diff --git a/signoff/sdram/final_summary_report.csv b/signoff/sdram/final_summary_report.csv
index 43b9118..24acce0 100644
--- a/signoff/sdram/final_summary_report.csv
+++ b/signoff/sdram/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/sdram,sdrc_top,sdram,Flow_completed,0h16m1s,0h5m47s,41017.14285714286,0.35,20508.57142857143,30,667.97,7178,0,0,0,0,0,0,0,0,0,-1,0,323270,57447,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,249088125,0.0,26.22,17.06,2.92,-1,-1,7082,7341,1219,1478,0,0,0,7178,197,107,83,91,354,212,31,2289,1267,1186,27,350,4248,0,4598,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,5
+0,/project/openlane/sdram,sdrc_top,sdram,Flow_completed,0h17m16s,0h6m17s,40708.57142857143,0.35,20354.285714285714,30,662.62,7124,0,0,0,0,0,0,0,0,0,-1,0,316920,56671,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,242866426,0.0,25.86,16.86,2.54,-1,-1,7028,7287,1219,1478,0,0,0,7124,196,107,83,98,352,210,34,2240,1267,1186,23,350,4248,0,4598,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,5
diff --git a/signoff/user_project_wrapper/OPENLANE_VERSION b/signoff/user_project_wrapper/OPENLANE_VERSION
index f6da8d7..bab6e84 100644
--- a/signoff/user_project_wrapper/OPENLANE_VERSION
+++ b/signoff/user_project_wrapper/OPENLANE_VERSION
@@ -1 +1 @@
-openlane v0.21-7-gaaf334d
+openlane v0.21-9-g94fe743
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 73ea77b..ef20129 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h46m33s,0h5m14s,3.3079078455790785,10.2784,1.6539539227895392,0,533.76,17,0,0,0,0,0,0,0,0,1,-1,-1,1233065,4146,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.28,4.44,0.98,2.46,-1,902,1520,902,1520,0,0,0,17,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,80,0.55,0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h46m33s,0h5m18s,3.3079078455790785,10.2784,1.6539539227895392,0,531.62,17,0,0,0,0,0,0,0,0,1,-1,-1,1233053,4238,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.29,4.44,0.96,2.45,-1,902,1520,902,1520,0,0,0,17,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,80,0.55,0,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_interconnect/OPENLANE_VERSION b/signoff/wb_interconnect/OPENLANE_VERSION
index ad796aa..bab6e84 100644
--- a/signoff/wb_interconnect/OPENLANE_VERSION
+++ b/signoff/wb_interconnect/OPENLANE_VERSION
@@ -1 +1 @@
-openlane v0.21-6-gbc3b032
+openlane v0.21-9-g94fe743
diff --git a/signoff/wb_interconnect/final_summary_report.csv b/signoff/wb_interconnect/final_summary_report.csv
index 32f2a54..d183141 100644
--- a/signoff/wb_interconnect/final_summary_report.csv
+++ b/signoff/wb_interconnect/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,Flow_completed,0h29m17s,0h4m13s,8309.090909090908,0.33,4154.545454545454,7,552.64,1371,0,0,0,0,0,0,0,0,0,-1,0,437660,18322,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,388524110,0.0,40.9,7.79,23.11,-1,-1,1097,1718,204,825,0,0,0,1371,244,0,75,15,135,0,0,180,455,438,11,94,3794,0,3888,100.0,10.0,10,AREA 0,4,50,1,180,180,0.5,0,sky130_fd_sc_hd,4,5
+0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,Flow_completed,0h24m29s,0h4m56s,8169.69696969697,0.33,4084.848484848485,7,559.88,1348,0,0,0,0,0,0,0,0,0,-1,0,417538,17849,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,375201274,0.0,39.41,7.47,21.49,-1,-1,1074,1695,202,823,0,0,0,1348,240,0,73,15,135,0,0,176,447,428,11,94,3794,0,3888,100.0,10.0,10,AREA 0,4,50,1,180,180,0.5,0,sky130_fd_sc_hd,4,5
diff --git a/verilog/rtl/digital_core/src/glbl_cfg.sv b/verilog/rtl/digital_core/src/glbl_cfg.sv
index 2b49beb..bf69fd0 100644
--- a/verilog/rtl/digital_core/src/glbl_cfg.sv
+++ b/verilog/rtl/digital_core/src/glbl_cfg.sv
@@ -446,10 +446,10 @@
//-----------------------------------------------------------------------
// reg-4
// recommended Default value:
-// 1'b1,3'h3,2'h3,4'h1,4'h7',4'h2,4'h2,4'h4,2'b00,2'b10 = 32'h2F17_2242
+// 1'b1,3'h3,2'h3,4'h1,4'h7',4'h2,4'h2,4'h4,2'b01,2'b10 = 32'h2F17_2246
//-----------------------------------------------------------------
assign cfg_sdr_width = reg_4[1:0] ; // 2'b10 // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
-assign cfg_colbits = reg_4[3:2] ; // 2'b00 // 8 Bit column address,
+assign cfg_colbits = reg_4[3:2] ; // 2'b00 8 Bit column address, 2'b01 - 9 Bit column address,
assign cfg_sdr_tras_d = reg_4[7:4] ; // 4'h4 // Active to precharge delay
assign cfg_sdr_trp_d = reg_4[11:8]; // 4'h2 // Precharge to active delay
assign cfg_sdr_trcd_d = reg_4[15:12]; // 4'h2 // Active to R/W delay
diff --git a/verilog/rtl/sdram_ctrl/src/core/sdrc_req_gen.v b/verilog/rtl/sdram_ctrl/src/core/sdrc_req_gen.v
index 5fd7bb9..8ea0148 100755
--- a/verilog/rtl/sdram_ctrl/src/core/sdrc_req_gen.v
+++ b/verilog/rtl/sdram_ctrl/src/core/sdrc_req_gen.v
@@ -65,6 +65,7 @@
- Dinesh Annayya, dinesha@opencores.org
Version : 0.0 - 8th Jan 2012
0.1 - 5th Feb 2012, column/row/bank address are register to improve the timing issue in FPGA synthesis
+ 0.2 - 19th Aug 2021, Address Mapping fix
@@ -206,11 +207,11 @@
req_len_int = req_len;
end else if(sdr_width == 2'b01) begin // 16 Bit SDR Mode
// Changed the address and length to match the 16 bit SDR Mode
- req_addr_int = {req_addr,1'b0};
+ req_addr_int = {1'b0,req_addr};
req_len_int = {req_len,1'b0};
end else begin // 8 Bit SDR Mode
// Changed the address and length to match the 16 bit SDR Mode
- req_addr_int = {req_addr,2'b0};
+ req_addr_int = {1'b0,req_addr};
req_len_int = {req_len,2'b0};
end
end
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
index d8b59a5..77a0163 100644
--- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
+++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -261,7 +261,7 @@
// Master Mapping
// -------------------------------------
assign m0_wb_wr.wbd_dat = m0_wbd_dat_i;
-assign m0_wb_wr.wbd_adr = m0_wbd_adr_i;
+assign m0_wb_wr.wbd_adr = {m0_wbd_adr_i[31:2],2'b00};
assign m0_wb_wr.wbd_sel = m0_wbd_sel_i;
assign m0_wb_wr.wbd_we = m0_wbd_we_i;
assign m0_wb_wr.wbd_cyc = m0_wbd_cyc_i;
@@ -269,7 +269,7 @@
assign m0_wb_wr.wbd_tid = m0_wbd_tid_i;
assign m1_wb_wr.wbd_dat = m1_wbd_dat_i;
-assign m1_wb_wr.wbd_adr = m1_wbd_adr_i;
+assign m1_wb_wr.wbd_adr = {m1_wbd_adr_i[31:2],2'b00};
assign m1_wb_wr.wbd_sel = m1_wbd_sel_i;
assign m1_wb_wr.wbd_we = m1_wbd_we_i;
assign m1_wb_wr.wbd_cyc = m1_wbd_cyc_i;
@@ -277,7 +277,7 @@
assign m1_wb_wr.wbd_tid = m1_wbd_tid_i;
assign m2_wb_wr.wbd_dat = m2_wbd_dat_i;
-assign m2_wb_wr.wbd_adr = m2_wbd_adr_i;
+assign m2_wb_wr.wbd_adr = {m2_wbd_adr_i[31:2],2'b00};
assign m2_wb_wr.wbd_sel = m2_wbd_sel_i;
assign m2_wb_wr.wbd_we = m2_wbd_we_i;
assign m2_wb_wr.wbd_cyc = m2_wbd_cyc_i;
