gpio test clean up
diff --git a/verilog/dv/user_gpio/Makefile b/verilog/dv/user_gpio/Makefile
index c072436..6c8a24b 100644
--- a/verilog/dv/user_gpio/Makefile
+++ b/verilog/dv/user_gpio/Makefile
@@ -14,41 +14,33 @@
#
# SPDX-License-Identifier: Apache-2.0
-## Caravel Pointers
-CARAVEL_ROOT ?= ../../../caravel
-CARAVEL_PATH ?= $(CARAVEL_ROOT)
-CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
-CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog
-CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
-CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+# ---- Include Partitioned Makefiles ----
-## User Project Pointers
-UPRJ_VERILOG_PATH ?= ../../../verilog
-UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
-UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
-UPRJ_BEHAVIOURAL_MODELS = ../model
-UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
-UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/i2cm/src/includes
-UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
+CONFIG = caravel_user_project
+
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+DESIGNS?=../../..
+TOOLS?=/opt/riscv64i/
+
+export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
GCC64_PREFIX?=riscv64-unknown-elf
-## RISCV GCC
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-PDK_PATH?=/opt/pdk/sky130A
## Simulation mode: RTL/GL
SIM?=RTL
DUMP?=OFF
+RISC_CORE?=0
### To Enable IVERILOG FST DUMP
export IVERILOG_DUMPER = fst
+
.SUFFIXES:
PATTERN = user_gpio
@@ -61,36 +53,33 @@
%.vvp: %_tb.v
ifeq ($(SIM),RTL)
ifeq ($(DUMP),OFF)
- iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
- -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
- -I $(UPRJ_BEHAVIOURAL_AGENTS) \
- -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) \
- -I $(UPRJ_INCLUDE_PATH3) \
+ iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
else
- iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
- -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
- -I $(UPRJ_BEHAVIOURAL_AGENTS) \
- -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) \
- -I $(UPRJ_INCLUDE_PATH3) \
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
endif
else
- iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
- -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \
- -I $(UPRJ_BEHAVIOURAL_AGENTS) \
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
$< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ endif
endif
%.vcd: %.vvp
vvp $<
-%.hex:
- echo @"This is user boot test, noting to compile the mangment core code"
-
# ---- Clean ----
diff --git a/verilog/dv/user_gpio/user_gpio_tb.v b/verilog/dv/user_gpio/user_gpio_tb.v
index 6bc0c7f..8badada 100644
--- a/verilog/dv/user_gpio/user_gpio_tb.v
+++ b/verilog/dv/user_gpio/user_gpio_tb.v
@@ -66,20 +66,12 @@
`default_nettype wire
-`timescale 1 ns / 1 ns
+`timescale 1 ns/1 ps
-// Note in caravel, 0x30XX_XXXX only come to user interface
-// So, using wb_host bank select we have changing MSB address [31:24] = 0x10
-`define ADDR_SPACE_UART 32'h3001_0000
-`define ADDR_SPACE_SSPI 32'h3001_00C0
-`define ADDR_SPACE_PINMUX 32'h3002_0000
-
-`define TB_GLBL user_gpio_tb
-
-`include "uprj_netlists.v"
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
`include "is62wvs1288.v"
-`include "user_reg_map.v"
+`define TB_GLBL user_gpio_tb
module user_gpio_tb;
reg clock;
