icache,dcache wishbone burst access cleanup
diff --git a/.gitmodules b/.gitmodules
index a8dbba9..df69a25 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -4,6 +4,6 @@
[submodule "verilog/rtl/qspim"]
path = verilog/rtl/qspim
url = https://github.com/dineshannayya/qspim.git
-[submodule "verilog/rtl/yifive/ycr1"]
- path = verilog/rtl/yifive/ycr1
- url = https://github.com/dineshannayya/ycr1.git
+[submodule "verilog/rtl/yifive/ycr1c"]
+ path = verilog/rtl/yifive/ycr1c
+ url = https://github.com/dineshannayya/ycr1c.git
diff --git a/verilog/dv/firmware/common.mk b/verilog/dv/firmware/common.mk
index 6075f73..402d346 100644
--- a/verilog/dv/firmware/common.mk
+++ b/verilog/dv/firmware/common.mk
@@ -58,8 +58,8 @@
$(bld_dir)/%.hex: $(bld_dir)/%.elf
$(RISCV_ROM_OBJCOPY) $^ $@
$(RISCV_RAM_OBJCOPY) $^ $@.ram
- #assign 0x0048_0xxx to 0x0000_0xxx to map to TCM Memory
- sed -i 's/@00480/@00000/g' $@.ram
+ #assign 0x0800_0xxx to 0x0000_0xxx to map to TCM Memory
+ sed -i 's/@08000/@00000/g' $@.ram
$(bld_dir)/%.dump: $(bld_dir)/%.elf
diff --git a/verilog/dv/firmware/link.ld b/verilog/dv/firmware/link.ld
index 5d75e36..0496122 100644
--- a/verilog/dv/firmware/link.ld
+++ b/verilog/dv/firmware/link.ld
@@ -26,8 +26,8 @@
MEMORY {
ROM (rxx) : ORIGIN = 0x0, LENGTH = 64K
- TCM (rwx) : ORIGIN = 0x00480000, LENGTH = 4K
- RAM (rwx) : ORIGIN = 0x10030000, LENGTH = 8K
+ RAM (rwx) : ORIGIN = 0x08000000, LENGTH = 8K
+ TCM (rwx) : ORIGIN = 0x0C480000, LENGTH = 2K
}
STACK_SIZE = 1024;
@@ -56,20 +56,20 @@
*(sc_test_section)
. = ALIGN(CL_SIZE);
PROVIDE(__TEXT_END__ = .);
- } >ROM
+ } >ROM
/* data segment */
.data : {
*(.data .data.*)
. = ALIGN(CL_SIZE);
- } >TCM
+ } >RAM
.sdata : {
__global_pointer$ = . + 0x800;
*(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*)
*(.sdata .sdata.* .gnu.linkonce.s.*)
. = ALIGN(CL_SIZE);
- } >TCM
+ } >RAM
/* thread-local data segment */
.tdata : {
@@ -78,14 +78,14 @@
*(.tdata .tdata.*)
PROVIDE(_tdata_end = .);
. = ALIGN(CL_SIZE);
- } >TCM
+ } >RAM
.tbss : {
PROVIDE(__BSS_START__ = .);
*(.tbss .tbss.*)
. = ALIGN(CL_SIZE);
PROVIDE(_tbss_end = .);
- } >TCM
+ } >RAM
/* bss segment */
.sbss : {
diff --git a/verilog/dv/firmware/ycr1_specific.h b/verilog/dv/firmware/ycr1_specific.h
index 0f8d70f..4c8c583 100644
--- a/verilog/dv/firmware/ycr1_specific.h
+++ b/verilog/dv/firmware/ycr1_specific.h
@@ -22,12 +22,12 @@
#define mcounten 0x7E0
// Memory-mapped registers
-#define mtime_ctrl 0x00490000
-#define mtime_div 0x00490004
-#define mtime 0x00490008
-#define mtimeh 0x0049000C
-#define mtimecmp 0x00490010
-#define mtimecmph 0x00490014
+#define mtime_ctrl 0x0C490000
+#define mtime_div 0x0C490004
+#define mtime 0x0C490008
+#define mtimeh 0x0C49000C
+#define mtimecmp 0x0C490010
+#define mtimecmph 0x0C490014
#define YCR1_MTIME_CTRL_EN 0
#define YCR1_MTIME_CTRL_CLKSRC 1
diff --git a/verilog/dv/risc_boot/Makefile b/verilog/dv/risc_boot/Makefile
index 5b1146a..c8c838c 100644
--- a/verilog/dv/risc_boot/Makefile
+++ b/verilog/dv/risc_boot/Makefile
@@ -30,7 +30,7 @@
UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
@@ -59,12 +59,12 @@
vvp: ${PATTERN:=.vvp}
%.vvp: %_tb.v %.hex
- ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_uart.c -o user_uart.o
- ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt_tcm.S -o crt_tcm.o
- ${GCC64_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -T $(YIFIVE_FIRMWARE_PATH)/link_tcm.ld user_uart.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -o user_uart.elf -N
+ ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_uart.c -o user_uart.o
+ ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o
+ ${GCC64_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -T $(YIFIVE_FIRMWARE_PATH)/link.ld user_uart.o crt.o -nostartfiles -nostdlib -lc -lgcc -o user_uart.elf -N
${GCC64_PREFIX}-objcopy -O verilog user_uart.elf user_uart.hex
${GCC64_PREFIX}-objdump -D user_uart.elf > user_uart.dump
- rm crt_tcm.o user_uart.o
+ rm crt.o user_uart.o
ifeq ($(SIM),RTL)
ifeq ($(DUMP),OFF)
iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v
index 4332e90..fec74e4 100644
--- a/verilog/dv/risc_boot/risc_boot_tb.v
+++ b/verilog/dv/risc_boot/risc_boot_tb.v
@@ -162,7 +162,7 @@
$display("Monitor: Test User Risc Boot Started");
// Wait for user risc core to boot up
- repeat (25000) @(posedge clock);
+ repeat (30000) @(posedge clock);
tb_uart.uart_init;
tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity,
uart_stick_parity, uart_timeout, uart_divisor);
diff --git a/verilog/dv/riscv_regress/Makefile b/verilog/dv/riscv_regress/Makefile
index 8687043..1703420 100644
--- a/verilog/dv/riscv_regress/Makefile
+++ b/verilog/dv/riscv_regress/Makefile
@@ -2,6 +2,9 @@
# Makefile for SCR1
#------------------------------------------------------------------------------
+SIM ?= RTL
+DUMP ?= OFF
+
# PARAMETERS
# CFG = <MAX, BASE, MIN, CUSTOM>
@@ -11,20 +14,20 @@
export BUS ?= WB
ifeq ($(CFG), MAX)
-# Predefined configuration SCR1_CFG_RV32IMC_MAX
+# Predefined configuration YCR1_CFG_RV32IMC_MAX
override ARCH := IMC
override VECT_IRQ := 1
override IPIC := 1
override TCM := 0
- override SIM_CFG_DEF := SCR1_CFG_RV32IMC_MAX
+ override SIM_CFG_DEF := YCR1_CFG_RV32IMC_MAX
else
ifeq ($(CFG), BASE)
- # Predefined configuration SCR1_CFG_RV32IC_BASE
+ # Predefined configuration YCR1_CFG_RV32IC_BASE
override ARCH := IC
override VECT_IRQ := 1
override IPIC := 1
override TCM := 0
- override SIM_CFG_DEF := SCR1_CFG_RV32IC_BASE
+ override SIM_CFG_DEF := YCR1_CFG_RV32IC_BASE
else
ifeq ($(CFG), MIN)
# Predefined configuration SCR1_CFG_RV32EC_MIN
@@ -32,10 +35,10 @@
override VECT_IRQ := 0
override IPIC := 0
override TCM := 0
- override SIM_CFG_DEF := SCR1_CFG_RV32EC_MIN
+ override SIM_CFG_DEF := YCR1_CFG_RV32EC_MIN
else
# CUSTOM configuration. Parameters can be overwritten
- # These options are for compiling tests only. Set the corresponding RTL parameters manually in the file scr1_arch_description.svh.
+ # These options are for compiling tests only. Set the corresponding RTL parameters manually in the file ycr1_arch_description.svh.
# ARCH = <IMC, IC, IM, I, EMC, EM, EC, E>
# VECT_IRQ = <0, 1>
# IPIC = <0, 1>
@@ -44,7 +47,7 @@
VECT_IRQ ?= 0
IPIC ?= 0
TCM ?= 0
- SIM_CFG_DEF = SCR1_CFG_$(CFG)
+ SIM_CFG_DEF = YCR1_CFG_$(CFG)
endif
endif
endif
@@ -83,9 +86,9 @@
TRACE ?= 0
ifeq ($(TRACE), 1)
- export SIM_TRACE_DEF = SCR1_TRACE_LOG_EN
+ export SIM_TRACE_DEF = YCR1_TRACE_LOG_EN
else
- export SIM_TRACE_DEF = SCR1_TRACE_LOG_DIS
+ export SIM_TRACE_DEF = YCR1_TRACE_LOG_DIS
endif
@@ -133,7 +136,7 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = $(root_dir)/../model
UPRJ_BEHAVIOURAL_AGENTS = $(root_dir)/../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
@@ -157,9 +160,11 @@
export CROSS_PREFIX ?= riscv64-unknown-elf-
export RISCV_GCC ?= $(CROSS_PREFIX)gcc
export RISCV_OBJDUMP ?= $(CROSS_PREFIX)objdump -D
+export RISCV_OBJCOPY ?= $(CROSS_PREFIX)objcopy -O verilog
export RISCV_ROM_OBJCOPY ?= $(CROSS_PREFIX)objcopy -j .text.init -j .text -j .rodata -j .rodata.str1.4 -O verilog
#Seperate the RAM content and write out in 32bit Little endian format to load it to TCM Memory
-export RISCV_RAM_OBJCOPY ?= $(CROSS_PREFIX)objcopy -R .text.init -R .text -R .rodata -R .rodata.str1.4 -R .riscv.attributes -R .comment -R .debug_abbrev -R .debug_loc -R .debug_str -O verilog --verilog-data-width=4 --reverse-bytes=4
+#export RISCV_RAM_OBJCOPY ?= $(CROSS_PREFIX)objcopy -R .text.init -R .text -R .rodata -R .rodata.str1.4 -R .riscv.attributes -R .comment -R .debug_abbrev -R .debug_loc -R .debug_str -O verilog --verilog-data-width=4 --reverse-bytes=4
+export RISCV_RAM_OBJCOPY ?= $(CROSS_PREFIX)objcopy -R .text.init -R .text -R .rodata -R .rodata.str1.4 -O verilog
export RISCV_READELF ?= $(CROSS_PREFIX)readelf -s
ifneq (,$(findstring e,$(ARCH_lowercase)))
@@ -177,11 +182,11 @@
TARGETS += riscv_isa
# Comment this target if you don't want to run the riscv_compliance
- #TARGETS += riscv_compliance
+ TARGETS += riscv_compliance
endif
# Comment this target if you don't want to run the isr_sample
-#TARGETS += isr_sample
+TARGETS += isr_sample
# Comment this target if you don't want to run the coremark
#TARGETS += coremark
@@ -194,7 +199,7 @@
# Targets
-.PHONY: tests run_iverilog run_modelsim run_modelsim_wlf run_vcs run_ncsim run_verilator run_verilator_wf run_iverilog_wf
+.PHONY: tests run_iverilog run_iverilog_wf run_modelsim run_modelsim_wlf run_vcs run_ncsim run_verilator run_verilator_wf
default: clean_test_list run_iverilog
diff --git a/verilog/dv/riscv_regress/riscv_runtests.sv b/verilog/dv/riscv_regress/riscv_runtests.sv
index 40dc43b..7a398c2 100644
--- a/verilog/dv/riscv_regress/riscv_runtests.sv
+++ b/verilog/dv/riscv_regress/riscv_runtests.sv
@@ -53,7 +53,7 @@
$display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", core2dmem_addr_o_r,`RISC_CORE.dmem2core_rdata_i,`RISC_CORE.dmem2core_resp_i);
end
**/
-/**
+/***
logic [31:0] test_count;
`define RISC_CORE u_top.u_riscv_top.i_core_top
`define RISC_EXU u_top.u_riscv_top.i_core_top.i_pipe_top.i_pipe_exu
@@ -69,15 +69,21 @@
test_count <= test_count+1;
end
end
-**/
+***/
-always_ff @(posedge clk) begin
+always @(posedge clk) begin
bit test_pass;
int unsigned f_test;
+ int unsigned f_test_ram;
if (test_running) begin
test_pass = 1;
rst_init <= 1'b0;
- if ((u_top.u_riscv_top.i_core_top.i_pipe_top.curr_pc == SCR1_SIM_EXIT_ADDR) & ~rst_init & &rst_cnt) begin
+ if(u_top.u_riscv_top.i_core_top.i_pipe_top.i_pipe_exu.pc_curr_ff === 32'hxxxx_xxxx) begin
+ $display("ERROR: CURRENT PC Counter State is Known");
+ $finish;
+ end
+ if ((u_top.u_riscv_top.i_core_top.i_pipe_top.i_pipe_exu.exu2pipe_pc_curr_o == YCR1_SIM_EXIT_ADDR) & ~rst_init & &rst_cnt) begin
+
`ifdef VERILATOR
logic [255:0] full_filename;
full_filename = test_file;
@@ -87,7 +93,6 @@
`endif // VERILATOR
if (is_compliance(test_file)) begin
-
logic [31:0] tmpv, start, stop, ref_data, test_data;
integer fd;
`ifdef VERILATOR
@@ -95,6 +100,13 @@
`else // VERILATOR
string tmpstr;
`endif // VERILATOR
+
+ // Flush the content of dcache for signature validation at app
+ // memory
+ force u_top.u_riscv_top.u_intf.u_dcache.cfg_force_flush = 1'b1;
+ wait(u_top.u_riscv_top.u_intf.u_dcache.force_flush_done == 1'b1);
+ release u_top.u_riscv_top.u_intf.u_dcache.cfg_force_flush;
+ $display("STATUS: Checking Complaince Test Status .... ");
test_running <= 1'b0;
test_pass = 1;
@@ -107,6 +119,7 @@
end
$fwrite(fd, "%s", tmpstr);
$fclose(fd);
+
$system("sh script.sh");
fd = $fopen("elfinfo", "r");
@@ -126,11 +139,14 @@
stop = tmpv;
end
$fclose(fd);
+ start = start & 32'h07FF_FFFF;
+ stop = stop & 32'h07FF_FFFF;
+ $display("Complaince Signature Start Address: %x End Address:%x",start,stop);
- if((start & 32'h1FFF) > 512)
- $display("ERROR: Start address is more than 512, Start: %x",start & 32'h1FFF);
- if((stop & 32'h1FFF) > 512)
- $display("ERROR: Stop address is more than 512, Start: %x",stop & 32'h1FFF);
+ //if((start & 32'h1FFF) > 512)
+ // $display("ERROR: Start address is more than 512, Start: %x",start & 32'h1FFF);
+ //if((stop & 32'h1FFF) > 512)
+ // $display("ERROR: Stop address is more than 512, Start: %x",stop & 32'h1FFF);
`ifdef SIGNATURE_OUT
@@ -140,10 +156,7 @@
`endif
fd = $fopen(tmpstr, "w");
while ((start != stop)) begin
- test_data[31:24] = u_top.u_tsram0_2kb.mem[(start & 32'h1FFF)+3];
- test_data[23:16] = u_top.u_tsram0_2kb.mem[(start & 32'h1FFF)+2];
- test_data[15:8] = u_top.u_tsram0_2kb.mem[(start & 32'h1FFF)+1];
- test_data[7:0] = u_top.u_tsram0_2kb.mem[(start & 32'h1FFF)+0];
+ test_data = u_top.u_mbist.u_sram0_2kb.mem[(start & 32'h1FFF)];
$fwrite(fd, "%x", test_data);
$fwrite(fd, "%s", "\n");
start += 4;
@@ -167,11 +180,13 @@
// other-wise need to switch bank
// --------------------------------------------------
//$writememh("sram0_out.hex",u_top.u_tsram0_2kb.mem,0,511);
- test_data = u_top.u_tsram0_2kb.mem[((start >> 2) & 32'h1FFF)];
+ test_data = u_top.u_mbist.u_sram0_2kb.mem[((start >> 2) & 32'h1FFF)];
//$display("Compare Addr: %x ref_data : %x, test_data: %x",start,ref_data,test_data);
test_pass &= (ref_data == test_data);
if(ref_data != test_data)
$display("ERROR: Compare Addr: %x Mem Addr: %x ref_data : %x, test_data: %x",start,start & 32'h1FFF,ref_data,test_data);
+ else
+ $display("STATUS: Compare Addr: %x Mem Addr: %x ref_data : %x",start,start & 32'h1FFF,ref_data);
start += 4;
end
$fclose(fd);
@@ -217,7 +232,7 @@
f_test = $fopen(test_file,"r");
if (f_test != 0) begin
// Launch new test
- `ifdef SCR1_TRACE_LOG_EN
+ `ifdef YCR1_TRACE_LOG_EN
u_top.u_riscv_top.i_core_top.i_pipe_top.i_tracelog.test_name = test_file;
`endif // SCR1_TRACE_LOG_EN
//i_memory_tb.test_file = test_file;
diff --git a/verilog/dv/riscv_regress/run_iverilog b/verilog/dv/riscv_regress/run_iverilog
index 8200d99..fbd8e05 100755
--- a/verilog/dv/riscv_regress/run_iverilog
+++ b/verilog/dv/riscv_regress/run_iverilog
@@ -9,9 +9,23 @@
riscv64-unknown-elf-gcc -o /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/build/iverilog_WB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0/hello.elf -T /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/build/iverilog_WB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0/sc_print.o /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/build/iverilog_WB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0/hello.o /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/build/iverilog_WB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0/crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32
rm /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/build/iverilog_WB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0/sc_print.o /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/build/iverilog_WB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0/crt_tcm.o /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/build/iverilog_WB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0/hello.o
-cd /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/build/iverilog_WB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0
+cd build/iverilog_WB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0
-iverilog -g2005-sv -DFUNCTIONAL -DWFDUMP -DSIM -I /opt/pdk/sky130A -I /home/dinesha/workarea/efabless/MPW-4/caravel/verilog/dv/caravel -I /home/dinesha/workarea/efabless/MPW-4/caravel/verilog/rtl -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../model -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog/rtl -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../agents -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog/rtl/syntacore/scr1/src/includes -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog/rtl/sdram_ctrl/src/defs -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog/rtl/i2cm/src/includes -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog/rtl/usb1_host/src/includes -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog/rtl/mbist/include -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress ../../user_risc_regress_tb.v -o user_risc_regress_tb.vvp
+iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $PDK_ROOT/sky130A \
+-I $CARAVEL_ROOT/verilog/dv/caravel \
+-I $CARAVEL_ROOT/verilog/rtl \
+-I ../../../model \
+-I ../../../../../verilog/rtl \
+-I ../../../../../verilog \
+-I ../../../agents \
+-I ../../../../../verilog/rtl/yifive/ycr1c/src/includes \
+-I ../../../../../verilog/rtl/sdram_ctrl/src/defs \
+-I ../../../../../verilog/rtl/i2cm/src/includes \
+-I ../../../../../verilog/rtl/usb1_host/src/includes \
+-I ../../../../../verilog/rtl/mbist/include \
+-I ../.. \
+../../user_risc_regress_tb.v \
+-o user_risc_regress_tb.vvp
iverilog-vpi ../../../vpi/system/system.c
diff --git a/verilog/dv/riscv_regress/tests/hello/hello.c b/verilog/dv/riscv_regress/tests/hello/hello.c
index 52cf1bc..af5c6e3 100644
--- a/verilog/dv/riscv_regress/tests/hello/hello.c
+++ b/verilog/dv/riscv_regress/tests/hello/hello.c
@@ -2,6 +2,6 @@
int main()
{
- sc_printf("Hello from SCR1!\n");
+ sc_printf("Hello from YCR1!\n");
return 0;
-}
\ No newline at end of file
+}
diff --git a/verilog/dv/riscv_regress/tests/isr_sample/timer.h b/verilog/dv/riscv_regress/tests/isr_sample/timer.h
index b81bcc8..827b849 100644
--- a/verilog/dv/riscv_regress/tests/isr_sample/timer.h
+++ b/verilog/dv/riscv_regress/tests/isr_sample/timer.h
@@ -4,12 +4,12 @@
#define MEM_MTIME_MASK 0xF0000000
-#define MEM_MTIME_CTRL 0x00490000
-#define MEM_MTIME_DIV 0x00490004
-#define MEM_MTIME 0x00490008
-#define MEM_MTIMEH 0x0049000C
-#define MEM_MTIMECMP 0x00490010
-#define MEM_MTIMECMPH 0x00490014
+#define MEM_MTIME_CTRL 0x0C490000
+#define MEM_MTIME_DIV 0x0C490004
+#define MEM_MTIME 0x0C490008
+#define MEM_MTIMEH 0x0C49000C
+#define MEM_MTIMECMP 0x0C490010
+#define MEM_MTIMECMPH 0x0C490014
#define TMP t0
#define TMP2 t1
@@ -78,7 +78,7 @@
.macro _run_timer
li TMP, MEM_MTIME_CTRL
lw TMP2, 0(TMP)
- li TMP3, (1 << SCR1_MTIME_CTRL_EN)
+ li TMP3, (1 << YCR1_MTIME_CTRL_EN)
or TMP2, TMP2, TMP3
sw TMP2, 0(TMP)
.endm
@@ -86,7 +86,7 @@
.macro _stop_timer
li TMP, MEM_MTIME_CTRL
lw TMP2, 0(TMP)
- li TMP3, (1 << SCR1_MTIME_CTRL_EN)
+ li TMP3, (1 << YCR1_MTIME_CTRL_EN)
not TMP3, TMP3
and TMP2, TMP2, TMP3
sw TMP2, 0(TMP)
diff --git a/verilog/dv/riscv_regress/tests/riscv_compliance/Makefile b/verilog/dv/riscv_regress/tests/riscv_compliance/Makefile
index e04fc87..98f3d5f 100644
--- a/verilog/dv/riscv_regress/tests/riscv_compliance/Makefile
+++ b/verilog/dv/riscv_regress/tests/riscv_compliance/Makefile
@@ -1,8 +1,6 @@
## @file
-## Syntacore SCR* tests
+## YCR* tests
##
-## @copyright 2015-2018 Syntacore. All rights reserved.
-## RISCV-Compliance
##
ARCH ?=im
@@ -16,7 +14,7 @@
ifeq (rv32e,$(findstring rv32e,$(ARCH)))
$(info >>> RV32E - no compliance tests)
-else ## ifdef SCR_BASE_RVE_EXT
+else ## ifdef YCR_BASE_RVE_EXT
#ifeq (rv32i,$(findstring rv32i,$(ARCH)))
ifeq ($(ARCH),$(filter $(ARCH),rv32i rv32im rv32imc rv32ic))
$(info >>> I32 TESTS)
@@ -134,8 +132,8 @@
$(dst_dir)/compliance_%.hex: $(dst_dir)/compliance_%.elf
$(RISCV_ROM_OBJCOPY) $^ $@
$(RISCV_RAM_OBJCOPY) $^ $@.ram
- #assign 0x0048_0xxx to 0x0000_0xxx to map to TCM Memory
- sed -i 's/@00480/@00000/g' $@.ram
+ #assign 0x0800_0xxx to 0x0000_0xxx to map to TCM Memory
+ sed -i 's/@08000/@00000/g' $@.ram
$(bld_dir)/compliance_%.dump: $(dst_dir)/compliance_%.elf
$(RISCV_OBJDUMP) -D -w -x -S $^ > $@
diff --git a/verilog/dv/riscv_regress/tests/riscv_isa/Makefile b/verilog/dv/riscv_regress/tests/riscv_isa/Makefile
index a572172..2f0fa3f 100644
--- a/verilog/dv/riscv_regress/tests/riscv_isa/Makefile
+++ b/verilog/dv/riscv_regress/tests/riscv_isa/Makefile
@@ -44,8 +44,8 @@
$(bld_dir)/%.hex: $(bld_dir)/%.elf
$(RISCV_ROM_OBJCOPY) $^ $@
$(RISCV_RAM_OBJCOPY) $^ $@.ram
- #assign 0x0048_0xxx to 0x0000_0xxx to map to TCM Memory
- sed -i 's/@00480/@00000/g' $@.ram
+ #assign 0x0800_0xxx to 0x0000_0xxx to map to TCM Memory
+ sed -i 's/@08000/@00000/g' $@.ram
$(bld_dir)/%.dump: $(bld_dir)/%.elf
$(RISCV_OBJDUMP) $^ > $@
diff --git a/verilog/dv/riscv_regress/user_risc_regress_tb.v b/verilog/dv/riscv_regress/user_risc_regress_tb.v
index 1384d19..41f5bb4 100644
--- a/verilog/dv/riscv_regress/user_risc_regress_tb.v
+++ b/verilog/dv/riscv_regress/user_risc_regress_tb.v
@@ -77,6 +77,12 @@
`include "uprj_netlists.v"
`include "mt48lc8m8a2.v"
+localparam [31:0] YCR1_SIM_EXIT_ADDR = 32'h0000_00F8;
+localparam [31:0] YCR1_SIM_PRINT_ADDR = 32'hF000_0000;
+localparam [31:0] YCR1_SIM_EXT_IRQ_ADDR = 32'hF000_0100;
+localparam [31:0] YCR1_SIM_SOFT_IRQ_ADDR = 32'hF000_0200;
+
+
module user_risc_regress_tb;
reg clock;
reg wb_rst_i;
@@ -133,7 +139,8 @@
int unsigned tests_passed;
int unsigned tests_total;
- logic [31:0] tem_mem[0:1047];
+ logic [7:0] tem_mem[0:4095];
+ logic [31:0] mem_data;
//-----------------------------------------------------------------
@@ -180,7 +187,9 @@
$dumpvars(1, user_risc_regress_tb);
$dumpvars(1, user_risc_regress_tb.u_top);
$dumpvars(0, user_risc_regress_tb.u_top.u_riscv_top);
- $dumpvars(0, user_risc_regress_tb.u_top.u_pinmux);
+ $dumpvars(0, user_risc_regress_tb.u_top.u_qspi_master);
+ $dumpvars(0, user_risc_regress_tb.u_top.u_intercon);
+ $dumpvars(0, user_risc_regress_tb.u_top.u_mbist);
end
`endif
@@ -200,17 +209,21 @@
// some of the RISCV test need SRAM area for specific
// instruction execution like fence
$sformat(test_ram_file, "%s.ram",test_file);
- // Load the RAM content to local temp memory
- $readmemh(test_ram_file,tem_mem);
// Split the Temp memory content to two sram file
$readmemh(test_ram_file,tem_mem);
- $writememh("sram0.hex",tem_mem,0,511);
- $writememh("sram1.hex",tem_mem,512,1023);
// Load the SRAM0/SRAM1 with 2KB data
- $write("\033[0;34m---Initializing the u_tsram0_2kb Memory with Hexfile: sram0.hex\033[0m\n");
- $readmemh("sram0.hex",u_top.u_tsram0_2kb.mem);
- $write("\033[0;34m---Initializing the u_tsram1_2kb Memory with Hexfile: sram1.hex\033[0m\n");
- $readmemh("sram1.hex",u_top.u_tsram1_2kb.mem);
+ $write("\033[0;34m---Initializing the u_sram0_2kb Memory with Hexfile: %s\033[0m\n",test_ram_file);
+ // Initializing the SRAM
+ for(i = 0 ; i < 2048; i = i +4) begin
+ mem_data = {tem_mem[i+3],tem_mem[i+2],tem_mem[i+1],tem_mem[i+0]};
+ //$display("Filling Mem Location : %x with data : %x",i, mem_data);
+ u_top.u_mbist.u_sram0_2kb.mem[i/4] = mem_data;
+ end
+ for(i = 2048 ; i < 4096; i = i +4) begin
+ mem_data = {tem_mem[i+3],tem_mem[i+2],tem_mem[i+1],tem_mem[i+0]};
+ //$display("Filling Mem Location : %x with data : %x",i, mem_data);
+ u_top.u_mbist.u_sram1_2kb.mem[(2048-i)/4] = mem_data;
+ end
//for(i =32'h00; i < 32'h100; i = i+1)
// $display("Location: %x, Data: %x", i, u_top.u_tsram0_2kb.mem[i]);
@@ -230,8 +243,10 @@
repeat (2) @(posedge clock);
#1;
+ // Enable the DCACHE Remap to SRAM region
+ wb_user_core_write('h3080_000C,{4'b0000,4'b1111, 24'h0});
// Remove all the reset
- wb_user_core_write('h3080_0000,'hF);
+ wb_user_core_write('h3080_0000,'h8F);
end
diff --git a/verilog/dv/uart_master/Makefile b/verilog/dv/uart_master/Makefile
index a207608..ec6f963 100644
--- a/verilog/dv/uart_master/Makefile
+++ b/verilog/dv/uart_master/Makefile
@@ -31,7 +31,7 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
diff --git a/verilog/dv/user_basic/Makefile b/verilog/dv/user_basic/Makefile
index 2c0b01f..e1558d4 100644
--- a/verilog/dv/user_basic/Makefile
+++ b/verilog/dv/user_basic/Makefile
@@ -29,7 +29,7 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
diff --git a/verilog/dv/user_i2cm/Makefile b/verilog/dv/user_i2cm/Makefile
index 605c623..5788ed8 100644
--- a/verilog/dv/user_i2cm/Makefile
+++ b/verilog/dv/user_i2cm/Makefile
@@ -29,7 +29,7 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
diff --git a/verilog/dv/user_mbist_test1/Makefile b/verilog/dv/user_mbist_test1/Makefile
index 3263b33..685d6ba 100644
--- a/verilog/dv/user_mbist_test1/Makefile
+++ b/verilog/dv/user_mbist_test1/Makefile
@@ -29,7 +29,7 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
@@ -84,7 +84,7 @@
endif
%.vcd: %.vvp
- vvp $<
+ vvp $< | tee sim_result.log
check-env:
ifndef PDK_ROOT
diff --git a/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v b/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v
index 9637b3c..076c60a 100644
--- a/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v
+++ b/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v
@@ -635,7 +635,6 @@
end else begin
$display("Monitor: Step-6.4: BIST Test with Five Memory Error insertion test Failed");
end
-
$dumpon;
$display("###################################################");
$display(" MBIST Test with Functional Access, continuation of previous MBIST Signature");
@@ -644,6 +643,8 @@
begin
// Remove the Bist Enable and Bist Run
wb_user_core_write(`GLBL_BIST_CTRL1,'h000);
+ // Remove WB and BIST RESET
+ wb_user_core_write(`WB_GLBL_CTRL,'h081);
// Fill Random Data
for (i=0; i< 9'h1FC; i=i+1) begin
@@ -850,80 +851,80 @@
repeat (1) @(posedge clock);
#1;
- if(u_top.u_sram0_2kb.web0 == 1'b0 &&
- ((num_fault[0] > 0 && u_top.u_sram0_2kb.addr0 == faultaddr[0]) ||
- (num_fault[0] > 1 && u_top.u_sram0_2kb.addr0 == faultaddr[1]) ||
- (num_fault[0] > 2 && u_top.u_sram0_2kb.addr0 == faultaddr[2]) ||
- (num_fault[0] > 3 && u_top.u_sram0_2kb.addr0 == faultaddr[3]) ||
- (num_fault[0] > 4 && u_top.u_sram0_2kb.addr0 == faultaddr[4]) ||
- (num_fault[0] > 5 && u_top.u_sram0_2kb.addr0 == faultaddr[5]) ||
- (num_fault[0] > 6 && u_top.u_sram0_2kb.addr0 == faultaddr[6]) ||
- (num_fault[0] > 7 && u_top.u_sram0_2kb.addr0 == faultaddr[7])))
+ if(u_top.u_mbist.u_sram0_2kb.web0 == 1'b0 &&
+ ((num_fault[0] > 0 && u_top.u_mbist.u_sram0_2kb.addr0 == faultaddr[0]) ||
+ (num_fault[0] > 1 && u_top.u_mbist.u_sram0_2kb.addr0 == faultaddr[1]) ||
+ (num_fault[0] > 2 && u_top.u_mbist.u_sram0_2kb.addr0 == faultaddr[2]) ||
+ (num_fault[0] > 3 && u_top.u_mbist.u_sram0_2kb.addr0 == faultaddr[3]) ||
+ (num_fault[0] > 4 && u_top.u_mbist.u_sram0_2kb.addr0 == faultaddr[4]) ||
+ (num_fault[0] > 5 && u_top.u_mbist.u_sram0_2kb.addr0 == faultaddr[5]) ||
+ (num_fault[0] > 6 && u_top.u_mbist.u_sram0_2kb.addr0 == faultaddr[6]) ||
+ (num_fault[0] > 7 && u_top.u_mbist.u_sram0_2kb.addr0 == faultaddr[7])))
begin
if(fault_type == 0) // Struck at 0
- force u_top.u_sram0_2kb.din0 = u_top.mem0_din_a & 32'hFFFF_FFFE;
+ force u_top.u_mbist.u_sram0_2kb.din0 = u_top.u_mbist.mem0_din_a & 32'hFFFF_FFFE;
else
- force u_top.u_sram0_2kb.din0 = u_top.mem0_din_a | 32'h1;
+ force u_top.u_mbist.u_sram0_2kb.din0 = u_top.u_mbist.mem0_din_a | 32'h1;
-> error_insert;
end else begin
- release u_top.u_sram0_2kb.din0;
+ release u_top.u_mbist.u_sram0_2kb.din0;
end
- if(u_top.u_sram1_2kb.web0 == 1'b0 &&
- ((num_fault[1] > 0 && u_top.u_sram1_2kb.addr0 == faultaddr[0]+1) ||
- (num_fault[1] > 1 && u_top.u_sram1_2kb.addr0 == faultaddr[1]+1) ||
- (num_fault[1] > 2 && u_top.u_sram1_2kb.addr0 == faultaddr[2]+1) ||
- (num_fault[1] > 3 && u_top.u_sram1_2kb.addr0 == faultaddr[3]+1) ||
- (num_fault[1] > 4 && u_top.u_sram1_2kb.addr0 == faultaddr[4]+1) ||
- (num_fault[1] > 5 && u_top.u_sram1_2kb.addr0 == faultaddr[5]+1) ||
- (num_fault[1] > 6 && u_top.u_sram1_2kb.addr0 == faultaddr[6]+1) ||
- (num_fault[1] > 7 && u_top.u_sram1_2kb.addr0 == faultaddr[7]+1)))
+ if(u_top.u_mbist.u_sram1_2kb.web0 == 1'b0 &&
+ ((num_fault[1] > 0 && u_top.u_mbist.u_sram1_2kb.addr0 == faultaddr[0]+1) ||
+ (num_fault[1] > 1 && u_top.u_mbist.u_sram1_2kb.addr0 == faultaddr[1]+1) ||
+ (num_fault[1] > 2 && u_top.u_mbist.u_sram1_2kb.addr0 == faultaddr[2]+1) ||
+ (num_fault[1] > 3 && u_top.u_mbist.u_sram1_2kb.addr0 == faultaddr[3]+1) ||
+ (num_fault[1] > 4 && u_top.u_mbist.u_sram1_2kb.addr0 == faultaddr[4]+1) ||
+ (num_fault[1] > 5 && u_top.u_mbist.u_sram1_2kb.addr0 == faultaddr[5]+1) ||
+ (num_fault[1] > 6 && u_top.u_mbist.u_sram1_2kb.addr0 == faultaddr[6]+1) ||
+ (num_fault[1] > 7 && u_top.u_mbist.u_sram1_2kb.addr0 == faultaddr[7]+1)))
begin
if(fault_type == 0) // Struck at 0
- force u_top.u_sram1_2kb.din0 = u_top.mem1_din_a & 32'hFFFF_FFFE;
+ force u_top.u_mbist.u_sram1_2kb.din0 = u_top.u_mbist.mem1_din_a & 32'hFFFF_FFFE;
else
- force u_top.u_sram1_2kb.din0 = u_top.mem1_din_a | 32'h1;
+ force u_top.u_mbist.u_sram1_2kb.din0 = u_top.u_mbist.mem1_din_a | 32'h1;
-> error_insert;
end else begin
- release u_top.u_sram1_2kb.din0;
+ release u_top.u_mbist.u_sram1_2kb.din0;
end
- if(u_top.u_sram2_2kb.web0 == 1'b0 &&
- ((num_fault[2] > 0 && u_top.u_sram2_2kb.addr0 == faultaddr[0]+2) ||
- (num_fault[2] > 1 && u_top.u_sram2_2kb.addr0 == faultaddr[1]+2) ||
- (num_fault[2] > 2 && u_top.u_sram2_2kb.addr0 == faultaddr[2]+2) ||
- (num_fault[2] > 3 && u_top.u_sram2_2kb.addr0 == faultaddr[3]+2) ||
- (num_fault[2] > 4 && u_top.u_sram2_2kb.addr0 == faultaddr[4]+2) ||
- (num_fault[2] > 5 && u_top.u_sram2_2kb.addr0 == faultaddr[5]+2) ||
- (num_fault[2] > 6 && u_top.u_sram2_2kb.addr0 == faultaddr[6]+2) ||
- (num_fault[2] > 7 && u_top.u_sram2_2kb.addr0 == faultaddr[7]+2)))
+ if(u_top.u_mbist.u_sram2_2kb.web0 == 1'b0 &&
+ ((num_fault[2] > 0 && u_top.u_mbist.u_sram2_2kb.addr0 == faultaddr[0]+2) ||
+ (num_fault[2] > 1 && u_top.u_mbist.u_sram2_2kb.addr0 == faultaddr[1]+2) ||
+ (num_fault[2] > 2 && u_top.u_mbist.u_sram2_2kb.addr0 == faultaddr[2]+2) ||
+ (num_fault[2] > 3 && u_top.u_mbist.u_sram2_2kb.addr0 == faultaddr[3]+2) ||
+ (num_fault[2] > 4 && u_top.u_mbist.u_sram2_2kb.addr0 == faultaddr[4]+2) ||
+ (num_fault[2] > 5 && u_top.u_mbist.u_sram2_2kb.addr0 == faultaddr[5]+2) ||
+ (num_fault[2] > 6 && u_top.u_mbist.u_sram2_2kb.addr0 == faultaddr[6]+2) ||
+ (num_fault[2] > 7 && u_top.u_mbist.u_sram2_2kb.addr0 == faultaddr[7]+2)))
begin
if(fault_type == 0) // Struck at 0
- force u_top.u_sram2_2kb.din0 = u_top.mem2_din_a & 32'hFFFF_FFFE;
+ force u_top.u_mbist.u_sram2_2kb.din0 = u_top.u_mbist.mem2_din_a & 32'hFFFF_FFFE;
else
- force u_top.u_sram2_2kb.din0 = u_top.mem2_din_a | 32'h1;
+ force u_top.u_mbist.u_sram2_2kb.din0 = u_top.u_mbist.mem2_din_a | 32'h1;
-> error_insert;
end else begin
- release u_top.u_sram2_2kb.din0;
+ release u_top.u_mbist.u_sram2_2kb.din0;
end
- if(u_top.u_sram3_2kb.web0 == 1'b0 &&
- ((num_fault[3] > 0 && u_top.u_sram3_2kb.addr0 == faultaddr[0]+3) ||
- (num_fault[3] > 1 && u_top.u_sram3_2kb.addr0 == faultaddr[1]+3) ||
- (num_fault[3] > 2 && u_top.u_sram3_2kb.addr0 == faultaddr[2]+3) ||
- (num_fault[3] > 3 && u_top.u_sram3_2kb.addr0 == faultaddr[3]+3) ||
- (num_fault[3] > 4 && u_top.u_sram3_2kb.addr0 == faultaddr[4]+3) ||
- (num_fault[3] > 5 && u_top.u_sram3_2kb.addr0 == faultaddr[5]+3) ||
- (num_fault[3] > 6 && u_top.u_sram3_2kb.addr0 == faultaddr[6]+3) ||
- (num_fault[3] > 7 && u_top.u_sram3_2kb.addr0 == faultaddr[7]+3)))
+ if(u_top.u_mbist.u_sram3_2kb.web0 == 1'b0 &&
+ ((num_fault[3] > 0 && u_top.u_mbist.u_sram3_2kb.addr0 == faultaddr[0]+3) ||
+ (num_fault[3] > 1 && u_top.u_mbist.u_sram3_2kb.addr0 == faultaddr[1]+3) ||
+ (num_fault[3] > 2 && u_top.u_mbist.u_sram3_2kb.addr0 == faultaddr[2]+3) ||
+ (num_fault[3] > 3 && u_top.u_mbist.u_sram3_2kb.addr0 == faultaddr[3]+3) ||
+ (num_fault[3] > 4 && u_top.u_mbist.u_sram3_2kb.addr0 == faultaddr[4]+3) ||
+ (num_fault[3] > 5 && u_top.u_mbist.u_sram3_2kb.addr0 == faultaddr[5]+3) ||
+ (num_fault[3] > 6 && u_top.u_mbist.u_sram3_2kb.addr0 == faultaddr[6]+3) ||
+ (num_fault[3] > 7 && u_top.u_mbist.u_sram3_2kb.addr0 == faultaddr[7]+3)))
begin
if(fault_type == 0) // Struck at 0
- force u_top.u_sram3_2kb.din0 = u_top.mem3_din_a & 32'hFFFF_FFFE;
+ force u_top.u_mbist.u_sram3_2kb.din0 = u_top.u_mbist.mem3_din_a & 32'hFFFF_FFFE;
else
- force u_top.u_sram3_2kb.din0 = u_top.mem3_din_a | 32'h1;
+ force u_top.u_mbist.u_sram3_2kb.din0 = u_top.u_mbist.mem3_din_a | 32'h1;
-> error_insert;
end else begin
- release u_top.u_sram3_2kb.din0;
+ release u_top.u_mbist.u_sram3_2kb.din0;
end
//if(u_top.u_sram5_1kb.web0 == 1'b0 &&
diff --git a/verilog/dv/user_risc_boot/Makefile b/verilog/dv/user_risc_boot/Makefile
index 26104a8..1057c10 100644
--- a/verilog/dv/user_risc_boot/Makefile
+++ b/verilog/dv/user_risc_boot/Makefile
@@ -29,7 +29,7 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
@@ -59,12 +59,12 @@
vvp: ${PATTERN:=.vvp}
%.vvp: %_tb.v
- ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_risc_boot.c -o user_risc_boot.o
- ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt_tcm.S -o crt_tcm.o
- ${GCC64_PREFIX}-gcc -o user_risc_boot.elf -T $(YIFIVE_FIRMWARE_PATH)/link_tcm.ld user_risc_boot.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
+ ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_risc_boot.c -o user_risc_boot.o
+ ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o
+ ${GCC64_PREFIX}-gcc -o user_risc_boot.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld user_risc_boot.o crt.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
${GCC64_PREFIX}-objcopy -O verilog user_risc_boot.elf user_risc_boot.hex
${GCC64_PREFIX}-objdump -D user_risc_boot.elf > user_risc_boot.dump
- rm crt_tcm.o user_risc_boot.o
+ rm crt.o user_risc_boot.o
ifeq ($(SIM),RTL)
ifeq ($(DUMP),OFF)
iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
diff --git a/verilog/dv/user_risc_soft_boot/Makefile b/verilog/dv/user_risc_soft_boot/Makefile
index 3998666..12f65be 100644
--- a/verilog/dv/user_risc_soft_boot/Makefile
+++ b/verilog/dv/user_risc_soft_boot/Makefile
@@ -29,7 +29,7 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
@@ -59,12 +59,12 @@
vvp: ${PATTERN:=.vvp}
%.vvp: %_tb.v
- ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_risc_boot.c -o user_risc_boot.o
- ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt_tcm.S -o crt_tcm.o
- ${GCC64_PREFIX}-gcc -o user_risc_boot.elf -T $(YIFIVE_FIRMWARE_PATH)/link_tcm.ld user_risc_boot.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
+ ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_risc_boot.c -o user_risc_boot.o
+ ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o
+ ${GCC64_PREFIX}-gcc -o user_risc_boot.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld user_risc_boot.o crt.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
${GCC64_PREFIX}-objcopy -O verilog user_risc_boot.elf user_risc_boot.hex
${GCC64_PREFIX}-objdump -D user_risc_boot.elf > user_risc_boot.dump
- rm crt_tcm.o user_risc_boot.o
+ rm crt.o user_risc_boot.o
ifeq ($(SIM),RTL)
ifeq ($(DUMP),OFF)
iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
diff --git a/verilog/dv/user_risc_soft_boot/user_risc_soft_boot_tb.v b/verilog/dv/user_risc_soft_boot/user_risc_soft_boot_tb.v
index dcf85c6..1350b07 100644
--- a/verilog/dv/user_risc_soft_boot/user_risc_soft_boot_tb.v
+++ b/verilog/dv/user_risc_soft_boot/user_risc_soft_boot_tb.v
@@ -136,7 +136,8 @@
`ifdef WFDUMP
initial begin
$dumpfile("simx.vcd");
- $dumpvars(4, user_risc_soft_boot_tb);
+ $dumpvars(4, user_risc_soft_boot_tb.u_top);
+ //$dumpvars(3, user_risc_soft_boot_tb.u_top.u_riscv_top);
end
`endif
@@ -155,26 +156,26 @@
tem_mem_32b[i] = {tem_mem[(i*4)+3],tem_mem[(i*4)+2],tem_mem[(i*4)+1],tem_mem[(i*4)]};
$writememh("sram_bank0.hex",tem_mem_32b,0,511);
- $readmemh("sram_bank0.hex",u_top.u_sram0_2kb.mem,0,511);
+ $readmemh("sram_bank0.hex",u_top.u_mbist.u_sram0_2kb.mem,0,511);
for(i =512; i < 1023; i = i+1)
tem_mem_32b[i-512] = {tem_mem[(i*4)+3],tem_mem[(i*4)+2],tem_mem[(i*4)+1],tem_mem[(i*4)]};
$writememh("sram_bank1.hex",tem_mem_32b,0,511);
- $readmemh("sram_bank1.hex",u_top.u_sram1_2kb.mem,0,511);
+ $readmemh("sram_bank1.hex",u_top.u_mbist.u_sram1_2kb.mem,0,511);
// Enable the SRAM Remap to boot region
wb_user_core_write('h3080_000C,{4'b1111,28'h0});
repeat (2) @(posedge clock);
#1;
// Remove the reset, mbist, wishbone, riscv
- wb_user_core_write('h3080_0000,'h83);
+ wb_user_core_write('h3080_0000,'h8F);
// Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (10) begin
- repeat (400) @(posedge clock);
- // $display("+1000 cycles");
+ repeat (24) begin
+ repeat (500) @(posedge clock);
+ //$display("+500 cycles");
end
diff --git a/verilog/dv/user_spi/Makefile b/verilog/dv/user_spi/Makefile
index 32bbfec..e0934e1 100644
--- a/verilog/dv/user_spi/Makefile
+++ b/verilog/dv/user_spi/Makefile
@@ -29,7 +29,7 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
@@ -54,17 +54,10 @@
all: ${PATTERN:=.vcd}
-hex: ${PATTERN:=.hex}
vvp: ${PATTERN:=.vvp}
%.vvp: %_tb.v
- ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_risc_boot.c -o user_risc_boot.o
- ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt_tcm.S -o crt_tcm.o
- ${GCC64_PREFIX}-gcc -o user_risc_boot.elf -T $(YIFIVE_FIRMWARE_PATH)/link_tcm.ld user_risc_boot.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
- ${GCC64_PREFIX}-objcopy -O verilog user_risc_boot.elf user_risc_boot.hex
- ${GCC64_PREFIX}-objdump -D user_risc_boot.elf > user_risc_boot.dump
- rm crt_tcm.o user_risc_boot.o
ifeq ($(SIM),RTL)
ifeq ($(DUMP),OFF)
iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
@@ -94,18 +87,13 @@
%.vcd: %.vvp
vvp $<
-%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s
- ${GCC64_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
-
%.hex:
echo @"This is user boot test, noting to compile the mangment core code"
-%.bin: %.elf
- ${GCC64_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
# ---- Clean ----
clean:
- rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump
+ rm -f *.vvp *.vcd *.log *.fst
.PHONY: clean hex all
diff --git a/verilog/dv/user_spi/flash0.hex b/verilog/dv/user_spi/flash0.hex
new file mode 100755
index 0000000..24a2e47
--- /dev/null
+++ b/verilog/dv/user_spi/flash0.hex
@@ -0,0 +1,79 @@
+@00000000
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 13 00 00 00 6F 00 00 00 FF FF FF FF
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+6F 00 60 18 13 00 00 00 13 00 00 00 13 00 00 00
+13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00
+13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00
+13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00
+93 00 00 00 13 01 00 00 93 01 00 00 13 02 00 00
+93 02 00 00 13 03 00 00 93 03 00 00 13 04 00 00
+93 04 00 00 13 05 00 00 93 05 00 00 13 06 00 00
+93 06 00 00 13 07 00 00 93 07 00 00 13 08 00 00
+93 08 00 00 13 09 00 00 93 09 00 00 13 0A 00 00
+93 0A 00 00 13 0B 00 00 93 0B 00 00 13 0C 00 00
+93 0C 00 00 13 0D 00 00 93 0D 00 00 13 0E 00 00
+93 0E 00 00 13 0F 00 00 93 0F 00 00 97 01 48 00
+93 81 41 62 13 05 00 40 97 05 48 00 93 85 85 D7
+17 06 48 00 13 06 06 E3 63 0D B5 00 29 A0 14 41
+94 C1 11 05 91 05 E3 9C C5 FE 17 06 48 00 13 06
+66 E1 97 05 48 00 93 85 E5 E0 21 A0 23 20 06 00
+11 06 E3 9D C5 FE 13 81 01 76 17 05 48 00 13 05
+65 DF 17 06 48 00 13 06 E6 DE B3 05 A6 40 13 87
+01 66 33 02 B7 40 92 85 17 06 48 00 13 06 86 DD
+29 A0 14 41 94 C1 11 05 91 05 E3 1C C5 FE 21 A0
+23 A0 05 00 91 05 E3 9D E5 FE B7 02 49 00 05 43
+23 A0 62 00 B7 02 49 00 91 02 13 03 30 06 23 A0
+62 00 B7 02 49 00 C1 02 7D 53 23 A0 62 00 23 A2
+62 00 01 45 81 45 97 02 48 00 E7 80 A2 CC 97 02
+48 00 93 82 22 D2 6D 71 06 C2 0A C4 0E C6 12 C8
+16 CA 1A CC 1E CE 22 D0 26 D2 2A D4 2E D6 32 D8
+36 DA 3A DC 3E DE C2 C0 C6 C2 CA C4 CE C6 D2 C8
+D6 CA DA CC DE CE E2 D0 E6 D2 EA D4 EE D6 F2 D8
+F6 DA FA DC FE DE 73 25 20 34 F3 25 10 34 0A 86
+EF 00 80 04 92 40 22 41 B2 41 42 42 D2 42 62 43
+F2 43 02 54 92 54 22 55 B2 55 42 56 D2 56 62 57
+F2 57 06 48 96 48 26 49 B6 49 46 4A D6 4A 66 4B
+F6 4B 06 5C 96 5C 26 5D B6 5D 46 5E D6 5E 66 5F
+F6 5F 51 61 73 00 20 30 6F F0 DF D1 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+@00000400
+37 37 22 11 B7 07 03 30 93 02 47 34 37 43 33 22
+23 AC 57 04 93 03 53 45 37 55 44 33 23 AE 77 04
+93 05 65 56 37 66 55 44 AC D3 93 06 76 67 37 78
+66 55 F4 D3 93 08 88 78 37 9E 77 66 23 A4 17 07
+93 0E 9E 89 23 A6 D7 07 01 A0 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+97 02 B8 FF 93 82 42 09 82 82 13 00 00 00 13 00
+00 00 13 00 00 00 13 00 00 00 13 00 00 00 01 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+@000004A0
+13 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/verilog/dv/user_spi/user_spi_tb.v b/verilog/dv/user_spi/user_spi_tb.v
index 2396183..486d6ea 100644
--- a/verilog/dv/user_spi/user_spi_tb.v
+++ b/verilog/dv/user_spi/user_spi_tb.v
@@ -229,7 +229,7 @@
$display("#############################################");
$display(" Read Identification (RDID:0x9F) ");
$display("#############################################");
- wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
+ wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,2'b00,P_SINGLE,P_SINGLE,4'b0001});
wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h4,2'b00,2'b00,P_FSM_CR,8'h00,8'h9F});
wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00190201);
@@ -1179,7 +1179,7 @@
// Quad flash
- s25fl256s #(.mem_file_name("user_risc_boot.hex"),
+ s25fl256s #(.mem_file_name("flash0.hex"),
.otp_file_name("none"),
.TimingModel("S25FL512SAGMFI010_F_30pF"))
u_spi_flash_256mb (
diff --git a/verilog/dv/user_uart/Makefile b/verilog/dv/user_uart/Makefile
index 95eba63..387f35d 100644
--- a/verilog/dv/user_uart/Makefile
+++ b/verilog/dv/user_uart/Makefile
@@ -29,7 +29,7 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
@@ -59,12 +59,12 @@
vvp: ${PATTERN:=.vvp}
%.vvp: %_tb.v
- ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_uart.c -o user_uart.o
- ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt_tcm.S -o crt_tcm.o
- ${GCC64_PREFIX}-gcc -o user_uart.elf -T $(YIFIVE_FIRMWARE_PATH)/link_tcm.ld user_uart.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
+ ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_uart.c -o user_uart.o
+ ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o
+ ${GCC64_PREFIX}-gcc -o user_uart.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld user_uart.o crt.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
${GCC64_PREFIX}-objcopy -O verilog user_uart.elf user_uart.hex
${GCC64_PREFIX}-objdump -D user_uart.elf > user_uart.dump
- rm crt_tcm.o user_uart.o
+ rm crt.o user_uart.o
ifeq ($(SIM),RTL)
ifeq ($(DUMP),OFF)
iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index edda128..7171ba6 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -149,7 +149,7 @@
`ifdef WFDUMP
initial begin
- $dumpfile("risc_boot.vcd");
+ $dumpfile("simx.vcd");
$dumpvars(1, user_uart_tb);
$dumpvars(0, user_uart_tb.u_top);
end
@@ -186,7 +186,7 @@
// Remove all the reset
wb_user_core_write('h3080_0000,'h1F);
- repeat (16000) @(posedge clock); // wait for Processor Get Ready
+ repeat (20000) @(posedge clock); // wait for Processor Get Ready
tb_uart.uart_init;
wb_user_core_write(`ADDR_SPACE_UART+8'h0,{3'h0,2'b00,1'b1,1'b1,1'b1});
diff --git a/verilog/dv/user_uart_master/Makefile b/verilog/dv/user_uart_master/Makefile
index dbe1ce7..b52caef 100644
--- a/verilog/dv/user_uart_master/Makefile
+++ b/verilog/dv/user_uart_master/Makefile
@@ -29,7 +29,7 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile
index d378ce7..a19be6a 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/wb_port/Makefile
@@ -30,7 +30,7 @@
UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
diff --git a/verilog/rtl/lib/sync_fifo2.sv b/verilog/rtl/lib/sync_fifo2.sv
new file mode 100755
index 0000000..f71ad30
--- /dev/null
+++ b/verilog/rtl/lib/sync_fifo2.sv
@@ -0,0 +1,222 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+/*********************************************************************
+
+ SYNC FIFO with empty,aempty,full,afull
+
+
+ Description: SYNC FIFO
+
+ To Do:
+ nothing
+
+ Author(s): Dinesh Annayya, dinesha@opencores.org
+
+ Copyright (C) 2000 Authors and OPENCORES.ORG
+
+ This source file may be used and distributed without
+ restriction provided that this copyright statement is not
+ removed from the file and that any derivative work contains
+ the original copyright notice and the associated disclaimer.
+
+ This source file is free software; you can redistribute it
+ and/or modify it under the terms of the GNU Lesser General
+ Public License as published by the Free Software Foundation;
+ either version 2.1 of the License, or (at your option) any
+later version.
+
+ This source is distributed in the hope that it will be
+ useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+ PURPOSE. See the GNU Lesser General Public License for more
+ details.
+
+ You should have received a copy of the GNU Lesser General
+ Public License along with this source; if not, download it
+ from http://www.opencores.org/lgpl.shtml
+
+*******************************************************************/
+
+//-------------------------------------------
+// sync FIFO
+//-----------------------------------------------
+//`timescale 1ns/1ps
+
+module sync_fifo2 (clk,
+ reset_n,
+ wr_en,
+ wr_data,
+ full,
+ afull,
+ rd_en,
+ empty,
+ aempty,
+ rd_data);
+
+ parameter W = 4'd8;
+ parameter DP = 3'd4;
+ parameter WR_FAST = 1'b1;
+ parameter RD_FAST = 1'b1;
+ parameter FULL_DP = DP;
+ parameter EMPTY_DP = 1'b0;
+
+ parameter AW = (DP == 2) ? 1 :
+ (DP == 4) ? 2 :
+ (DP == 8) ? 3 :
+ (DP == 16) ? 4 :
+ (DP == 32) ? 5 :
+ (DP == 64) ? 6 :
+ (DP == 128) ? 7 :
+ (DP == 256) ? 8 : 0;
+
+ output [W-1 : 0] rd_data;
+ input [W-1 : 0] wr_data;
+ input clk, reset_n, wr_en, rd_en;
+ output full, empty;
+ output afull, aempty; // about full and about to empty
+
+
+ // synopsys translate_off
+
+ initial begin
+ if (AW == 0) begin
+ $display ("%m : ERROR!!! Fifo depth %d not in range 2 to 256", DP);
+ end // if (AW == 0)
+ end // initial begin
+
+ // synopsys translate_on
+
+ reg [W-1 : 0] mem[DP-1 : 0];
+
+ /*********************** write side ************************/
+ reg [AW:0] wr_ptr;
+ reg full_q;
+ wire full_c;
+ wire afull_c;
+ wire [AW:0]wr_ptr_inc = wr_ptr + 1'b1;
+ wire [AW:0]wr_cnt = get_cnt(wr_ptr, rd_ptr);
+
+ assign full_c = (wr_cnt == FULL_DP) ? 1'b1 : 1'b0;
+ assign afull_c = (wr_cnt == FULL_DP-1) ? 1'b1 : 1'b0;
+
+
+ always @(posedge clk or negedge reset_n) begin
+ if (!reset_n) begin
+ wr_ptr <= 0;
+ full_q <= 0;
+ end
+ else if (wr_en) begin
+ wr_ptr <= wr_ptr_inc;
+ if (wr_cnt == (FULL_DP-1)) begin
+ full_q <= 1'b1;
+ end
+ end
+ else begin
+ if (full_q && (wr_cnt<FULL_DP)) begin
+ full_q <= 1'b0;
+ end
+ end
+ end
+
+ assign full = (WR_FAST == 1) ? full_c : full_q;
+ assign afull = afull_c;
+
+ always @(posedge clk) begin
+ if (wr_en) begin
+ mem[wr_ptr[AW-1:0]] <= wr_data;
+ end
+ end
+
+
+
+ /************************ read side *****************************/
+ reg [AW:0] rd_ptr;
+ reg empty_q;
+ wire empty_c;
+ wire aempty_c;
+ wire [AW:0] rd_ptr_inc = rd_ptr + 1'b1;
+ wire [AW:0] rd_cnt = get_cnt(wr_ptr, rd_ptr);
+
+ assign empty_c = (rd_cnt == 0) ? 1'b1 : 1'b0;
+ assign aempty_c = (rd_cnt == 1) ? 1'b1 : 1'b0;
+
+ always @(posedge clk or negedge reset_n) begin
+ if (!reset_n) begin
+ rd_ptr <= 0;
+ empty_q <= 1'b1;
+ end
+ else begin
+ if (rd_en) begin
+ rd_ptr <= rd_ptr_inc;
+ if (rd_cnt==(EMPTY_DP+1)) begin
+ empty_q <= 1'b1;
+ end
+ end
+ else begin
+ if (empty_q && (rd_cnt!=EMPTY_DP)) begin
+ empty_q <= 1'b0;
+ end
+ end
+ end
+ end
+
+ assign empty = (RD_FAST == 1) ? empty_c : empty_q;
+ assign aempty = aempty_c;
+
+ reg [W-1 : 0] rd_data_q;
+
+ wire [W-1 : 0] rd_data_c = mem[rd_ptr[AW-1:0]];
+
+
+ always @(posedge clk) begin
+ rd_data_q <= rd_data_c;
+ end
+ assign rd_data = (RD_FAST == 1) ? rd_data_c : rd_data_q;
+
+
+
+
+function [AW:0] get_cnt;
+input [AW:0] wr_ptr, rd_ptr;
+begin
+ if (wr_ptr >= rd_ptr) begin
+ get_cnt = (wr_ptr - rd_ptr);
+ end
+ else begin
+ get_cnt = DP*2 - (rd_ptr - wr_ptr);
+ end
+end
+endfunction
+
+// synopsys translate_off
+always @(posedge clk) begin
+ if (wr_en && full) begin
+ $display($time, "%m Error! afifo overflow!");
+ $stop;
+ end
+end
+
+always @(posedge clk) begin
+ if (rd_en && empty) begin
+ $display($time, "%m error! afifo underflow!");
+ $stop;
+ end
+end
+// synopsys translate_on
+
+endmodule
diff --git a/verilog/rtl/lib/sync_wbb.sv b/verilog/rtl/lib/sync_wbb.sv
new file mode 100644
index 0000000..a8c8209
--- /dev/null
+++ b/verilog/rtl/lib/sync_wbb.sv
@@ -0,0 +1,334 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// sync Wishbone Interface iBurst Enable and lack ////
+//// ////
+//// This file is part of the YIFive cores project ////
+//// http://www.opencores.org/cores/yifive/ ////
+//// ////
+//// Description ////
+//// This block does async Wishbone from one clock to other ////
+//// clock domain
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 25th Feb 2021, Dinesh A ////
+//// initial version ////
+//// 0.2 - 28th Feb 2021, Dinesh A ////
+//// reduced the response FIFO path depth to 2 as ////
+//// return path used by only read logic and read is ////
+//// blocking request and expect only one location will ////
+//// be used ////
+//// 0.3 - 20 Jan 2022, Dinesh A ////
+//// added wishbone burst mode. Additional signal added ////
+//// A. *bl - 10 Bit word Burst count, 1 - 1 DW(32 bit)////
+//// B. *lack - Last Burst ack ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+module sync_wbb
+ #(parameter AW = 32,
+ parameter BW = 4,
+ parameter BL = 10,
+ parameter DW = 32)
+ (
+
+ // Master Port
+ input logic rst_n , // Regular Reset signal
+ input logic clk_i , // System clock
+ input logic wbm_cyc_i , // strobe/request
+ input logic wbm_stb_i , // strobe/request
+ input logic [AW-1:0] wbm_adr_i , // address
+ input logic wbm_we_i , // write
+ input logic [DW-1:0] wbm_dat_i , // data output
+ input logic [BW-1:0] wbm_sel_i , // byte enable
+ input logic [3:0] wbm_tid_i ,
+ input logic [BL-1:0] wbm_bl_i , // Burst Count
+ input logic wbm_bry_i , // Burst Ready
+ output logic [DW-1:0] wbm_dat_o , // data input
+ output logic wbm_ack_o , // acknowlegement
+ output logic wbm_lack_o , // Last Burst access
+ output logic wbm_err_o , // error
+
+ // Slave Port
+ output logic wbs_cyc_o , // strobe/request
+ output logic wbs_stb_o , // strobe/request
+ output logic [AW-1:0] wbs_adr_o , // address
+ output logic wbs_we_o , // write
+ output logic [DW-1:0] wbs_dat_o , // data output
+ output logic [BW-1:0] wbs_sel_o , // byte enable
+ output logic [3:0] wbs_tid_o ,
+ output logic [BL-1:0] wbs_bl_o , // Burst Count
+ output logic wbs_bry_o , // Busrt WData Avialble Or Ready To accept Rdata
+ input logic [DW-1:0] wbs_dat_i , // data input
+ input logic wbs_ack_i , // acknowlegement
+ input logic wbs_lack_i , // Last Ack
+ input logic wbs_err_i // error
+
+ );
+
+
+
+parameter CFW = AW+DW+BW+BL+4+1 ; // COMMAND FIFO WIDTH
+parameter RFW = DW+1+1 ; // RESPONSE FIFO WIDTH
+
+parameter IDLE = 2'b00;
+parameter WRITE_DATA = 2'b01;
+parameter READ_DATA = 2'b10;
+
+
+//-------------------------------------------------
+// Master Interface
+// -------------------------------------------------
+logic m_cmd_wr_en ;
+logic [CFW-1:0] m_cmd_wr_data ;
+logic m_cmd_wr_full ;
+logic m_cmd_wr_afull ;
+
+logic m_resp_rd_empty ;
+logic m_resp_rd_aempty ;
+logic m_resp_rd_en ;
+logic [RFW-1:0] m_resp_rd_data ;
+logic [BL-1:0] m_bl_cnt ;
+logic [1:0] m_state ;
+
+// Master Write Interface
+
+
+
+assign m_cmd_wr_data = {wbm_adr_i,wbm_we_i,wbm_dat_i,wbm_sel_i,wbm_tid_i,wbm_bl_i};
+
+assign wbm_dat_o = m_resp_rd_data[DW-1:0];
+assign wbm_err_o = 'b0;
+
+always@(negedge rst_n or posedge clk_i)
+begin
+ if(rst_n == 0) begin
+ m_cmd_wr_en <= 'b0;
+ m_resp_rd_en <= 'b0;
+ m_state <= 'h0;
+ m_bl_cnt <= 'h0;
+ wbm_ack_o <= 'b0;
+ wbm_lack_o <= 'b0;
+ end else begin
+ case(m_state)
+ IDLE: begin
+ // Read DATA
+ if(wbm_stb_i && !wbm_we_i && wbm_bry_i && !m_cmd_wr_full && !wbm_lack_o) begin
+ m_bl_cnt <= wbm_bl_i;
+ m_cmd_wr_en <= 'b1;
+ m_state <= READ_DATA;
+ end else if(wbm_stb_i && wbm_we_i && wbm_bry_i && !m_cmd_wr_full && !wbm_lack_o) begin
+ wbm_ack_o <= 'b1;
+ m_cmd_wr_en <= 'b1;
+ m_bl_cnt <= wbm_bl_i-1;
+ if(wbm_bl_i == 'h1) begin
+ wbm_lack_o <= 'b1;
+ m_state <= IDLE;
+ end else begin
+ m_bl_cnt <= wbm_bl_i-1;
+ m_state <= WRITE_DATA;
+ end
+ end else begin
+ m_resp_rd_en <= 'b0;
+ m_cmd_wr_en <= 'b0;
+ wbm_ack_o <= 'b0;
+ wbm_lack_o <= 'b0;
+ end
+ end
+
+ // Write next Transaction
+ WRITE_DATA: begin
+ if(m_cmd_wr_full != 1 && wbm_bry_i) begin
+ wbm_ack_o <= 'b1;
+ m_cmd_wr_en <= 'b1;
+ if(m_bl_cnt == 1) begin
+ wbm_lack_o <= 'b1;
+ m_state <= IDLE;
+ end else begin
+ m_bl_cnt <= m_bl_cnt-1;
+ end
+ end else begin
+ m_cmd_wr_en <= 'b0;
+ wbm_ack_o <= 'b0;
+ wbm_lack_o <= 'b0;
+ end
+ end
+
+ // Read Transaction
+ READ_DATA: begin
+ // Check Back to Back Ack and last Location case
+ if(((wbm_ack_o == 0 && m_resp_rd_empty != 1) ||
+ (wbm_ack_o == 1 && m_resp_rd_aempty != 1)) && wbm_bry_i) begin
+ m_resp_rd_en <= 'b1;
+ wbm_ack_o <= 'b1;
+ if(m_bl_cnt == 1) begin
+ wbm_lack_o <= 'b1;
+ m_state <= IDLE;
+ end else begin
+ m_bl_cnt <= m_bl_cnt-1;
+ end
+ end else begin
+ m_resp_rd_en <= 'b0;
+ m_cmd_wr_en <= 'b0;
+ wbm_ack_o <= 'b0;
+ wbm_lack_o <= 'b0;
+ end
+ end
+ endcase
+ end
+end
+
+
+//------------------------------
+// Slave Interface
+//-------------------------------
+
+logic [CFW-1:0] s_cmd_rd_data ;
+logic [CFW-1:0] s_cmd_rd_data_l ;
+logic s_cmd_rd_empty ;
+logic s_cmd_rd_aempty ;
+logic s_cmd_rd_en ;
+logic s_resp_wr_en ;
+logic [RFW-1:0] s_resp_wr_data ;
+logic s_resp_wr_full ;
+logic s_resp_wr_afull ;
+logic wbs_ack_f ;
+logic wbs_stb_l ;
+logic wbs_burst ;
+
+wire wbs_stb_pedge = (wbs_stb_l == 1'b0) && wbs_stb_o;
+
+
+always@(negedge rst_n or posedge clk_i)
+begin
+ if(rst_n == 0) begin
+ wbs_ack_f <= 1'b0;
+ wbs_stb_l <= 1'b0;
+ wbs_burst <= 'h0;
+ s_cmd_rd_data_l <= 'h0;
+ end else begin
+ wbs_ack_f <= wbs_lack_i;
+ wbs_stb_l <= wbs_stb_o;
+ if(s_cmd_rd_en)
+ s_cmd_rd_data_l <= s_cmd_rd_data;
+ if(wbs_stb_pedge && wbs_bl_o > 'h1)
+ wbs_burst <= 1'b1;
+ else if(wbs_lack_i)
+ wbs_burst <= 1'b0;
+ end
+end
+
+
+// Read Interface
+
+
+assign {wbs_adr_o,wbs_we_o,wbs_dat_o,wbs_sel_o,wbs_tid_o,wbs_bl_o} = (s_cmd_rd_empty) ? s_cmd_rd_data_l: s_cmd_rd_data;
+// All the downstream logic expect Stobe is getting de-asserted
+// atleast for 1 cycle after ack is generated
+assign wbs_stb_o = (wbs_burst) ? 1'b1 : ((wbs_ack_f) ? 1'b0 : (s_cmd_rd_empty) ? 1'b0: 1'b1);
+assign wbs_cyc_o = (wbs_burst) ? 1'b1 : ((wbs_ack_f) ? 1'b0 : (s_cmd_rd_empty) ? 1'b0: 1'b1);
+
+// Generate bust ready only we have space inside response fifo
+// In Write Phase,
+// Generate burst ready, only when we have wdata & space in response fifo
+// In Read Phase
+// Generate burst ready, only when space in response fifo
+//
+assign wbs_bry_o = (wbs_we_o) ? ((s_cmd_rd_empty || (s_cmd_rd_en && s_cmd_rd_aempty)) ? 1'b0: 1'b1) :
+ (s_resp_wr_full || (s_resp_wr_en && s_resp_wr_afull)) ? 1'b0: 1'b1;
+
+// During Write phase, cmd fifo will have wdata, so dequeue for every ack
+// During Read Phase, cmd fifo will be written only one time, hold the bus
+// untill last ack received
+assign s_cmd_rd_en = (wbs_stb_o && wbs_we_o) ? wbs_ack_i: wbs_lack_i;
+
+// Write Interface
+// response send only for read logic
+assign s_resp_wr_en = wbs_stb_o & (!wbs_we_o) & wbs_ack_i ;
+assign s_resp_wr_data = {wbs_err_i,wbs_lack_i,wbs_dat_i};
+
+sync_fifo2 #(.W(CFW), .DP(4),.WR_FAST(1), .RD_FAST(1)) u_cmd_if (
+ // Sync w.r.t WR clock
+ .clk (clk_i ),
+ .reset_n (rst_n ),
+ .wr_en (m_cmd_wr_en ),
+ .wr_data (m_cmd_wr_data ),
+ .full (m_cmd_wr_full ),
+ .afull (m_cmd_wr_afull ),
+
+ // Sync w.r.t RD Clock
+ .rd_en (s_cmd_rd_en ),
+ .empty (s_cmd_rd_empty ), // sync'ed to rd_clk
+ .aempty (s_cmd_rd_aempty ), // sync'ed to rd_clk
+ .rd_data (s_cmd_rd_data )
+ );
+
+
+// Response used only for read path,
+// As cache access will be busrt of 512 location, To
+// support continous ack, depth is increase to 8 location
+sync_fifo2 #(.W(RFW), .DP(4), .WR_FAST(1), .RD_FAST(1)) u_resp_if (
+ // Sync w.r.t WR clock
+ .clk (clk_i ),
+ .reset_n (rst_n ),
+ .wr_en (s_resp_wr_en ),
+ .wr_data (s_resp_wr_data ),
+ .full (s_resp_wr_full ),
+ .afull (s_resp_wr_afull ),
+
+ // Sync w.r.t RD Clock
+ .rd_en (m_resp_rd_en ),
+ .empty (m_resp_rd_empty ), // sync'ed to rd_clk
+ .aempty (m_resp_rd_aempty ), // sync'ed to rd_clk
+ .rd_data (m_resp_rd_data )
+ );
+
+
+
+endmodule
diff --git a/verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv b/verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv
index 5e22d3e..8f31671 100644
--- a/verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv
+++ b/verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv
@@ -68,16 +68,13 @@
// WB I/F
input logic [(BIST_NO_SRAM+1)/2-1:0] sram_id ,
input logic wb_clk_i , // System clock
- input logic wb_cyc_i , // strobe/request
- input logic [(BIST_NO_SRAM+1)/2-1:0] wb_cs_i , // Chip Select
- input logic wb_stb_i , // strobe/request
- input logic [BIST_ADDR_WD-1:0] wb_adr_i , // address
- input logic wb_we_i , // write
- input logic [BIST_DATA_WD-1:0] wb_dat_i , // data output
- input logic [BIST_DATA_WD/8-1:0] wb_sel_i , // byte enable
- output logic [BIST_DATA_WD-1:0] wb_dat_o , // data input
- output logic wb_ack_o , // acknowlegement
- output logic wb_err_o , // error
+ input logic [(BIST_NO_SRAM+1)/2-1:0] mem_cs , // Chip Select
+ input logic mem_req , // strobe/request
+ input logic [BIST_ADDR_WD-1:0] mem_addr , // address
+ input logic mem_we , // write
+ input logic [BIST_DATA_WD-1:0] mem_wdata , // data output
+ input logic [BIST_DATA_WD/8-1:0] mem_wmask , // byte enable
+ output logic [BIST_DATA_WD-1:0] mem_rdata , // data input
// MEM PORT
output logic func_clk ,
output logic func_cen ,
@@ -92,23 +89,14 @@
// Memory Write PORT
assign func_clk = wb_clk_i;
-assign func_cen = (wb_cs_i == sram_id) ? !wb_stb_i : 1'b1;
-assign func_web = (wb_cs_i == sram_id) ? !wb_we_i : 1'b1;
-assign func_mask = wb_sel_i;
-assign func_addr = wb_adr_i;
-assign func_din = wb_dat_i;
-assign wb_dat_o = func_dout;
+assign func_cen = (mem_cs == sram_id) ? !mem_req : 1'b1;
+assign func_web = (mem_cs == sram_id) ? !mem_we : 1'b1;
+assign func_mask = mem_wmask;
+assign func_addr = mem_addr;
+assign func_din = mem_wdata;
+assign mem_rdata = func_dout;
-assign wb_err_o = 1'b0;
-// Generate Once cycle delayed ACK to get the data from SRAM
-always_ff @(negedge rst_n or posedge wb_clk_i) begin
- if ( rst_n == 1'b0 ) begin
- wb_ack_o<= 'h0;
- end else begin
- wb_ack_o <= (wb_cs_i == sram_id) & (wb_stb_i == 1'b1) & (wb_ack_o == 0);
- end
-end
endmodule
diff --git a/verilog/rtl/mbist/src/core/mbist_repair_addr.sv b/verilog/rtl/mbist/src/core/mbist_repair_addr.sv
index 983f661..47871d6 100644
--- a/verilog/rtl/mbist/src/core/mbist_repair_addr.sv
+++ b/verilog/rtl/mbist/src/core/mbist_repair_addr.sv
@@ -99,7 +99,10 @@
begin
AddressOut = AddressIn;
for(index=0; index < BIST_ERR_LIMIT; index=index+1) begin
- if(ErrorCnt > index && AddressIn == RepairMem[index]) AddressOut = BIST_REPAIR_ADDR_START+index;
+ if(ErrorCnt > index && AddressIn == RepairMem[index]) begin
+ AddressOut = BIST_REPAIR_ADDR_START+index;
+ $display("STATUS: MBIST ADDRESS REPAIR: %m => Old Addr: %x Nex Addr: %x",AddressIn,AddressOut);
+ end
end
end
diff --git a/verilog/rtl/mbist/src/top/mbist_top.sv b/verilog/rtl/mbist/src/top/mbist_top.sv
index a1094cf..806ce13 100644
--- a/verilog/rtl/mbist/src/top/mbist_top.sv
+++ b/verilog/rtl/mbist/src/top/mbist_top.sv
@@ -90,16 +90,13 @@
// WB I/F
input wire wb_clk_i, // System clock
input wire wb_clk2_i, // System clock2 is no cts
- input wire wb_cyc_i, // strobe/request
- input wire wb_stb_i, // strobe/request
- input wire [(BIST_NO_SRAM+1)/2-1:0] wb_cs_i,
- input wire [BIST_ADDR_WD-1:0] wb_adr_i, // address
- input wire wb_we_i , // write
- input wire [BIST_DATA_WD-1:0] wb_dat_i, // data output
- input wire [BIST_DATA_WD/8-1:0] wb_sel_i, // byte enable
- output wire [BIST_DATA_WD-1:0] wb_dat_o, // data input
- output wire wb_ack_o, // acknowlegement
- output wire wb_err_o, // error
+ input wire mem_req, // strobe/request
+ input wire [(BIST_NO_SRAM+1)/2-1:0] mem_cs,
+ input wire [BIST_ADDR_WD-1:0] mem_addr, // address
+ input wire mem_we , // write
+ input wire [BIST_DATA_WD-1:0] mem_wdata, // data output
+ input wire [BIST_DATA_WD/8-1:0] mem_wmask, // byte enable
+ output wire [BIST_DATA_WD-1:0] mem_rdata, // data input
// towards memory
// PORT-A
@@ -183,8 +180,6 @@
wire bist_wr ;
wire bist_rd ;
wire [BIST_DATA_WD-1:0] wb_dat[0:BIST_NO_SRAM-1]; // data input
-wire wb_ack[0:BIST_NO_SRAM-1]; // acknowlegement
-wire wb_err[0:BIST_NO_SRAM-1]; // error
//--------------------------------------------------------
// As yosys does not support two dimensional var,
@@ -256,9 +251,7 @@
assign bist_sdo = bist_ms_sdo[3];
// Pick the correct read path
-assign wb_dat_o = wb_dat[wb_cs_i];
-assign wb_ack_o = wb_ack[wb_cs_i];
-assign wb_err_o = wb_err[wb_cs_i];
+assign mem_rdata = wb_dat[mem_cs];
assign bist_wr = (cmd_phase && op_write);
assign bist_rd = (cmd_phase && op_read);
@@ -497,16 +490,13 @@
// WB I/F
.sram_id (NO_SRAM_WD'(sram_no) ),
.wb_clk_i (wb_clk2_i ), // System clock
- .wb_cyc_i (wb_cyc_i ), // strobe/request
- .wb_cs_i (wb_cs_i ), // Chip Select
- .wb_stb_i (wb_stb_i ), // strobe/request
- .wb_adr_i (wb_adr_i ), // address
- .wb_we_i (wb_we_i ), // write
- .wb_dat_i (wb_dat_i ), // data output
- .wb_sel_i (wb_sel_i ), // byte enable
- .wb_dat_o (wb_dat[sram_no] ), // data input
- .wb_ack_o (wb_ack[sram_no] ), // acknowlegement
- .wb_err_o (wb_err[sram_no] ), // error
+ .mem_cs (mem_cs ), // Chip Select
+ .mem_req (mem_req ), // strobe/request
+ .mem_addr (mem_addr ), // address
+ .mem_we (mem_we ), // write
+ .mem_wdata (mem_wdata ), // data output
+ .mem_wmask (mem_wmask ), // byte enable
+ .mem_rdata (wb_dat[sram_no] ), // data input
// MEM A PORT
.func_clk (func_clk[sram_no] ),
.func_cen (func_cen[sram_no] ),
diff --git a/verilog/rtl/mbist_wrapper/src/mbist_wb.sv b/verilog/rtl/mbist_wrapper/src/mbist_wb.sv
new file mode 100644
index 0000000..ef989dd
--- /dev/null
+++ b/verilog/rtl/mbist_wrapper/src/mbist_wb.sv
@@ -0,0 +1,179 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//
+// MBIST wishbone Burst access to SRAM Write and Read access
+// Note: BUSRT crossing the SRAM boundary is not supported due to sram
+// 2 cycle pipe line delay
+//////////////////////////////////////////////////////////////////////
+
+module mbist_wb
+ #(
+ parameter BIST_NO_SRAM = 4,
+ parameter BIST_ADDR_WD = 9,
+ parameter BIST_DATA_WD = 32) (
+
+`ifdef USE_POWER_PINS
+ inout vccd1, // User area 1 1.8V supply
+ inout vssd1, // User area 1 digital ground
+`endif
+
+
+ input logic rst_n,
+
+
+ // WB I/F
+ input logic wb_clk_i, // System clock
+ input logic wb_stb_i, // strobe/request
+ input logic [BIST_ADDR_WD-1:0] wb_adr_i, // address
+ input logic [(BIST_NO_SRAM+1)/2-1:0] wb_cs_i, // address
+ input logic wb_we_i , // write
+ input logic [BIST_DATA_WD-1:0] wb_dat_i, // data output
+ input logic [BIST_DATA_WD/8-1:0] wb_sel_i, // byte enable
+ input logic [9:0] wb_bl_i, // Burst Length
+ input logic wb_bry_i, // Burst Ready
+ output logic [BIST_DATA_WD-1:0] wb_dat_o, // data input
+ output logic wb_ack_o, // acknowlegement
+ output logic wb_lack_o, // acknowlegement
+ output logic wb_err_o, // error
+
+ output logic mem_req,
+ output logic [(BIST_NO_SRAM+1)/2-1:0] mem_cs,
+ output logic [BIST_ADDR_WD-1:0] mem_addr,
+ output logic [31:0] mem_wdata,
+ output logic mem_we,
+ output logic [3:0] mem_wmask,
+ input logic [31:0] mem_rdata
+
+
+
+
+);
+
+parameter IDLE = 2'b00;
+parameter WRITE_ACTION = 2'b01;
+parameter READ_ACTION1 = 2'b10;
+parameter READ_ACTION2 = 2'b11;
+
+
+logic [9:0] mem_bl_cnt ;
+logic wb_ack_l ;
+logic [BIST_ADDR_WD-1:0] mem_next_addr;
+logic [1:0] state;
+logic mem_hval; // Mem Hold Data valid
+logic [31:0] mem_hdata; // Mem Hold Data
+
+
+assign mem_wdata = wb_dat_i;
+
+always @(negedge rst_n, posedge wb_clk_i) begin
+ if (~rst_n) begin
+ mem_bl_cnt <= 'h0;
+ mem_addr <= 'h0;
+ mem_next_addr <= 'h0;
+ wb_ack_l <= 'b0;
+ wb_dat_o <= 'h0;
+ mem_req <= 'b0;
+ mem_cs <= 'b0;
+ mem_wmask <= 'h0;
+ mem_we <= 'h0;
+ mem_hval <= 'b0;
+ mem_hdata <= 'h0;
+ state <= IDLE;
+ end else begin
+ case(state)
+ IDLE: begin
+ mem_bl_cnt <= 'h1;
+ wb_ack_o <= 'b0;
+ wb_lack_o <= 'b0;
+ if(wb_stb_i && wb_bry_i && ~wb_we_i && !wb_lack_o) begin
+ mem_cs <= wb_cs_i;
+ mem_addr <= wb_adr_i;
+ mem_req <= 'b1;
+ mem_we <= 'b0;
+ state <= READ_ACTION1;
+ end else if(wb_stb_i && wb_bry_i && wb_we_i && !wb_lack_o) begin
+ mem_cs <= wb_cs_i;
+ mem_next_addr<= wb_adr_i;
+ mem_we <= 'b1;
+ mem_wmask <= wb_sel_i;
+ state <= WRITE_ACTION;
+ end else begin
+ mem_req <= 1'b0;
+ end
+ end
+
+ WRITE_ACTION: begin
+ if (wb_stb_i && wb_bry_i ) begin
+ wb_ack_o <= 'b1;
+ mem_req <= 1'b1;
+ mem_addr <= mem_next_addr;
+ if((wb_stb_i && wb_bry_i ) && (wb_bl_i == mem_bl_cnt)) begin
+ wb_lack_o <= 'b1;
+ state <= IDLE;
+ end else begin
+ mem_bl_cnt <= mem_bl_cnt+1;
+ mem_next_addr<= mem_next_addr+1;
+ end
+ end else begin
+ wb_ack_o <= 'b0;
+ mem_req <= 1'b0;
+ end
+ end
+ READ_ACTION1: begin
+ mem_addr <= mem_addr +1;
+ mem_hval <= 1'b0;
+ wb_ack_l <= 'b1;
+ mem_bl_cnt <= 'h1;
+ state <= READ_ACTION2;
+ end
+
+ // Wait for Ack from application layer
+ READ_ACTION2: begin
+ // If the not the last ack, update memory pointer
+ // accordingly
+ wb_ack_l <= wb_ack_o;
+ if (wb_stb_i && wb_bry_i ) begin
+ wb_ack_o <= 1'b1;
+ mem_bl_cnt <= mem_bl_cnt+1;
+ mem_addr <= mem_addr +1;
+ if(wb_ack_l || wb_ack_o ) begin // If back to back ack
+ wb_dat_o <= mem_rdata;
+ mem_hval <= 1'b0;
+ end else begin // Pick from previous holding data
+ mem_hval <= 1'b1;
+ wb_dat_o <= mem_hdata;
+ mem_hdata <= mem_rdata;
+ end
+ if((wb_stb_i && wb_bry_i ) && (wb_bl_i == mem_bl_cnt)) begin
+ wb_lack_o <= 1'b1;
+ state <= IDLE;
+ end
+ end else begin
+ wb_ack_o <= 1'b0;
+ if(!mem_hval) begin
+ mem_hdata <= mem_rdata;
+ mem_hval <= 1'b1;
+ end
+ end
+ end
+ endcase
+ end
+end
+
+endmodule
diff --git a/verilog/rtl/mbist_wrapper/src/mbist_wrapper.sv b/verilog/rtl/mbist_wrapper/src/mbist_wrapper.sv
index e33134a..c838f52 100644
--- a/verilog/rtl/mbist_wrapper/src/mbist_wrapper.sv
+++ b/verilog/rtl/mbist_wrapper/src/mbist_wrapper.sv
@@ -97,8 +97,11 @@
input wire wb_we_i , // write
input wire [BIST_DATA_WD-1:0] wb_dat_i, // data output
input wire [BIST_DATA_WD/8-1:0] wb_sel_i, // byte enable
+ input wire [9:0] wb_bl_i, // burst
+ input wire wb_bry_i, // burst ready
output wire [BIST_DATA_WD-1:0] wb_dat_o, // data input
output wire wb_ack_o, // acknowlegement
+ output wire wb_lack_o, // acknowlegement
output wire wb_err_o // error
@@ -107,10 +110,8 @@
);
-parameter BIST_NO_SRAM= 4; // NO of MBIST MEMORY
parameter NO_SRAM_WD = (BIST_NO_SRAM+1)/2;
parameter BIST1_ADDR_WD = 11; // 512x32 SRAM
-parameter BIST_DATA_WD = 32;
// FUNCTIONAL PORT
// towards memory MBIST1
@@ -143,6 +144,55 @@
wire [BIST1_ADDR_WD-1:2] mem2_addr_b;
wire [BIST1_ADDR_WD-1:2] mem3_addr_b;
+logic mem_req;
+logic [(BIST_NO_SRAM+1)/2-1:0] mem_cs;
+logic [BIST_ADDR_WD-1:0] mem_addr;
+logic [31:0] mem_wdata;
+logic mem_we;
+logic [3:0] mem_wmask;
+logic [31:0] mem_rdata;
+
+mbist_wb #(
+ .BIST_NO_SRAM (4 ),
+ .BIST_ADDR_WD (BIST1_ADDR_WD-2 ),
+ .BIST_DATA_WD (BIST_DATA_WD )
+ )
+ u_wb (
+
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+
+ .rst_n (rst_n ),
+ // WB I/F
+ .wb_clk_i (wb_clk_i ),
+ .wb_stb_i (wb_stb_i ),
+ .wb_cs_i (wb_cs_i ),
+ .wb_adr_i (wb_adr_i ),
+ .wb_we_i (wb_we_i ),
+ .wb_dat_i (wb_dat_i ),
+ .wb_sel_i (wb_sel_i ),
+ .wb_bl_i (wb_bl_i ),
+ .wb_bry_i (wb_bry_i ),
+ .wb_dat_o (wb_dat_o ),
+ .wb_ack_o (wb_ack_o ),
+ .wb_lack_o (wb_lack_o ),
+ .wb_err_o ( ),
+
+ .mem_req (mem_req ),
+ .mem_cs (mem_cs ),
+ .mem_addr (mem_addr ),
+ .mem_we (mem_we ),
+ .mem_wdata (mem_wdata ),
+ .mem_wmask (mem_wmask ),
+ .mem_rdata (mem_rdata )
+
+
+
+
+);
+
mbist_top #(
`ifndef SYNTHESIS
@@ -171,16 +221,13 @@
// WB I/F
.wb_clk2_i (wb_clk2_i ),
.wb_clk_i (wb_clk_i ),
- .wb_cyc_i (wb_cyc_i ),
- .wb_stb_i (wb_stb_i ),
- .wb_cs_i (wb_cs_i ),
- .wb_adr_i (wb_adr_i ),
- .wb_we_i (wb_we_i ),
- .wb_dat_i (wb_dat_i ),
- .wb_sel_i (wb_sel_i ),
- .wb_dat_o (wb_dat_o ),
- .wb_ack_o (wb_ack_o ),
- .wb_err_o ( ),
+ .mem_req (mem_req ),
+ .mem_cs (mem_cs ),
+ .mem_addr (mem_addr ),
+ .mem_we (mem_we ),
+ .mem_wdata (mem_wdata ),
+ .mem_wmask (mem_wmask ),
+ .mem_rdata (mem_rdata ),
.rst_n (rst_n ),
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv
index 1eb04e1..c59c28f 100644
--- a/verilog/rtl/pinmux/src/pinmux_reg.sv
+++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -721,7 +721,7 @@
//-----------------------------------------
// Software Reg-2, Release date: <DAY><MONTH><YEAR>
// ----------------------------------------
-gen_32b_reg #(32'h1501_2022) u_reg_23 (
+gen_32b_reg #(32'h0202_2022) u_reg_23 (
//List of Inputs
.reset_n (h_reset_n ),
.clk (mclk ),
@@ -734,9 +734,9 @@
);
//-----------------------------------------
-// Software Reg-3: Poject Revison 3.0 = 0003100
+// Software Reg-3: Poject Revison 3.2 = 0003200
// ----------------------------------------
-gen_32b_reg #(32'h0003_1000) u_reg_24 (
+gen_32b_reg #(32'h0003_2000) u_reg_24 (
//List of Inputs
.reset_n (h_reset_n ),
.clk (mclk ),
diff --git a/verilog/rtl/qspim b/verilog/rtl/qspim
index f7a1f82..50b382d 160000
--- a/verilog/rtl/qspim
+++ b/verilog/rtl/qspim
@@ -1 +1 @@
-Subproject commit f7a1f824fda54c5103bcbd5b9401f36d28551491
+Subproject commit 50b382d05288f8b0d59c8c9e575719d4f3f00911
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index b9fc454..b81ad7e 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -105,44 +105,54 @@
`include "wb_host/src/wb_host.sv"
`include "lib/async_wb.sv"
- `include "lib/wb_stagging.sv"
+ `include "lib/sync_wbb.sv"
+ `include "lib/sync_fifo2.sv"
`include "wb_interconnect/src/wb_arb.sv"
`include "wb_interconnect/src/wb_interconnect.sv"
- `include "yifive/ycr1/src/core/pipeline/ycr1_pipe_hdu.sv"
- `include "yifive/ycr1/src/core/pipeline/ycr1_pipe_tdu.sv"
- `include "yifive/ycr1/src/core/pipeline/ycr1_ipic.sv"
- `include "yifive/ycr1/src/core/pipeline/ycr1_pipe_csr.sv"
- `include "yifive/ycr1/src/core/pipeline/ycr1_pipe_exu.sv"
- `include "yifive/ycr1/src/core/pipeline/ycr1_pipe_ialu.sv"
- `include "yifive/ycr1/src/core/pipeline/ycr1_pipe_idu.sv"
- `include "yifive/ycr1/src/core/pipeline/ycr1_pipe_ifu.sv"
- `include "yifive/ycr1/src/core/pipeline/ycr1_pipe_lsu.sv"
- `include "yifive/ycr1/src/core/pipeline/ycr1_pipe_mprf.sv"
- `include "yifive/ycr1/src/core/pipeline/ycr1_pipe_mul.sv"
- `include "yifive/ycr1/src/core/pipeline/ycr1_pipe_div.sv"
- `include "yifive/ycr1/src/core/pipeline/ycr1_pipe_top.sv"
- `include "yifive/ycr1/src/core/primitives/ycr1_reset_cells.sv"
- `include "yifive/ycr1/src/core/primitives/ycr1_cg.sv"
- `include "yifive/ycr1/src/core/ycr1_clk_ctrl.sv"
- `include "yifive/ycr1/src/core/ycr1_tapc_shift_reg.sv"
- `include "yifive/ycr1/src/core/ycr1_tapc.sv"
- `include "yifive/ycr1/src/core/ycr1_tapc_synchronizer.sv"
- `include "yifive/ycr1/src/core/ycr1_core_top.sv"
- `include "yifive/ycr1/src/core/ycr1_dm.sv"
- `include "yifive/ycr1/src/core/ycr1_dmi.sv"
- `include "yifive/ycr1/src/core/ycr1_scu.sv"
-
- `include "yifive/ycr1/src/top/ycr1_imem_router.sv"
- `include "yifive/ycr1/src/top/ycr1_dmem_router.sv"
- `include "yifive/ycr1/src/top/ycr1_dp_memory.sv"
- `include "yifive/ycr1/src/top/ycr1_tcm.sv"
- `include "yifive/ycr1/src/top/ycr1_timer.sv"
- `include "yifive/ycr1/src/top/ycr1_dmem_wb.sv"
- `include "yifive/ycr1/src/top/ycr1_imem_wb.sv"
- `include "yifive/ycr1/src/top/ycr1_intf.sv"
- `include "yifive/ycr1/src/top/ycr1_top_wb.sv"
+ `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_hdu.sv"
+ `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_tdu.sv"
+ `include "yifive/ycr1c/src/core/pipeline/ycr1_ipic.sv"
+ `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_csr.sv"
+ `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_exu.sv"
+ `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_ialu.sv"
+ `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_idu.sv"
+ `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_ifu.sv"
+ `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_lsu.sv"
+ `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_mprf.sv"
+ `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_mul.sv"
+ `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_div.sv"
+ `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_top.sv"
+ `include "yifive/ycr1c/src/core/primitives/ycr1_reset_cells.sv"
+ `include "yifive/ycr1c/src/core/primitives/ycr1_cg.sv"
+ `include "yifive/ycr1c/src/core/ycr1_clk_ctrl.sv"
+ `include "yifive/ycr1c/src/core/ycr1_tapc_shift_reg.sv"
+ `include "yifive/ycr1c/src/core/ycr1_tapc.sv"
+ `include "yifive/ycr1c/src/core/ycr1_tapc_synchronizer.sv"
+ `include "yifive/ycr1c/src/core/ycr1_core_top.sv"
+ `include "yifive/ycr1c/src/core/ycr1_dm.sv"
+ `include "yifive/ycr1c/src/core/ycr1_dmi.sv"
+ `include "yifive/ycr1c/src/core/ycr1_scu.sv"
+ `include "yifive/ycr1c/src/top/ycr1_imem_router.sv"
+ `include "yifive/ycr1c/src/top/ycr1_dmem_router.sv"
+ `include "yifive/ycr1c/src/top/ycr1_dp_memory.sv"
+ `include "yifive/ycr1c/src/top/ycr1_tcm.sv"
+ `include "yifive/ycr1c/src/top/ycr1_timer.sv"
+ `include "yifive/ycr1c/src/top/ycr1_dmem_wb.sv"
+ `include "yifive/ycr1c/src/top/ycr1_imem_wb.sv"
+ `include "yifive/ycr1c/src/top/ycr1_intf.sv"
+ `include "yifive/ycr1c/src/top/ycr1_top_wb.sv"
+ `include "yifive/ycr1c/src/top/ycr1_icache_router.sv"
+ `include "yifive/ycr1c/src/top/ycr1_dcache_router.sv"
+ `include "yifive/ycr1c/src/cache/src/core/icache_top.sv"
+ `include "yifive/ycr1c/src/cache/src/core/icache_app_fsm.sv"
+ `include "yifive/ycr1c/src/cache/src/core/icache_tag_fifo.sv"
+ `include "yifive/ycr1c/src/cache/src/core/dcache_tag_fifo.sv"
+ `include "yifive/ycr1c/src/cache/src/core/dcache_top.sv"
+ `include "yifive/ycr1c/src/lib/ycr1_async_wbb.sv"
+ `include "yifive/ycr1c/src/lib/ycr1_arb.sv"
+
`include "lib/sync_fifo.sv"
`include "mbist/src/core/mbist_addr_gen.sv"
@@ -156,6 +166,8 @@
`include "mbist/src/core/mbist_mem_wrapper.sv"
`include "mbist/src/top/mbist_top.sv"
+ `include "mbist_wrapper/src/mbist_wb.sv"
+ `include "mbist_wrapper/src/mbist_wrapper.sv"
`include "uart2wb/src/uart2wb.sv"
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 0c0f7cf..efe14c3 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -152,6 +152,9 @@
//// yfive/ycr1 on sankranti 2022 (A Hindu New Year) ////
//// 3.1 Jan 15, 2022, Dinesh A ////
//// Major changes in qspim logic to handle special mode ////
+//// 3.2 Feb 02, 2022, Dinesh A ////
+//// Bug fix around icache/dcache and wishbone burst ////
+//// access clean-up ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
@@ -237,16 +240,34 @@
parameter BIST_DATA_WD = 32;
//---------------------------------------------------------------------
-// Wishbone Risc V Instruction Memory Interface
+// Wishbone Risc V Dcache Memory Interface
//---------------------------------------------------------------------
-wire wbd_riscv_imem_stb_i; // strobe/request
-wire [WB_WIDTH-1:0] wbd_riscv_imem_adr_i; // address
-wire wbd_riscv_imem_we_i; // write
-wire [WB_WIDTH-1:0] wbd_riscv_imem_dat_i; // data output
-wire [3:0] wbd_riscv_imem_sel_i; // byte enable
-wire [WB_WIDTH-1:0] wbd_riscv_imem_dat_o; // data input
-wire wbd_riscv_imem_ack_o; // acknowlegement
-wire wbd_riscv_imem_err_o; // error
+wire wbd_riscv_dcache_stb_i; // strobe/request
+wire [WB_WIDTH-1:0] wbd_riscv_dcache_adr_i; // address
+wire wbd_riscv_dcache_we_i; // write
+wire [WB_WIDTH-1:0] wbd_riscv_dcache_dat_i; // data output
+wire [3:0] wbd_riscv_dcache_sel_i; // byte enable
+wire [9:0] wbd_riscv_dcache_bl_i; // burst length
+wire wbd_riscv_dcache_bry_i; // burst ready
+wire [WB_WIDTH-1:0] wbd_riscv_dcache_dat_o; // data input
+wire wbd_riscv_dcache_ack_o; // acknowlegement
+wire wbd_riscv_dcache_lack_o;// last burst acknowlegement
+wire wbd_riscv_dcache_err_o; // error
+
+//---------------------------------------------------------------------
+// Wishbone Risc V Icache Memory Interface
+//---------------------------------------------------------------------
+wire wbd_riscv_icache_stb_i; // strobe/request
+wire [WB_WIDTH-1:0] wbd_riscv_icache_adr_i; // address
+wire wbd_riscv_icache_we_i; // write
+wire [WB_WIDTH-1:0] wbd_riscv_icache_dat_i; // data output
+wire [3:0] wbd_riscv_icache_sel_i; // byte enable
+wire [9:0] wbd_riscv_icache_bl_i; // burst length
+wire wbd_riscv_icache_bry_i; // burst ready
+wire [WB_WIDTH-1:0] wbd_riscv_icache_dat_o; // data input
+wire wbd_riscv_icache_ack_o; // acknowlegement
+wire wbd_riscv_icache_lack_o;// last burst acknowlegement
+wire wbd_riscv_icache_err_o; // error
//---------------------------------------------------------------------
// RISC V Wishbone Data Memory Interface
@@ -335,9 +356,12 @@
wire wbd_mbist_we_o; // write
wire [WB_WIDTH-1:0] wbd_mbist_dat_o; // data output
wire [3:0] wbd_mbist_sel_o; // byte enable
+wire [9:0] wbd_mbist_bl_o; // byte enable
+wire wbd_mbist_bry_o; // byte enable
wire wbd_mbist_cyc_o ;
wire [WB_WIDTH-1:0] wbd_mbist_dat_i; // data input
wire wbd_mbist_ack_i; // acknowlegement
+wire wbd_mbist_lack_i; // acknowlegement
wire wbd_mbist_err_i; // error
//----------------------------------------------------
@@ -557,33 +581,33 @@
// towards memory MBIST1
// PORT-A
-wire [BIST_NO_SRAM-1:0] mem_clk_a;
-wire [BIST1_ADDR_WD-1:2] mem0_addr_a;
-wire [BIST1_ADDR_WD-1:2] mem1_addr_a;
-wire [BIST1_ADDR_WD-1:2] mem2_addr_a;
-wire [BIST1_ADDR_WD-1:2] mem3_addr_a;
-wire [BIST_NO_SRAM-1:0] mem_cen_a;
-wire [BIST_NO_SRAM-1:0] mem_web_a;
-wire [BIST_DATA_WD/8-1:0] mem0_mask_a;
-wire [BIST_DATA_WD/8-1:0] mem1_mask_a;
-wire [BIST_DATA_WD/8-1:0] mem2_mask_a;
-wire [BIST_DATA_WD/8-1:0] mem3_mask_a;
-wire [BIST_DATA_WD-1:0] mem0_din_a;
-wire [BIST_DATA_WD-1:0] mem1_din_a;
-wire [BIST_DATA_WD-1:0] mem2_din_a;
-wire [BIST_DATA_WD-1:0] mem3_din_a;
-wire [BIST_DATA_WD-1:0] mem0_dout_a;
-wire [BIST_DATA_WD-1:0] mem1_dout_a;
-wire [BIST_DATA_WD-1:0] mem2_dout_a;
-wire [BIST_DATA_WD-1:0] mem3_dout_a;
+//wire [BIST_NO_SRAM-1:0] mem_clk_a;
+//wire [BIST1_ADDR_WD-1:2] mem0_addr_a;
+//wire [BIST1_ADDR_WD-1:2] mem1_addr_a;
+//wire [BIST1_ADDR_WD-1:2] mem2_addr_a;
+//wire [BIST1_ADDR_WD-1:2] mem3_addr_a;
+//wire [BIST_NO_SRAM-1:0] mem_cen_a;
+//wire [BIST_NO_SRAM-1:0] mem_web_a;
+//wire [BIST_DATA_WD/8-1:0] mem0_mask_a;
+//wire [BIST_DATA_WD/8-1:0] mem1_mask_a;
+//wire [BIST_DATA_WD/8-1:0] mem2_mask_a;
+//wire [BIST_DATA_WD/8-1:0] mem3_mask_a;
+//wire [BIST_DATA_WD-1:0] mem0_din_a;
+//wire [BIST_DATA_WD-1:0] mem1_din_a;
+//wire [BIST_DATA_WD-1:0] mem2_din_a;
+//wire [BIST_DATA_WD-1:0] mem3_din_a;
+//wire [BIST_DATA_WD-1:0] mem0_dout_a;
+//wire [BIST_DATA_WD-1:0] mem1_dout_a;
+//wire [BIST_DATA_WD-1:0] mem2_dout_a;
+//wire [BIST_DATA_WD-1:0] mem3_dout_a;
// PORT-B
-wire [BIST_NO_SRAM-1:0] mem_clk_b;
-wire [BIST_NO_SRAM-1:0] mem_cen_b;
-wire [BIST1_ADDR_WD-1:2] mem0_addr_b;
-wire [BIST1_ADDR_WD-1:2] mem1_addr_b;
-wire [BIST1_ADDR_WD-1:2] mem2_addr_b;
-wire [BIST1_ADDR_WD-1:2] mem3_addr_b;
+//wire [BIST_NO_SRAM-1:0] mem_clk_b;
+//wire [BIST_NO_SRAM-1:0] mem_cen_b;
+//wire [BIST1_ADDR_WD-1:2] mem0_addr_b;
+//wire [BIST1_ADDR_WD-1:2] mem1_addr_b;
+//wire [BIST1_ADDR_WD-1:2] mem2_addr_b;
+//wire [BIST1_ADDR_WD-1:2] mem3_addr_b;
wire [3:0] spi_csn;
@@ -730,33 +754,50 @@
.sram0_addr1 (sram0_addr1 ),
.sram0_dout1 (sram0_dout1 ),
- // SRAM-1 PORT-0
- .sram1_clk0 (sram1_clk0 ),
- .sram1_csb0 (sram1_csb0 ),
- .sram1_web0 (sram1_web0 ),
- .sram1_addr0 (sram1_addr0 ),
- .sram1_wmask0 (sram1_wmask0 ),
- .sram1_din0 (sram1_din0 ),
- .sram1_dout0 (sram1_dout0 ),
-
- // SRAM PORT-0
- .sram1_clk1 (sram1_clk1 ),
- .sram1_csb1 (sram1_csb1 ),
- .sram1_addr1 (sram1_addr1 ),
- .sram1_dout1 (sram1_dout1 ),
+ // // SRAM-1 PORT-0
+ // .sram1_clk0 (sram1_clk0 ),
+ // .sram1_csb0 (sram1_csb0 ),
+ // .sram1_web0 (sram1_web0 ),
+ // .sram1_addr0 (sram1_addr0 ),
+ // .sram1_wmask0 (sram1_wmask0 ),
+ // .sram1_din0 (sram1_din0 ),
+ // .sram1_dout0 (sram1_dout0 ),
+ //
+ // // SRAM PORT-0
+ // .sram1_clk1 (sram1_clk1 ),
+ // .sram1_csb1 (sram1_csb1 ),
+ // .sram1_addr1 (sram1_addr1 ),
+ // .sram1_dout1 (sram1_dout1 ),
`endif
- .wb_rst_n (wbd_int_rst_n ),
- .wb_clk (wbd_clk_riscv_skew ),
- // Instruction memory interface
- .wbd_imem_stb_o (wbd_riscv_imem_stb_i ),
- .wbd_imem_adr_o (wbd_riscv_imem_adr_i ),
- .wbd_imem_we_o (wbd_riscv_imem_we_i ),
- .wbd_imem_dat_o (wbd_riscv_imem_dat_i ),
- .wbd_imem_sel_o (wbd_riscv_imem_sel_i ),
- .wbd_imem_dat_i (wbd_riscv_imem_dat_o ),
- .wbd_imem_ack_i (wbd_riscv_imem_ack_o ),
- .wbd_imem_err_i (wbd_riscv_imem_err_o ),
+ .wb_rst_n (wbd_int_rst_n ),
+ .wb_clk (wbd_clk_riscv_skew ),
+
+ // Instruction cache memory interface
+ .wb_icache_stb_o (wbd_riscv_icache_stb_i ),
+ .wb_icache_adr_o (wbd_riscv_icache_adr_i ),
+ .wb_icache_we_o (wbd_riscv_icache_we_i ),
+ .wb_icache_dat_o (wbd_riscv_icache_dat_i ),
+ .wb_icache_sel_o (wbd_riscv_icache_sel_i ),
+ .wb_icache_bl_o (wbd_riscv_icache_bl_i ),
+ .wb_icache_bry_o (wbd_riscv_icache_bry_i ),
+ .wb_icache_dat_i (wbd_riscv_icache_dat_o ),
+ .wb_icache_ack_i (wbd_riscv_icache_ack_o ),
+ .wb_icache_lack_i (wbd_riscv_icache_lack_o ),
+ .wb_icache_err_i (wbd_riscv_icache_err_o ),
+
+ // Data cache memory interface
+ .wb_dcache_stb_o (wbd_riscv_dcache_stb_i ),
+ .wb_dcache_adr_o (wbd_riscv_dcache_adr_i ),
+ .wb_dcache_we_o (wbd_riscv_dcache_we_i ),
+ .wb_dcache_dat_o (wbd_riscv_dcache_dat_i ),
+ .wb_dcache_sel_o (wbd_riscv_dcache_sel_i ),
+ .wb_dcache_bl_o (wbd_riscv_dcache_bl_i ),
+ .wb_dcache_bry_o (wbd_riscv_dcache_bry_i ),
+ .wb_dcache_dat_i (wbd_riscv_dcache_dat_o ),
+ .wb_dcache_ack_i (wbd_riscv_dcache_ack_o ),
+ .wb_dcache_lack_i (wbd_riscv_dcache_lack_o ),
+ .wb_dcache_err_i (wbd_riscv_dcache_err_o ),
// Data memory interface
.wbd_dmem_stb_o (wbd_riscv_dmem_stb_i ),
@@ -790,6 +831,7 @@
.dout1 (sram0_dout1)
);
+/***
sky130_sram_2kbyte_1rw1r_32x512_8 u_tsram1_2kb(
`ifdef USE_POWER_PINS
.vccd1 (vccd1),// User area 1 1.8V supply
@@ -809,7 +851,7 @@
.addr1 (sram1_addr1),
.dout1 (sram1_dout1)
);
-
+***/
`endif
@@ -991,27 +1033,44 @@
.m0_wbd_ack_o (wbd_int_ack_o ),
.m0_wbd_err_o (wbd_int_err_o ),
- // Master 0 Interface
- .m1_wbd_dat_i (wbd_riscv_imem_dat_i ),
- .m1_wbd_adr_i (wbd_riscv_imem_adr_i ),
- .m1_wbd_sel_i (wbd_riscv_imem_sel_i ),
- .m1_wbd_we_i (wbd_riscv_imem_we_i ),
- .m1_wbd_cyc_i (wbd_riscv_imem_stb_i ),
- .m1_wbd_stb_i (wbd_riscv_imem_stb_i ),
- .m1_wbd_dat_o (wbd_riscv_imem_dat_o ),
- .m1_wbd_ack_o (wbd_riscv_imem_ack_o ),
- .m1_wbd_err_o (wbd_riscv_imem_err_o ),
-
// Master 1 Interface
- .m2_wbd_dat_i (wbd_riscv_dmem_dat_i ),
- .m2_wbd_adr_i (wbd_riscv_dmem_adr_i ),
- .m2_wbd_sel_i (wbd_riscv_dmem_sel_i ),
- .m2_wbd_we_i (wbd_riscv_dmem_we_i ),
- .m2_wbd_cyc_i (wbd_riscv_dmem_stb_i ),
- .m2_wbd_stb_i (wbd_riscv_dmem_stb_i ),
- .m2_wbd_dat_o (wbd_riscv_dmem_dat_o ),
- .m2_wbd_ack_o (wbd_riscv_dmem_ack_o ),
- .m2_wbd_err_o (wbd_riscv_dmem_err_o ),
+ .m1_wbd_dat_i (wbd_riscv_dmem_dat_i ),
+ .m1_wbd_adr_i (wbd_riscv_dmem_adr_i ),
+ .m1_wbd_sel_i (wbd_riscv_dmem_sel_i ),
+ .m1_wbd_we_i (wbd_riscv_dmem_we_i ),
+ .m1_wbd_cyc_i (wbd_riscv_dmem_stb_i ),
+ .m1_wbd_stb_i (wbd_riscv_dmem_stb_i ),
+ .m1_wbd_dat_o (wbd_riscv_dmem_dat_o ),
+ .m1_wbd_ack_o (wbd_riscv_dmem_ack_o ),
+ .m1_wbd_err_o (wbd_riscv_dmem_err_o ),
+
+ // Master 2 Interface
+ .m2_wbd_dat_i (wbd_riscv_dcache_dat_i ),
+ .m2_wbd_adr_i (wbd_riscv_dcache_adr_i ),
+ .m2_wbd_sel_i (wbd_riscv_dcache_sel_i ),
+ .m2_wbd_bl_i (wbd_riscv_dcache_bl_i ),
+ .m2_wbd_bry_i (wbd_riscv_dcache_bry_i ),
+ .m2_wbd_we_i (wbd_riscv_dcache_we_i ),
+ .m2_wbd_cyc_i (wbd_riscv_dcache_stb_i ),
+ .m2_wbd_stb_i (wbd_riscv_dcache_stb_i ),
+ .m2_wbd_dat_o (wbd_riscv_dcache_dat_o ),
+ .m2_wbd_ack_o (wbd_riscv_dcache_ack_o ),
+ .m2_wbd_lack_o (wbd_riscv_dcache_lack_o ),
+ .m2_wbd_err_o (wbd_riscv_dcache_err_o ),
+
+ // Master 3 Interface
+ .m3_wbd_dat_i (wbd_riscv_icache_dat_i ),
+ .m3_wbd_adr_i (wbd_riscv_icache_adr_i ),
+ .m3_wbd_sel_i (wbd_riscv_icache_sel_i ),
+ .m3_wbd_bl_i (wbd_riscv_icache_bl_i ),
+ .m3_wbd_bry_i (wbd_riscv_icache_bry_i ),
+ .m3_wbd_we_i (wbd_riscv_icache_we_i ),
+ .m3_wbd_cyc_i (wbd_riscv_icache_stb_i ),
+ .m3_wbd_stb_i (wbd_riscv_icache_stb_i ),
+ .m3_wbd_dat_o (wbd_riscv_icache_dat_o ),
+ .m3_wbd_ack_o (wbd_riscv_icache_ack_o ),
+ .m3_wbd_lack_o (wbd_riscv_icache_lack_o ),
+ .m3_wbd_err_o (wbd_riscv_icache_err_o ),
// Slave 0 Interface
@@ -1054,9 +1113,12 @@
// .s3_wbd_err_i (1'b0 ), - Moved inside IP
.s3_wbd_dat_i (wbd_mbist_dat_i ),
.s3_wbd_ack_i (wbd_mbist_ack_i ),
+ .s3_wbd_lack_i (wbd_mbist_lack_i ),
.s3_wbd_dat_o (wbd_mbist_dat_o ),
.s3_wbd_adr_o (wbd_mbist_adr_o ),
.s3_wbd_sel_o (wbd_mbist_sel_o ),
+ .s3_wbd_bry_o (wbd_mbist_bry_o ),
+ .s3_wbd_bl_o (wbd_mbist_bl_o ),
.s3_wbd_we_o (wbd_mbist_we_o ),
.s3_wbd_cyc_o (wbd_mbist_cyc_o ),
.s3_wbd_stb_o (wbd_mbist_stb_o )
@@ -1224,9 +1286,9 @@
);
-//------------- MBIST1 - 512x32 ----
+//------------- MBIST - 512x32 ----
-mbist_top #(
+mbist_wrapper #(
`ifndef SYNTHESIS
.BIST_NO_SRAM (4 ),
.BIST_ADDR_WD (BIST1_ADDR_WD-2 ),
@@ -1260,8 +1322,11 @@
.wb_we_i (wbd_mbist_we_o ),
.wb_dat_i (wbd_mbist_dat_o),
.wb_sel_i (wbd_mbist_sel_o),
+ .wb_bl_i (wbd_mbist_bl_o),
+ .wb_bry_i (wbd_mbist_bry_o),
.wb_dat_o (wbd_mbist_dat_i),
.wb_ack_o (wbd_mbist_ack_i),
+ .wb_lack_o (wbd_mbist_lack_i),
.wb_err_o ( ),
.rst_n (bist_rst_n ),
@@ -1280,40 +1345,41 @@
.bist_correct (bist_correct ),
.bist_error (bist_error ),
.bist_done (bist_done ),
- .bist_sdo (bist_sdo ),
+ .bist_sdo (bist_sdo )
- // towards memory
- // PORT-A
- .mem_clk_a (mem_clk_a ),
- .mem_addr_a0 (mem0_addr_a ),
- .mem_addr_a1 (mem1_addr_a ),
- .mem_addr_a2 (mem2_addr_a ),
- .mem_addr_a3 (mem3_addr_a ),
- .mem_cen_a (mem_cen_a ),
- .mem_web_a (mem_web_a ),
- .mem_mask_a0 (mem0_mask_a ),
- .mem_mask_a1 (mem1_mask_a ),
- .mem_mask_a2 (mem2_mask_a ),
- .mem_mask_a3 (mem3_mask_a ),
- .mem_din_a0 (mem0_din_a ),
- .mem_din_a1 (mem1_din_a ),
- .mem_din_a2 (mem2_din_a ),
- .mem_din_a3 (mem3_din_a ),
- .mem_dout_a0 (mem0_dout_a ),
- .mem_dout_a1 (mem1_dout_a ),
- .mem_dout_a2 (mem2_dout_a ),
- .mem_dout_a3 (mem3_dout_a ),
- // PORT-B
- .mem_clk_b (mem_clk_b ),
- .mem_cen_b (mem_cen_b ),
- .mem_addr_b0 (mem0_addr_b ),
- .mem_addr_b1 (mem1_addr_b ),
- .mem_addr_b2 (mem2_addr_b ),
- .mem_addr_b3 (mem3_addr_b )
+ // // towards memory
+ // // PORT-A
+ // .mem_clk_a (mem_clk_a ),
+ // .mem_addr_a0 (mem0_addr_a ),
+ // .mem_addr_a1 (mem1_addr_a ),
+ // .mem_addr_a2 (mem2_addr_a ),
+ // .mem_addr_a3 (mem3_addr_a ),
+ // .mem_cen_a (mem_cen_a ),
+ // .mem_web_a (mem_web_a ),
+ // .mem_mask_a0 (mem0_mask_a ),
+ // .mem_mask_a1 (mem1_mask_a ),
+ // .mem_mask_a2 (mem2_mask_a ),
+ // .mem_mask_a3 (mem3_mask_a ),
+ // .mem_din_a0 (mem0_din_a ),
+ // .mem_din_a1 (mem1_din_a ),
+ // .mem_din_a2 (mem2_din_a ),
+ // .mem_din_a3 (mem3_din_a ),
+ // .mem_dout_a0 (mem0_dout_a ),
+ // .mem_dout_a1 (mem1_dout_a ),
+ // .mem_dout_a2 (mem2_dout_a ),
+ // .mem_dout_a3 (mem3_dout_a ),
+ // // PORT-B
+ // .mem_clk_b (mem_clk_b ),
+ // .mem_cen_b (mem_cen_b ),
+ // .mem_addr_b0 (mem0_addr_b ),
+ // .mem_addr_b1 (mem1_addr_b ),
+ // .mem_addr_b2 (mem2_addr_b ),
+ // .mem_addr_b3 (mem3_addr_b )
);
+/***
sky130_sram_2kbyte_1rw1r_32x512_8 u_sram0_2kb(
`ifdef USE_POWER_PINS
.vccd1 (vccd1),// User area 1 1.8V supply
@@ -1395,6 +1461,8 @@
.dout1 ()
);
+**/
+
/***
sar_adc u_adc (
`ifdef USE_POWER_PINS
diff --git a/verilog/rtl/wb_interconnect/src/wb_arb.sv b/verilog/rtl/wb_interconnect/src/wb_arb.sv
index 16e0da7..aefac4a 100644
--- a/verilog/rtl/wb_interconnect/src/wb_arb.sv
+++ b/verilog/rtl/wb_interconnect/src/wb_arb.sv
@@ -68,7 +68,7 @@
input clk;
input rstn;
-input [2:0] req; // Req input
+input [3:0] req; // Req input
output [1:0] gnt; // Grant output
///////////////////////////////////////////////////////////////////////
@@ -80,7 +80,8 @@
parameter [1:0]
grant0 = 3'h0,
grant1 = 3'h1,
- grant2 = 3'h2;
+ grant2 = 3'h2,
+ grant3 = 3'h3;
///////////////////////////////////////////////////////////////////////
// Local Registers and Wires
@@ -115,11 +116,13 @@
if(!req[0] ) begin
if(req[1]) next_state = grant1;
else if(req[2]) next_state = grant2;
+ else if(req[3]) next_state = grant3;
end
grant1:
// if this req is dropped or next is asserted, check for other req's
if(!req[1] ) begin
if(req[2]) next_state = grant2;
+ if(req[3]) next_state = grant3;
else if(req[0]) next_state = grant0;
end
grant2:
@@ -127,6 +130,14 @@
if(!req[2] ) begin
if(req[0]) next_state = grant0;
else if(req[1]) next_state = grant1;
+ else if(req[3]) next_state = grant3;
+ end
+ grant3:
+ // if this req is dropped or next is asserted, check for other req's
+ if(!req[3] ) begin
+ if(req[0]) next_state = grant0;
+ else if(req[1]) next_state = grant1;
+ else if(req[2]) next_state = grant2;
end
endcase
end
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
index 14e716e..1f83bc6 100644
--- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
+++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -158,6 +158,8 @@
input logic [31:0] m2_wbd_dat_i,
input logic [31:0] m2_wbd_adr_i,
input logic [3:0] m2_wbd_sel_i,
+ input logic [9:0] m2_wbd_bl_i,
+ input logic m2_wbd_bry_i,
input logic m2_wbd_we_i,
input logic m2_wbd_cyc_i,
input logic m2_wbd_stb_i,
@@ -166,6 +168,19 @@
output logic m2_wbd_lack_o,
output logic m2_wbd_err_o,
+ // Master 3 Interface
+ input logic [31:0] m3_wbd_dat_i,
+ input logic [31:0] m3_wbd_adr_i,
+ input logic [3:0] m3_wbd_sel_i,
+ input logic [9:0] m3_wbd_bl_i,
+ input logic m3_wbd_bry_i,
+ input logic m3_wbd_we_i,
+ input logic m3_wbd_cyc_i,
+ input logic m3_wbd_stb_i,
+ output logic [31:0] m3_wbd_dat_o,
+ output logic m3_wbd_ack_o,
+ output logic m3_wbd_lack_o,
+ output logic m3_wbd_err_o,
// Slave 0 Interface
input logic [31:0] s0_wbd_dat_i,
@@ -207,10 +222,13 @@
// MBIST
input logic [31:0] s3_wbd_dat_i,
input logic s3_wbd_ack_i,
+ input logic s3_wbd_lack_i,
// input logic s3_wbd_err_i,
output logic [31:0] s3_wbd_dat_o,
output logic [12:0] s3_wbd_adr_o,
output logic [3:0] s3_wbd_sel_o,
+ output logic [9:0] s3_wbd_bl_o,
+ output logic s3_wbd_bry_o,
output logic s3_wbd_we_o,
output logic s3_wbd_cyc_o,
output logic s3_wbd_stb_o
@@ -253,11 +271,13 @@
type_wb_wr_intf m0_wb_wr;
type_wb_wr_intf m1_wb_wr;
type_wb_wr_intf m2_wb_wr;
+type_wb_wr_intf m3_wb_wr;
// Master Read Interface
type_wb_rd_intf m0_wb_rd;
type_wb_rd_intf m1_wb_rd;
type_wb_rd_intf m2_wb_rd;
+type_wb_rd_intf m3_wb_rd;
// Slave Write Interface
type_wb_wr_intf s0_wb_wr;
@@ -351,16 +371,30 @@
(boot_remap[1] && m2_wbd_adr_i[31:11] == 21'h1) ? TARGET_MBIST:
(boot_remap[2] && m2_wbd_adr_i[31:11] == 21'h2) ? TARGET_MBIST:
(boot_remap[3] && m2_wbd_adr_i[31:11] == 21'h3) ? TARGET_MBIST:
- (dcache_remap[0] && m1_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0000_0) ? TARGET_MBIST:
- (dcache_remap[1] && m1_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0000_1) ? TARGET_MBIST:
- (dcache_remap[2] && m1_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0001_0) ? TARGET_MBIST:
- (dcache_remap[3] && m1_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0001_1) ? TARGET_MBIST:
+ (dcache_remap[0] && m2_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0000_0) ? TARGET_MBIST:
+ (dcache_remap[1] && m2_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0000_1) ? TARGET_MBIST:
+ (dcache_remap[2] && m2_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0001_0) ? TARGET_MBIST:
+ (dcache_remap[3] && m2_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0001_1) ? TARGET_MBIST:
(m2_wbd_adr_i[31:28] == 4'b0000 ) ? TARGET_SPI_MEM :
(m2_wbd_adr_i[31:16] == 16'h1000 ) ? TARGET_SPI_REG :
(m2_wbd_adr_i[31:16] == 16'h1001 ) ? TARGET_UART :
(m2_wbd_adr_i[31:16] == 16'h1002 ) ? TARGET_PINMUX :
(m2_wbd_adr_i[31:16] == 16'h1003 ) ? TARGET_MBIST :
4'b0000;
+wire [3:0] m3_wbd_tid_i = (boot_remap[0] && m3_wbd_adr_i[31:11] == 21'h0) ? TARGET_MBIST:
+ (boot_remap[1] && m3_wbd_adr_i[31:11] == 21'h1) ? TARGET_MBIST:
+ (boot_remap[2] && m3_wbd_adr_i[31:11] == 21'h2) ? TARGET_MBIST:
+ (boot_remap[3] && m3_wbd_adr_i[31:11] == 21'h3) ? TARGET_MBIST:
+ (dcache_remap[0] && m3_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0000_0) ? TARGET_MBIST:
+ (dcache_remap[1] && m3_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0000_1) ? TARGET_MBIST:
+ (dcache_remap[2] && m3_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0001_0) ? TARGET_MBIST:
+ (dcache_remap[3] && m3_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0001_1) ? TARGET_MBIST:
+ (m3_wbd_adr_i[31:28] == 4'b0000 ) ? TARGET_SPI_MEM :
+ (m3_wbd_adr_i[31:16] == 16'h1000 ) ? TARGET_SPI_REG :
+ (m3_wbd_adr_i[31:16] == 16'h1001 ) ? TARGET_UART :
+ (m3_wbd_adr_i[31:16] == 16'h1002 ) ? TARGET_PINMUX :
+ (m3_wbd_adr_i[31:16] == 16'h1003 ) ? TARGET_MBIST :
+ 4'b0000;
//----------------------------------------
// Master Mapping
// -------------------------------------
@@ -387,13 +421,23 @@
assign m2_wb_wr.wbd_dat = m2_wbd_dat_i;
assign m2_wb_wr.wbd_adr = {m2_wbd_adr_i[31:2],2'b00};
assign m2_wb_wr.wbd_sel = m2_wbd_sel_i;
-assign m2_wb_wr.wbd_bl = 'h1;
-assign m2_wb_wr.wbd_bry = 'b1;
+assign m2_wb_wr.wbd_bl = m2_wbd_bl_i;
+assign m2_wb_wr.wbd_bry = m2_wbd_bry_i;
assign m2_wb_wr.wbd_we = m2_wbd_we_i;
assign m2_wb_wr.wbd_cyc = m2_wbd_cyc_i;
assign m2_wb_wr.wbd_stb = m2_wbd_stb_i;
assign m2_wb_wr.wbd_tid = m2_wbd_tid_i;
+assign m3_wb_wr.wbd_dat = m3_wbd_dat_i;
+assign m3_wb_wr.wbd_adr = {m3_wbd_adr_i[31:2],2'b00};
+assign m3_wb_wr.wbd_sel = m3_wbd_sel_i;
+assign m3_wb_wr.wbd_bl = m3_wbd_bl_i;
+assign m3_wb_wr.wbd_bry = m3_wbd_bry_i;
+assign m3_wb_wr.wbd_we = m3_wbd_we_i;
+assign m3_wb_wr.wbd_cyc = m3_wbd_cyc_i;
+assign m3_wb_wr.wbd_stb = m3_wbd_stb_i;
+assign m3_wb_wr.wbd_tid = m3_wbd_tid_i;
+
assign m0_wbd_dat_o = m0_wb_rd.wbd_dat;
assign m0_wbd_ack_o = m0_wb_rd.wbd_ack;
assign m0_wbd_lack_o = m0_wb_rd.wbd_lack;
@@ -409,6 +453,11 @@
assign m2_wbd_lack_o = m2_wb_rd.wbd_lack;
assign m2_wbd_err_o = m2_wb_rd.wbd_err;
+assign m3_wbd_dat_o = m3_wb_rd.wbd_dat;
+assign m3_wbd_ack_o = m3_wb_rd.wbd_ack;
+assign m3_wbd_lack_o = m3_wb_rd.wbd_lack;
+assign m3_wbd_err_o = m3_wb_rd.wbd_err;
+
//----------------------------------------
// Slave Mapping
// -------------------------------------
@@ -439,6 +488,8 @@
assign s3_wbd_dat_o = s3_wb_wr.wbd_dat[31:0] ;
assign s3_wbd_adr_o = s3_wb_wr.wbd_adr[12:0] ; // MBIST Need 13 bit
assign s3_wbd_sel_o = s3_wb_wr.wbd_sel[3:0] ;
+ assign s3_wbd_bl_o = s3_wb_wr.wbd_bl ;
+ assign s3_wbd_bry_o = s3_wb_wr.wbd_bry ;
assign s3_wbd_we_o = s3_wb_wr.wbd_we ;
assign s3_wbd_cyc_o = s3_wb_wr.wbd_cyc ;
assign s3_wbd_stb_o = s3_wb_wr.wbd_stb ;
@@ -461,7 +512,7 @@
assign s3_wb_rd.wbd_dat = s3_wbd_dat_i ;
assign s3_wb_rd.wbd_ack = s3_wbd_ack_i ;
- assign s3_wb_rd.wbd_lack = s3_wbd_ack_i ;
+ assign s3_wb_rd.wbd_lack = s3_wbd_lack_i ;
assign s3_wb_rd.wbd_err = 1'b0; // s3_wbd_err_i ; - unused
//
@@ -472,7 +523,8 @@
wb_arb u_wb_arb(
.clk(clk_i),
.rstn(rst_n),
- .req({ m2_wbd_stb_i & !m2_wbd_lack_o,
+ .req({ m3_wbd_stb_i & !m3_wbd_lack_o,
+ m2_wbd_stb_i & !m2_wbd_lack_o,
m1_wbd_stb_i & !m1_wbd_lack_o,
m0_wbd_stb_i & !m0_wbd_lack_o}),
.gnt(gnt)
@@ -485,6 +537,7 @@
3'h0: m_bus_wr = m0_wb_wr;
3'h1: m_bus_wr = m1_wb_wr;
3'h2: m_bus_wr = m2_wb_wr;
+ 3'h3: m_bus_wr = m3_wb_wr;
default: m_bus_wr = m0_wb_wr;
endcase
end
@@ -513,41 +566,42 @@
assign m0_wb_rd = (gnt == 2'b00) ? m_bus_rd : 'h0;
assign m1_wb_rd = (gnt == 2'b01) ? m_bus_rd : 'h0;
assign m2_wb_rd = (gnt == 2'b10) ? m_bus_rd : 'h0;
+assign m3_wb_rd = (gnt == 2'b11) ? m_bus_rd : 'h0;
// Stagging FF to break write and read timing path
-wb_stagging u_m_wb_stage(
+sync_wbb u_sync_wbb(
.clk_i (clk_i ),
.rst_n (rst_n ),
// WishBone Input master I/P
- .m_wbd_dat_i (m_bus_wr.wbd_dat ),
- .m_wbd_adr_i (m_bus_wr.wbd_adr ),
- .m_wbd_sel_i (m_bus_wr.wbd_sel ),
- .m_wbd_bl_i (m_bus_wr.wbd_bl ),
- .m_wbd_bry_i (m_bus_wr.wbd_bry ),
- .m_wbd_we_i (m_bus_wr.wbd_we ),
- .m_wbd_cyc_i (m_bus_wr.wbd_cyc ),
- .m_wbd_stb_i (m_bus_wr.wbd_stb ),
- .m_wbd_tid_i (m_bus_wr.wbd_tid ),
- .m_wbd_dat_o (m_bus_rd.wbd_dat ),
- .m_wbd_ack_o (m_bus_rd.wbd_ack ),
- .m_wbd_lack_o (m_bus_rd.wbd_lack ),
- .m_wbd_err_o (m_bus_rd.wbd_err ),
+ .wbm_dat_i (m_bus_wr.wbd_dat ),
+ .wbm_adr_i (m_bus_wr.wbd_adr ),
+ .wbm_sel_i (m_bus_wr.wbd_sel ),
+ .wbm_bl_i (m_bus_wr.wbd_bl ),
+ .wbm_bry_i (m_bus_wr.wbd_bry ),
+ .wbm_we_i (m_bus_wr.wbd_we ),
+ .wbm_cyc_i (m_bus_wr.wbd_cyc ),
+ .wbm_stb_i (m_bus_wr.wbd_stb ),
+ .wbm_tid_i (m_bus_wr.wbd_tid ),
+ .wbm_dat_o (m_bus_rd.wbd_dat ),
+ .wbm_ack_o (m_bus_rd.wbd_ack ),
+ .wbm_lack_o (m_bus_rd.wbd_lack ),
+ .wbm_err_o (m_bus_rd.wbd_err ),
// Slave Interface
- .s_wbd_dat_i (s_bus_rd.wbd_dat ),
- .s_wbd_ack_i (s_bus_rd.wbd_ack ),
- .s_wbd_lack_i (s_bus_rd.wbd_lack ),
- .s_wbd_err_i (s_bus_rd.wbd_err ),
- .s_wbd_dat_o (s_bus_wr.wbd_dat ),
- .s_wbd_adr_o (s_bus_wr.wbd_adr ),
- .s_wbd_sel_o (s_bus_wr.wbd_sel ),
- .s_wbd_bl_o (s_bus_wr.wbd_bl ),
- .s_wbd_bry_o (s_bus_wr.wbd_bry ),
- .s_wbd_we_o (s_bus_wr.wbd_we ),
- .s_wbd_cyc_o (s_bus_wr.wbd_cyc ),
- .s_wbd_stb_o (s_bus_wr.wbd_stb ),
- .s_wbd_tid_o (s_bus_wr.wbd_tid )
+ .wbs_dat_i (s_bus_rd.wbd_dat ),
+ .wbs_ack_i (s_bus_rd.wbd_ack ),
+ .wbs_lack_i (s_bus_rd.wbd_lack ),
+ .wbs_err_i (s_bus_rd.wbd_err ),
+ .wbs_dat_o (s_bus_wr.wbd_dat ),
+ .wbs_adr_o (s_bus_wr.wbd_adr ),
+ .wbs_sel_o (s_bus_wr.wbd_sel ),
+ .wbs_bl_o (s_bus_wr.wbd_bl ),
+ .wbs_bry_o (s_bus_wr.wbd_bry ),
+ .wbs_we_o (s_bus_wr.wbd_we ),
+ .wbs_cyc_o (s_bus_wr.wbd_cyc ),
+ .wbs_stb_o (s_bus_wr.wbd_stb ),
+ .wbs_tid_o (s_bus_wr.wbd_tid )
);
diff --git a/verilog/rtl/yifive/ycr1 b/verilog/rtl/yifive/ycr1
deleted file mode 160000
index f7438dc..0000000
--- a/verilog/rtl/yifive/ycr1
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit f7438dc651a838e2e922f6dc1753949329e7b5a9
diff --git a/verilog/rtl/yifive/ycr1c b/verilog/rtl/yifive/ycr1c
new file mode 160000
index 0000000..8b57442
--- /dev/null
+++ b/verilog/rtl/yifive/ycr1c
@@ -0,0 +1 @@
+Subproject commit 8b5744202fecf8a87d84da5dc7583a84aeef4fc1
