full chip sta clean-up: cpu,spi,rtc clock generation moved from glbl_cfg to wb_host
diff --git a/openlane/glbl_cfg/pin_order.cfg b/openlane/glbl_cfg/pin_order.cfg
index 022eda4..770b1f7 100644
--- a/openlane/glbl_cfg/pin_order.cfg
+++ b/openlane/glbl_cfg/pin_order.cfg
@@ -1,54 +1,16 @@
#BUS_SORT
#MANUAL_PLACE
-#E
-cpu_clk 0000 0
-rtc_clk
#N
mclk 0000 0
reset_n
-user_clock1
-user_clock2
user_irq\[2\]
user_irq\[1\]
user_irq\[0\]
-device_idcode\[31\]
-device_idcode\[30\]
-device_idcode\[29\]
-device_idcode\[28\]
-device_idcode\[27\]
-device_idcode\[26\]
-device_idcode\[25\]
-device_idcode\[24\]
-device_idcode\[23\]
-device_idcode\[22\]
-device_idcode\[21\]
-device_idcode\[20\]
-device_idcode\[19\]
-device_idcode\[18\]
-device_idcode\[17\]
-device_idcode\[16\]
-device_idcode\[15\]
-device_idcode\[14\]
-device_idcode\[13\]
-device_idcode\[12\]
-device_idcode\[11\]
-device_idcode\[10\]
-device_idcode\[9\]
-device_idcode\[8\]
-device_idcode\[7\]
-device_idcode\[6\]
-device_idcode\[5\]
-device_idcode\[4\]
-device_idcode\[3\]
-device_idcode\[2\]
-device_idcode\[1\]
-device_idcode\[0\]
#W
-sdram_clk 0000 0
-sdr_init_done
+sdr_init_done 0000 0
cfg_sdr_width\[1]
cfg_sdr_width\[0]
cfg_colbits\[1\]
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
index 6c17252..0c6de99 100755
--- a/openlane/wb_host/config.tcl
+++ b/openlane/wb_host/config.tcl
@@ -42,6 +42,7 @@
$script_dir/../../verilog/rtl/lib/clk_ctl.v \
$script_dir/../../verilog/rtl/lib/registers.v"
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
set ::env(SDC_FILE) "$script_dir/base.sdc"
set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
@@ -57,7 +58,7 @@
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 400 200"
+set ::env(DIE_AREA) "0 0 500 200"
# If you're going to use multiple power domains, then keep this disabled.
diff --git a/openlane/wb_host/pin_order.cfg b/openlane/wb_host/pin_order.cfg
index db8f388..d0b09f1 100644
--- a/openlane/wb_host/pin_order.cfg
+++ b/openlane/wb_host/pin_order.cfg
@@ -5,12 +5,36 @@
#E
wbs_clk_i 0000 0 2
wbs_clk_out
+cpu_clk
+rtc_clk
+wbd_int_rst_n
+cpu_rst_n
+spi_rst_n
+sdram_rst_n
+cfg_clk_ctrl1\[27\]
+cfg_clk_ctrl1\[26\]
+cfg_clk_ctrl1\[25\]
+cfg_clk_ctrl1\[24\]
+cfg_clk_ctrl1\[11\]
+cfg_clk_ctrl1\[10\]
+cfg_clk_ctrl1\[9\]
+cfg_clk_ctrl1\[8\]
+
+
+#W
+cfg_clk_ctrl1\[15\]
+cfg_clk_ctrl1\[14\]
+cfg_clk_ctrl1\[13\]
+cfg_clk_ctrl1\[12\]
+sdram_clk
#S
-wbm_clk_i 0000 0 2
+user_clock2 0000 0 2
+user_clock1
+wbm_clk_i
wbm_rst_i
wbm_ack_o
wbm_cyc_i
@@ -226,22 +250,10 @@
wbs_err_i
wbs_cyc_o
-cfg_glb_ctrl\[7\]
-cfg_glb_ctrl\[6\]
-cfg_glb_ctrl\[5\]
-cfg_glb_ctrl\[4\]
-cfg_glb_ctrl\[3\]
-cfg_glb_ctrl\[2\]
-cfg_glb_ctrl\[1\]
-cfg_glb_ctrl\[0\]
cfg_clk_ctrl1\[31\]
cfg_clk_ctrl1\[30\]
cfg_clk_ctrl1\[29\]
cfg_clk_ctrl1\[28\]
-cfg_clk_ctrl1\[27\]
-cfg_clk_ctrl1\[26\]
-cfg_clk_ctrl1\[25\]
-cfg_clk_ctrl1\[24\]
cfg_clk_ctrl1\[23\]
cfg_clk_ctrl1\[22\]
cfg_clk_ctrl1\[21\]
@@ -250,14 +262,6 @@
cfg_clk_ctrl1\[18\]
cfg_clk_ctrl1\[17\]
cfg_clk_ctrl1\[16\]
-cfg_clk_ctrl1\[15\]
-cfg_clk_ctrl1\[14\]
-cfg_clk_ctrl1\[13\]
-cfg_clk_ctrl1\[12\]
-cfg_clk_ctrl1\[11\]
-cfg_clk_ctrl1\[10\]
-cfg_clk_ctrl1\[9\]
-cfg_clk_ctrl1\[8\]
cfg_clk_ctrl1\[7\]
cfg_clk_ctrl1\[6\]
cfg_clk_ctrl1\[5\]
diff --git a/signoff/glbl_cfg/final_summary_report.csv b/signoff/glbl_cfg/final_summary_report.csv
index 7678a6e..359db11 100644
--- a/signoff/glbl_cfg/final_summary_report.csv
+++ b/signoff/glbl_cfg/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/glbl_cfg,glbl_cfg,glbl_cfg,Flow_completed,0h5m17s,0h3m22s,47033.33333333334,0.12,23516.66666666667,41,563.02,2822,0,0,0,0,0,0,0,5,0,-1,0,155613,24467,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,112650425,0.0,31.24,31.63,0.44,-1,-1,2677,2873,477,673,0,0,0,2822,1,0,3,9,474,0,3,571,588,548,10,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,4
+0,/project/openlane/glbl_cfg,glbl_cfg,glbl_cfg,Flow_completed,0h5m23s,0h3m25s,45883.33333333334,0.12,22941.66666666667,40,553.93,2753,0,0,0,0,0,0,0,4,0,-1,0,141562,23694,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,98863982,0.0,29.06,28.48,0.34,-1,-1,2637,2802,459,624,0,0,0,2753,1,0,3,0,471,0,0,562,577,533,10,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 7d44fb6..cd729d9 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h39m34s,0h4m46s,3.3079078455790785,10.2784,1.6539539227895392,0,569.55,17,0,0,0,0,0,0,0,0,24,-1,-1,1188369,4056,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.3,4.07,0.96,2.29,-1,852,1470,852,1470,0,0,0,17,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h40m38s,0h4m51s,3.3079078455790785,10.2784,1.6539539227895392,0,568.44,17,0,0,0,0,0,0,0,0,24,-1,-1,1182176,4163,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.24,4.03,1.04,2.32,-1,848,1466,848,1466,0,0,0,17,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv
index d6c67a7..2cc30c1 100644
--- a/signoff/wb_host/final_summary_report.csv
+++ b/signoff/wb_host/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_host,wb_host,wb_host,Flow_completed,0h5m32s,0h3m51s,72650.0,0.08,36325.0,58,563.27,2906,0,0,0,0,0,0,0,3,0,-1,0,155769,24752,-2.71,-2.71,-2.68,-2.68,-2.73,-85.53,-85.53,-84.64,-84.64,-87.05,121784250,0.0,55.83,29.09,15.64,-1,-1,2753,3014,454,715,0,0,0,2906,77,0,2,14,32,25,10,769,589,744,14,130,905,0,1035,78.55459544383346,12.73,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,5
+0,/project/openlane/wb_host,wb_host,wb_host,Flow_completed,0h5m36s,0h3m45s,61400.0,0.1,30700.0,49,587.03,3070,0,0,0,0,0,0,0,1,0,-1,0,173130,26433,-2.81,-2.81,-2.74,-2.74,-2.73,-85.26,-85.26,-84.77,-84.77,-85.68,139031696,0.0,48.06,23.93,17.81,-1,-1,2926,3180,551,805,0,0,0,3070,78,0,3,11,50,27,10,799,605,775,14,130,1139,0,1269,78.55459544383346,12.73,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,5
diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v
index 26eeaf8..2cb80c3 100644
--- a/verilog/dv/risc_boot/risc_boot_tb.v
+++ b/verilog/dv/risc_boot/risc_boot_tb.v
@@ -440,6 +440,42 @@
force uut.mprj.u_uart_core.u_lineclk_buf.VPB =USER_VDD1V8;
force uut.mprj.u_uart_core.u_lineclk_buf.VGND =VSS;
force uut.mprj.u_uart_core.u_lineclk_buf.VNB = VSS;
+
+ force uut.mprj.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_buf_wb_rst.VPB =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_buf_wb_rst.VGND =VSS;
+ force uut.mprj.u_wb_host.u_buf_wb_rst.VNB = VSS;
+
+ force uut.mprj.u_wb_host.u_buf_cpu_rst.VPWR =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_buf_cpu_rst.VPB =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_buf_cpu_rst.VGND =VSS;
+ force uut.mprj.u_wb_host.u_buf_cpu_rst.VNB = VSS;
+
+ force uut.mprj.u_wb_host.u_buf_spi_rst.VPWR =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_buf_spi_rst.VPB =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_buf_spi_rst.VGND =VSS;
+ force uut.mprj.u_wb_host.u_buf_spi_rst.VNB = VSS;
+
+ force uut.mprj.u_wb_host.u_buf_sdram_rst.VPWR =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_buf_sdram_rst.VPB =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_buf_sdram_rst.VGND =VSS;
+ force uut.mprj.u_wb_host.u_buf_sdram_rst.VNB = VSS;
+
+ force uut.mprj.u_wb_host.u_clkbuf_sdram.VPWR =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_clkbuf_sdram.VPB =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_clkbuf_sdram.VGND =VSS;
+ force uut.mprj.u_wb_host.u_clkbuf_sdram.VNB = VSS;
+
+ force uut.mprj.u_wb_host.u_clkbuf_cpu.VPWR =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_clkbuf_cpu.VPB =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_clkbuf_cpu.VGND =VSS;
+ force uut.mprj.u_wb_host.u_clkbuf_cpu.VNB = VSS;
+
+ force uut.mprj.u_wb_host.u_clkbuf_rtc.VPWR =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_clkbuf_rtc.VPB =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_clkbuf_rtc.VGND =VSS;
+ force uut.mprj.u_wb_host.u_clkbuf_rtc.VNB = VSS;
+
end
`endif
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
index bb63a42..aa4c71a 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -311,6 +311,41 @@
force u_top.u_uart_core.u_lineclk_buf.VPB =USER_VDD1V8;
force u_top.u_uart_core.u_lineclk_buf.VGND =VSS;
force u_top.u_uart_core.u_lineclk_buf.VNB = VSS;
+
+ force u_top.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_wb_rst.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_wb_rst.VGND =VSS;
+ force u_top.u_wb_host.u_buf_wb_rst.VNB = VSS;
+
+ force u_top.u_wb_host.u_buf_cpu_rst.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_cpu_rst.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_cpu_rst.VGND =VSS;
+ force u_top.u_wb_host.u_buf_cpu_rst.VNB = VSS;
+
+ force u_top.u_wb_host.u_buf_spi_rst.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_spi_rst.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_spi_rst.VGND =VSS;
+ force u_top.u_wb_host.u_buf_spi_rst.VNB = VSS;
+
+ force u_top.u_wb_host.u_buf_sdram_rst.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_sdram_rst.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_sdram_rst.VGND =VSS;
+ force u_top.u_wb_host.u_buf_sdram_rst.VNB = VSS;
+
+ force u_top.u_wb_host.u_clkbuf_sdram.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_clkbuf_sdram.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_clkbuf_sdram.VGND =VSS;
+ force u_top.u_wb_host.u_clkbuf_sdram.VNB = VSS;
+
+ force u_top.u_wb_host.u_clkbuf_cpu.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_clkbuf_cpu.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_clkbuf_cpu.VGND =VSS;
+ force u_top.u_wb_host.u_clkbuf_cpu.VNB = VSS;
+
+ force u_top.u_wb_host.u_clkbuf_rtc.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_clkbuf_rtc.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_clkbuf_rtc.VGND =VSS;
+ force u_top.u_wb_host.u_clkbuf_rtc.VNB = VSS;
end
`endif
diff --git a/verilog/dv/user_spi/user_spi_tb.v b/verilog/dv/user_spi/user_spi_tb.v
index 0489af7..60ad1f9 100644
--- a/verilog/dv/user_spi/user_spi_tb.v
+++ b/verilog/dv/user_spi/user_spi_tb.v
@@ -445,6 +445,41 @@
force u_top.u_uart_core.u_lineclk_buf.VPB =USER_VDD1V8;
force u_top.u_uart_core.u_lineclk_buf.VGND =VSS;
force u_top.u_uart_core.u_lineclk_buf.VNB = VSS;
+
+ force u_top.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_wb_rst.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_wb_rst.VGND =VSS;
+ force u_top.u_wb_host.u_buf_wb_rst.VNB = VSS;
+
+ force u_top.u_wb_host.u_buf_cpu_rst.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_cpu_rst.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_cpu_rst.VGND =VSS;
+ force u_top.u_wb_host.u_buf_cpu_rst.VNB = VSS;
+
+ force u_top.u_wb_host.u_buf_spi_rst.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_spi_rst.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_spi_rst.VGND =VSS;
+ force u_top.u_wb_host.u_buf_spi_rst.VNB = VSS;
+
+ force u_top.u_wb_host.u_buf_sdram_rst.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_sdram_rst.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_sdram_rst.VGND =VSS;
+ force u_top.u_wb_host.u_buf_sdram_rst.VNB = VSS;
+
+ force u_top.u_wb_host.u_clkbuf_sdram.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_clkbuf_sdram.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_clkbuf_sdram.VGND =VSS;
+ force u_top.u_wb_host.u_clkbuf_sdram.VNB = VSS;
+
+ force u_top.u_wb_host.u_clkbuf_cpu.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_clkbuf_cpu.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_clkbuf_cpu.VGND =VSS;
+ force u_top.u_wb_host.u_clkbuf_cpu.VNB = VSS;
+
+ force u_top.u_wb_host.u_clkbuf_rtc.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_clkbuf_rtc.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_clkbuf_rtc.VGND =VSS;
+ force u_top.u_wb_host.u_clkbuf_rtc.VNB = VSS;
end
`endif
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index 9f3e22c..d6fb8a0 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -149,7 +149,7 @@
`ifdef WFDUMP
initial begin
$dumpfile("risc_boot.vcd");
- $dumpvars(3, user_uart_tb);
+ $dumpvars(4, user_uart_tb);
end
`endif
@@ -350,6 +350,41 @@
force u_top.u_uart_core.u_lineclk_buf.VPB =USER_VDD1V8;
force u_top.u_uart_core.u_lineclk_buf.VGND =VSS;
force u_top.u_uart_core.u_lineclk_buf.VNB = VSS;
+
+ force u_top.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_wb_rst.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_wb_rst.VGND =VSS;
+ force u_top.u_wb_host.u_buf_wb_rst.VNB = VSS;
+
+ force u_top.u_wb_host.u_buf_cpu_rst.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_cpu_rst.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_cpu_rst.VGND =VSS;
+ force u_top.u_wb_host.u_buf_cpu_rst.VNB = VSS;
+
+ force u_top.u_wb_host.u_buf_spi_rst.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_spi_rst.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_spi_rst.VGND =VSS;
+ force u_top.u_wb_host.u_buf_spi_rst.VNB = VSS;
+
+ force u_top.u_wb_host.u_buf_sdram_rst.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_sdram_rst.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_buf_sdram_rst.VGND =VSS;
+ force u_top.u_wb_host.u_buf_sdram_rst.VNB = VSS;
+
+ force u_top.u_wb_host.u_clkbuf_sdram.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_clkbuf_sdram.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_clkbuf_sdram.VGND =VSS;
+ force u_top.u_wb_host.u_clkbuf_sdram.VNB = VSS;
+
+ force u_top.u_wb_host.u_clkbuf_cpu.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_clkbuf_cpu.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_clkbuf_cpu.VGND =VSS;
+ force u_top.u_wb_host.u_clkbuf_cpu.VNB = VSS;
+
+ force u_top.u_wb_host.u_clkbuf_rtc.VPWR =USER_VDD1V8;
+ force u_top.u_wb_host.u_clkbuf_rtc.VPB =USER_VDD1V8;
+ force u_top.u_wb_host.u_clkbuf_rtc.VGND =VSS;
+ force u_top.u_wb_host.u_clkbuf_rtc.VNB = VSS;
end
`endif
//------------------------------------------------------
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v
index 1ea0baa..7b12e0e 100644
--- a/verilog/dv/wb_port/wb_port_tb.v
+++ b/verilog/dv/wb_port/wb_port_tb.v
@@ -225,6 +225,42 @@
force uut.mprj.u_uart_core.u_lineclk_buf.VPB =USER_VDD1V8;
force uut.mprj.u_uart_core.u_lineclk_buf.VGND =VSS;
force uut.mprj.u_uart_core.u_lineclk_buf.VNB = VSS;
+
+ force uut.mprj.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_buf_wb_rst.VPB =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_buf_wb_rst.VGND =VSS;
+ force uut.mprj.u_wb_host.u_buf_wb_rst.VNB = VSS;
+
+ force uut.mprj.u_wb_host.u_buf_cpu_rst.VPWR =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_buf_cpu_rst.VPB =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_buf_cpu_rst.VGND =VSS;
+ force uut.mprj.u_wb_host.u_buf_cpu_rst.VNB = VSS;
+
+ force uut.mprj.u_wb_host.u_buf_spi_rst.VPWR =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_buf_spi_rst.VPB =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_buf_spi_rst.VGND =VSS;
+ force uut.mprj.u_wb_host.u_buf_spi_rst.VNB = VSS;
+
+ force uut.mprj.u_wb_host.u_buf_sdram_rst.VPWR =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_buf_sdram_rst.VPB =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_buf_sdram_rst.VGND =VSS;
+ force uut.mprj.u_wb_host.u_buf_sdram_rst.VNB = VSS;
+
+ force uut.mprj.u_wb_host.u_clkbuf_sdram.VPWR =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_clkbuf_sdram.VPB =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_clkbuf_sdram.VGND =VSS;
+ force uut.mprj.u_wb_host.u_clkbuf_sdram.VNB = VSS;
+
+ force uut.mprj.u_wb_host.u_clkbuf_cpu.VPWR =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_clkbuf_cpu.VPB =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_clkbuf_cpu.VGND =VSS;
+ force uut.mprj.u_wb_host.u_clkbuf_cpu.VNB = VSS;
+
+ force uut.mprj.u_wb_host.u_clkbuf_rtc.VPWR =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_clkbuf_rtc.VPB =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_clkbuf_rtc.VGND =VSS;
+ force uut.mprj.u_wb_host.u_clkbuf_rtc.VNB = VSS;
+
end
`endif
endmodule
diff --git a/verilog/rtl/digital_core/src/glbl_cfg.sv b/verilog/rtl/digital_core/src/glbl_cfg.sv
index 74557e7..a14597f 100644
--- a/verilog/rtl/digital_core/src/glbl_cfg.sv
+++ b/verilog/rtl/digital_core/src/glbl_cfg.sv
@@ -66,10 +66,7 @@
module glbl_cfg (
input logic mclk,
- input logic user_clock1,
- input logic user_clock2,
input logic reset_n,
- output logic [31:0] device_idcode,
// Reg Bus Interface Signal
input logic reg_cs,
@@ -82,13 +79,6 @@
output logic [31:0] reg_rdata,
output logic reg_ack,
- // SDRAM Clock
-
- output logic sdram_clk,
- output logic cpu_clk,
- output logic rtc_clk,
-
-
// Risc configuration
output logic [31:0] fuse_mhartid,
output logic [15:0] irq_lines,
@@ -270,22 +260,8 @@
// -----------------------------------------------------------------
-// SDRAM Clock source & div selection
-wire cfg_sdram_clk_src_sel = reg_0[4];
-wire cfg_sdram_clk_div = reg_0[5];
-wire [1:0] cfg_sdram_clk_ratio = reg_0[7:6];
-// Core Clock source & div selection
-wire cfg_cpu_clk_src_sel = reg_0[8];
-wire cfg_cpu_clk_div = reg_0[9];
-wire [1:0] cfg_cpu_clk_ratio = reg_0[11:10];
-
-// RTC Clock source & div selection
-wire cfg_rtc_clk_src_sel = reg_0[12];
-wire cfg_rtc_clk_div = reg_0[13];
-wire [1:0] cfg_rtc_clk_ratio = reg_0[15:14];
-
-generic_register #(8,0 ) u_reg0_be0 (
+generic_register #(8,8'hAA ) u_reg0_be0 (
.we ({8{sw_wr_en_0 &
wr_be[0] }} ),
.data_in (sw_reg_wdata[7:0] ),
@@ -296,7 +272,7 @@
.data_out (reg_0[7:0] )
);
-generic_register #(8,0 ) u_reg0_be1 (
+generic_register #(8,8'hBB ) u_reg0_be1 (
.we ({8{sw_wr_en_0 &
wr_be[1] }} ),
.data_in (sw_reg_wdata[15:8] ),
@@ -306,7 +282,7 @@
//List of Outs
.data_out (reg_0[15:8] )
);
-generic_register #(8,0 ) u_reg0_be2 (
+generic_register #(8,8'hCC ) u_reg0_be2 (
.we ({8{sw_wr_en_0 &
wr_be[2] }} ),
.data_in (sw_reg_wdata[23:16] ),
@@ -317,7 +293,7 @@
.data_out (reg_0[23:16] )
);
-generic_register #(8,0 ) u_reg0_be3 (
+generic_register #(8,8'hDD ) u_reg0_be3 (
.we ({8{sw_wr_en_0 &
wr_be[3] }} ),
.data_in (sw_reg_wdata[31:24] ),
@@ -333,7 +309,6 @@
//-----------------------------------------------------------------------
// reg-1, reset value = 32'hA55A_A55A
// -----------------------------------------------------------------
-assign device_idcode = reg_1[31:0];
generic_register #(.WD(8),.RESET_DEFAULT(8'h5A)) u_reg1_be0 (
.we ({8{sw_wr_en_1 &
@@ -1062,66 +1037,5 @@
-//----------------------------------
-// Generate SDRAM Clock Generation
-//----------------------------------
-wire sdram_clk_div;
-wire sdram_ref_clk;
-
-assign sdram_ref_clk = (cfg_sdram_clk_src_sel) ? user_clock2 :user_clock1;
-
-
-
-assign sdram_clk = (cfg_sdram_clk_div) ? sdram_clk_div : sdram_ref_clk;
-
-
-clk_ctl #(1) u_sdramclk (
- // Outputs
- .clk_o (sdram_clk_div ),
- // Inputs
- .mclk (sdram_ref_clk ),
- .reset_n (reset_n ),
- .clk_div_ratio (cfg_sdram_clk_ratio)
- );
-
-
-//----------------------------------
-// Generate CORE Clock Generation
-//----------------------------------
-wire cpu_clk_div;
-wire cpu_ref_clk;
-
-assign cpu_ref_clk = (cfg_cpu_clk_src_sel) ? user_clock2 : user_clock1;
-assign cpu_clk = (cfg_cpu_clk_div) ? cpu_clk_div : cpu_ref_clk;
-
-
-clk_ctl #(1) u_cpuclk (
- // Outputs
- .clk_o (cpu_clk_div ),
- // Inputs
- .mclk (cpu_ref_clk ),
- .reset_n (reset_n ),
- .clk_div_ratio (cfg_cpu_clk_ratio)
- );
-
-//----------------------------------
-// Generate RTC Clock Generation
-//----------------------------------
-wire rtc_clk_div;
-wire rtc_ref_clk;
-
-assign rtc_ref_clk = (cfg_rtc_clk_src_sel) ? user_clock2 : user_clock1;
-assign rtc_clk = (cfg_rtc_clk_div) ? rtc_clk_div : rtc_ref_clk;
-
-
-clk_ctl #(1) u_rtcclk (
- // Outputs
- .clk_o (rtc_clk_div ),
- // Inputs
- .mclk (rtc_ref_clk ),
- .reset_n (reset_n ),
- .clk_div_ratio (cfg_rtc_clk_ratio)
- );
-
endmodule
diff --git a/verilog/rtl/lib/async_wb.sv b/verilog/rtl/lib/async_wb.sv
index dac5928..ecad725 100644
--- a/verilog/rtl/lib/async_wb.sv
+++ b/verilog/rtl/lib/async_wb.sv
@@ -150,7 +150,7 @@
// Slave Interface
//-------------------------------
-logic [70:0] s_cmd_rd_data ;
+logic [68:0] s_cmd_rd_data ;
logic s_cmd_rd_empty ;
logic s_cmd_rd_aempty ;
logic s_cmd_rd_en ;
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index d5665d0..bb9c9b2 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -330,12 +330,8 @@
/////////////////////////////////////////////////////////
-// Generating acive low wishbone reset
-// //////////////////////////////////////////////////////
-assign wbd_int_rst_n = cfg_glb_ctrl[0];
-assign cpu_rst_n = cfg_glb_ctrl[1];
-assign spi_rst_n = cfg_glb_ctrl[2];
-assign sdram_rst_n = cfg_glb_ctrl[3];
+// Clock Skew Ctrl
+////////////////////////////////////////////////////////
assign cfg_cska_wi = cfg_clk_ctrl1[3:0];
assign cfg_cska_riscv = cfg_clk_ctrl1[7:4];
@@ -354,6 +350,17 @@
wb_host u_wb_host(
+ .user_clock1 (wb_clk_i ),
+ .user_clock2 (user_clock2 ),
+
+ .sdram_clk (sdram_clk ),
+ .cpu_clk (cpu_clk ),
+ .rtc_clk (rtc_clk ),
+
+ .wbd_int_rst_n (wbd_int_rst_n ),
+ .cpu_rst_n (cpu_rst_n ),
+ .spi_rst_n (spi_rst_n ),
+ .sdram_rst_n (sdram_rst_n ),
// Master Port
.wbm_rst_i (wb_rst_i ),
@@ -381,7 +388,6 @@
.wbs_ack_i (wbd_int_ack_o ),
.wbs_err_i (wbd_int_err_o ),
- .cfg_glb_ctrl (cfg_glb_ctrl ),
.cfg_clk_ctrl1 (cfg_clk_ctrl1 ),
.cfg_clk_ctrl2 (cfg_clk_ctrl2 )
@@ -614,9 +620,6 @@
.mclk (wbd_clk_glbl ),
.reset_n (wbd_int_rst_n ),
- .user_clock1 (wb_clk_i ),
- .user_clock2 (user_clock2 ),
- .device_idcode ( ),
// Reg Bus Interface Signal
.reg_cs (wbd_glbl_stb_o ),
@@ -629,12 +632,6 @@
.reg_rdata (wbd_glbl_dat_i ),
.reg_ack (wbd_glbl_ack_i ),
- // SDRAM Clock
-
- .sdram_clk (sdram_clk ),
- .cpu_clk (cpu_clk ),
- .rtc_clk (rtc_clk ),
-
// Risc configuration
.fuse_mhartid (fuse_mhartid ),
.irq_lines (irq_lines ),
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv
index 8f9a6dd..e91913b 100644
--- a/verilog/rtl/wb_host/src/wb_host.sv
+++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -69,6 +69,17 @@
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
+ input logic user_clock1 ,
+ input logic user_clock2 ,
+
+ output logic sdram_clk ,
+ output logic cpu_clk ,
+ output logic rtc_clk ,
+ // Global Reset control
+ output logic wbd_int_rst_n ,
+ output logic cpu_rst_n ,
+ output logic spi_rst_n ,
+ output logic sdram_rst_n ,
// Master Port
input logic wbm_rst_i , // Regular Reset signal
@@ -96,7 +107,6 @@
input logic wbs_ack_i , // acknowlegement
input logic wbs_err_i , // error
- output logic [7:0] cfg_glb_ctrl ,
output logic [31:0] cfg_clk_ctrl1 ,
output logic [31:0] cfg_clk_ctrl2
@@ -130,14 +140,33 @@
logic [7:0] cfg_bank_sel;
logic [31:0] wbm_adr_int;
logic wbm_stb_int;
+logic [23:0] reg_0; // Software_Reg_0
-logic [2:0] cfg_wb_clk_ctr;
-
+logic [2:0] cfg_wb_clk_ctrl;
+logic [2:0] cfg_sdram_clk_ctrl;
+logic [2:0] cfg_cpu_clk_ctrl;
+logic [2:0] cfg_rtc_clk_ctrl;
+logic [7:0] cfg_glb_ctrl;
assign wbm_rst_n = !wbm_rst_i;
assign wbs_rst_n = !wbm_rst_i;
+sky130_fd_sc_hd__bufbuf_16 u_buf_wb_rst (.A(cfg_glb_ctrl[0]),.X(wbd_int_rst_n));
+sky130_fd_sc_hd__bufbuf_16 u_buf_cpu_rst (.A(cfg_glb_ctrl[1]),.X(cpu_rst_n));
+sky130_fd_sc_hd__bufbuf_16 u_buf_spi_rst (.A(cfg_glb_ctrl[2]),.X(spi_rst_n));
+sky130_fd_sc_hd__bufbuf_16 u_buf_sdram_rst (.A(cfg_glb_ctrl[3]),.X(sdram_rst_n));
+
+// To reduce the load/Timing Wishbone I/F, Strobe is register to create
+// multi-cycle
+logic wb_req;
+always_ff @(negedge wbm_rst_n or posedge wbm_clk_i) begin
+ if ( wbm_rst_n == 1'b0 ) begin
+ wb_req <= '0;
+ end else begin
+ wb_req <= wbm_stb_i && (wbm_ack_o == 0) ;
+ end
+end
assign wbm_dat_o = (reg_sel) ? reg_rdata : wbm_dat_int; // data input
assign wbm_ack_o = (reg_sel) ? reg_ack : wbm_ack_int; // acknowlegement
@@ -156,7 +185,7 @@
// added indirect MSB 8 bit address select option
// So Address will be {Bank_Sel[7:0], wbm_adr_i[23:0}
// ---------------------------------------------------------------------
-assign reg_sel = wbm_stb_i & (wbm_adr_i[23] == 1'b1);
+assign reg_sel = wb_req & (wbm_adr_i[23] == 1'b1);
assign sw_addr = wbm_adr_i [3:2];
assign sw_rd_en = reg_sel & !wbm_we_i;
@@ -187,12 +216,22 @@
end
end
+
+//-------------------------------------
+// Global + Clock Control
+// -------------------------------------
+assign cfg_glb_ctrl = reg_0[7:0];
+assign cfg_wb_clk_ctrl = reg_0[10:8];
+assign cfg_sdram_clk_ctrl = reg_0[15:12];
+assign cfg_cpu_clk_ctrl = reg_0[19:16];
+assign cfg_rtc_clk_ctrl = reg_0[23:20];
+
always @( *)
begin
reg_out [31:0] = 8'd0;
case (sw_addr [1:0])
- 2'b00 : reg_out [31:0] = {21'h0,cfg_wb_clk_ctr[2:0],cfg_glb_ctrl [7:0]};
+ 2'b00 : reg_out [31:0] = {8'h0, reg_0[23:0]};
2'b01 : reg_out [31:0] = {24'h0,cfg_bank_sel [7:0]};
2'b10 : reg_out [31:0] = cfg_clk_ctrl1 [31:0];
2'b11 : reg_out [31:0] = cfg_clk_ctrl2 [31:0];
@@ -202,15 +241,14 @@
-generic_register #(11,0 ) u_glb_ctrl (
- .we ({11{sw_wr_en_0}} ),
- .data_in (wbm_dat_i[10:0] ),
+generic_register #(24,0 ) u_glb_ctrl (
+ .we ({24{sw_wr_en_0}} ),
+ .data_in (wbm_dat_i[23:0] ),
.reset_n (wbm_rst_n ),
.clk (wbm_clk_i ),
//List of Outs
- .data_out ({cfg_wb_clk_ctr[2:0],
- cfg_glb_ctrl[7:0]} )
+ .data_out (reg_0[23:0])
);
generic_register #(8,8'h30 ) u_bank_sel (
@@ -245,7 +283,7 @@
);
-assign wbm_stb_int = wbm_stb_i & !reg_sel;
+assign wbm_stb_int = wb_req & !reg_sel;
// Since design need more than 16MB address space, we have implemented
// indirect access
@@ -288,8 +326,8 @@
logic cfg_wb_clk_div;
logic [1:0] cfg_wb_clk_ratio;
-assign cfg_wb_clk_ratio = cfg_wb_clk_ctr[1:0];
-assign cfg_wb_clk_div = cfg_wb_clk_ctr[2];
+assign cfg_wb_clk_ratio = cfg_wb_clk_ctrl[1:0];
+assign cfg_wb_clk_div = cfg_wb_clk_ctrl[2];
assign wbs_clk_out = (cfg_wb_clk_div) ? wb_clk_div : wbm_clk_i;
@@ -304,5 +342,82 @@
.clk_div_ratio (cfg_wb_clk_ratio )
);
+//----------------------------------
+// Generate SDRAM Clock Generation
+//----------------------------------
+wire sdram_clk_div;
+wire sdram_ref_clk;
+wire sdram_clk_int;
+
+wire cfg_sdram_clk_src_sel = cfg_sdram_clk_ctrl[0];
+wire cfg_sdram_clk_div = cfg_sdram_clk_ctrl[1];
+wire [1:0] cfg_sdram_clk_ratio = cfg_sdram_clk_ctrl[3:2];
+assign sdram_ref_clk = (cfg_sdram_clk_src_sel) ? user_clock2 :user_clock1;
+assign sdram_clk_int = (cfg_sdram_clk_div) ? sdram_clk_div : sdram_ref_clk;
+
+sky130_fd_sc_hd__clkbuf_16 u_clkbuf_sdram (.A (sdram_clk_int), . X(sdram_clk));
+
+clk_ctl #(1) u_sdramclk (
+ // Outputs
+ .clk_o (sdram_clk_div ),
+ // Inputs
+ .mclk (sdram_ref_clk ),
+ .reset_n (reset_n ),
+ .clk_div_ratio (cfg_sdram_clk_ratio)
+ );
+
+
+//----------------------------------
+// Generate CORE Clock Generation
+//----------------------------------
+wire cpu_clk_div;
+wire cpu_ref_clk;
+wire cpu_clk_int;
+
+wire cfg_cpu_clk_src_sel = cfg_cpu_clk_ctrl[0];
+wire cfg_cpu_clk_div = cfg_cpu_clk_ctrl[1];
+wire [1:0] cfg_cpu_clk_ratio = cfg_cpu_clk_ctrl[3:2];
+
+assign cpu_ref_clk = (cfg_cpu_clk_src_sel) ? user_clock2 : user_clock1;
+assign cpu_clk_int = (cfg_cpu_clk_div) ? cpu_clk_div : cpu_ref_clk;
+
+
+sky130_fd_sc_hd__clkbuf_16 u_clkbuf_cpu (.A (cpu_clk_int), . X(cpu_clk));
+
+clk_ctl #(1) u_cpuclk (
+ // Outputs
+ .clk_o (cpu_clk_div ),
+ // Inputs
+ .mclk (cpu_ref_clk ),
+ .reset_n (reset_n ),
+ .clk_div_ratio (cfg_cpu_clk_ratio)
+ );
+
+//----------------------------------
+// Generate RTC Clock Generation
+//----------------------------------
+wire rtc_clk_div;
+wire rtc_ref_clk;
+wire rtc_clk_int;
+wire cfg_rtc_clk_src_sel = cfg_rtc_clk_ctrl[0];
+wire cfg_rtc_clk_div = cfg_rtc_clk_ctrl[1];
+wire [1:0] cfg_rtc_clk_ratio = cfg_rtc_clk_ctrl[3:2];
+
+assign rtc_ref_clk = (cfg_rtc_clk_src_sel) ? user_clock2 : user_clock1;
+assign rtc_clk_int = (cfg_rtc_clk_div) ? rtc_clk_div : rtc_ref_clk;
+
+
+sky130_fd_sc_hd__clkbuf_16 u_clkbuf_rtc (.A (rtc_clk_int), . X(rtc_clk));
+
+clk_ctl #(1) u_rtcclk (
+ // Outputs
+ .clk_o (rtc_clk_div ),
+ // Inputs
+ .mclk (rtc_ref_clk ),
+ .reset_n (reset_n ),
+ .clk_div_ratio (cfg_rtc_clk_ratio)
+ );
+
+
endmodule
