timing clean, syntacore gds link fix, 8KB SRAM added
diff --git a/Makefile b/Makefile
index 4570335..dc3de7c 100644
--- a/Makefile
+++ b/Makefile
@@ -57,9 +57,9 @@
TARGET_PATH=$(shell pwd)
VERIFY_COMMAND="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} DUMP=${DUMP} && make"
$(DV_PATTERNS): verify-% : ./verilog/dv/%
- docker run -v ${TARGET_PATH}:${TARGET_PATH} \
+ docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \
-v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
- -e TARGET_PATH=${TARGET_PATH} \
+ -e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \
-e CARAVEL_ROOT=${CARAVEL_ROOT} \
-u $(id -u $$USER):$(id -g $$USER) dineshannayya/dv_setup:latest \
sh -c $(VERIFY_COMMAND)
diff --git a/openlane/Makefile b/openlane/Makefile
index 18c4a16..a960416 100644
--- a/openlane/Makefile
+++ b/openlane/Makefile
@@ -19,8 +19,8 @@
CONFIG = $(foreach block,$(BLOCKS), ./$(block)/config.tcl)
CLEAN = $(foreach block,$(BLOCKS), clean-$(block))
-OPENLANE_TAG = mpw4
-OPENLANE_IMAGE_NAME = dineshannayya/openlane:$(OPENLANE_TAG)
+OPENLANE_TAG ?= mpw4
+OPENLANE_IMAGE_NAME ?= dineshannayya/openlane:$(OPENLANE_TAG)
OPENLANE_BASIC_COMMAND = "cd /project/openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
OPENLANE_INTERACTIVE_COMMAND = "cd /project/openlane && flow.tcl -it -file ./$*/interactive.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
@@ -31,29 +31,32 @@
@exit 1
$(BLOCKS) : % : ./%/config.tcl FORCE
-#ifeq ($(OPENLANE_ROOT),)
-# @echo "Please export OPENLANE_ROOT"
-# @exit 1
-#endif
-#ifeq ($(PDK_ROOT),)
-# @echo "Please export PDK_ROOT"
-# @exit 1
-#endif
+ifeq ($(OPENLANE_ROOT),)
+ @echo "Please export OPENLANE_ROOT"
+ @exit 1
+endif
+ifeq ($(PDK_ROOT),)
+ @echo "Please export PDK_ROOT"
+ @exit 1
+endif
@echo "###############################################"
@sleep 1
@if [ -f ./$*/interactive.tcl ]; then\
- docker run -it \
+ docker run -it -v $(OPENLANE_ROOT):/openLANE_flow \
-v $(PDK_ROOT):$(PDK_ROOT) \
-v $(PWD)/..:/project \
-v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+ -e PDK_ROOT=$(PDK_ROOT) \
-e CARAVEL_ROOT=$(CARAVEL_ROOT) \
-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
$(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_INTERACTIVE_COMMAND);\
else\
- docker run -it \
+ docker run -it -v $(OPENLANE_ROOT):/openLANE_flow \
+ -v $(PDK_ROOT):$(PDK_ROOT) \
-v $(PWD)/..:/project \
-v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+ -e PDK_ROOT=$(PDK_ROOT) \
-e CARAVEL_ROOT=$(CARAVEL_ROOT) \
-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
$(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_BASIC_COMMAND);\
@@ -69,7 +72,7 @@
@echo "Please export OPENLANE_ROOT"
@exit 1
endif
- git clone https://github.com/The-OpenROAD-Project/OpenLane --branch=$(OPENLANE_TAG) --depth=1 $(OPENLANE_ROOT) && \
+ git clone https://github.com/efabless/OpenLane --branch=$(OPENLANE_TAG) --depth=1 $(OPENLANE_ROOT) && \
cd $(OPENLANE_ROOT) && \
export IMAGE_NAME=efabless/openlane:$(OPENLANE_TAG) && \
make openlane
diff --git a/openlane/mbist1/base.sdc b/openlane/mbist1/base.sdc
new file mode 100644
index 0000000..8ae25b1
--- /dev/null
+++ b/openlane/mbist1/base.sdc
@@ -0,0 +1,163 @@
+###############################################################################
+# Created by write_sdc
+# Sun Nov 14 09:33:23 2021
+###############################################################################
+current_design mbist_top
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name wb_clk_i -period 10.0000 [get_ports {wb_clk_i}]
+create_generated_clock -name bist_mem_clk_a -add -source [get_ports {wb_clk_i}] -master_clock [get_clocks wb_clk_i] -divide_by 1 -comment {Mem Clock A} [get_ports mem_clk_a]
+create_generated_clock -name bist_mem_clk_b -add -source [get_ports {wb_clk_i}] -master_clock [get_clocks wb_clk_i] -divide_by 1 -comment {Mem Clock B} [get_ports mem_clk_b]
+
+set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks {wb_clk_i bist_mem_clk_a bist_mem_clk_b}]
+
+set_clock_transition 0.1500 [get_clocks {wb_clk_i}]
+set_clock_uncertainty -setup 0.2500 wb_clk_i
+set_clock_uncertainty -setup 0.2500 mem_clk_a
+set_clock_uncertainty -setup 0.2500 mem_clk_b
+
+set_clock_uncertainty -hold 0.2500 wb_clk_i
+set_clock_uncertainty -hold 0.2500 mem_clk_a
+set_clock_uncertainty -hold 0.2500 mem_clk_b
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
+set_input_delay -max 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rst_n}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rst_n}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_correct}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_done}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[0]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[1]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[2]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[3]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdo}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_correct}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_done}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[0]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[1]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[2]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[3]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdo}]
+
+set_false_path -from [get_ports {bist_en}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_load}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_run}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdi}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_shift}]
+
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_en}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_load}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_run}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdi}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_shift}]
+
+## Functional Inputs
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[*]}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_stb_i}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_cyc_i}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_we_i}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbd_mbist1_dat_o[*]}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[*]}]
+
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[*]}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_stb_i}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_cyc_i}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_we_i}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbd_mbist1_dat_o[*]}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[*]}]
+
+set_output_delay -max 5 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[*]}]
+set_output_delay -max 5 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_ack_o}]
+set_output_delay -max 5 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_err_o}]
+
+set_output_delay -min 1 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[*]}]
+set_output_delay -min 1 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_ack_o}]
+set_output_delay -min 1 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_err_o}]
+
+## Towards MEMORY from MBIST CLOCK
+## PORT-A
+set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[*]}]
+set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[*]}]
+
+
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[*]}]
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_a}]
+
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[*]}]
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_a}]
+
+
+
+## PORT-B
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_cen_b}]
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_din_b[*]}]
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_mask_b[*]}]
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_web_b}]
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_addr_b[*]}]
+
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_cen_b}]
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_din_b[*]}]
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_mask_b[*]}]
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_web_b}]
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_addr_b[*]}]
+
+
+# Set max delay for clock skew
+
+set_max_delay 3.5 -from [get_ports {wbd_clk_int}]
+set_max_delay 2 -to [get_ports {wbd_clk_mbist}]
+set_max_delay 3.5 -from wbd_clk_int -to wbd_clk_mbist
+
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {bist_correct}]
+set_load -pin_load 0.0334 [get_ports {bist_done}]
+set_load -pin_load 0.0334 [get_ports {bist_error}]
+set_load -pin_load 0.0334 [get_ports {bist_sdo}]
+set_load -pin_load 0.0334 [get_ports {mem_cen_a}]
+set_load -pin_load 0.0334 [get_ports {mem_cen_b}]
+set_load -pin_load 0.0334 [get_ports {mem_clk_a}]
+set_load -pin_load 0.0334 [get_ports {mem_clk_b}]
+set_load -pin_load 0.0334 [get_ports {mem_web_b}]
+set_load -pin_load 0.0334 [get_ports {bist_error_cnt[3]}]
+set_load -pin_load 0.0334 [get_ports {bist_error_cnt[2]}]
+set_load -pin_load 0.0334 [get_ports {bist_error_cnt[1]}]
+set_load -pin_load 0.0334 [get_ports {bist_error_cnt[0]}]
+set_load -pin_load 0.0334 [get_ports {wb_cyc_i}]
+set_load -pin_load 0.0334 [get_ports {wb_stb_i}]
+set_load -pin_load 0.0334 [get_ports {wb_adr_i[*]}]
+set_load -pin_load 0.0334 [get_ports {wb_we_i}]
+set_load -pin_load 0.0334 [get_ports {wb_dat_i[*]}]
+set_load -pin_load 0.0334 [get_ports {wb_sel_i[*]}]
+set_load -pin_load 0.0334 [get_ports {mem_addr_a[*]}]
+set_load -pin_load 0.0334 [get_ports {mem_addr_b[*]}]
+set_load -pin_load 0.0334 [get_ports {mem_din_b[*]}]
+set_load -pin_load 0.0334 [get_ports {mem_mask_b[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_en}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_load}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_run}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_sdi}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_shift}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_we_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[*]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]
diff --git a/openlane/mbist1/config.tcl b/openlane/mbist1/config.tcl
new file mode 100755
index 0000000..cc310b7
--- /dev/null
+++ b/openlane/mbist1/config.tcl
@@ -0,0 +1,113 @@
+# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+# Global
+# ------
+
+set script_dir [file dirname [file normalize [info script]]]
+# Name
+
+set ::env(DESIGN_NAME) mbist_top1
+
+set ::env(DESIGN_IS_CORE) "0"
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "u_cts_wb_clk_b1.u_buf/X u_cts_wb_clk_b2.u_buf/X u_mem_sel.u_cts_mem_clk_a.u_buf/X u_mem_sel.u_cts_mem_clk_b.u_buf/X"
+
+set ::env(SYNTH_MAX_FANOUT) 4
+
+# Sources
+# -------
+
+# Local sources + no2usb sources
+set ::env(VERILOG_FILES) "\
+ $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
+ $script_dir/../../verilog/rtl/mbist/src/core/mbist_addr_gen.sv \
+ $script_dir/../../verilog/rtl/mbist/src/core/mbist_fsm.sv \
+ $script_dir/../../verilog/rtl/mbist/src/core/mbist_op_sel.sv \
+ $script_dir/../../verilog/rtl/mbist/src/core/mbist_repair_addr.sv \
+ $script_dir/../../verilog/rtl/mbist/src/core/mbist_sti_sel.sv \
+ $script_dir/../../verilog/rtl/mbist/src/core/mbist_pat_sel.sv \
+ $script_dir/../../verilog/rtl/mbist/src/core/mbist_mux.sv \
+ $script_dir/../../verilog/rtl/mbist/src/core/mbist_data_cmp.sv \
+ $script_dir/../../verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv \
+ $script_dir/../../verilog/rtl/mbist/src/top/mbist_top1.sv \
+ $script_dir/../../verilog/rtl/lib/ctech_cells.sv \
+ $script_dir/../../verilog/rtl/lib/reset_sync.sv \
+ "
+
+set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/mbist/include ]
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+
+
+set ::env(SYNTH_PARAMS) "BIST_ADDR_WD 9,\
+ BIST_DATA_WD 32,\
+ BIST_ADDR_START 9'h000,\
+ BIST_ADDR_END 9'h1FB,\
+ BIST_REPAIR_ADDR_START 9'h1FC,\
+ BIST_RAD_WD_I 9,\
+ BIST_RAD_WD_O 9\
+ "
+
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(SDC_FILE) "$script_dir/base.sdc"
+set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+
+# Floorplanning
+# -------------
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 200 350"
+
+
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 1
+
+#set ::env(PDN_CFG) $script_dir/pdn.tcl
+
+
+set ::env(PL_TIME_DRIVEN) 1
+set ::env(PL_TARGET_DENSITY) "0.35"
+
+
+
+set ::env(FP_IO_VEXTEND) 4
+set ::env(FP_IO_HEXTEND) 4
+
+set ::env(FP_PDN_VPITCH) 100
+set ::env(FP_PDN_HPITCH) 100
+set ::env(FP_PDN_VWIDTH) 5
+set ::env(FP_PDN_HWIDTH) 5
+
+set ::env(GLB_RT_MAXLAYER) 5
+set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "0"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/mbist1/interactive.tcl b/openlane/mbist1/interactive.tcl
new file mode 100644
index 0000000..f59586f
--- /dev/null
+++ b/openlane/mbist1/interactive.tcl
@@ -0,0 +1,219 @@
+#!/usr/bin/tclsh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+# Copyright 2020 Efabless Corporation
+# Copyright 2020 Sylvain Munaut
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+package require openlane;
+
+
+proc run_placement_step {args} {
+ # set pdndef_dirname [file dirname $::env(pdn_tmp_file_tag).def]
+ # set pdndef [lindex [glob $pdndef_dirname/*pdn*] 0]
+ # set_def $pdndef
+ if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
+ set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
+ }
+
+ run_placement
+}
+
+proc run_cts_step {args} {
+ # set_def $::env(opendp_result_file_tag).def
+ if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
+ set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
+ }
+
+ run_cts
+ run_resizer_timing
+}
+
+proc run_routing_step {args} {
+ # set resizerdef_dirname [file dirname $::env(resizer_tmp_file_tag)_timing.def]
+ # set resizerdef [lindex [glob $resizerdef_dirname/*resizer*] 0]
+ # set_def $resizerdef
+ if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
+ set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
+ }
+ run_routing
+}
+
+proc run_diode_insertion_2_5_step {args} {
+ # set_def $::env(tritonRoute_result_file_tag).def
+ if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
+ set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
+ }
+ if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
+ run_antenna_check
+ heal_antenna_violators; # modifies the routed DEF
+ }
+
+}
+
+proc run_power_pins_insertion_step {args} {
+ # set_def $::env(tritonRoute_result_file_tag).def
+ if { ! [ info exists ::env(POWER_PINS_INSERTION_CURRENT_DEF) ] } {
+ set ::env(POWER_PINS_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(POWER_PINS_INSERTION_CURRENT_DEF)
+ }
+ if { $::env(LVS_INSERT_POWER_PINS) } {
+ write_powered_verilog
+ set_netlist $::env(lvs_result_file_tag).powered.v
+ }
+
+}
+
+proc run_lvs_step {{ lvs_enabled 1 }} {
+ # set_def $::env(tritonRoute_result_file_tag).def
+ if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
+ set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
+ }
+ if { $lvs_enabled } {
+ run_magic_spice_export
+ run_lvs; # requires run_magic_spice_export
+ }
+
+}
+
+proc run_drc_step {{ drc_enabled 1 }} {
+ if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
+ set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
+ }
+ if { $drc_enabled } {
+ run_magic_drc
+ run_klayout_drc
+ }
+}
+
+proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
+ if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
+ set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
+ }
+ if { $antenna_check_enabled } {
+ run_antenna_check
+ }
+}
+
+proc run_flow {args} {
+ set script_dir [file dirname [file normalize [info script]]]
+
+ set options {
+ {-design required}
+ {-save_path optional}
+ {-no_lvs optional}
+ {-no_drc optional}
+ {-no_antennacheck optional}
+ }
+ set flags {-save}
+ parse_key_args "run_flow" args arg_values $options flags_map $flags -no_consume
+
+ prep {*}$args
+
+ set LVS_ENABLED 1
+ set DRC_ENABLED 1
+ set ANTENNACHECK_ENABLED 1
+
+ set steps [dict create "synthesis" {run_synthesis "" } \
+ "floorplan" {run_floorplan ""} \
+ "placement" {run_placement_step ""} \
+ "cts" {run_cts_step ""} \
+ "routing" {run_routing_step ""}\
+ "diode_insertion" {run_diode_insertion_2_5_step ""} \
+ "power_pins_insertion" {run_power_pins_insertion_step ""} \
+ "gds_magic" {run_magic ""} \
+ "gds_drc_klayout" {run_klayout ""} \
+ "gds_xor_klayout" {run_klayout_gds_xor ""} \
+ "lvs" "run_lvs_step $LVS_ENABLED" \
+ "drc" "run_drc_step $DRC_ENABLED" \
+ "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \
+ "cvc" {run_lef_cvc}
+ ]
+
+ set_if_unset arg_values(-to) "cvc";
+
+ if { [info exists ::env(CURRENT_STEP) ] } {
+ puts "\[INFO\]:Picking up where last execution left off"
+ puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)]
+ } else {
+ set ::env(CURRENT_STEP) "synthesis";
+ }
+ set_if_unset arg_values(-from) $::env(CURRENT_STEP);
+ set exe 0;
+ dict for {step_name step_exe} $steps {
+ if { [ string equal $arg_values(-from) $step_name ] } {
+ set exe 1;
+ }
+
+ if { $exe } {
+ # For when it fails
+ set ::env(CURRENT_STEP) $step_name
+ [lindex $step_exe 0] [lindex $step_exe 1] ;
+ }
+
+ if { [ string equal $arg_values(-to) $step_name ] } {
+ set exe 0:
+ break;
+ }
+
+ }
+
+ # for when it resumes
+ set steps_as_list [dict keys $steps]
+ set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
+ set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
+
+ if { [info exists flags_map(-save) ] } {
+ if { ! [info exists arg_values(-save_path)] } {
+ set arg_values(-save_path) ""
+ }
+ save_views -lef_path $::env(magic_result_file_tag).lef \
+ -def_path $::env(CURRENT_DEF) \
+ -gds_path $::env(magic_result_file_tag).gds \
+ -mag_path $::env(magic_result_file_tag).mag \
+ -maglef_path $::env(magic_result_file_tag).lef.mag \
+ -spice_path $::env(magic_result_file_tag).spice \
+ -spef_path $::env(CURRENT_SPEF) \
+ -verilog_path $::env(CURRENT_NETLIST) \
+ -save_path $arg_values(-save_path) \
+ -tag $::env(RUN_TAG)
+ }
+
+
+ calc_total_runtime
+ save_state
+ generate_final_summary_report
+
+ check_timing_violations
+
+ puts_success "Flow Completed Without Fatal Errors."
+
+}
+
+run_flow {*}$argv
diff --git a/openlane/mbist1/pin_order.cfg b/openlane/mbist1/pin_order.cfg
new file mode 100644
index 0000000..82dd636
--- /dev/null
+++ b/openlane/mbist1/pin_order.cfg
@@ -0,0 +1,213 @@
+#BUS_SORT
+
+#MANUAL_PLACE
+
+
+#S
+rst_n 0000 0
+
+
+
+#E
+cfg_cska_mbist\[3\] 0000 0 4
+cfg_cska_mbist\[2\]
+cfg_cska_mbist\[1\]
+cfg_cska_mbist\[0\]
+wb_clk_i
+wbd_clk_mbist
+wbd_clk_int
+
+wb_cyc_i 0025 0 2
+wb_stb_i
+wb_we_i
+wb_adr_i\[8\]
+wb_adr_i\[7\]
+wb_adr_i\[6\]
+wb_adr_i\[5\]
+wb_adr_i\[4\]
+wb_adr_i\[3\]
+wb_adr_i\[2\]
+wb_adr_i\[1\]
+wb_adr_i\[0\]
+wb_dat_i\[31\]
+wb_dat_i\[30\]
+wb_dat_i\[29\]
+wb_dat_i\[28\]
+wb_dat_i\[27\]
+wb_dat_i\[26\]
+wb_dat_i\[25\]
+wb_dat_i\[24\]
+wb_dat_i\[23\]
+wb_dat_i\[22\]
+wb_dat_i\[21\]
+wb_dat_i\[20\]
+wb_dat_i\[19\]
+wb_dat_i\[18\]
+wb_dat_i\[17\]
+wb_dat_i\[16\]
+wb_dat_i\[15\]
+wb_dat_i\[14\]
+wb_dat_i\[13\]
+wb_dat_i\[12\]
+wb_dat_i\[11\]
+wb_dat_i\[10\]
+wb_dat_i\[9\]
+wb_dat_i\[8\]
+wb_dat_i\[7\]
+wb_dat_i\[6\]
+wb_dat_i\[5\]
+wb_dat_i\[4\]
+wb_dat_i\[3\]
+wb_dat_i\[2\]
+wb_dat_i\[1\]
+wb_dat_i\[0\]
+wb_sel_i\[3\]
+wb_sel_i\[2\]
+wb_sel_i\[1\]
+wb_sel_i\[0\]
+wb_dat_o\[31\]
+wb_dat_o\[30\]
+wb_dat_o\[29\]
+wb_dat_o\[28\]
+wb_dat_o\[27\]
+wb_dat_o\[26\]
+wb_dat_o\[25\]
+wb_dat_o\[24\]
+wb_dat_o\[23\]
+wb_dat_o\[22\]
+wb_dat_o\[21\]
+wb_dat_o\[20\]
+wb_dat_o\[19\]
+wb_dat_o\[18\]
+wb_dat_o\[17\]
+wb_dat_o\[16\]
+wb_dat_o\[15\]
+wb_dat_o\[14\]
+wb_dat_o\[13\]
+wb_dat_o\[12\]
+wb_dat_o\[11\]
+wb_dat_o\[10\]
+wb_dat_o\[9\]
+wb_dat_o\[8\]
+wb_dat_o\[7\]
+wb_dat_o\[6\]
+wb_dat_o\[5\]
+wb_dat_o\[4\]
+wb_dat_o\[3\]
+wb_dat_o\[2\]
+wb_dat_o\[1\]
+wb_dat_o\[0\]
+wb_ack_o
+wb_err_o
+
+
+bist_error_cnt\[3\] 0150 0 2
+bist_error_cnt\[2\]
+bist_error_cnt\[1\]
+bist_error_cnt\[0\]
+bist_correct
+bist_error
+bist_done
+bist_sdo
+bist_shift
+bist_sdi
+bist_load
+bist_run
+bist_en
+
+#W
+mem_clk_b 0000 0 2
+mem_cen_b
+mem_web_b
+mem_mask_b\[0\]
+mem_mask_b\[1\]
+mem_mask_b\[2\]
+mem_mask_b\[3\]
+mem_addr_b\[0\]
+mem_addr_b\[1\]
+mem_addr_b\[2\]
+mem_addr_b\[3\]
+mem_addr_b\[4\]
+mem_addr_b\[5\]
+mem_addr_b\[6\]
+mem_addr_b\[7\]
+mem_addr_b\[8\]
+mem_din_b\[0\]
+mem_din_b\[1\]
+mem_din_b\[2\]
+mem_din_b\[3\]
+mem_din_b\[4\]
+mem_din_b\[5\]
+mem_din_b\[6\]
+mem_din_b\[7\]
+mem_din_b\[8\]
+mem_din_b\[9\]
+mem_din_b\[10\]
+mem_din_b\[11\]
+mem_din_b\[12\]
+mem_din_b\[13\]
+mem_din_b\[14\]
+mem_din_b\[15\]
+mem_din_b\[16\]
+mem_din_b\[17\]
+mem_din_b\[18\]
+mem_din_b\[19\]
+mem_din_b\[20\]
+mem_din_b\[21\]
+mem_din_b\[22\]
+mem_din_b\[23\]
+mem_din_b\[24\]
+mem_din_b\[25\]
+mem_din_b\[26\]
+mem_din_b\[27\]
+mem_din_b\[28\]
+mem_din_b\[29\]
+mem_din_b\[30\]
+mem_din_b\[31\]
+
+
+mem_dout_a\[0\] 0100 0 2
+mem_dout_a\[1\]
+mem_dout_a\[2\]
+mem_dout_a\[3\]
+mem_dout_a\[4\]
+mem_dout_a\[5\]
+mem_dout_a\[6\]
+mem_dout_a\[7\]
+mem_dout_a\[8\]
+mem_dout_a\[9\]
+mem_dout_a\[10\]
+mem_dout_a\[11\]
+mem_dout_a\[12\]
+mem_dout_a\[13\]
+mem_dout_a\[14\]
+mem_dout_a\[15\]
+mem_dout_a\[16\]
+mem_dout_a\[17\]
+mem_dout_a\[18\]
+mem_dout_a\[19\]
+mem_dout_a\[20\]
+mem_dout_a\[21\]
+mem_dout_a\[22\]
+mem_dout_a\[23\]
+mem_dout_a\[24\]
+mem_dout_a\[25\]
+mem_dout_a\[26\]
+mem_dout_a\[27\]
+mem_dout_a\[28\]
+mem_dout_a\[29\]
+mem_dout_a\[30\]
+mem_dout_a\[31\]
+
+
+mem_clk_a 0200 0 2
+mem_cen_a
+mem_addr_a\[8\]
+mem_addr_a\[7\]
+mem_addr_a\[6\]
+mem_addr_a\[5\]
+mem_addr_a\[4\]
+mem_addr_a\[3\]
+mem_addr_a\[2\]
+mem_addr_a\[1\]
+mem_addr_a\[0\]
diff --git a/openlane/mbist1/sta.tcl b/openlane/mbist1/sta.tcl
new file mode 100644
index 0000000..57a6c35
--- /dev/null
+++ b/openlane/mbist1/sta.tcl
@@ -0,0 +1,88 @@
+# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+
+set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
+set ::env(LIB_TYPICAL) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib"
+set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
+set ::env(DESIGN_NAME) "mbist_top"
+set ::env(BASE_SDC_FILE) "base.sdc"
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
+set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
+set ::env(SYNTH_CAP_LOAD) "17.65"
+set ::env(WIRE_RC_LAYER) "met1"
+
+#To disable empty filler cell black box get created
+#set link_make_black_boxes 0
+
+
+set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
+define_corners wc bc tt
+read_liberty -corner bc $::env(LIB_FASTEST)
+read_liberty -corner wc $::env(LIB_SLOWEST)
+read_liberty -corner tt $::env(LIB_TYPICAL)
+
+
+read_verilog ../user_project_wrapper/netlist/mbist.v
+link_design $::env(DESIGN_NAME)
+
+
+read_spef ../../spef/mbist_top.spef
+
+
+read_sdc -echo $::env(BASE_SDC_FILE)
+
+# check for missing constraints
+check_setup -verbose > unconstraints.rpt
+
+set_operating_conditions -analysis_type single
+# Propgate the clock
+set_propagated_clock [all_clocks]
+
+report_tns
+report_wns
+#report_power
+echo "################ CORNER : WC (SLOW) TIMING Report ###################" > timing_ss_max.rpt
+report_checks -unique -path_delay max -slack_max -0.0 -group_count 100 -corner wc >> timing_ss_max.rpt
+report_checks -group_count 100 -path_delay max -path_group bist_clk -corner wc >> timing_ss_max.rpt
+report_checks -group_count 100 -path_delay max -path_group mem_clk_a -corner wc >> timing_ss_max.rpt
+report_checks -group_count 100 -path_delay max -path_group mem_clk_b -corner wc >> timing_ss_max.rpt
+report_checks -path_delay max -corner wc >> timing_ss_max.rpt
+
+echo "################ CORNER : BC (SLOW) TIMING Report ###################" > timing_ff_min.rpt
+report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner bc >> timing_ff_min.rpt
+report_checks -group_count 100 -path_delay min -path_group bist_clk -corner bc >> timing_ff_min.rpt
+report_checks -group_count 100 -path_delay min -path_group mem_clk_a -corner bc >> timing_ff_min.rpt
+report_checks -group_count 100 -path_delay min -path_group mem_clk_b -corner bc >> timing_ff_min.rpt
+report_checks -path_delay min -corner bc >> timing_ff_min.rpt
+
+echo "################ CORNER : TT (MAX) TIMING Report ###################" > timing_tt_max.rpt
+report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner tt >> timing_tt_max.rpt
+report_checks -group_count 100 -path_delay max -path_group bist_clk -corner tt >> timing_tt_max.rpt
+report_checks -group_count 100 -path_delay max -path_group mem_clk_a -corner tt >> timing_tt_max.rpt
+report_checks -group_count 100 -path_delay max -path_group mem_clk_b -corner tt >> timing_tt_max.rpt
+report_checks -path_delay min -corner tt >> timing_tt_min.rpt
+
+echo "################ CORNER : TT (MIN) TIMING Report ###################" > timing_tt_min.rpt
+report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner tt >> timing_tt_min.rpt
+report_checks -group_count 100 -path_delay min -path_group bist_clk -corner tt >> timing_tt_min.rpt
+report_checks -group_count 100 -path_delay min -path_group mem_clk_a -corner tt >> timing_tt_min.rpt
+report_checks -group_count 100 -path_delay min -path_group mem_clk_b -corner tt >> timing_tt_min.rpt
+report_checks -path_delay min -corner tt >> timing_tt_min.rpt
+
+report_checks -path_delay min
+
+#exit
diff --git a/openlane/pinmux/base.sdc b/openlane/pinmux/base.sdc
index 0fc0261..b6a4983 100644
--- a/openlane/pinmux/base.sdc
+++ b/openlane/pinmux/base.sdc
@@ -8,15 +8,20 @@
###############################################################################
create_clock -name mclk -period 10.0000 [get_ports {mclk}]
set_propagated_clock [get_clocks {mclk}]
-set_clock_uncertainty -rise_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -setup 0.2500
+set_clock_uncertainty -rise_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -setup 0.2500
-set_clock_uncertainty -rise_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -hold 0.2500
+set_clock_uncertainty -rise_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -hold 0.2500
+set_clock_uncertainty -fall_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -hold 0.2500
+set_clock_uncertainty -fall_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -hold 0.2500
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
### ClkSkew Adjust
set_case_analysis 0 [get_ports {cfg_cska_pinmux[0]}]
diff --git a/openlane/pinmux/config.tcl b/openlane/pinmux/config.tcl
index 562c1d7..99ecdb7 100755
--- a/openlane/pinmux/config.tcl
+++ b/openlane/pinmux/config.tcl
@@ -37,15 +37,17 @@
# Local sources + no2usb sources
set ::env(VERILOG_FILES) "\
$script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
- $script_dir/../../verilog/rtl/pinmux/src/pinmux.sv \
+ $script_dir/../../verilog/rtl/pinmux/src/pinmux.sv \
$script_dir/../../verilog/rtl/pinmux/src/pinmux_reg.sv \
- $script_dir/../../verilog/rtl/pinmux/src/gpio_intr.sv \
- $script_dir/../../verilog/rtl/pinmux/src/pwm.sv \
- $script_dir/../../verilog/rtl/lib/pulse_gen_type1.sv \
- $script_dir/../../verilog/rtl/lib/pulse_gen_type2.sv \
+ $script_dir/../../verilog/rtl/pinmux/src/gpio_intr.sv \
+ $script_dir/../../verilog/rtl/pinmux/src/pwm.sv \
+ $script_dir/../../verilog/rtl/lib/pulse_gen_type1.sv \
+ $script_dir/../../verilog/rtl/lib/pulse_gen_type2.sv \
+ $script_dir/../../verilog/rtl/lib/ser_inf_32b.sv \
$script_dir/../../verilog/rtl/lib/registers.v"
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
set ::env(SDC_FILE) "$script_dir/base.sdc"
set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
@@ -62,7 +64,7 @@
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 500 400"
+set ::env(DIE_AREA) "0 0 550 450"
# If you're going to use multiple power domains, then keep this disabled.
diff --git a/openlane/pinmux/pin_order.cfg b/openlane/pinmux/pin_order.cfg
index 2c09746..3a35f08 100644
--- a/openlane/pinmux/pin_order.cfg
+++ b/openlane/pinmux/pin_order.cfg
@@ -1,16 +1,11 @@
#BUS_SORT
#MANUAL_PLACE
-#N
-wbd_clk_int 0000 0 4
-cfg_cska_pinmux\[3\]
-cfg_cska_pinmux\[2\]
-cfg_cska_pinmux\[1\]
-cfg_cska_pinmux\[0\]
-wbd_clk_pinmux
-mclk
-h_reset_n
-
+#S
+h_reset_n 000 0 2
+user_irq\[0\]
+user_irq\[1\]
+user_irq\[2\]
usb_dp_o
usb_dn_o
usb_oen
@@ -29,9 +24,156 @@
spim_miso
spim_mosi
pulse1m_mclk
-
i2cm_intr
usb_intr
+pinmux_debug\[0\] 0100 0 2
+pinmux_debug\[1\]
+pinmux_debug\[2\]
+pinmux_debug\[3\]
+pinmux_debug\[4\]
+pinmux_debug\[5\]
+pinmux_debug\[6\]
+pinmux_debug\[7\]
+pinmux_debug\[8\]
+pinmux_debug\[9\]
+pinmux_debug\[10\]
+pinmux_debug\[11\]
+pinmux_debug\[12\]
+pinmux_debug\[13\]
+pinmux_debug\[14\]
+pinmux_debug\[15\]
+pinmux_debug\[16\]
+pinmux_debug\[17\]
+pinmux_debug\[18\]
+pinmux_debug\[19\]
+pinmux_debug\[20\]
+pinmux_debug\[21\]
+pinmux_debug\[22\]
+pinmux_debug\[23\]
+pinmux_debug\[24\]
+pinmux_debug\[25\]
+pinmux_debug\[26\]
+pinmux_debug\[27\]
+pinmux_debug\[28\]
+pinmux_debug\[29\]
+pinmux_debug\[30\]
+pinmux_debug\[31\]
+
+#W
+bist_error_cnt3\[3\] 000 0 2
+bist_error_cnt3\[2\]
+bist_error_cnt3\[1\]
+bist_error_cnt3\[0\]
+bist_correct\[3\]
+bist_error\[3\]
+bist_done\[3\]
+bist_sdo\[3\]
+bist_shift\[3\]
+bist_sdi\[3\]
+bist_load\[3\]
+bist_run\[3\]
+bist_en\[3\]
+
+bist_error_cnt2\[3\]
+bist_error_cnt2\[2\]
+bist_error_cnt2\[1\]
+bist_error_cnt2\[0\]
+bist_correct\[2\]
+bist_error\[2\]
+bist_done\[2\]
+bist_sdo\[2\]
+bist_shift\[2\]
+bist_sdi\[2\]
+bist_load\[2\]
+bist_run\[2\]
+bist_en\[2\]
+
+bist_error_cnt1\[3\]
+bist_error_cnt1\[2\]
+bist_error_cnt1\[1\]
+bist_error_cnt1\[0\]
+bist_correct\[1\]
+bist_error\[1\]
+bist_done\[1\]
+bist_sdo\[1\]
+bist_shift\[1\]
+bist_sdi\[1\]
+bist_load\[1\]
+bist_run\[1\]
+bist_en\[1\]
+
+bist_error_cnt0\[3\]
+bist_error_cnt0\[2\]
+bist_error_cnt0\[1\]
+bist_error_cnt0\[0\]
+bist_correct\[0\]
+bist_error\[0\]
+bist_done\[0\]
+bist_sdo\[0\]
+bist_shift\[0\]
+bist_sdi\[0\]
+bist_load\[0\]
+bist_run\[0\]
+bist_en\[0\]
+
+soft_irq
+irq_lines\[15\]
+irq_lines\[14\]
+irq_lines\[13\]
+irq_lines\[12\]
+irq_lines\[11\]
+irq_lines\[10\]
+irq_lines\[9\]
+irq_lines\[8\]
+irq_lines\[7\]
+irq_lines\[6\]
+irq_lines\[5\]
+irq_lines\[4\]
+irq_lines\[3\]
+irq_lines\[2\]
+irq_lines\[1\]
+irq_lines\[0\]
+fuse_mhartid\[31\]
+fuse_mhartid\[30\]
+fuse_mhartid\[29\]
+fuse_mhartid\[28\]
+fuse_mhartid\[27\]
+fuse_mhartid\[26\]
+fuse_mhartid\[25\]
+fuse_mhartid\[24\]
+fuse_mhartid\[23\]
+fuse_mhartid\[22\]
+fuse_mhartid\[21\]
+fuse_mhartid\[20\]
+fuse_mhartid\[19\]
+fuse_mhartid\[18\]
+fuse_mhartid\[17\]
+fuse_mhartid\[16\]
+fuse_mhartid\[15\]
+fuse_mhartid\[14\]
+fuse_mhartid\[13\]
+fuse_mhartid\[12\]
+fuse_mhartid\[11\]
+fuse_mhartid\[10\]
+fuse_mhartid\[9\]
+fuse_mhartid\[8\]
+fuse_mhartid\[7\]
+fuse_mhartid\[6\]
+fuse_mhartid\[5\]
+fuse_mhartid\[4\]
+fuse_mhartid\[3\]
+fuse_mhartid\[2\]
+fuse_mhartid\[1\]
+fuse_mhartid\[0\]
+
+cfg_cska_pinmux\[3\]
+cfg_cska_pinmux\[2\]
+cfg_cska_pinmux\[1\]
+cfg_cska_pinmux\[0\]
+wbd_clk_int
+wbd_clk_pinmux
+mclk
+
reg_cs 200 0
@@ -114,7 +256,70 @@
reg_rdata\[0\]
reg_ack
-digital_io_in\[23\] 300 0
+
+#N
+digital_io_oen\[37\] 000 0 2
+digital_io_out\[37\]
+digital_io_in\[37\]
+digital_io_oen\[36\]
+digital_io_out\[36\]
+digital_io_in\[36\]
+digital_io_oen\[35\]
+digital_io_out\[35\]
+digital_io_in\[35\]
+digital_io_oen\[34\]
+digital_io_out\[34\]
+digital_io_in\[34\]
+digital_io_oen\[33\]
+digital_io_out\[33\]
+digital_io_in\[33\]
+digital_io_oen\[32\]
+digital_io_out\[32\]
+digital_io_in\[32\]
+digital_io_oen\[31\]
+digital_io_out\[31\]
+digital_io_in\[31\]
+digital_io_oen\[30\]
+digital_io_out\[30\]
+digital_io_in\[30\]
+digital_io_oen\[29\]
+digital_io_out\[29\]
+digital_io_in\[29\]
+digital_io_oen\[28\]
+digital_io_out\[28\]
+
+
+
+digital_io_in\[28\] 0300 0 2
+digital_io_oen\[27\]
+digital_io_out\[27\]
+digital_io_in\[27\]
+digital_io_oen\[26\]
+digital_io_out\[26\]
+digital_io_in\[26\]
+digital_io_oen\[25\]
+digital_io_out\[25\]
+digital_io_in\[25\]
+digital_io_oen\[24\]
+digital_io_out\[24\]
+digital_io_in\[24\]
+
+sflash_oen\[0\] 350 0 2
+sflash_oen\[1\]
+sflash_oen\[2\]
+sflash_oen\[3\]
+sflash_ss
+sflash_sck
+sflash_do\[0\]
+sflash_do\[1\]
+sflash_do\[2\]
+sflash_do\[3\]
+sflash_di\[0\]
+sflash_di\[1\]
+sflash_di\[2\]
+sflash_di\[3\]
+
+digital_io_in\[23\] 400 0
digital_io_out\[23\]
digital_io_oen\[23\]
digital_io_in\[22\]
@@ -142,39 +347,6 @@
digital_io_out\[15\]
digital_io_oen\[15\]
-#S
-pinmux_debug\[0\] 0000 0 4
-pinmux_debug\[1\]
-pinmux_debug\[2\]
-pinmux_debug\[3\]
-pinmux_debug\[4\]
-pinmux_debug\[5\]
-pinmux_debug\[6\]
-pinmux_debug\[7\]
-pinmux_debug\[8\]
-pinmux_debug\[9\]
-pinmux_debug\[10\]
-pinmux_debug\[11\]
-pinmux_debug\[12\]
-pinmux_debug\[13\]
-pinmux_debug\[14\]
-pinmux_debug\[15\]
-pinmux_debug\[16\]
-pinmux_debug\[17\]
-pinmux_debug\[18\]
-pinmux_debug\[19\]
-pinmux_debug\[20\]
-pinmux_debug\[21\]
-pinmux_debug\[22\]
-pinmux_debug\[23\]
-pinmux_debug\[24\]
-pinmux_debug\[25\]
-pinmux_debug\[26\]
-pinmux_debug\[27\]
-pinmux_debug\[28\]
-pinmux_debug\[29\]
-pinmux_debug\[30\]
-pinmux_debug\[31\]
#E
digital_io_in\[0\] 0000 0 4
@@ -223,118 +395,4 @@
digital_io_out\[14\]
digital_io_oen\[14\]
-#W
-digital_io_oen\[37\] 000 0 2
-digital_io_out\[37\]
-digital_io_in\[37\]
-digital_io_oen\[36\]
-digital_io_out\[36\]
-digital_io_in\[36\]
-digital_io_oen\[35\]
-digital_io_out\[35\]
-digital_io_in\[35\]
-digital_io_oen\[34\]
-digital_io_out\[34\]
-digital_io_in\[34\]
-digital_io_oen\[33\]
-digital_io_out\[33\]
-digital_io_in\[33\]
-digital_io_oen\[32\]
-digital_io_out\[32\]
-digital_io_in\[32\]
-digital_io_oen\[31\]
-digital_io_out\[31\]
-digital_io_in\[31\]
-digital_io_oen\[30\]
-digital_io_out\[30\]
-digital_io_in\[30\]
-digital_io_oen\[29\]
-digital_io_out\[29\]
-digital_io_in\[29\]
-digital_io_oen\[28\]
-digital_io_out\[28\]
-
-irq_lines\[15\] 200 0 2
-irq_lines\[14\]
-irq_lines\[13\]
-irq_lines\[12\]
-irq_lines\[11\]
-irq_lines\[10\]
-irq_lines\[9\]
-irq_lines\[8\]
-irq_lines\[7\]
-irq_lines\[6\]
-irq_lines\[5\]
-irq_lines\[4\]
-irq_lines\[3\]
-irq_lines\[2\]
-irq_lines\[1\]
-irq_lines\[0\]
-soft_irq
-fuse_mhartid\[31\]
-fuse_mhartid\[30\]
-fuse_mhartid\[29\]
-fuse_mhartid\[28\]
-fuse_mhartid\[27\]
-fuse_mhartid\[26\]
-fuse_mhartid\[25\]
-fuse_mhartid\[24\]
-fuse_mhartid\[23\]
-fuse_mhartid\[22\]
-fuse_mhartid\[21\]
-fuse_mhartid\[20\]
-fuse_mhartid\[19\]
-fuse_mhartid\[18\]
-fuse_mhartid\[17\]
-fuse_mhartid\[16\]
-fuse_mhartid\[15\]
-fuse_mhartid\[14\]
-fuse_mhartid\[13\]
-fuse_mhartid\[12\]
-fuse_mhartid\[11\]
-fuse_mhartid\[10\]
-fuse_mhartid\[9\]
-fuse_mhartid\[8\]
-fuse_mhartid\[7\]
-fuse_mhartid\[6\]
-fuse_mhartid\[5\]
-fuse_mhartid\[4\]
-fuse_mhartid\[3\]
-fuse_mhartid\[2\]
-fuse_mhartid\[1\]
-fuse_mhartid\[0\]
-
-user_irq\[0\]
-user_irq\[1\]
-user_irq\[2\]
-
-
-digital_io_in\[28\] 0300 0 2
-digital_io_oen\[27\]
-digital_io_out\[27\]
-digital_io_in\[27\]
-digital_io_oen\[26\]
-digital_io_out\[26\]
-digital_io_in\[26\]
-digital_io_oen\[25\]
-digital_io_out\[25\]
-digital_io_in\[25\]
-digital_io_oen\[24\]
-digital_io_out\[24\]
-digital_io_in\[24\]
-
-sflash_oen\[0\] 350 0 2
-sflash_oen\[1\]
-sflash_oen\[2\]
-sflash_oen\[3\]
-sflash_ss
-sflash_sck
-sflash_do\[0\]
-sflash_do\[1\]
-sflash_do\[2\]
-sflash_do\[3\]
-sflash_di\[0\]
-sflash_di\[1\]
-sflash_di\[2\]
-sflash_di\[3\]
diff --git a/openlane/qspim/base.sdc b/openlane/qspim/base.sdc
index 5c0233e..a9e2aaf 100644
--- a/openlane/qspim/base.sdc
+++ b/openlane/qspim/base.sdc
@@ -22,22 +22,27 @@
set_case_analysis 0 [get_ports {cfg_cska_sp_co[0]}]
set_propagated_clock [get_clocks {spiclk}]
-set_clock_uncertainty -rise_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {spiclk}] -rise_to [get_clocks {spiclk}] -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {spiclk}] -rise_to [get_clocks {spiclk}] -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {spiclk}] -fall_to [get_clocks {spiclk}] -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {spiclk}] -fall_to [get_clocks {spiclk}] -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {spiclk}] -rise_to [get_clocks {spiclk}] -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {spiclk}] -rise_to [get_clocks {spiclk}] -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {spiclk}] -fall_to [get_clocks {spiclk}] -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {spiclk}] -fall_to [get_clocks {spiclk}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -hold 0.2500
+set_clock_uncertainty -rise_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -setup 0.2500
+set_clock_uncertainty -rise_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -hold 0.2500
+set_clock_uncertainty -rise_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -hold 0.2500
+set_clock_uncertainty -fall_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -hold 0.2500
+set_clock_uncertainty -fall_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -setup 0.2500
+set_clock_uncertainty -rise_from [get_clocks {spiclk}] -rise_to [get_clocks {spiclk}] -hold 0.2500
+set_clock_uncertainty -rise_from [get_clocks {spiclk}] -rise_to [get_clocks {spiclk}] -setup 0.2500
+set_clock_uncertainty -rise_from [get_clocks {spiclk}] -fall_to [get_clocks {spiclk}] -hold 0.2500
+set_clock_uncertainty -rise_from [get_clocks {spiclk}] -fall_to [get_clocks {spiclk}] -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {spiclk}] -rise_to [get_clocks {spiclk}] -hold 0.2500
+set_clock_uncertainty -fall_from [get_clocks {spiclk}] -rise_to [get_clocks {spiclk}] -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {spiclk}] -fall_to [get_clocks {spiclk}] -hold 0.2500
+set_clock_uncertainty -fall_from [get_clocks {spiclk}] -fall_to [get_clocks {spiclk}] -setup 0.2500
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
### ClkSkew Adjust
set_case_analysis 0 [get_ports {cfg_cska_spi[0]}]
diff --git a/openlane/qspim/config.tcl b/openlane/qspim/config.tcl
index fc9f6f7..4b3958f 100755
--- a/openlane/qspim/config.tcl
+++ b/openlane/qspim/config.tcl
@@ -46,8 +46,10 @@
$script_dir/../../verilog/rtl/qspim/src/qspim_ctrl.sv \
$script_dir/../../verilog/rtl/qspim/src/qspim_rx.sv \
$script_dir/../../verilog/rtl/qspim/src/qspim_tx.sv \
+ $script_dir/../../verilog/rtl/lib/ctech_cells.sv \
"
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
set ::env(SDC_FILE) "$script_dir/base.sdc"
set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
diff --git a/openlane/qspim/pin_order.cfg b/openlane/qspim/pin_order.cfg
index e45ddae..3ebdd7a 100644
--- a/openlane/qspim/pin_order.cfg
+++ b/openlane/qspim/pin_order.cfg
@@ -1,22 +1,8 @@
#BUS_SORT
#MANUAL_PLACE
-#W
-cfg_cska_sp_co\[3\] 0000 0
-cfg_cska_sp_co\[2\]
-cfg_cska_sp_co\[1\]
-cfg_cska_sp_co\[0\]
-cfg_cska_spi\[3\]
-cfg_cska_spi\[2\]
-cfg_cska_spi\[1\]
-cfg_cska_spi\[0\]
-wbd_clk_int
-wbd_clk_spi
-mclk
-rst_n
-
#E
-spi_debug\[0\] 0000 0
+spi_debug\[0\] 0000 0 2
spi_debug\[1\]
spi_debug\[2\]
spi_debug\[3\]
@@ -49,7 +35,7 @@
spi_debug\[30\]
spi_debug\[31\]
-spi_sdi\[3\] 0200 0
+spi_sdi\[3\] 0200 0 2
spi_sdi\[2\]
spi_sdi\[1\]
spi_sdi\[0\]
@@ -64,108 +50,123 @@
spi_oen\[1\]
spi_oen\[0\]
-#S
-wbd_stb_i 0000 0
-wbd_we_i 0000 1
-wbd_adr_i\[31\] 0000 2
-wbd_adr_i\[30\] 0000 3
-wbd_adr_i\[29\] 0000 4
-wbd_adr_i\[28\] 0000 5
-wbd_adr_i\[27\] 0000 6
-wbd_adr_i\[26\] 0000 7
-wbd_adr_i\[25\] 0000 8
-wbd_adr_i\[24\] 0000 9
-wbd_adr_i\[23\] 0000 10
-wbd_adr_i\[22\] 0000 11
-wbd_adr_i\[21\] 0000 12
-wbd_adr_i\[20\] 0000 13
-wbd_adr_i\[19\] 0000 14
-wbd_adr_i\[18\] 0000 15
-wbd_adr_i\[17\] 0000 16
-wbd_adr_i\[16\] 0000 17
-wbd_adr_i\[15\] 0000 18
-wbd_adr_i\[14\] 0000 19
-wbd_adr_i\[13\] 0000 20
-wbd_adr_i\[12\] 0000 21
-wbd_adr_i\[11\] 0000 22
-wbd_adr_i\[10\] 0000 23
-wbd_adr_i\[9\] 0000 24
-wbd_adr_i\[8\] 0000 25
-wbd_adr_i\[7\] 0000 26
-wbd_adr_i\[6\] 0000 27
-wbd_adr_i\[5\] 0000 28
-wbd_adr_i\[4\] 0000 29
-wbd_adr_i\[3\] 0000 30
-wbd_adr_i\[2\] 0000 31
-wbd_adr_i\[1\] 0000 32
-wbd_adr_i\[0\] 0000 33
-wbd_sel_i\[3\] 0000 34
-wbd_sel_i\[2\] 0000 35
-wbd_sel_i\[1\] 0000 36
-wbd_sel_i\[0\] 0000 37
-wbd_dat_i\[31\] 0000 38
-wbd_dat_i\[30\] 0000 39
-wbd_dat_i\[29\] 0000 40
-wbd_dat_i\[28\] 0000 41
-wbd_dat_i\[27\] 0000 42
-wbd_dat_i\[26\] 0000 43
-wbd_dat_i\[25\] 0000 44
-wbd_dat_i\[24\] 0000 45
-wbd_dat_i\[23\] 0000 46
-wbd_dat_i\[22\] 0000 47
-wbd_dat_i\[21\] 0000 48
-wbd_dat_i\[20\] 0000 49
-wbd_dat_i\[19\] 0000 50
-wbd_dat_i\[18\] 0000 51
-wbd_dat_i\[17\] 0000 52
-wbd_dat_i\[16\] 0000 53
-wbd_dat_i\[15\] 0000 54
-wbd_dat_i\[14\] 0000 55
-wbd_dat_i\[13\] 0000 56
-wbd_dat_i\[12\] 0000 57
-wbd_dat_i\[11\] 0000 58
-wbd_dat_i\[10\] 0000 59
-wbd_dat_i\[9\] 0000 60
-wbd_dat_i\[8\] 0000 61
-wbd_dat_i\[7\] 0000 62
-wbd_dat_i\[6\] 0000 63
-wbd_dat_i\[5\] 0000 64
-wbd_dat_i\[4\] 0000 65
-wbd_dat_i\[3\] 0000 66
-wbd_dat_i\[2\] 0000 67
-wbd_dat_i\[1\] 0000 68
-wbd_dat_i\[0\] 0000 69
-wbd_dat_o\[31\] 0000 70
-wbd_dat_o\[30\] 0000 71
-wbd_dat_o\[29\] 0000 72
-wbd_dat_o\[28\] 0000 73
-wbd_dat_o\[27\] 0000 74
-wbd_dat_o\[26\] 0000 75
-wbd_dat_o\[25\] 0000 76
-wbd_dat_o\[24\] 0000 77
-wbd_dat_o\[23\] 0000 78
-wbd_dat_o\[22\] 0000 79
-wbd_dat_o\[21\] 0000 80
-wbd_dat_o\[20\] 0000 81
-wbd_dat_o\[19\] 0000 82
-wbd_dat_o\[18\] 0000 83
-wbd_dat_o\[17\] 0000 84
-wbd_dat_o\[16\] 0000 85
-wbd_dat_o\[15\] 0000 86
-wbd_dat_o\[14\] 0000 87
-wbd_dat_o\[13\] 0000 88
-wbd_dat_o\[12\] 0000 89
-wbd_dat_o\[11\] 0000 90
-wbd_dat_o\[10\] 0000 91
-wbd_dat_o\[9\] 0000 92
-wbd_dat_o\[8\] 0000 93
-wbd_dat_o\[7\] 0000 94
-wbd_dat_o\[6\] 0000 95
-wbd_dat_o\[5\] 0000 96
-wbd_dat_o\[4\] 0000 97
-wbd_dat_o\[3\] 0000 98
-wbd_dat_o\[2\] 0000 99
-wbd_dat_o\[1\] 0000 100
-wbd_dat_o\[0\] 0000 101
-wbd_ack_o 0000 102
-wbd_err_o 0000 103
+#N
+rst_n
+
+#W
+cfg_cska_sp_co\[3\] 0000 0 2
+cfg_cska_sp_co\[2\]
+cfg_cska_sp_co\[1\]
+cfg_cska_sp_co\[0\]
+cfg_cska_spi\[3\]
+cfg_cska_spi\[2\]
+cfg_cska_spi\[1\]
+cfg_cska_spi\[0\]
+wbd_clk_int
+wbd_clk_spi
+mclk
+
+wbd_stb_i 0100 0 2
+wbd_we_i
+wbd_adr_i\[31\]
+wbd_adr_i\[30\]
+wbd_adr_i\[29\]
+wbd_adr_i\[28\]
+wbd_adr_i\[27\]
+wbd_adr_i\[26\]
+wbd_adr_i\[25\]
+wbd_adr_i\[24\]
+wbd_adr_i\[23\]
+wbd_adr_i\[22\]
+wbd_adr_i\[21\]
+wbd_adr_i\[20\]
+wbd_adr_i\[19\]
+wbd_adr_i\[18\]
+wbd_adr_i\[17\]
+wbd_adr_i\[16\]
+wbd_adr_i\[15\]
+wbd_adr_i\[14\]
+wbd_adr_i\[13\]
+wbd_adr_i\[12\]
+wbd_adr_i\[11\]
+wbd_adr_i\[10\]
+wbd_adr_i\[9\]
+wbd_adr_i\[8\]
+wbd_adr_i\[7\]
+wbd_adr_i\[6\]
+wbd_adr_i\[5\]
+wbd_adr_i\[4\]
+wbd_adr_i\[3\]
+wbd_adr_i\[2\]
+wbd_adr_i\[1\]
+wbd_adr_i\[0\]
+wbd_sel_i\[3\]
+wbd_sel_i\[2\]
+wbd_sel_i\[1\]
+wbd_sel_i\[0\]
+wbd_dat_i\[31\]
+wbd_dat_i\[30\]
+wbd_dat_i\[29\]
+wbd_dat_i\[28\]
+wbd_dat_i\[27\]
+wbd_dat_i\[26\]
+wbd_dat_i\[25\]
+wbd_dat_i\[24\]
+wbd_dat_i\[23\]
+wbd_dat_i\[22\]
+wbd_dat_i\[21\]
+wbd_dat_i\[20\]
+wbd_dat_i\[19\]
+wbd_dat_i\[18\]
+wbd_dat_i\[17\]
+wbd_dat_i\[16\]
+wbd_dat_i\[15\]
+wbd_dat_i\[14\]
+wbd_dat_i\[13\]
+wbd_dat_i\[12\]
+wbd_dat_i\[11\]
+wbd_dat_i\[10\]
+wbd_dat_i\[9\]
+wbd_dat_i\[8\]
+wbd_dat_i\[7\]
+wbd_dat_i\[6\]
+wbd_dat_i\[5\]
+wbd_dat_i\[4\]
+wbd_dat_i\[3\]
+wbd_dat_i\[2\]
+wbd_dat_i\[1\]
+wbd_dat_i\[0\]
+wbd_dat_o\[31\]
+wbd_dat_o\[30\]
+wbd_dat_o\[29\]
+wbd_dat_o\[28\]
+wbd_dat_o\[27\]
+wbd_dat_o\[26\]
+wbd_dat_o\[25\]
+wbd_dat_o\[24\]
+wbd_dat_o\[23\]
+wbd_dat_o\[22\]
+wbd_dat_o\[21\]
+wbd_dat_o\[20\]
+wbd_dat_o\[19\]
+wbd_dat_o\[18\]
+wbd_dat_o\[17\]
+wbd_dat_o\[16\]
+wbd_dat_o\[15\]
+wbd_dat_o\[14\]
+wbd_dat_o\[13\]
+wbd_dat_o\[12\]
+wbd_dat_o\[11\]
+wbd_dat_o\[10\]
+wbd_dat_o\[9\]
+wbd_dat_o\[8\]
+wbd_dat_o\[7\]
+wbd_dat_o\[6\]
+wbd_dat_o\[5\]
+wbd_dat_o\[4\]
+wbd_dat_o\[3\]
+wbd_dat_o\[2\]
+wbd_dat_o\[1\]
+wbd_dat_o\[0\]
+wbd_ack_o
+wbd_err_o
diff --git a/openlane/sar_adc/config.tcl b/openlane/sar_adc/config.tcl
index ac93cf0..7b6c845 100644
--- a/openlane/sar_adc/config.tcl
+++ b/openlane/sar_adc/config.tcl
@@ -41,13 +41,13 @@
set ::env(CLOCK_PERIOD) "100"
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
-#set ::env(PDN_CFG) $script_dir/pdn.tcl
+set ::env(PDN_CFG) $script_dir/pdn.tcl
set ::env(FP_SIZING) "absolute"
set ::env(DIE_AREA) "0 0 500 300"
-set ::env(FP_HORIZONTAL_HALO) 15
-set ::env(FP_VERTICAL_HALO) 15
+#set ::env(FP_HORIZONTAL_HALO) 15
+#set ::env(FP_VERTICAL_HALO) 15
#set ::env(GLB_RT_OBS) "met2 109.85000 19.89500 171.54500 69.22000"
set ::env(CLOCK_TREE_SYNTH) 0
@@ -59,7 +59,7 @@
set ::env(FP_PDN_CHECK_NODES) 0
set ::env(FP_PDN_VPITCH) "45"
set ::env(FP_PDN_VWIDTH) "3.5"
-
+#
set ::env(FP_PDN_HPITCH) "40"
set ::env(FP_PDN_HWIDTH) "6.5"
@@ -68,8 +68,8 @@
set ::env(DIODE_INSERTION_STRATEGY) 4
-set ::env(FP_VERTICAL_HALO) "35"
-set ::env(FP_HERTICAL_HALO) "35"
+#set ::env(FP_VERTICAL_HALO) "35"
+#set ::env(FP_HERTICAL_HALO) "35"
## Internal Macros
diff --git a/openlane/sar_adc/interactive.tcl b/openlane/sar_adc/interactive.tcl
new file mode 100644
index 0000000..b44b517
--- /dev/null
+++ b/openlane/sar_adc/interactive.tcl
@@ -0,0 +1,219 @@
+#!/usr/bin/tclsh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+# Copyright 2020 Efabless Corporation
+# Copyright 2020 Sylvain Munaut
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+package require openlane;
+
+
+proc run_placement_step {args} {
+ # set pdndef_dirname [file dirname $::env(pdn_tmp_file_tag).def]
+ # set pdndef [lindex [glob $pdndef_dirname/*pdn*] 0]
+ # set_def $pdndef
+ if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
+ set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
+ }
+
+ run_placement
+}
+
+proc run_cts_step {args} {
+ # set_def $::env(opendp_result_file_tag).def
+ if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
+ set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
+ }
+
+ run_cts
+ run_resizer_timing
+}
+
+proc run_routing_step {args} {
+ # set resizerdef_dirname [file dirname $::env(resizer_tmp_file_tag)_timing.def]
+ # set resizerdef [lindex [glob $resizerdef_dirname/*resizer*] 0]
+ # set_def $resizerdef
+ if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
+ set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
+ }
+ run_routing
+}
+
+proc run_diode_insertion_2_5_step {args} {
+ # set_def $::env(tritonRoute_result_file_tag).def
+ if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
+ set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
+ }
+ if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
+ run_antenna_check
+ heal_antenna_violators; # modifies the routed DEF
+ }
+
+}
+
+proc run_power_pins_insertion_step {args} {
+ # set_def $::env(tritonRoute_result_file_tag).def
+ if { ! [ info exists ::env(POWER_PINS_INSERTION_CURRENT_DEF) ] } {
+ set ::env(POWER_PINS_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(POWER_PINS_INSERTION_CURRENT_DEF)
+ }
+ if { $::env(LVS_INSERT_POWER_PINS) } {
+ write_powered_verilog
+ set_netlist $::env(lvs_result_file_tag).powered.v
+ }
+
+}
+
+proc run_lvs_step {{ lvs_enabled 1 }} {
+ # set_def $::env(tritonRoute_result_file_tag).def
+ if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
+ set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
+ }
+ if { $lvs_enabled } {
+ run_magic_spice_export
+ run_lvs; # requires run_magic_spice_export
+ }
+
+}
+
+proc run_drc_step {{ drc_enabled 1 }} {
+ if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
+ set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
+ }
+ if { $drc_enabled } {
+ run_magic_drc
+ run_klayout_drc
+ }
+}
+
+proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
+ if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
+ set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
+ }
+ if { $antenna_check_enabled } {
+ run_antenna_check
+ }
+}
+
+proc run_flow {args} {
+ set script_dir [file dirname [file normalize [info script]]]
+
+ set options {
+ {-design required}
+ {-save_path optional}
+ {-no_lvs optional}
+ {-no_drc optional}
+ {-no_antennacheck optional}
+ }
+ set flags {-save}
+ parse_key_args "run_flow" args arg_values $options flags_map $flags -no_consume
+
+ prep {*}$args
+
+ set LVS_ENABLED 1
+ set DRC_ENABLED 0
+ set ANTENNACHECK_ENABLED 1
+
+ set steps [dict create "synthesis" {run_synthesis "" } \
+ "floorplan" {run_floorplan ""} \
+ "placement" {run_placement_step ""} \
+ "cts" {run_cts_step ""} \
+ "routing" {run_routing_step ""}\
+ "diode_insertion" {run_diode_insertion_2_5_step ""} \
+ "power_pins_insertion" {run_power_pins_insertion_step ""} \
+ "gds_magic" {run_magic ""} \
+ "gds_drc_klayout" {run_klayout ""} \
+ "gds_xor_klayout" {run_klayout_gds_xor ""} \
+ "lvs" "run_lvs_step $LVS_ENABLED" \
+ "drc" "run_drc_step $DRC_ENABLED" \
+ "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \
+ "cvc" {run_lef_cvc}
+ ]
+
+ set_if_unset arg_values(-to) "cvc";
+
+ if { [info exists ::env(CURRENT_STEP) ] } {
+ puts "\[INFO\]:Picking up where last execution left off"
+ puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)]
+ } else {
+ set ::env(CURRENT_STEP) "synthesis";
+ }
+ set_if_unset arg_values(-from) $::env(CURRENT_STEP);
+ set exe 0;
+ dict for {step_name step_exe} $steps {
+ if { [ string equal $arg_values(-from) $step_name ] } {
+ set exe 1;
+ }
+
+ if { $exe } {
+ # For when it fails
+ set ::env(CURRENT_STEP) $step_name
+ [lindex $step_exe 0] [lindex $step_exe 1] ;
+ }
+
+ if { [ string equal $arg_values(-to) $step_name ] } {
+ set exe 0:
+ break;
+ }
+
+ }
+
+ # for when it resumes
+ set steps_as_list [dict keys $steps]
+ set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
+ set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
+
+ if { [info exists flags_map(-save) ] } {
+ if { ! [info exists arg_values(-save_path)] } {
+ set arg_values(-save_path) ""
+ }
+ save_views -lef_path $::env(magic_result_file_tag).lef \
+ -def_path $::env(CURRENT_DEF) \
+ -gds_path $::env(magic_result_file_tag).gds \
+ -mag_path $::env(magic_result_file_tag).mag \
+ -maglef_path $::env(magic_result_file_tag).lef.mag \
+ -spice_path $::env(magic_result_file_tag).spice \
+ -spef_path $::env(CURRENT_SPEF) \
+ -verilog_path $::env(CURRENT_NETLIST) \
+ -save_path $arg_values(-save_path) \
+ -tag $::env(RUN_TAG)
+ }
+
+
+ calc_total_runtime
+ save_state
+ generate_final_summary_report
+
+ check_timing_violations
+
+ puts_success "Flow Completed Without Fatal Errors."
+
+}
+
+run_flow {*}$argv
diff --git a/openlane/sar_adc/pdn.tcl b/openlane/sar_adc/pdn.tcl
index de972f1..c23f68f 100644
--- a/openlane/sar_adc/pdn.tcl
+++ b/openlane/sar_adc/pdn.tcl
@@ -13,118 +13,80 @@
if { [info exists ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS)] } {
if { $::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) == 1 } {
- # to parameterize -- needs a PDNGEN fix
- set pdngen::global_connections {
- VPWR {
- {inst_name .* pin_name VPWR}
- {inst_name .* pin_name VPB}
- }
- VGND {
- {inst_name .* pin_name VGND}
- {inst_name .* pin_name VNB}
- }
- }
+ add_global_connection -net $::env(VDD_NET) -inst_pattern .* -pin_pattern {VPWR} -power
+ add_global_connection -net $::env(VDD_NET) -inst_pattern .* -pin_pattern {VPB} -power
+ add_global_connection -net $::env(GND_NET) -inst_pattern .* -pin_pattern {VGND} -ground
+ add_global_connection -net $::env(GND_NET) -inst_pattern .* -pin_pattern {VNB} -ground
}
}
-# Used if the design is the core of the chip
-set stdcell_core {
- name grid
- straps {
- $::env(FP_PDN_LOWER_LAYER) {width $::env(FP_PDN_VWIDTH) pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
- $::env(FP_PDN_UPPER_LAYER) {width $::env(FP_PDN_HWIDTH) pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
- }
- connect {{$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}}
- pins { $::env(FP_PDN_UPPER_LAYER) }
-}
+set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET)
-# Used if the design is a macro in the core
-set stdcell_macro {
- name grid
- straps {
- $::env(FP_PDN_LOWER_LAYER) {width $::env(FP_PDN_VWIDTH) pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
- $::env(FP_PDN_UPPER_LAYER) {width $::env(FP_PDN_HWIDTH) pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
- }
- connect {{$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}}
-}
-
-# Assesses whether the deisgn is the core of the chip or not based on the value of $::env(DESIGN_IS_CORE) and uses the appropriate stdcell section
-if { [info exists ::env(DESIGN_IS_CORE)] } {
- if { $::env(DESIGN_IS_CORE) == 1 } {
- set stdcell $stdcell_core
- } else {
- set stdcell $stdcell_macro
- }
+# Assesses whether the deisgn is the core of the chip or not based on the
+# value of $::env(DESIGN_IS_CORE) and uses the appropriate stdcell section
+if { $::env(DESIGN_IS_CORE) == 1 } {
+ # Used if the design is the core of the chip
+ define_pdn_grid -name stdcell_grid -starts_with POWER -voltage_domain CORE -pins [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
+ add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_LOWER_LAYER) -width $::env(FP_PDN_VWIDTH) -pitch $::env(FP_PDN_VPITCH) -offset $::env(FP_PDN_VOFFSET) -starts_with POWER
+ add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_UPPER_LAYER) -width $::env(FP_PDN_HWIDTH) -pitch $::env(FP_PDN_HPITCH) -offset $::env(FP_PDN_HOFFSET) -starts_with POWER
+ add_pdn_connect -grid stdcell_grid -layers [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
} else {
- set stdcell $stdcell_core
+ # Used if the design is a macro in the core
+ define_pdn_grid -name stdcell_grid -starts_with POWER -voltage_domain CORE -pins $::env(FP_PDN_LOWER_LAYER)
+ add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_LOWER_LAYER) -width $::env(FP_PDN_VWIDTH) -pitch $::env(FP_PDN_VPITCH) -offset $::env(FP_PDN_VOFFSET) -starts_with POWER
}
+# Adds the standard cell rails if enabled.
+if { $::env(FP_PDN_ENABLE_RAILS) == 1 } {
+ add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_RAILS_LAYER) -width $::env(FP_PDN_RAIL_WIDTH) -followpins -starts_with POWER
+ add_pdn_connect -grid stdcell_grid -layers [subst {$::env(FP_PDN_RAILS_LAYER) $::env(FP_PDN_LOWER_LAYER)}]
+}
+
+
# Adds the core ring if enabled.
-if { [info exists ::env(FP_PDN_CORE_RING)] } {
- if { $::env(FP_PDN_CORE_RING) == 1 } {
- dict append stdcell core_ring {
- $::env(FP_PDN_LOWER_LAYER) {width $::env(FP_PDN_CORE_RING_VWIDTH) spacing $::env(FP_PDN_CORE_RING_VSPACING) core_offset $::env(FP_PDN_CORE_RING_VOFFSET)}
- }
- }
+if { $::env(FP_PDN_CORE_RING) == 1 } {
+ add_pdn_ring -grid stdcell_grid -layer [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}] \
+ -widths [subst {$::env(FP_PDN_CORE_RING_VWIDTH) $::env(FP_PDN_CORE_RING_HWIDTH)}] \
+ -spacings [subst {$::env(FP_PDN_CORE_RING_VSPACING) $::env(FP_PDN_CORE_RING_HSPACING)}] \
+ -core_offset [subst {$::env(FP_PDN_CORE_RING_VOFFSET) $::env(FP_PDN_CORE_RING_HOFFSET)}]
}
-# Adds the core ring if enabled.
-if { [info exists ::env(FP_PDN_ENABLE_RAILS)] } {
- if { $::env(FP_PDN_ENABLE_RAILS) == 1 } {
- dict append stdcell rails {
- $::env(FP_PDN_RAILS_LAYER) {width $::env(FP_PDN_RAIL_WIDTH) pitch $::env(PLACE_SITE_HEIGHT) offset $::env(FP_PDN_RAIL_OFFSET)}
- }
- dict update stdcell connect current_connect {
- append current_connect { {$::env(FP_PDN_RAILS_LAYER) $::env(FP_PDN_LOWER_LAYER)}}
- }
- } else {
- dict append stdcell rails {}
- }
-}
-
-pdngen::specify_grid stdcell [subst $stdcell]
-
# A general macro that follows the premise of the set heirarchy. You may want to modify this or add other macro configs
-# TODO: generate automatically per instance:
-
-if { $::env(VDD_NET) == "vccd1" } {
- set macro {
- orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
- power_pins "$::env(VDD_NET)"
- ground_pins "$::env(GND_NET)"
- blockages "li1 met1 met2 met3 met4"
- straps {
- }
- connect {{met4_PIN_ver met5}}
+# The macro power pin names are assumed to match the VDD and GND net names
+# TODO: parameterize the power pin names
+set macro {
+ orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
+ power_pins $::env(VDD_NET)
+ ground_pins $::env(GND_NET)
+ blockages "li1 met1 met2 met3 met4"
+ straps {
}
-} elseif { $::env(VDD_NET) == "vdda1" } {
- set macro {
- orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
- power_pins "vdda1"
- ground_pins "vssa1"
- blockages "li1 met1 met2 met3 met4"
- straps {
- }
- connect {{met4_PIN_ver met5}}
- }
-} else {
- set macro {
- orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
- power_pins "$::env(VDD_NET) vdd"
- ground_pins "$::env(GND_NET) gnd"
- blockages "li1 met1 met2 met3 met4"
- straps {
- }
- connect {{met4_PIN_ver met5}}
- }
+ connect {{$::env(FP_PDN_LOWER_LAYER)_PIN_ver $::env(FP_PDN_UPPER_LAYER)}}
}
-pdngen::specify_grid macro [subst $macro]
-
-set ::halo [expr min($::env(FP_HORIZONTAL_HALO), $::env(FP_VERTICAL_HALO))]
+if { $::env(FP_PDN_ENABLE_MACROS_GRID) == 1} {
+ if { [llength $::env(FP_PDN_MACROS)] > 0 } {
+ # generate automatically per instance:
+ foreach macro_instance $::env(FP_PDN_MACROS) {
+ set macro_instance_grid [subst $macro]
+ dict append $macro_instance_grid instance $macro_instance
+ set ::halo [list $::env(FP_HORIZONTAL_HALO) $::env(FP_VERTICAL_HALO)]
+ pdngen::specify_grid macro [subst $macro_instance_grid]
+ }
+ } else {
+ set ::halo [list $::env(FP_HORIZONTAL_HALO) $::env(FP_VERTICAL_HALO)]
+ pdngen::specify_grid macro [subst $macro]
+ }
+ # CAN NOT ENABLE THE TCL COMMAND BECAUSE THERE IS NO ARGUMENT FOR SPECIFYING THE POWER AND GROUND PIN NAMES ON THE MACRO
+ # define_pdn_grid -macro -orient {R0 R180 MX MY R90 R270 MXR90 MYR90} -grid_over_pg_pins -starts_with POWER -pin_direction vertical -halo [subst {$::env(FP_HORIZONTAL_HALO) $::env(FP_VERTICAL_HALO)}]
+ # add_pdn_connect -layers [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
+} else {
+ define_pdn_grid -macro -orient {R0 R180 MX MY R90 R270 MXR90 MYR90} -grid_over_pg_pins -starts_with POWER -halo [subst {$::env(FP_HORIZONTAL_HALO) $::env(FP_VERTICAL_HALO)}]
+}
# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
set ::rails_start_with "POWER" ;
# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
-set ::stripes_start_with "POWER" ;
\ No newline at end of file
+set ::stripes_start_with "POWER" ;
+
diff --git a/openlane/sar_adc/pin_order.cfg b/openlane/sar_adc/pin_order.cfg
index 9f5fbf6..b68e105 100644
--- a/openlane/sar_adc/pin_order.cfg
+++ b/openlane/sar_adc/pin_order.cfg
@@ -2,9 +2,11 @@
#MANUAL_PLACE
#S
-clk
reset_n
pulse1m_mclk
+
+#W
+clk 000 0 2
reg_cs
reg_wr
reg_addr\[7\]
diff --git a/openlane/syntacore/base.sdc b/openlane/syntacore/base.sdc
index c4f07bb..a811f4a 100644
--- a/openlane/syntacore/base.sdc
+++ b/openlane/syntacore/base.sdc
@@ -9,30 +9,37 @@
create_clock -name core_clk -period 20.0000 [get_ports {core_clk}]
create_clock -name rtc_clk -period 40.0000 [get_ports {rtc_clk}]
create_clock -name wb_clk -period 10.0000 [get_ports {wb_clk}]
-set_clock_uncertainty -rise_from [get_clocks {core_clk}] -rise_to [get_clocks {core_clk}] -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {core_clk}] -rise_to [get_clocks {core_clk}] -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {core_clk}] -fall_to [get_clocks {core_clk}] -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {core_clk}] -fall_to [get_clocks {core_clk}] -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {core_clk}] -rise_to [get_clocks {core_clk}] -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {core_clk}] -rise_to [get_clocks {core_clk}] -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {core_clk}] -fall_to [get_clocks {core_clk}] -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {core_clk}] -fall_to [get_clocks {core_clk}] -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}] -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}] -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}] -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}] -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}] -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}] -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}] -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}] -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}] -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}] -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}] -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}] -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}] -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}] -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}] -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {core_clk}] -rise_to [get_clocks {core_clk}] -hold 0.2500
+set_clock_uncertainty -rise_from [get_clocks {core_clk}] -rise_to [get_clocks {core_clk}] -setup 0.2500
+set_clock_uncertainty -rise_from [get_clocks {core_clk}] -fall_to [get_clocks {core_clk}] -hold 0.2500
+set_clock_uncertainty -rise_from [get_clocks {core_clk}] -fall_to [get_clocks {core_clk}] -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {core_clk}] -rise_to [get_clocks {core_clk}] -hold 0.2500
+set_clock_uncertainty -fall_from [get_clocks {core_clk}] -rise_to [get_clocks {core_clk}] -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {core_clk}] -fall_to [get_clocks {core_clk}] -hold 0.2500
+set_clock_uncertainty -fall_from [get_clocks {core_clk}] -fall_to [get_clocks {core_clk}] -setup 0.2500
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}] -hold 0.2500
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}] -setup 0.2500
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}] -hold 0.2500
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}] -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}] -hold 0.2500
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}] -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}] -hold 0.2500
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}] -setup 0.2500
+set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}] -hold 0.2500
+set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}] -setup 0.2500
+set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}] -hold 0.2500
+set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}] -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}] -hold 0.2500
+set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}] -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}] -hold 0.2500
+set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}] -setup 0.2500
+
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
set_clock_groups -name async_clock -asynchronous \
-group [get_clocks {core_clk}]\
-group [get_clocks {rtc_clk}]\
diff --git a/openlane/syntacore/config.tcl b/openlane/syntacore/config.tcl
index 15b5632..5f94296 100755
--- a/openlane/syntacore/config.tcl
+++ b/openlane/syntacore/config.tcl
@@ -88,7 +88,7 @@
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) [list 0.0 0.0 1000.0 900.0]
+set ::env(DIE_AREA) [list 0.0 0.0 1500.0 500.0]
# If you're going to use multiple power domains, then keep this disabled.
@@ -98,7 +98,7 @@
set ::env(PL_TIME_DRIVEN) 1
-set ::env(PL_TARGET_DENSITY) "0.35"
+set ::env(PL_TARGET_DENSITY) "0.33"
# helps in anteena fix
set ::env(USE_ARC_ANTENNA_CHECK) "0"
diff --git a/openlane/syntacore/pin_order.cfg b/openlane/syntacore/pin_order.cfg
index 99853b7..cf28a0a 100644
--- a/openlane/syntacore/pin_order.cfg
+++ b/openlane/syntacore/pin_order.cfg
@@ -2,27 +2,68 @@
#MANUAL_PLACE
+
#E
-core_clk 800 0
-rtc_clk
-cpu_rst_n
+soft_irq 0000 0 2
+irq_lines\[15\]
+irq_lines\[14\]
+irq_lines\[13\]
+irq_lines\[12\]
+irq_lines\[11\]
+irq_lines\[10\]
+irq_lines\[9\]
+irq_lines\[8\]
+irq_lines\[7\]
+irq_lines\[6\]
+irq_lines\[5\]
+irq_lines\[4\]
+irq_lines\[3\]
+irq_lines\[2\]
+irq_lines\[1\]
+irq_lines\[0\]
+fuse_mhartid\[31\]
+fuse_mhartid\[30\]
+fuse_mhartid\[29\]
+fuse_mhartid\[28\]
+fuse_mhartid\[27\]
+fuse_mhartid\[26\]
+fuse_mhartid\[25\]
+fuse_mhartid\[24\]
+fuse_mhartid\[23\]
+fuse_mhartid\[22\]
+fuse_mhartid\[21\]
+fuse_mhartid\[20\]
+fuse_mhartid\[19\]
+fuse_mhartid\[18\]
+fuse_mhartid\[17\]
+fuse_mhartid\[16\]
+fuse_mhartid\[15\]
+fuse_mhartid\[14\]
+fuse_mhartid\[13\]
+fuse_mhartid\[12\]
+fuse_mhartid\[11\]
+fuse_mhartid\[10\]
+fuse_mhartid\[9\]
+fuse_mhartid\[8\]
+fuse_mhartid\[7\]
+fuse_mhartid\[6\]
+fuse_mhartid\[5\]
+fuse_mhartid\[4\]
+fuse_mhartid\[3\]
+fuse_mhartid\[2\]
+fuse_mhartid\[1\]
+fuse_mhartid\[0\]
-
-#W
-cfg_cska_riscv\[3\] 0000 0 4
+cfg_cska_riscv\[3\]
cfg_cska_riscv\[2\]
cfg_cska_riscv\[1\]
cfg_cska_riscv\[0\]
wbd_clk_int
wbd_clk_riscv
wb_clk
-wb_rst_n
-pwrup_rst_n
-rst_n
-
-#N
-wbd_imem_stb_o 0000 0
+
+wbd_imem_stb_o 0150 0
wbd_imem_we_o
wbd_imem_adr_o\[31\]
wbd_imem_adr_o\[30\]
@@ -127,7 +168,7 @@
wbd_imem_ack_i
wbd_imem_err_i
-wbd_dmem_stb_o 0500 0 2
+wbd_dmem_stb_o 0350 0 2
wbd_dmem_we_o
wbd_dmem_adr_o\[31\]
wbd_dmem_adr_o\[30\]
@@ -232,58 +273,133 @@
wbd_dmem_ack_i
wbd_dmem_err_i
-irq_lines\[15\] 800 0 2
-irq_lines\[14\]
-irq_lines\[13\]
-irq_lines\[12\]
-irq_lines\[11\]
-irq_lines\[10\]
-irq_lines\[9\]
-irq_lines\[8\]
-irq_lines\[7\]
-irq_lines\[6\]
-irq_lines\[5\]
-irq_lines\[4\]
-irq_lines\[3\]
-irq_lines\[2\]
-irq_lines\[1\]
-irq_lines\[0\]
-soft_irq
-fuse_mhartid\[31\]
-fuse_mhartid\[30\]
-fuse_mhartid\[29\]
-fuse_mhartid\[28\]
-fuse_mhartid\[27\]
-fuse_mhartid\[26\]
-fuse_mhartid\[25\]
-fuse_mhartid\[24\]
-fuse_mhartid\[23\]
-fuse_mhartid\[22\]
-fuse_mhartid\[21\]
-fuse_mhartid\[20\]
-fuse_mhartid\[19\]
-fuse_mhartid\[18\]
-fuse_mhartid\[17\]
-fuse_mhartid\[16\]
-fuse_mhartid\[15\]
-fuse_mhartid\[14\]
-fuse_mhartid\[13\]
-fuse_mhartid\[12\]
-fuse_mhartid\[11\]
-fuse_mhartid\[10\]
-fuse_mhartid\[9\]
-fuse_mhartid\[8\]
-fuse_mhartid\[7\]
-fuse_mhartid\[6\]
-fuse_mhartid\[5\]
-fuse_mhartid\[4\]
-fuse_mhartid\[3\]
-fuse_mhartid\[2\]
-fuse_mhartid\[1\]
-fuse_mhartid\[0\]
#S
-riscv_debug\[0\] 300 0 4
+sram_dout0\[31\] 000 0 4
+sram_dout0\[30\]
+sram_dout0\[29\]
+sram_dout0\[28\]
+sram_dout0\[27\]
+sram_dout0\[26\]
+sram_dout0\[25\]
+sram_dout0\[24\]
+sram_dout0\[23\]
+sram_dout0\[22\]
+sram_dout0\[21\]
+sram_dout0\[20\]
+sram_dout0\[19\]
+sram_dout0\[18\]
+sram_dout0\[17\]
+sram_dout0\[16\]
+sram_dout0\[15\]
+sram_dout0\[14\]
+sram_dout0\[13\]
+sram_dout0\[12\]
+sram_dout0\[11\]
+sram_dout0\[10\]
+sram_dout0\[9\]
+sram_dout0\[8\]
+sram_dout0\[7\]
+sram_dout0\[6\]
+sram_dout0\[5\]
+sram_dout0\[4\]
+sram_dout0\[3\]
+sram_dout0\[2\]
+sram_dout0\[1\]
+sram_dout0\[0\]
+
+sram_din0\[31\] 200 0 4
+sram_din0\[30\]
+sram_din0\[29\]
+sram_din0\[28\]
+sram_din0\[27\]
+sram_din0\[26\]
+sram_din0\[25\]
+sram_din0\[24\]
+sram_din0\[23\]
+sram_din0\[22\]
+sram_din0\[21\]
+sram_din0\[20\]
+sram_din0\[19\]
+sram_din0\[18\]
+sram_din0\[17\]
+sram_din0\[16\]
+sram_din0\[15\]
+sram_din0\[14\]
+sram_din0\[13\]
+sram_din0\[12\]
+sram_din0\[11\]
+sram_din0\[10\]
+sram_din0\[9\]
+sram_din0\[8\]
+sram_din0\[7\]
+sram_din0\[6\]
+sram_din0\[5\]
+sram_din0\[4\]
+sram_din0\[3\]
+sram_din0\[2\]
+sram_din0\[1\]
+sram_din0\[0\]
+sram_wmask0\[3\]
+sram_wmask0\[2\]
+sram_wmask0\[1\]
+sram_wmask0\[0\]
+sram_web0
+sram_csb0
+sram_addr0\[8\]
+sram_addr0\[7\]
+sram_addr0\[6\]
+sram_addr0\[5\]
+sram_addr0\[4\]
+sram_addr0\[3\]
+sram_addr0\[2\]
+sram_addr0\[1\]
+sram_addr0\[0\]
+
+sram_csb1 400 0 4
+sram_addr1\[8\]
+sram_addr1\[7\]
+sram_addr1\[6\]
+sram_addr1\[5\]
+sram_addr1\[4\]
+sram_addr1\[3\]
+sram_addr1\[2\]
+sram_addr1\[1\]
+sram_addr1\[0\]
+sram_dout1\[0\]
+sram_dout1\[1\]
+sram_dout1\[2\]
+sram_dout1\[3\]
+sram_dout1\[4\]
+sram_dout1\[5\]
+sram_dout1\[6\]
+sram_dout1\[7\]
+sram_dout1\[8\]
+sram_dout1\[9\]
+sram_dout1\[10\]
+sram_dout1\[11\]
+sram_dout1\[12\]
+sram_dout1\[13\]
+sram_dout1\[14\]
+sram_dout1\[15\]
+sram_dout1\[16\]
+sram_dout1\[17\]
+sram_dout1\[18\]
+sram_dout1\[19\]
+sram_dout1\[20\]
+sram_dout1\[21\]
+sram_dout1\[22\]
+sram_dout1\[23\]
+sram_dout1\[24\]
+sram_dout1\[25\]
+sram_dout1\[26\]
+sram_dout1\[27\]
+sram_dout1\[28\]
+sram_dout1\[29\]
+sram_dout1\[30\]
+sram_dout1\[31\]
+
+riscv_debug\[0\] 1000 0 2
riscv_debug\[1\]
riscv_debug\[2\]
riscv_debug\[3\]
@@ -348,126 +464,10 @@
riscv_debug\[62\]
riscv_debug\[63\]
-sram_dout0\[31\] 500 0 4
-sram_dout0\[30\]
-sram_dout0\[29\]
-sram_dout0\[28\]
-sram_dout0\[27\]
-sram_dout0\[26\]
-sram_dout0\[25\]
-sram_dout0\[24\]
-sram_dout0\[23\]
-sram_dout0\[22\]
-sram_dout0\[21\]
-sram_dout0\[20\]
-sram_dout0\[19\]
-sram_dout0\[18\]
-sram_dout0\[17\]
-sram_dout0\[16\]
-sram_dout0\[15\]
-sram_dout0\[14\]
-sram_dout0\[13\]
-sram_dout0\[12\]
-sram_dout0\[11\]
-sram_dout0\[10\]
-sram_dout0\[9\]
-sram_dout0\[8\]
-sram_dout0\[7\]
-sram_dout0\[6\]
-sram_dout0\[5\]
-sram_dout0\[4\]
-sram_dout0\[3\]
-sram_dout0\[2\]
-sram_dout0\[1\]
-sram_dout0\[0\]
-sram_din0\[31\] 700 0 4
-sram_din0\[30\]
-sram_din0\[29\]
-sram_din0\[28\]
-sram_din0\[27\]
-sram_din0\[26\]
-sram_din0\[25\]
-sram_din0\[24\]
-sram_din0\[23\]
-sram_din0\[22\]
-sram_din0\[21\]
-sram_din0\[20\]
-sram_din0\[19\]
-sram_din0\[18\]
-sram_din0\[17\]
-sram_din0\[16\]
-sram_din0\[15\]
-sram_din0\[14\]
-sram_din0\[13\]
-sram_din0\[12\]
-sram_din0\[11\]
-sram_din0\[10\]
-sram_din0\[9\]
-sram_din0\[8\]
-sram_din0\[7\]
-sram_din0\[6\]
-sram_din0\[5\]
-sram_din0\[4\]
-sram_din0\[3\]
-sram_din0\[2\]
-sram_din0\[1\]
-sram_din0\[0\]
-sram_wmask0\[3\]
-sram_wmask0\[2\]
-sram_wmask0\[1\]
-sram_wmask0\[0\]
-sram_web0
-sram_csb0
-sram_addr0\[8\]
-sram_addr0\[7\]
-sram_addr0\[6\]
-sram_addr0\[5\]
-sram_addr0\[4\]
-sram_addr0\[3\]
-sram_addr0\[2\]
-sram_addr0\[1\]
-sram_addr0\[0\]
-
-sram_csb1 900 0 4
-sram_addr1\[8\]
-sram_addr1\[7\]
-sram_addr1\[6\]
-sram_addr1\[5\]
-sram_addr1\[4\]
-sram_addr1\[3\]
-sram_addr1\[2\]
-sram_addr1\[1\]
-sram_addr1\[0\]
-sram_dout1\[0\]
-sram_dout1\[1\]
-sram_dout1\[2\]
-sram_dout1\[3\]
-sram_dout1\[4\]
-sram_dout1\[5\]
-sram_dout1\[6\]
-sram_dout1\[7\]
-sram_dout1\[8\]
-sram_dout1\[9\]
-sram_dout1\[10\]
-sram_dout1\[11\]
-sram_dout1\[12\]
-sram_dout1\[13\]
-sram_dout1\[14\]
-sram_dout1\[15\]
-sram_dout1\[16\]
-sram_dout1\[17\]
-sram_dout1\[18\]
-sram_dout1\[19\]
-sram_dout1\[20\]
-sram_dout1\[21\]
-sram_dout1\[22\]
-sram_dout1\[23\]
-sram_dout1\[24\]
-sram_dout1\[25\]
-sram_dout1\[26\]
-sram_dout1\[27\]
-sram_dout1\[28\]
-sram_dout1\[29\]
-sram_dout1\[30\]
-sram_dout1\[31\]
+wb_rst_n 1200 0 2
+pwrup_rst_n
+rst_n
+core_clk
+rtc_clk
+cpu_rst_n
diff --git a/openlane/uart_i2cm_usb_spi/base.sdc b/openlane/uart_i2cm_usb_spi/base.sdc
index e651ed1..8623b71 100644
--- a/openlane/uart_i2cm_usb_spi/base.sdc
+++ b/openlane/uart_i2cm_usb_spi/base.sdc
@@ -7,24 +7,31 @@
# Timing Constraints
###############################################################################
create_clock -name app_clk -period 10.0000 [get_ports {app_clk}]
-create_clock -name line_clk -period 100.0000 [get_pins {u_uart_core.u_lineclk_buf/X}]
+create_clock -name line_clk -period 100.0000 [get_pins {u_uart_core.u_lineclk_buf.u_buf/X}]
create_clock -name usb_clk -period 100.0000 [get_ports {usb_clk}]
-set_clock_uncertainty -rise_from [get_clocks {app_clk}] -rise_to [get_clocks {app_clk}] -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {app_clk}] -rise_to [get_clocks {app_clk}] -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {app_clk}] -fall_to [get_clocks {app_clk}] -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {app_clk}] -fall_to [get_clocks {app_clk}] -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {app_clk}] -rise_to [get_clocks {app_clk}] -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {app_clk}] -rise_to [get_clocks {app_clk}] -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {app_clk}] -fall_to [get_clocks {app_clk}] -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {app_clk}] -fall_to [get_clocks {app_clk}] -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}] -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}] -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}] -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}] -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}] -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}] -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}] -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}] -setup 0.2000
+
+set_clock_uncertainty -rise_from [get_clocks {app_clk}] -rise_to [get_clocks {app_clk}] -hold 0.2500
+set_clock_uncertainty -rise_from [get_clocks {app_clk}] -rise_to [get_clocks {app_clk}] -setup 0.2500
+set_clock_uncertainty -rise_from [get_clocks {app_clk}] -fall_to [get_clocks {app_clk}] -hold 0.2500
+set_clock_uncertainty -rise_from [get_clocks {app_clk}] -fall_to [get_clocks {app_clk}] -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {app_clk}] -rise_to [get_clocks {app_clk}] -hold 0.2500
+set_clock_uncertainty -fall_from [get_clocks {app_clk}] -rise_to [get_clocks {app_clk}] -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {app_clk}] -fall_to [get_clocks {app_clk}] -hold 0.2500
+set_clock_uncertainty -fall_from [get_clocks {app_clk}] -fall_to [get_clocks {app_clk}] -setup 0.2500
+set_clock_uncertainty -rise_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}] -hold 0.2500
+set_clock_uncertainty -rise_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}] -setup 0.2500
+set_clock_uncertainty -rise_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}] -hold 0.2500
+set_clock_uncertainty -rise_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}] -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}] -hold 0.2500
+set_clock_uncertainty -fall_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}] -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}] -hold 0.2500
+set_clock_uncertainty -fall_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}] -setup 0.2500
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
set_clock_groups -name async_clock -asynchronous \
-group [get_clocks {app_clk}]\
-group [get_clocks {line_clk}] -comment {Async Clock group}
diff --git a/openlane/uart_i2cm_usb_spi/config.tcl b/openlane/uart_i2cm_usb_spi/config.tcl
index c23e79b..852ba18 100644
--- a/openlane/uart_i2cm_usb_spi/config.tcl
+++ b/openlane/uart_i2cm_usb_spi/config.tcl
@@ -27,7 +27,7 @@
# Timing configuration
set ::env(CLOCK_PERIOD) "10"
-set ::env(CLOCK_PORT) "app_clk usb_clk"
+set ::env(CLOCK_PORT) "app_clk usb_clk u_uart_core.line_clk_16x"
set ::env(SYNTH_MAX_FANOUT) 4
@@ -64,10 +64,12 @@
$script_dir/../../verilog/rtl/sspim/src/sspim_if.sv \
$script_dir/../../verilog/rtl/sspim/src/sspim_cfg.sv \
$script_dir/../../verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv\
+ $script_dir/../../verilog/rtl/lib/ctech_cells.sv \
"
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/i2cm/src/includes $script_dir/../../verilog/rtl/usb1_host/src/includes ]
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
set ::env(SDC_FILE) "$script_dir/base.sdc"
set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
diff --git a/openlane/uart_i2cm_usb_spi/pin_order.cfg b/openlane/uart_i2cm_usb_spi/pin_order.cfg
index 860fa18..3fc5625 100644
--- a/openlane/uart_i2cm_usb_spi/pin_order.cfg
+++ b/openlane/uart_i2cm_usb_spi/pin_order.cfg
@@ -1,8 +1,16 @@
#BUS_SORT
#MANUAL_PLACE
-#S
-reg_cs 0000 0 2
+#W
+cfg_cska_uart\[3\] 0000 0 2
+cfg_cska_uart\[2\]
+cfg_cska_uart\[1\]
+cfg_cska_uart\[0\]
+wbd_clk_int
+wbd_clk_uart
+app_clk
+
+reg_cs 0100 0 2
reg_wr
reg_addr\[7\]
reg_addr\[6\]
@@ -83,17 +91,15 @@
reg_rdata\[0\]
reg_ack
-cfg_cska_uart\[3\] 0400 0 2
-cfg_cska_uart\[2\]
-cfg_cska_uart\[1\]
-cfg_cska_uart\[0\]
-wbd_clk_int
-wbd_clk_uart
-app_clk
+
+#S
usb_clk
uart_rstn
i2c_rstn
usb_rstn
+
+
+#E
scl_pad_i
scl_pad_o
scl_pad_oen_o
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index a6ec28b..3241211 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -65,9 +65,8 @@
$proj_dir/../../verilog/gl/qspim.v \
$proj_dir/../../verilog/gl/wb_interconnect.v \
$proj_dir/../../verilog/gl/pinmux.v \
- $proj_dir/../../verilog/gl/sar_adc.v \
+ $proj_dir/../../verilog/gl/mbist1.v \
$proj_dir/../../verilog/gl/uart_i2cm_usb_spi.v \
- $proj_dir/../../verilog/rtl/sar_adc/DAC_8BIT.v \
$proj_dir/../../verilog/gl/wb_host.v \
$proj_dir/../../verilog/gl/syntacore.v \
$proj_dir/../../verilog/rtl/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v \
@@ -79,8 +78,7 @@
$lef_root/wb_interconnect.lef \
$lef_root/uart_i2cm_usb_spi.lef \
$lef_root/wb_host.lef \
- $lef_root/sar_adc.lef \
- $lef_root/DAC_8BIT.lef \
+ $lef_root/mbist1.lef \
$lef_root/syntacore.lef \
$lef_root/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
"
@@ -91,8 +89,8 @@
$gds_root/wb_interconnect.gds \
$gds_root/uart_i2cm_usb_spi.gds \
$gds_root/wb_host.gds \
- $gds_root/sar_adc.gds \
- $gds_root/DAC_8BIT.gds \
+ $gds_root/mbist1.gds \
+ $gds_root/syntacore.gds \
$gds_root/sky130_sram_2kbyte_1rw1r_32x512_8.gds \
"
@@ -110,27 +108,49 @@
set ::env(FP_PDN_ENABLE_MACROS_GRID) "1"
set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) "1"
-set ::env(VDD_NETS) "vccd1 vccd2 vdda1 vdda2"
-set ::env(GND_NETS) "vssd1 vssd2 vssa1 vssa2"
+set ::env(VDD_NETS) "vccd1"
+set ::env(GND_NETS) "vssd1"
-set ::env(VDD_PIN) "vccd1 vccd2 vdda1 vdda2"
-set ::env(GND_PIN) "vssd1 vssd2 vssa1 vssa2"
+set ::env(VDD_PIN) "vccd1"
+set ::env(GND_PIN) "vssd1"
-set ::env(GLB_RT_OBS) " li1 1200 200 1883.1 616.54,\
- met1 1200 200 1883.1 616.54,\
- met2 1200 200 1883.1 616.54,\
- met3 1200 200 1883.1 616.54,\
- met4 1200 200 1883.1 616.54,\
+set ::env(GLB_RT_OBS) "
+ li1 200 175 883.1 591.54,\
+ met1 200 175 883.1 591.54,\
+ met2 200 175 883.1 591.54,\
+ met3 200 175 883.1 591.54,\
+ li1 200 1300 883.1 1716.54,\
+ met1 200 1300 883.1 1716.54,\
+ met2 200 1300 883.1 1716.54,\
+ met3 200 1300 883.1 1716.54,\
+ li1 200 1850 883.1 2266.54,\
+ met1 200 1850 883.1 2266.54,\
+ met2 200 1850 883.1 2266.54,\
+ met3 200 1850 883.1 2266.54,\
+ li1 200 2400 883.1 2816.54,\
+ met1 200 2400 883.1 2816.54,\
+ met2 200 2400 883.1 2816.54,\
+ met3 200 2400 883.1 2816.54,\
+ li1 200 2950 883.1 3366.54,\
+ met1 200 2950 883.1 3366.54,\
+ met2 200 2950 883.1 3366.54,\
+ met3 200 2950 883.1 3366.54,\
met5 0 0 2920 3520"
set ::env(FP_PDN_MACRO_HOOKS) "\
- u_adc vccd1 vssd1 \
- u_adc vccd2 vssd2 \
u_intercon vccd1 vssd1 \
u_pinmux vccd1 vssd1 \
u_qspi_master vccd1 vssd1 \
u_riscv_top vccd1 vssd1 \
u_sram_2kb vccd1 vssd1 \
+ u_mbist1 vccd1 vssd1 \
+ u_mbist2 vccd1 vssd1 \
+ u_mbist3 vccd1 vssd1 \
+ u_mbist4 vccd1 vssd1 \
+ u_sram1_2kb vccd1 vssd1 \
+ u_sram2_2kb vccd1 vssd1 \
+ u_sram3_2kb vccd1 vssd1 \
+ u_sram4_2kb vccd1 vssd1 \
u_uart_i2c_usb_spi vccd1 vssd1 \
u_wb_host vccd1 vssd1 \
"
@@ -160,7 +180,7 @@
set ::env(QUIT_ON_TR_DRC) "0"
-set ::env(FP_PDN_HPITCH) "140"
-set ::env(FP_PDN_VPITCH) "140"
+set ::env(FP_PDN_HPITCH) "100"
+set ::env(FP_PDN_VPITCH) "180"
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index bc47034..a224082 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,8 +1,19 @@
-u_qspi_master 300 2700 N
-u_uart_i2c_usb_spi 1000 2700 N
-u_adc 2000 2700 N
-u_riscv_top 400 800 N
-u_sram_2kb 1200 200 N
-u_pinmux 2200 1600 N
-u_intercon 300 2350 N
-u_wb_host 300 300 N
+u_qspi_master 2200 700 N
+u_uart_i2c_usb_spi 2200 1400 N
+u_pinmux 2200 2300 N
+u_riscv_top 200 700 N
+u_sram_2kb 200 175 N
+
+u_mbist1 1100 1300 N
+u_sram1_2kb 200 1300 N
+
+u_mbist2 1100 1850 N
+u_sram2_2kb 200 1850 N
+
+u_mbist3 1100 2400 N
+u_sram3_2kb 200 2400 N
+
+u_mbist4 1100 2950 N
+u_sram4_2kb 200 2950 N
+u_intercon 1850 700 N
+u_wb_host 1750 200 N
diff --git a/openlane/wb_host/base.sdc b/openlane/wb_host/base.sdc
index 431a8f9..479be45 100644
--- a/openlane/wb_host/base.sdc
+++ b/openlane/wb_host/base.sdc
@@ -8,22 +8,28 @@
###############################################################################
create_clock -name wbm_clk_i -period 10.0000 [get_ports {wbm_clk_i}]
create_clock -name wbs_clk_i -period 10.0000 [get_ports {wbs_clk_i}]
-set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}] -hold 0.2000
-set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}] -setup 0.4000
-set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}] -hold 0.2000
-set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}] -setup 0.4000
-set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}] -hold 0.2000
-set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}] -setup 0.4000
-set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}] -hold 0.2000
-set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}] -setup 0.4000
-set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}] -hold 0.2000
-set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}] -setup 0.4000
-set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}] -hold 0.2000
-set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}] -setup 0.4000
-set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}] -hold 0.2000
-set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}] -setup 0.4000
-set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}] -hold 0.2000
-set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}] -setup 0.4000
+set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}] -hold 0.2500
+set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}] -setup 0.2500
+set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}] -hold 0.2500
+set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}] -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}] -hold 0.2500
+set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}] -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}] -hold 0.2500
+set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}] -setup 0.2500
+set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}] -hold 0.2500
+set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}] -setup 0.2500
+set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}] -hold 0.2500
+set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}] -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}] -hold 0.2500
+set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}] -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}] -hold 0.2500
+set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}] -setup 0.2500
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
set_clock_groups -name async_clock -asynchronous \
-group [get_clocks {wbs_clk_i}]\
-group [get_clocks {wbm_clk_i}] -comment {Async Clock group}
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
index e74c723..a3cd647 100755
--- a/openlane/wb_host/config.tcl
+++ b/openlane/wb_host/config.tcl
@@ -44,6 +44,7 @@
$script_dir/../../verilog/rtl/lib/registers.v"
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
set ::env(SDC_FILE) "$script_dir/base.sdc"
set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
@@ -59,7 +60,7 @@
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 400 300"
+set ::env(DIE_AREA) "0 0 350 250"
# If you're going to use multiple power domains, then keep this disabled.
@@ -69,7 +70,7 @@
set ::env(PL_TIME_DRIVEN) 1
-set ::env(PL_TARGET_DENSITY) "0.30"
+set ::env(PL_TARGET_DENSITY) "0.41"
diff --git a/openlane/wb_host/pin_order.cfg b/openlane/wb_host/pin_order.cfg
index 8bd1e35..27bcf92 100644
--- a/openlane/wb_host/pin_order.cfg
+++ b/openlane/wb_host/pin_order.cfg
@@ -5,12 +5,28 @@
#W
sspim_rst_n 0000 0 4
-cpu_rst_n
qspim_rst_n
-cfg_clk_ctrl1\[15\]
-cfg_clk_ctrl1\[14\]
-cfg_clk_ctrl1\[13\]
-cfg_clk_ctrl1\[12\]
+uart_rst_n
+i2cm_rst_n
+usb_rst_n
+bist_rst_n
+usb_clk
+cfg_clk_ctrl1\[31\]
+cfg_clk_ctrl1\[30\]
+cfg_clk_ctrl1\[29\]
+cfg_clk_ctrl1\[28\]
+cfg_clk_ctrl2\[27\]
+cfg_clk_ctrl2\[26\]
+cfg_clk_ctrl2\[25\]
+cfg_clk_ctrl2\[24\]
+cfg_clk_ctrl2\[23\]
+cfg_clk_ctrl2\[22\]
+cfg_clk_ctrl2\[21\]
+cfg_clk_ctrl2\[20\]
+cfg_clk_ctrl2\[19\]
+cfg_clk_ctrl2\[18\]
+cfg_clk_ctrl2\[17\]
+cfg_clk_ctrl2\[16\]
@@ -127,27 +143,73 @@
wbm_dat_o\[31\]
wbm_err_o
-cfg_clk_ctrl1\[11\] 200 0 4
-cfg_clk_ctrl1\[10\]
-cfg_clk_ctrl1\[9\]
-cfg_clk_ctrl1\[8\]
+
+#N
+cpu_clk 0000 0 2
+rtc_clk
+cpu_rst_n
+
+wbd_int_rst_n 0100 0 2
+cfg_clk_ctrl2\[31\]
+cfg_clk_ctrl2\[30\]
+cfg_clk_ctrl2\[29\]
+cfg_clk_ctrl2\[28\]
+cfg_clk_ctrl2\[15\]
+cfg_clk_ctrl2\[14\]
+cfg_clk_ctrl2\[13\]
+cfg_clk_ctrl2\[12\]
+cfg_clk_ctrl2\[11\]
+cfg_clk_ctrl2\[10\]
+cfg_clk_ctrl2\[9\]
+cfg_clk_ctrl2\[8\]
+cfg_clk_ctrl2\[7\]
+cfg_clk_ctrl2\[6\]
+cfg_clk_ctrl2\[5\]
+cfg_clk_ctrl2\[4\]
+cfg_clk_ctrl2\[3\]
+cfg_clk_ctrl2\[2\]
+cfg_clk_ctrl2\[1\]
+cfg_clk_ctrl2\[0\]
cfg_clk_ctrl1\[27\]
cfg_clk_ctrl1\[26\]
cfg_clk_ctrl1\[25\]
cfg_clk_ctrl1\[24\]
-wbs_clk_i 300 0 4
-wbd_clk_wh
-wbs_clk_out
+cfg_clk_ctrl1\[23\]
+cfg_clk_ctrl1\[22\]
+cfg_clk_ctrl1\[21\]
+cfg_clk_ctrl1\[20\]
+cfg_clk_ctrl1\[19\]
+cfg_clk_ctrl1\[18\]
+cfg_clk_ctrl1\[17\]
+cfg_clk_ctrl1\[16\]
+cfg_clk_ctrl1\[15\]
+cfg_clk_ctrl1\[14\]
+cfg_clk_ctrl1\[13\]
+cfg_clk_ctrl1\[12\]
+cfg_clk_ctrl1\[11\]
+cfg_clk_ctrl1\[10\]
+cfg_clk_ctrl1\[9\]
+cfg_clk_ctrl1\[8\]
+cfg_clk_ctrl1\[3\]
+cfg_clk_ctrl1\[2\]
+cfg_clk_ctrl1\[1\]
+cfg_clk_ctrl1\[0\]
wbd_clk_int
+wbs_clk_out
+wbs_clk_i
+wbd_clk_wh
+cfg_clk_ctrl1\[7\]
cfg_cska_wh\[3\]
+cfg_clk_ctrl1\[6\]
cfg_cska_wh\[2\]
+cfg_clk_ctrl1\[5\]
cfg_cska_wh\[1\]
+cfg_clk_ctrl1\[4\]
cfg_cska_wh\[0\]
-cpu_clk
-rtc_clk
-#N
-wbs_stb_o 0000 0 2
+
+
+wbs_stb_o 0160 0 2
wbs_we_o
wbs_adr_o\[31\]
wbs_adr_o\[30\]
@@ -253,63 +315,5 @@
wbs_err_i
wbs_cyc_o
-cfg_clk_ctrl1\[31\]
-cfg_clk_ctrl1\[30\]
-cfg_clk_ctrl1\[29\]
-cfg_clk_ctrl1\[28\]
-cfg_clk_ctrl1\[23\]
-cfg_clk_ctrl1\[22\]
-cfg_clk_ctrl1\[21\]
-cfg_clk_ctrl1\[20\]
-cfg_clk_ctrl1\[19\]
-cfg_clk_ctrl1\[18\]
-cfg_clk_ctrl1\[17\]
-cfg_clk_ctrl1\[16\]
-cfg_clk_ctrl1\[7\]
-cfg_clk_ctrl1\[6\]
-cfg_clk_ctrl1\[5\]
-cfg_clk_ctrl1\[4\]
-cfg_clk_ctrl1\[3\]
-cfg_clk_ctrl1\[2\]
-cfg_clk_ctrl1\[1\]
-cfg_clk_ctrl1\[0\]
-cfg_clk_ctrl2\[31\]
-cfg_clk_ctrl2\[30\]
-cfg_clk_ctrl2\[29\]
-cfg_clk_ctrl2\[28\]
-cfg_clk_ctrl2\[27\]
-cfg_clk_ctrl2\[26\]
-cfg_clk_ctrl2\[25\]
-cfg_clk_ctrl2\[24\]
-cfg_clk_ctrl2\[23\]
-cfg_clk_ctrl2\[22\]
-cfg_clk_ctrl2\[21\]
-cfg_clk_ctrl2\[20\]
-cfg_clk_ctrl2\[19\]
-cfg_clk_ctrl2\[18\]
-cfg_clk_ctrl2\[17\]
-cfg_clk_ctrl2\[16\]
-cfg_clk_ctrl2\[15\]
-cfg_clk_ctrl2\[14\]
-cfg_clk_ctrl2\[13\]
-cfg_clk_ctrl2\[12\]
-cfg_clk_ctrl2\[11\]
-cfg_clk_ctrl2\[10\]
-cfg_clk_ctrl2\[9\]
-cfg_clk_ctrl2\[8\]
-cfg_clk_ctrl2\[7\]
-cfg_clk_ctrl2\[6\]
-cfg_clk_ctrl2\[5\]
-cfg_clk_ctrl2\[4\]
-cfg_clk_ctrl2\[3\]
-cfg_clk_ctrl2\[2\]
-cfg_clk_ctrl2\[1\]
-cfg_clk_ctrl2\[0\]
-uart_rst_n
-i2cm_rst_n
-usb_rst_n
-usb_clk
-uart_i2c_usb_sel\[1\]
-uart_i2c_usb_sel\[0\]
-wbd_int_rst_n
+
diff --git a/openlane/wb_interconnect/base.sdc b/openlane/wb_interconnect/base.sdc
index 0f6fb06..37358bb 100644
--- a/openlane/wb_interconnect/base.sdc
+++ b/openlane/wb_interconnect/base.sdc
@@ -7,14 +7,19 @@
# Timing Constraints
###############################################################################
create_clock -name clk_i -period 10.0000 [get_ports {clk_i}]
-set_clock_uncertainty -rise_from [get_clocks {clk_i}] -rise_to [get_clocks {clk_i}] -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {clk_i}] -rise_to [get_clocks {clk_i}] -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {clk_i}] -fall_to [get_clocks {clk_i}] -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {clk_i}] -fall_to [get_clocks {clk_i}] -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {clk_i}] -rise_to [get_clocks {clk_i}] -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {clk_i}] -rise_to [get_clocks {clk_i}] -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {clk_i}] -fall_to [get_clocks {clk_i}] -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {clk_i}] -fall_to [get_clocks {clk_i}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {clk_i}] -rise_to [get_clocks {clk_i}] -hold 0.2500
+set_clock_uncertainty -rise_from [get_clocks {clk_i}] -rise_to [get_clocks {clk_i}] -setup 0.2500
+set_clock_uncertainty -rise_from [get_clocks {clk_i}] -fall_to [get_clocks {clk_i}] -hold 0.2500
+set_clock_uncertainty -rise_from [get_clocks {clk_i}] -fall_to [get_clocks {clk_i}] -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {clk_i}] -rise_to [get_clocks {clk_i}] -hold 0.2500
+set_clock_uncertainty -fall_from [get_clocks {clk_i}] -rise_to [get_clocks {clk_i}] -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {clk_i}] -fall_to [get_clocks {clk_i}] -hold 0.2500
+set_clock_uncertainty -fall_from [get_clocks {clk_i}] -fall_to [get_clocks {clk_i}] -setup 0.2500
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
#Clock Skew adjustment
set_case_analysis 0 [get_ports {cfg_cska_wi[0]}]
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index 8fa3187..fc3e712 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl
@@ -43,6 +43,11 @@
"
set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore/scr1/src/includes $script_dir/../../verilog/rtl/sdram_ctrl/src/defs ]
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+
+set ::env(SYNTH_PARAMS) "CH_CLK_WD 8,\
+ CH_DATA_WD 137 \
+ "
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
set ::env(SDC_FILE) "$script_dir/base.sdc"
@@ -60,7 +65,7 @@
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 2200 150"
+set ::env(DIE_AREA) "0 0 160 2500"
# If you're going to use multiple power domains, then keep this disabled.
diff --git a/openlane/wb_interconnect/interactive.tcl b/openlane/wb_interconnect/interactive.tcl
new file mode 100644
index 0000000..b44b517
--- /dev/null
+++ b/openlane/wb_interconnect/interactive.tcl
@@ -0,0 +1,219 @@
+#!/usr/bin/tclsh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+# Copyright 2020 Efabless Corporation
+# Copyright 2020 Sylvain Munaut
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+package require openlane;
+
+
+proc run_placement_step {args} {
+ # set pdndef_dirname [file dirname $::env(pdn_tmp_file_tag).def]
+ # set pdndef [lindex [glob $pdndef_dirname/*pdn*] 0]
+ # set_def $pdndef
+ if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
+ set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
+ }
+
+ run_placement
+}
+
+proc run_cts_step {args} {
+ # set_def $::env(opendp_result_file_tag).def
+ if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
+ set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
+ }
+
+ run_cts
+ run_resizer_timing
+}
+
+proc run_routing_step {args} {
+ # set resizerdef_dirname [file dirname $::env(resizer_tmp_file_tag)_timing.def]
+ # set resizerdef [lindex [glob $resizerdef_dirname/*resizer*] 0]
+ # set_def $resizerdef
+ if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
+ set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
+ }
+ run_routing
+}
+
+proc run_diode_insertion_2_5_step {args} {
+ # set_def $::env(tritonRoute_result_file_tag).def
+ if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
+ set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
+ }
+ if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
+ run_antenna_check
+ heal_antenna_violators; # modifies the routed DEF
+ }
+
+}
+
+proc run_power_pins_insertion_step {args} {
+ # set_def $::env(tritonRoute_result_file_tag).def
+ if { ! [ info exists ::env(POWER_PINS_INSERTION_CURRENT_DEF) ] } {
+ set ::env(POWER_PINS_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(POWER_PINS_INSERTION_CURRENT_DEF)
+ }
+ if { $::env(LVS_INSERT_POWER_PINS) } {
+ write_powered_verilog
+ set_netlist $::env(lvs_result_file_tag).powered.v
+ }
+
+}
+
+proc run_lvs_step {{ lvs_enabled 1 }} {
+ # set_def $::env(tritonRoute_result_file_tag).def
+ if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
+ set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
+ }
+ if { $lvs_enabled } {
+ run_magic_spice_export
+ run_lvs; # requires run_magic_spice_export
+ }
+
+}
+
+proc run_drc_step {{ drc_enabled 1 }} {
+ if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
+ set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
+ }
+ if { $drc_enabled } {
+ run_magic_drc
+ run_klayout_drc
+ }
+}
+
+proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
+ if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
+ set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
+ }
+ if { $antenna_check_enabled } {
+ run_antenna_check
+ }
+}
+
+proc run_flow {args} {
+ set script_dir [file dirname [file normalize [info script]]]
+
+ set options {
+ {-design required}
+ {-save_path optional}
+ {-no_lvs optional}
+ {-no_drc optional}
+ {-no_antennacheck optional}
+ }
+ set flags {-save}
+ parse_key_args "run_flow" args arg_values $options flags_map $flags -no_consume
+
+ prep {*}$args
+
+ set LVS_ENABLED 1
+ set DRC_ENABLED 0
+ set ANTENNACHECK_ENABLED 1
+
+ set steps [dict create "synthesis" {run_synthesis "" } \
+ "floorplan" {run_floorplan ""} \
+ "placement" {run_placement_step ""} \
+ "cts" {run_cts_step ""} \
+ "routing" {run_routing_step ""}\
+ "diode_insertion" {run_diode_insertion_2_5_step ""} \
+ "power_pins_insertion" {run_power_pins_insertion_step ""} \
+ "gds_magic" {run_magic ""} \
+ "gds_drc_klayout" {run_klayout ""} \
+ "gds_xor_klayout" {run_klayout_gds_xor ""} \
+ "lvs" "run_lvs_step $LVS_ENABLED" \
+ "drc" "run_drc_step $DRC_ENABLED" \
+ "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \
+ "cvc" {run_lef_cvc}
+ ]
+
+ set_if_unset arg_values(-to) "cvc";
+
+ if { [info exists ::env(CURRENT_STEP) ] } {
+ puts "\[INFO\]:Picking up where last execution left off"
+ puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)]
+ } else {
+ set ::env(CURRENT_STEP) "synthesis";
+ }
+ set_if_unset arg_values(-from) $::env(CURRENT_STEP);
+ set exe 0;
+ dict for {step_name step_exe} $steps {
+ if { [ string equal $arg_values(-from) $step_name ] } {
+ set exe 1;
+ }
+
+ if { $exe } {
+ # For when it fails
+ set ::env(CURRENT_STEP) $step_name
+ [lindex $step_exe 0] [lindex $step_exe 1] ;
+ }
+
+ if { [ string equal $arg_values(-to) $step_name ] } {
+ set exe 0:
+ break;
+ }
+
+ }
+
+ # for when it resumes
+ set steps_as_list [dict keys $steps]
+ set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
+ set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
+
+ if { [info exists flags_map(-save) ] } {
+ if { ! [info exists arg_values(-save_path)] } {
+ set arg_values(-save_path) ""
+ }
+ save_views -lef_path $::env(magic_result_file_tag).lef \
+ -def_path $::env(CURRENT_DEF) \
+ -gds_path $::env(magic_result_file_tag).gds \
+ -mag_path $::env(magic_result_file_tag).mag \
+ -maglef_path $::env(magic_result_file_tag).lef.mag \
+ -spice_path $::env(magic_result_file_tag).spice \
+ -spef_path $::env(CURRENT_SPEF) \
+ -verilog_path $::env(CURRENT_NETLIST) \
+ -save_path $arg_values(-save_path) \
+ -tag $::env(RUN_TAG)
+ }
+
+
+ calc_total_runtime
+ save_state
+ generate_final_summary_report
+
+ check_timing_violations
+
+ puts_success "Flow Completed Without Fatal Errors."
+
+}
+
+run_flow {*}$argv
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg
index fdc7903..d2855e3 100644
--- a/openlane/wb_interconnect/pin_order.cfg
+++ b/openlane/wb_interconnect/pin_order.cfg
@@ -2,19 +2,66 @@
#MANUAL_PLACE
-#E
-cfg_cska_wi\[3\] 000 0
+#S
+rst_n 000 0 2
+boot_remap\[3\]
+boot_remap\[2\]
+boot_remap\[1\]
+boot_remap\[0\]
+ch_data_in\[35\]
+ch_data_in\[34\]
+ch_data_in\[33\]
+ch_data_in\[32\]
+ch_data_in\[31\]
+ch_data_in\[30\]
+ch_data_in\[29\]
+ch_data_in\[28\]
+ch_data_in\[27\]
+ch_data_in\[26\]
+ch_data_in\[25\]
+ch_data_in\[24\]
+ch_data_in\[23\]
+ch_data_in\[22\]
+ch_data_in\[21\]
+ch_data_in\[20\]
+ch_data_in\[19\]
+ch_data_in\[18\]
+ch_data_in\[17\]
+ch_data_in\[16\]
+ch_data_in\[15\]
+ch_data_in\[14\]
+ch_data_in\[13\]
+ch_data_in\[12\]
+ch_data_in\[11\]
+ch_data_in\[10\]
+ch_data_in\[9\]
+ch_data_in\[8\]
+ch_data_in\[7\]
+ch_data_in\[6\]
+ch_data_in\[5\]
+ch_data_in\[4\]
+ch_data_in\[3\]
+ch_data_in\[2\]
+ch_data_in\[1\]
+ch_data_in\[0\]
+cfg_cska_wi\[3\]
cfg_cska_wi\[2\]
cfg_cska_wi\[1\]
cfg_cska_wi\[0\]
+ch_clk_in\[7\]
+ch_clk_in\[6\]
+ch_clk_in\[5\]
+ch_clk_in\[4\]
+ch_clk_in\[3\]
+ch_clk_in\[2\]
+ch_clk_in\[1\]
+ch_clk_in\[0\]
wbd_clk_int
wbd_clk_wi
clk_i
-rst_n
-#S
-m0_wbd_stb_i 0000 0 2
+m0_wbd_stb_i 050 0 2
m0_wbd_we_i
m0_wbd_adr_i\[31\]
m0_wbd_adr_i\[30\]
@@ -122,7 +169,65 @@
-m1_wbd_stb_i 200 0 2
+#W
+ch_data_out\[84\] 0000 0 2
+ch_data_out\[83\]
+ch_data_out\[82\]
+ch_data_out\[81\]
+ch_data_out\[80\]
+ch_data_out\[79\]
+ch_data_out\[78\]
+ch_data_out\[77\]
+ch_data_out\[76\]
+ch_data_out\[75\]
+ch_data_out\[74\]
+ch_data_out\[73\]
+ch_data_out\[72\]
+ch_data_out\[71\]
+ch_data_out\[70\]
+ch_data_out\[69\]
+ch_data_out\[68\]
+ch_data_out\[67\]
+ch_data_out\[66\]
+ch_data_out\[65\]
+ch_data_out\[64\]
+ch_data_out\[63\]
+ch_data_out\[62\]
+ch_data_out\[61\]
+ch_data_out\[60\]
+ch_data_out\[59\]
+ch_data_out\[58\]
+ch_data_out\[57\]
+ch_data_out\[56\]
+ch_data_out\[55\]
+ch_data_out\[54\]
+ch_data_out\[53\]
+ch_data_out\[52\]
+ch_data_out\[51\]
+ch_data_out\[50\]
+ch_data_out\[49\]
+ch_data_out\[48\]
+ch_data_out\[47\]
+ch_data_out\[46\]
+ch_data_out\[45\]
+ch_data_out\[44\]
+ch_data_out\[43\]
+ch_data_out\[42\]
+ch_data_out\[41\]
+ch_data_out\[40\]
+ch_data_out\[39\]
+ch_data_out\[38\]
+ch_data_out\[37\]
+ch_data_out\[36\]
+
+ch_data_out\[3\]
+ch_data_out\[2\]
+ch_data_out\[1\]
+ch_data_out\[0\]
+
+ch_clk_out\[0\]
+
+m1_wbd_stb_i 0150 0 2
m1_wbd_we_i
m1_wbd_adr_i\[31\]
m1_wbd_adr_i\[30\]
@@ -228,7 +333,7 @@
m1_wbd_err_o
m1_wbd_cyc_i
-m2_wbd_stb_i 0700 0 2
+m2_wbd_stb_i 0350 0 2
m2_wbd_we_i
m2_wbd_adr_i\[31\]
m2_wbd_adr_i\[30\]
@@ -332,10 +437,21 @@
m2_wbd_dat_o\[0\]
m2_wbd_ack_o
m2_wbd_err_o
-m2_wbd_cyc_i
+m2_wbd_cyc_i
-s3_wbd_stb_o 1900 0 2
+
+ch_data_out\[23\] 600 0 2
+ch_data_out\[22\]
+ch_data_out\[21\]
+ch_data_out\[20\]
+ch_clk_out\[4\]
+
+s3_wbd_cyc_o 625 0 2
+s3_wbd_stb_o
s3_wbd_we_o
+s3_wbd_adr_o\[10\]
+s3_wbd_adr_o\[9\]
+s3_wbd_adr_o\[8\]
s3_wbd_adr_o\[7\]
s3_wbd_adr_o\[6\]
s3_wbd_adr_o\[5\]
@@ -344,32 +460,28 @@
s3_wbd_adr_o\[2\]
s3_wbd_adr_o\[1\]
s3_wbd_adr_o\[0\]
-s3_wbd_sel_o\[3\]
-s3_wbd_sel_o\[2\]
-s3_wbd_sel_o\[1\]
-s3_wbd_sel_o\[0\]
-s3_wbd_dat_o\[31\]
-s3_wbd_dat_o\[30\]
-s3_wbd_dat_o\[29\]
-s3_wbd_dat_o\[28\]
-s3_wbd_dat_o\[27\]
-s3_wbd_dat_o\[26\]
-s3_wbd_dat_o\[25\]
-s3_wbd_dat_o\[24\]
-s3_wbd_dat_o\[23\]
-s3_wbd_dat_o\[22\]
-s3_wbd_dat_o\[21\]
-s3_wbd_dat_o\[20\]
-s3_wbd_dat_o\[19\]
-s3_wbd_dat_o\[18\]
-s3_wbd_dat_o\[17\]
-s3_wbd_dat_o\[16\]
-s3_wbd_dat_o\[15\]
-s3_wbd_dat_o\[14\]
-s3_wbd_dat_o\[13\]
-s3_wbd_dat_o\[12\]
-s3_wbd_dat_o\[11\]
-s3_wbd_dat_o\[10\]
+s3_wbd_dat_o\[31\]
+s3_wbd_dat_o\[30\]
+s3_wbd_dat_o\[29\]
+s3_wbd_dat_o\[28\]
+s3_wbd_dat_o\[27\]
+s3_wbd_dat_o\[26\]
+s3_wbd_dat_o\[25\]
+s3_wbd_dat_o\[24\]
+s3_wbd_dat_o\[23\]
+s3_wbd_dat_o\[22\]
+s3_wbd_dat_o\[21\]
+s3_wbd_dat_o\[20\]
+s3_wbd_dat_o\[19\]
+s3_wbd_dat_o\[18\]
+s3_wbd_dat_o\[17\]
+s3_wbd_dat_o\[16\]
+s3_wbd_dat_o\[15\]
+s3_wbd_dat_o\[14\]
+s3_wbd_dat_o\[13\]
+s3_wbd_dat_o\[12\]
+s3_wbd_dat_o\[11\]
+s3_wbd_dat_o\[10\]
s3_wbd_dat_o\[9\]
s3_wbd_dat_o\[8\]
s3_wbd_dat_o\[7\]
@@ -380,28 +492,32 @@
s3_wbd_dat_o\[2\]
s3_wbd_dat_o\[1\]
s3_wbd_dat_o\[0\]
-s3_wbd_dat_i\[31\]
-s3_wbd_dat_i\[30\]
-s3_wbd_dat_i\[29\]
-s3_wbd_dat_i\[28\]
-s3_wbd_dat_i\[27\]
-s3_wbd_dat_i\[26\]
-s3_wbd_dat_i\[25\]
-s3_wbd_dat_i\[24\]
-s3_wbd_dat_i\[23\]
-s3_wbd_dat_i\[22\]
-s3_wbd_dat_i\[21\]
-s3_wbd_dat_i\[20\]
-s3_wbd_dat_i\[19\]
-s3_wbd_dat_i\[18\]
-s3_wbd_dat_i\[17\]
-s3_wbd_dat_i\[16\]
-s3_wbd_dat_i\[15\]
-s3_wbd_dat_i\[14\]
-s3_wbd_dat_i\[13\]
-s3_wbd_dat_i\[12\]
-s3_wbd_dat_i\[11\]
-s3_wbd_dat_i\[10\]
+s3_wbd_sel_o\[3\]
+s3_wbd_sel_o\[2\]
+s3_wbd_sel_o\[1\]
+s3_wbd_sel_o\[0\]
+s3_wbd_dat_i\[31\]
+s3_wbd_dat_i\[30\]
+s3_wbd_dat_i\[29\]
+s3_wbd_dat_i\[28\]
+s3_wbd_dat_i\[27\]
+s3_wbd_dat_i\[26\]
+s3_wbd_dat_i\[25\]
+s3_wbd_dat_i\[24\]
+s3_wbd_dat_i\[23\]
+s3_wbd_dat_i\[22\]
+s3_wbd_dat_i\[21\]
+s3_wbd_dat_i\[20\]
+s3_wbd_dat_i\[19\]
+s3_wbd_dat_i\[18\]
+s3_wbd_dat_i\[17\]
+s3_wbd_dat_i\[16\]
+s3_wbd_dat_i\[15\]
+s3_wbd_dat_i\[14\]
+s3_wbd_dat_i\[13\]
+s3_wbd_dat_i\[12\]
+s3_wbd_dat_i\[11\]
+s3_wbd_dat_i\[10\]
s3_wbd_dat_i\[9\]
s3_wbd_dat_i\[8\]
s3_wbd_dat_i\[7\]
@@ -413,10 +529,351 @@
s3_wbd_dat_i\[1\]
s3_wbd_dat_i\[0\]
s3_wbd_ack_i
-s3_wbd_cyc_o
-#N
-s0_wbd_stb_o 0000 0 2
+ch_data_in\[97\] 750 0 2
+ch_data_in\[96\]
+ch_data_in\[95\]
+ch_data_in\[94\]
+ch_data_in\[93\]
+ch_data_in\[92\]
+ch_data_in\[91\]
+ch_data_in\[90\]
+
+ch_data_out\[89\]
+ch_data_out\[88\]
+ch_data_out\[87\]
+ch_data_out\[86\]
+ch_data_out\[85\]
+
+
+ch_data_out\[27\] 1150 0 2
+ch_data_out\[26\]
+ch_data_out\[25\]
+ch_data_out\[24\]
+ch_clk_out\[5\]
+
+s4_wbd_cyc_o 1175 0 2
+s4_wbd_stb_o
+s4_wbd_we_o
+s4_wbd_adr_o\[10\]
+s4_wbd_adr_o\[9\]
+s4_wbd_adr_o\[8\]
+s4_wbd_adr_o\[7\]
+s4_wbd_adr_o\[6\]
+s4_wbd_adr_o\[5\]
+s4_wbd_adr_o\[4\]
+s4_wbd_adr_o\[3\]
+s4_wbd_adr_o\[2\]
+s4_wbd_adr_o\[1\]
+s4_wbd_adr_o\[0\]
+s4_wbd_dat_o\[31\]
+s4_wbd_dat_o\[30\]
+s4_wbd_dat_o\[29\]
+s4_wbd_dat_o\[28\]
+s4_wbd_dat_o\[27\]
+s4_wbd_dat_o\[26\]
+s4_wbd_dat_o\[25\]
+s4_wbd_dat_o\[24\]
+s4_wbd_dat_o\[23\]
+s4_wbd_dat_o\[22\]
+s4_wbd_dat_o\[21\]
+s4_wbd_dat_o\[20\]
+s4_wbd_dat_o\[19\]
+s4_wbd_dat_o\[18\]
+s4_wbd_dat_o\[17\]
+s4_wbd_dat_o\[16\]
+s4_wbd_dat_o\[15\]
+s4_wbd_dat_o\[14\]
+s4_wbd_dat_o\[13\]
+s4_wbd_dat_o\[12\]
+s4_wbd_dat_o\[11\]
+s4_wbd_dat_o\[10\]
+s4_wbd_dat_o\[9\]
+s4_wbd_dat_o\[8\]
+s4_wbd_dat_o\[7\]
+s4_wbd_dat_o\[6\]
+s4_wbd_dat_o\[5\]
+s4_wbd_dat_o\[4\]
+s4_wbd_dat_o\[3\]
+s4_wbd_dat_o\[2\]
+s4_wbd_dat_o\[1\]
+s4_wbd_dat_o\[0\]
+s4_wbd_sel_o\[3\]
+s4_wbd_sel_o\[2\]
+s4_wbd_sel_o\[1\]
+s4_wbd_sel_o\[0\]
+s4_wbd_dat_i\[31\]
+s4_wbd_dat_i\[30\]
+s4_wbd_dat_i\[29\]
+s4_wbd_dat_i\[28\]
+s4_wbd_dat_i\[27\]
+s4_wbd_dat_i\[26\]
+s4_wbd_dat_i\[25\]
+s4_wbd_dat_i\[24\]
+s4_wbd_dat_i\[23\]
+s4_wbd_dat_i\[22\]
+s4_wbd_dat_i\[21\]
+s4_wbd_dat_i\[20\]
+s4_wbd_dat_i\[19\]
+s4_wbd_dat_i\[18\]
+s4_wbd_dat_i\[17\]
+s4_wbd_dat_i\[16\]
+s4_wbd_dat_i\[15\]
+s4_wbd_dat_i\[14\]
+s4_wbd_dat_i\[13\]
+s4_wbd_dat_i\[12\]
+s4_wbd_dat_i\[11\]
+s4_wbd_dat_i\[10\]
+s4_wbd_dat_i\[9\]
+s4_wbd_dat_i\[8\]
+s4_wbd_dat_i\[7\]
+s4_wbd_dat_i\[6\]
+s4_wbd_dat_i\[5\]
+s4_wbd_dat_i\[4\]
+s4_wbd_dat_i\[3\]
+s4_wbd_dat_i\[2\]
+s4_wbd_dat_i\[1\]
+s4_wbd_dat_i\[0\]
+s4_wbd_ack_i
+
+ch_data_in\[110\] 1300 0 2
+ch_data_in\[109\]
+ch_data_in\[108\]
+ch_data_in\[107\]
+ch_data_in\[106\]
+ch_data_in\[105\]
+ch_data_in\[104\]
+ch_data_in\[103\]
+
+ch_data_out\[102\]
+ch_data_out\[101\]
+ch_data_out\[100\]
+ch_data_out\[99\]
+ch_data_out\[98\]
+
+
+ch_data_out\[31\] 1700 0 2
+ch_data_out\[30\]
+ch_data_out\[29\]
+ch_data_out\[28\]
+ch_clk_out\[6\]
+
+s5_wbd_cyc_o 1725 0 2
+s5_wbd_stb_o
+s5_wbd_we_o
+s5_wbd_adr_o\[10\]
+s5_wbd_adr_o\[9\]
+s5_wbd_adr_o\[8\]
+s5_wbd_adr_o\[7\]
+s5_wbd_adr_o\[6\]
+s5_wbd_adr_o\[5\]
+s5_wbd_adr_o\[4\]
+s5_wbd_adr_o\[3\]
+s5_wbd_adr_o\[2\]
+s5_wbd_adr_o\[1\]
+s5_wbd_adr_o\[0\]
+s5_wbd_dat_o\[31\]
+s5_wbd_dat_o\[30\]
+s5_wbd_dat_o\[29\]
+s5_wbd_dat_o\[28\]
+s5_wbd_dat_o\[27\]
+s5_wbd_dat_o\[26\]
+s5_wbd_dat_o\[25\]
+s5_wbd_dat_o\[24\]
+s5_wbd_dat_o\[23\]
+s5_wbd_dat_o\[22\]
+s5_wbd_dat_o\[21\]
+s5_wbd_dat_o\[20\]
+s5_wbd_dat_o\[19\]
+s5_wbd_dat_o\[18\]
+s5_wbd_dat_o\[17\]
+s5_wbd_dat_o\[16\]
+s5_wbd_dat_o\[15\]
+s5_wbd_dat_o\[14\]
+s5_wbd_dat_o\[13\]
+s5_wbd_dat_o\[12\]
+s5_wbd_dat_o\[11\]
+s5_wbd_dat_o\[10\]
+s5_wbd_dat_o\[9\]
+s5_wbd_dat_o\[8\]
+s5_wbd_dat_o\[7\]
+s5_wbd_dat_o\[6\]
+s5_wbd_dat_o\[5\]
+s5_wbd_dat_o\[4\]
+s5_wbd_dat_o\[3\]
+s5_wbd_dat_o\[2\]
+s5_wbd_dat_o\[1\]
+s5_wbd_dat_o\[0\]
+s5_wbd_sel_o\[3\]
+s5_wbd_sel_o\[2\]
+s5_wbd_sel_o\[1\]
+s5_wbd_sel_o\[0\]
+s5_wbd_dat_i\[31\]
+s5_wbd_dat_i\[30\]
+s5_wbd_dat_i\[29\]
+s5_wbd_dat_i\[28\]
+s5_wbd_dat_i\[27\]
+s5_wbd_dat_i\[26\]
+s5_wbd_dat_i\[25\]
+s5_wbd_dat_i\[24\]
+s5_wbd_dat_i\[23\]
+s5_wbd_dat_i\[22\]
+s5_wbd_dat_i\[21\]
+s5_wbd_dat_i\[20\]
+s5_wbd_dat_i\[19\]
+s5_wbd_dat_i\[18\]
+s5_wbd_dat_i\[17\]
+s5_wbd_dat_i\[16\]
+s5_wbd_dat_i\[15\]
+s5_wbd_dat_i\[14\]
+s5_wbd_dat_i\[13\]
+s5_wbd_dat_i\[12\]
+s5_wbd_dat_i\[11\]
+s5_wbd_dat_i\[10\]
+s5_wbd_dat_i\[9\]
+s5_wbd_dat_i\[8\]
+s5_wbd_dat_i\[7\]
+s5_wbd_dat_i\[6\]
+s5_wbd_dat_i\[5\]
+s5_wbd_dat_i\[4\]
+s5_wbd_dat_i\[3\]
+s5_wbd_dat_i\[2\]
+s5_wbd_dat_i\[1\]
+s5_wbd_dat_i\[0\]
+s5_wbd_ack_i
+
+ch_data_in\[123\] 1850 0 2
+ch_data_in\[122\]
+ch_data_in\[121\]
+ch_data_in\[120\]
+ch_data_in\[119\]
+ch_data_in\[118\]
+ch_data_in\[117\]
+ch_data_in\[116\]
+
+ch_data_out\[115\]
+ch_data_out\[114\]
+ch_data_out\[113\]
+ch_data_out\[112\]
+ch_data_out\[111\]
+
+ch_data_out\[35\] 2250 0 2
+ch_data_out\[34\]
+ch_data_out\[33\]
+ch_data_out\[32\]
+ch_clk_out\[7\]
+
+s6_wbd_cyc_o 2275 0 2
+s6_wbd_stb_o
+s6_wbd_we_o
+s6_wbd_adr_o\[10\]
+s6_wbd_adr_o\[9\]
+s6_wbd_adr_o\[8\]
+s6_wbd_adr_o\[7\]
+s6_wbd_adr_o\[6\]
+s6_wbd_adr_o\[5\]
+s6_wbd_adr_o\[4\]
+s6_wbd_adr_o\[3\]
+s6_wbd_adr_o\[2\]
+s6_wbd_adr_o\[1\]
+s6_wbd_adr_o\[0\]
+s6_wbd_dat_o\[31\]
+s6_wbd_dat_o\[30\]
+s6_wbd_dat_o\[29\]
+s6_wbd_dat_o\[28\]
+s6_wbd_dat_o\[27\]
+s6_wbd_dat_o\[26\]
+s6_wbd_dat_o\[25\]
+s6_wbd_dat_o\[24\]
+s6_wbd_dat_o\[23\]
+s6_wbd_dat_o\[22\]
+s6_wbd_dat_o\[21\]
+s6_wbd_dat_o\[20\]
+s6_wbd_dat_o\[19\]
+s6_wbd_dat_o\[18\]
+s6_wbd_dat_o\[17\]
+s6_wbd_dat_o\[16\]
+s6_wbd_dat_o\[15\]
+s6_wbd_dat_o\[14\]
+s6_wbd_dat_o\[13\]
+s6_wbd_dat_o\[12\]
+s6_wbd_dat_o\[11\]
+s6_wbd_dat_o\[10\]
+s6_wbd_dat_o\[9\]
+s6_wbd_dat_o\[8\]
+s6_wbd_dat_o\[7\]
+s6_wbd_dat_o\[6\]
+s6_wbd_dat_o\[5\]
+s6_wbd_dat_o\[4\]
+s6_wbd_dat_o\[3\]
+s6_wbd_dat_o\[2\]
+s6_wbd_dat_o\[1\]
+s6_wbd_dat_o\[0\]
+s6_wbd_sel_o\[3\]
+s6_wbd_sel_o\[2\]
+s6_wbd_sel_o\[1\]
+s6_wbd_sel_o\[0\]
+s6_wbd_dat_i\[31\]
+s6_wbd_dat_i\[30\]
+s6_wbd_dat_i\[29\]
+s6_wbd_dat_i\[28\]
+s6_wbd_dat_i\[27\]
+s6_wbd_dat_i\[26\]
+s6_wbd_dat_i\[25\]
+s6_wbd_dat_i\[24\]
+s6_wbd_dat_i\[23\]
+s6_wbd_dat_i\[22\]
+s6_wbd_dat_i\[21\]
+s6_wbd_dat_i\[20\]
+s6_wbd_dat_i\[19\]
+s6_wbd_dat_i\[18\]
+s6_wbd_dat_i\[17\]
+s6_wbd_dat_i\[16\]
+s6_wbd_dat_i\[15\]
+s6_wbd_dat_i\[14\]
+s6_wbd_dat_i\[13\]
+s6_wbd_dat_i\[12\]
+s6_wbd_dat_i\[11\]
+s6_wbd_dat_i\[10\]
+s6_wbd_dat_i\[9\]
+s6_wbd_dat_i\[8\]
+s6_wbd_dat_i\[7\]
+s6_wbd_dat_i\[6\]
+s6_wbd_dat_i\[5\]
+s6_wbd_dat_i\[4\]
+s6_wbd_dat_i\[3\]
+s6_wbd_dat_i\[2\]
+s6_wbd_dat_i\[1\]
+s6_wbd_dat_i\[0\]
+s6_wbd_ack_i
+
+ch_data_in\[136\] 2400 0 2
+ch_data_in\[135\]
+ch_data_in\[134\]
+ch_data_in\[133\]
+ch_data_in\[132\]
+ch_data_in\[131\]
+ch_data_in\[130\]
+ch_data_in\[129\]
+
+ch_data_out\[128\]
+ch_data_out\[127\]
+ch_data_out\[126\]
+ch_data_out\[125\]
+ch_data_out\[124\]
+
+#E
+ch_data_out\[19\] 0000 0 2
+ch_data_out\[18\]
+ch_data_out\[17\]
+ch_data_out\[16\]
+ch_data_out\[7\]
+ch_data_out\[6\]
+ch_data_out\[5\]
+ch_data_out\[4\]
+ch_clk_out\[1\]
+
+s0_wbd_stb_o 0100 0 2
s0_wbd_we_o
s0_wbd_adr_o\[31\]
s0_wbd_adr_o\[30\]
@@ -521,32 +978,15 @@
s0_wbd_ack_i
s0_wbd_cyc_o
-s1_wbd_stb_o 0700 0 2
+
+ch_data_out\[11\] 0700 0 2
+ch_data_out\[10\]
+ch_data_out\[9\]
+ch_data_out\[8\]
+ch_clk_out\[2\]
+
+s1_wbd_stb_o 0800 0 2
s1_wbd_we_o
-s1_wbd_adr_o\[31\]
-s1_wbd_adr_o\[30\]
-s1_wbd_adr_o\[29\]
-s1_wbd_adr_o\[28\]
-s1_wbd_adr_o\[27\]
-s1_wbd_adr_o\[26\]
-s1_wbd_adr_o\[25\]
-s1_wbd_adr_o\[24\]
-s1_wbd_adr_o\[23\]
-s1_wbd_adr_o\[22\]
-s1_wbd_adr_o\[21\]
-s1_wbd_adr_o\[20\]
-s1_wbd_adr_o\[19\]
-s1_wbd_adr_o\[18\]
-s1_wbd_adr_o\[17\]
-s1_wbd_adr_o\[16\]
-s1_wbd_adr_o\[15\]
-s1_wbd_adr_o\[14\]
-s1_wbd_adr_o\[13\]
-s1_wbd_adr_o\[12\]
-s1_wbd_adr_o\[11\]
-s1_wbd_adr_o\[10\]
-s1_wbd_adr_o\[9\]
-s1_wbd_adr_o\[8\]
s1_wbd_adr_o\[7\]
s1_wbd_adr_o\[6\]
s1_wbd_adr_o\[5\]
@@ -624,9 +1064,122 @@
s1_wbd_dat_i\[1\]
s1_wbd_dat_i\[0\]
s1_wbd_ack_i
-s1_wbd_cyc_o
+s1_wbd_cyc_o
-s2_wbd_stb_o 1700 0 2
+ch_data_out\[136\] 1600 0 2
+ch_data_out\[135\]
+ch_data_out\[134\]
+ch_data_out\[133\]
+ch_data_out\[132\]
+ch_data_out\[131\]
+ch_data_out\[130\]
+ch_data_out\[129\]
+ch_data_in\[128\]
+ch_data_in\[127\]
+ch_data_in\[126\]
+ch_data_in\[125\]
+ch_data_in\[124\]
+
+ch_data_out\[123\]
+ch_data_out\[122\]
+ch_data_out\[121\]
+ch_data_out\[120\]
+ch_data_out\[119\]
+ch_data_out\[118\]
+ch_data_out\[117\]
+ch_data_out\[116\]
+ch_data_in\[115\]
+ch_data_in\[114\]
+ch_data_in\[113\]
+ch_data_in\[112\]
+ch_data_in\[111\]
+
+ch_data_out\[110\]
+ch_data_out\[109\]
+ch_data_out\[108\]
+ch_data_out\[107\]
+ch_data_out\[106\]
+ch_data_out\[105\]
+ch_data_out\[104\]
+ch_data_out\[103\]
+ch_data_in\[102\]
+ch_data_in\[101\]
+ch_data_in\[100\]
+ch_data_in\[99\]
+ch_data_in\[98\]
+
+
+ch_data_out\[97\]
+ch_data_out\[96\]
+ch_data_out\[95\]
+ch_data_out\[94\]
+ch_data_out\[93\]
+ch_data_out\[92\]
+ch_data_out\[91\]
+ch_data_out\[90\]
+ch_data_in\[89\]
+ch_data_in\[88\]
+ch_data_in\[87\]
+ch_data_in\[86\]
+ch_data_in\[85\]
+
+ch_data_in\[84\]
+ch_data_in\[83\]
+ch_data_in\[82\]
+ch_data_in\[81\]
+ch_data_in\[80\]
+ch_data_in\[79\]
+ch_data_in\[78\]
+ch_data_in\[77\]
+ch_data_in\[76\]
+ch_data_in\[75\]
+ch_data_in\[74\]
+ch_data_in\[73\]
+ch_data_in\[72\]
+ch_data_in\[71\]
+ch_data_in\[70\]
+ch_data_in\[69\]
+ch_data_in\[68\]
+ch_data_in\[67\]
+ch_data_in\[66\]
+ch_data_in\[65\]
+ch_data_in\[64\]
+ch_data_in\[63\]
+ch_data_in\[62\]
+ch_data_in\[61\]
+ch_data_in\[60\]
+ch_data_in\[59\]
+ch_data_in\[58\]
+ch_data_in\[57\]
+ch_data_in\[56\]
+ch_data_in\[55\]
+ch_data_in\[54\]
+ch_data_in\[53\]
+ch_data_in\[52\]
+ch_data_in\[51\]
+ch_data_in\[50\]
+ch_data_in\[49\]
+ch_data_in\[48\]
+ch_data_in\[47\]
+ch_data_in\[46\]
+ch_data_in\[45\]
+ch_data_in\[44\]
+ch_data_in\[43\]
+ch_data_in\[42\]
+ch_data_in\[41\]
+ch_data_in\[40\]
+ch_data_in\[39\]
+ch_data_in\[38\]
+ch_data_in\[37\]
+ch_data_in\[36\]
+
+ch_data_out\[15\]
+ch_data_out\[14\]
+ch_data_out\[13\]
+ch_data_out\[12\]
+ch_clk_out\[3\]
+
+s2_wbd_stb_o 1800 0 2
s2_wbd_we_o
s2_wbd_adr_o\[7\]
s2_wbd_adr_o\[6\]
@@ -636,32 +1189,32 @@
s2_wbd_adr_o\[2\]
s2_wbd_adr_o\[1\]
s2_wbd_adr_o\[0\]
-s2_wbd_sel_o\[3\]
-s2_wbd_sel_o\[2\]
-s2_wbd_sel_o\[1\]
-s2_wbd_sel_o\[0\]
-s2_wbd_dat_o\[31\]
-s2_wbd_dat_o\[30\]
-s2_wbd_dat_o\[29\]
-s2_wbd_dat_o\[28\]
-s2_wbd_dat_o\[27\]
-s2_wbd_dat_o\[26\]
-s2_wbd_dat_o\[25\]
-s2_wbd_dat_o\[24\]
-s2_wbd_dat_o\[23\]
-s2_wbd_dat_o\[22\]
-s2_wbd_dat_o\[21\]
-s2_wbd_dat_o\[20\]
-s2_wbd_dat_o\[19\]
-s2_wbd_dat_o\[18\]
-s2_wbd_dat_o\[17\]
-s2_wbd_dat_o\[16\]
-s2_wbd_dat_o\[15\]
-s2_wbd_dat_o\[14\]
-s2_wbd_dat_o\[13\]
-s2_wbd_dat_o\[12\]
-s2_wbd_dat_o\[11\]
-s2_wbd_dat_o\[10\]
+s2_wbd_sel_o\[3\]
+s2_wbd_sel_o\[2\]
+s2_wbd_sel_o\[1\]
+s2_wbd_sel_o\[0\]
+s2_wbd_dat_o\[31\]
+s2_wbd_dat_o\[30\]
+s2_wbd_dat_o\[29\]
+s2_wbd_dat_o\[28\]
+s2_wbd_dat_o\[27\]
+s2_wbd_dat_o\[26\]
+s2_wbd_dat_o\[25\]
+s2_wbd_dat_o\[24\]
+s2_wbd_dat_o\[23\]
+s2_wbd_dat_o\[22\]
+s2_wbd_dat_o\[21\]
+s2_wbd_dat_o\[20\]
+s2_wbd_dat_o\[19\]
+s2_wbd_dat_o\[18\]
+s2_wbd_dat_o\[17\]
+s2_wbd_dat_o\[16\]
+s2_wbd_dat_o\[15\]
+s2_wbd_dat_o\[14\]
+s2_wbd_dat_o\[13\]
+s2_wbd_dat_o\[12\]
+s2_wbd_dat_o\[11\]
+s2_wbd_dat_o\[10\]
s2_wbd_dat_o\[9\]
s2_wbd_dat_o\[8\]
s2_wbd_dat_o\[7\]
@@ -672,28 +1225,28 @@
s2_wbd_dat_o\[2\]
s2_wbd_dat_o\[1\]
s2_wbd_dat_o\[0\]
-s2_wbd_dat_i\[31\]
-s2_wbd_dat_i\[30\]
-s2_wbd_dat_i\[29\]
-s2_wbd_dat_i\[28\]
-s2_wbd_dat_i\[27\]
-s2_wbd_dat_i\[26\]
-s2_wbd_dat_i\[25\]
-s2_wbd_dat_i\[24\]
-s2_wbd_dat_i\[23\]
-s2_wbd_dat_i\[22\]
-s2_wbd_dat_i\[21\]
-s2_wbd_dat_i\[20\]
-s2_wbd_dat_i\[19\]
-s2_wbd_dat_i\[18\]
-s2_wbd_dat_i\[17\]
-s2_wbd_dat_i\[16\]
-s2_wbd_dat_i\[15\]
-s2_wbd_dat_i\[14\]
-s2_wbd_dat_i\[13\]
-s2_wbd_dat_i\[12\]
-s2_wbd_dat_i\[11\]
-s2_wbd_dat_i\[10\]
+s2_wbd_dat_i\[31\]
+s2_wbd_dat_i\[30\]
+s2_wbd_dat_i\[29\]
+s2_wbd_dat_i\[28\]
+s2_wbd_dat_i\[27\]
+s2_wbd_dat_i\[26\]
+s2_wbd_dat_i\[25\]
+s2_wbd_dat_i\[24\]
+s2_wbd_dat_i\[23\]
+s2_wbd_dat_i\[22\]
+s2_wbd_dat_i\[21\]
+s2_wbd_dat_i\[20\]
+s2_wbd_dat_i\[19\]
+s2_wbd_dat_i\[18\]
+s2_wbd_dat_i\[17\]
+s2_wbd_dat_i\[16\]
+s2_wbd_dat_i\[15\]
+s2_wbd_dat_i\[14\]
+s2_wbd_dat_i\[13\]
+s2_wbd_dat_i\[12\]
+s2_wbd_dat_i\[11\]
+s2_wbd_dat_i\[10\]
s2_wbd_dat_i\[9\]
s2_wbd_dat_i\[8\]
s2_wbd_dat_i\[7\]
diff --git a/signoff/mbist1/OPENLANE_VERSION b/signoff/mbist1/OPENLANE_VERSION
new file mode 100644
index 0000000..80c7664
--- /dev/null
+++ b/signoff/mbist1/OPENLANE_VERSION
@@ -0,0 +1 @@
+openlane N/A
diff --git a/signoff/mbist1/PDK_SOURCES b/signoff/mbist1/PDK_SOURCES
new file mode 100644
index 0000000..ca3684a
--- /dev/null
+++ b/signoff/mbist1/PDK_SOURCES
@@ -0,0 +1,6 @@
+-ne openlane
+8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b
+-ne skywater-pdk
+c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+-ne open_pdks
+14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
diff --git a/signoff/mbist1/final_summary_report.csv b/signoff/mbist1/final_summary_report.csv
new file mode 100644
index 0000000..c629a6b
--- /dev/null
+++ b/signoff/mbist1/final_summary_report.csv
@@ -0,0 +1,2 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/mbist1,mbist_top1,mbist1,flow_completed,0h4m45s,-1,35628.57142857143,0.07,17814.285714285714,21.94,556.2,1247,0,0,0,0,0,0,0,2,0,0,-1,83477,14731,-1.26,-1.78,-1,-1.69,-1,-20.05,-28.55,-1,-34.55,-1,51119249.0,14.63,28.27,23.81,8.18,0.47,-1,1182,2538,325,1649,0,0,0,1156,0,0,0,0,0,0,0,4,231,261,16,240,854,0,1094,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.35,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/pinmux/final_summary_report.csv b/signoff/pinmux/final_summary_report.csv
index b987a4d..bc9656d 100644
--- a/signoff/pinmux/final_summary_report.csv
+++ b/signoff/pinmux/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/pinmux,pinmux,pinmux,flow_completed,0h15m41s,-1,51320.0,0.2,25660.0,30.79,695.11,5132,0,0,0,0,0,0,-1,1,0,-1,-1,344100,53314,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,244475608.0,3.9,42.41,35.28,8.88,0.72,-1,3179,7916,495,5232,0,0,0,3823,0,0,0,0,0,0,0,4,1147,1169,12,278,2608,0,2886,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.35,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/pinmux,pinmux,pinmux,flow_completed,0h24m22s,-1,46327.27272727273,0.2475,23163.636363636364,27.14,711.29,5733,0,0,0,0,0,0,-1,1,0,-1,-1,426122,64960,0.0,-0.15,-1,0.0,-1,0.0,-4.48,-1,0.0,-1,294610837.0,2.99,41.93,31.98,13.81,0.52,-1,3584,8628,542,5585,0,0,0,4221,0,0,0,0,0,0,0,4,1345,1351,16,314,3259,0,3573,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.35,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/qspim/final_summary_report.csv b/signoff/qspim/final_summary_report.csv
index e6c0759..b8e1b13 100644
--- a/signoff/qspim/final_summary_report.csv
+++ b/signoff/qspim/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/qspim,qspim_top,qspim,flow_completed,0h8m55s,-1,64809.09090909091,0.22,32404.545454545456,37.66,681.69,7129,0,0,0,0,0,0,-1,1,0,-1,-1,318392,63729,0.0,-2.67,-1,0.0,-1,0.0,-819.01,-1,0.0,-1,216470544.0,12.44,34.1,35.23,1.44,0.85,-1,5836,8788,495,3446,0,0,0,6886,0,0,0,0,0,0,0,4,1766,2187,21,388,2940,0,3328,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.4,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/qspim,qspim_top,qspim,flow_completed,0h8m51s,-1,64727.27272727273,0.22,32363.636363636364,37.61,693.52,7120,0,0,0,0,0,0,-1,1,0,-1,-1,300881,62676,0.0,-4.31,-1,0.0,-1,0.0,-1599.52,-1,0.0,-1,205184440.0,6.18,33.84,32.42,0.61,1.6,-1,5860,8812,519,3470,0,0,0,6886,0,0,0,0,0,0,0,4,1764,2182,20,388,2940,0,3328,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.4,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/syntacore/final_summary_report.csv b/signoff/syntacore/final_summary_report.csv
index 5922abf..7f9e60e 100644
--- a/signoff/syntacore/final_summary_report.csv
+++ b/signoff/syntacore/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/syntacore,scr1_top_wb,syntacore,flow_completed,0h35m29s,-1,46440.0,0.9,23220.0,26.62,1189.66,20898,0,-1,-1,-1,-1,0,-1,1,0,-1,-1,1305802,210415,-1.28,-16.34,-1,0.0,-1,-1532.9,-19449.86,-1,0.0,-1,974068194.0,0.4,36.26,30.68,5.68,0.54,-1,18304,29655,1036,12280,0,0,0,21716,0,0,0,0,0,0,0,4,5144,5849,49,644,12312,0,12956,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.35,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/syntacore,scr1_top_wb,syntacore,flow_completed,1h33m29s,-1,55728.0,0.75,27864.0,32.5,1199.69,20898,0,-1,-1,-1,-1,0,-1,1,0,-1,-1,1799741,253072,-2.04,-16.74,-1,-0.12,-1,-2459.49,-21364.73,-1,-0.15,-1,1416553880.0,6.55,67.08,25.24,36.63,0.0,-1,18304,29655,1036,12280,0,0,0,21716,0,0,0,0,0,0,0,4,5144,5849,49,350,10177,0,10527,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.33,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/uart_i2cm_usb_spi/final_summary_report.csv b/signoff/uart_i2cm_usb_spi/final_summary_report.csv
index f174563..b018192 100644
--- a/signoff/uart_i2cm_usb_spi/final_summary_report.csv
+++ b/signoff/uart_i2cm_usb_spi/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/uart_i2cm_usb_spi,uart_i2c_usb_spi_top,uart_i2cm_usb_spi,flow_completed,0h18m42s,-1,64205.71428571429,0.35,32102.857142857145,37.64,817.74,11236,0,0,0,0,0,0,-1,1,0,-1,-1,448590,98997,-4.36,-4.77,-1,-4.64,-1,-136.52,-148.03,-1,-140.88,-1,266589420.0,0.0,31.08,30.38,1.28,0.32,-1,8583,12990,1537,5887,0,0,0,9761,0,0,0,0,0,0,0,4,2731,2697,24,498,4643,0,5141,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.45,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/uart_i2cm_usb_spi,uart_i2c_usb_spi_top,uart_i2cm_usb_spi,flow_completed,0h14m3s,-1,64045.71428571429,0.35,32022.857142857145,37.57,832.49,11208,0,0,0,0,0,0,-1,1,0,-1,-1,436470,97856,-4.53,-4.87,-1,-4.61,-1,-141.45,-152.51,-1,-139.04,-1,264189380.0,3.96,30.67,29.3,0.93,0.27,-1,8571,12978,1539,5889,0,0,0,9747,0,0,0,0,0,0,0,4,2731,2697,26,498,4643,0,5141,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.45,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 707b3cf..2298dac 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h16m37s,-1,1.5566625155666252,10.2784,0.7783312577833126,-1,525.17,8,0,0,0,0,0,0,-1,0,0,-1,-1,1352380,5198,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,50744.38,1.67,4.74,0.68,0.97,-1,164,1798,164,1798,0,0,0,8,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,140,140,0.55,0.0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h37m34s,-1,2.9187422166874217,10.2784,1.4593711083437109,-1,532.38,15,0,0,0,0,0,0,-1,0,0,-1,-1,1472939,10679,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,9849.37,4.62,3.23,0.53,0.52,-1,298,2697,298,2697,0,0,0,15,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,100,0.55,0.0,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv
index 835cf74..64e4de6 100644
--- a/signoff/wb_host/final_summary_report.csv
+++ b/signoff/wb_host/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_host,wb_host,wb_host,flow_completed,0h5m7s,-1,46400.0,0.12,23200.0,28.29,596.42,2784,0,0,0,0,0,0,-1,2,0,0,-1,158497,24726,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,123635068.0,1.13,33.63,28.63,3.38,0.03,-1,1375,3017,698,2338,0,0,0,1465,0,0,0,0,0,0,0,4,782,967,13,204,1560,0,1764,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/wb_host,wb_host,wb_host,flow_completed,0h6m16s,-1,63908.571428571435,0.0875,31954.285714285717,39.91,592.74,2796,0,0,0,0,0,0,0,1,0,0,-1,142732,25079,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,103335902.0,2.56,41.03,34.71,4.26,0.62,-1,1403,3046,726,2367,0,0,0,1466,0,0,0,0,0,0,0,4,783,970,13,166,1105,0,1271,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.41,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/wb_interconnect/final_summary_report.csv b/signoff/wb_interconnect/final_summary_report.csv
index b7fde79..ff1a200 100644
--- a/signoff/wb_interconnect/final_summary_report.csv
+++ b/signoff/wb_interconnect/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow_completed,0h6m21s,-1,7460.606060606059,0.33,3730.3030303030296,3.76,616.7,1231,0,-1,-1,-1,-1,0,0,1,0,-1,-1,444821,19265,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,389589929.0,1.18,42.09,8.8,21.99,0.19,-1,848,2750,173,2075,0,0,0,1169,0,0,0,0,0,0,0,4,435,509,7,94,4140,0,4234,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.5,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow_completed,0h6m50s,-1,9035.0,0.4,4517.5,3.86,674.82,1807,0,-1,-1,-1,-1,0,-1,1,0,-1,-1,690765,27420,0.0,0.0,-1,-0.07,-1,0.0,0.0,-1,-0.14,-1,611850677.0,26.99,15.84,53.48,1.44,22.81,-1,1268,3988,208,2928,0,0,0,1682,0,0,0,0,0,0,0,4,540,639,7,1822,5021,0,6843,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.5,0.0,sky130_fd_sc_hd,4,4
diff --git a/sta/scripts/caravel_timing.tcl b/sta/scripts/caravel_timing.tcl
new file mode 100644
index 0000000..695b0fa
--- /dev/null
+++ b/sta/scripts/caravel_timing.tcl
@@ -0,0 +1,188 @@
+
+ set ::env(USER_ROOT) "/home/dinesha/workarea/opencore/git/riscduino"
+ set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-4/caravel_openframe"
+ set ::env(PDK_ROOT) "/opt/pdk_mpw4"
+
+ read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
+ read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
+ read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib
+ read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib
+ read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib
+ read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_gpiov2_tt_tt_025C_1v80_3v30.lib
+ read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_hvc_wpad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_025C_1v80_3v30.lib
+ read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_100C_1v80_3v30.lib
+ read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_power_lvc_wpad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib
+ read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib
+ read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib
+ read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib
+ read_verilog $::env(CARAVEL_ROOT)/mgmt_core_wrapper/verilog/gl/mgmt_core.v
+ read_verilog $::env(CARAVEL_ROOT)/mgmt_core_wrapper/verilog/gl/DFFRAM.v
+ read_verilog $::env(CARAVEL_ROOT)/mgmt_core_wrapper/verilog/gl/mgmt_core_wrapper.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/caravel_clocking.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/digital_pll.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/housekeeping.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_logic_high.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_control_block.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_defaults_block.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_defaults_block_0403.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_defaults_block_1803.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mgmt_protect_hv.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mprj_logic_high.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mprj2_logic_high.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mgmt_protect.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/user_id_programming.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/xres_buf.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/spare_logic_block.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/chip_io.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/caravel.v
+
+ # User project netlist
+ read_verilog $::env(USER_ROOT)/verilog/gl/qspim.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/syntacore.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/uart_i2cm_usb_spi.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/wb_host.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/wb_interconnect.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/pinmux.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/mbist1.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/user_project_wrapper.v
+
+
+ link_design caravel
+
+ read_spef -path soc/DFFRAM_0 $::env(CARAVEL_ROOT)/mgmt_core_wrapper/spef/DFFRAM.spef
+ read_spef -path soc/core $::env(CARAVEL_ROOT)/mgmt_core_wrapper/spef/mgmt_core.spef
+ read_spef -path soc $::env(CARAVEL_ROOT)/mgmt_core_wrapper/spef/mgmt_core_wrapper.spef
+ read_spef -path padframe $::env(CARAVEL_ROOT)/spef/chip_io.spef
+ read_spef -path rstb_level $::env(CARAVEL_ROOT)/spef/xres_buf.spef
+ read_spef -path pll $::env(CARAVEL_ROOT)/spef/digital_pll.spef
+ read_spef -path housekeeping $::env(CARAVEL_ROOT)/spef/housekeeping.spef
+ read_spef -path mgmt_buffers/powergood_check $::env(CARAVEL_ROOT)/spef/mgmt_protect_hv.spef
+ read_spef -path mgmt_buffers/mprj_logic_high_inst $::env(CARAVEL_ROOT)/spef/mprj_logic_high.spef
+ read_spef -path mgmt_buffers/mprj2_logic_high_inst $::env(CARAVEL_ROOT)/spef/mprj2_logic_high.spef
+ read_spef -path clocking $::env(CARAVEL_ROOT)/spef/caravel_clocking.spef
+ read_spef -path mgmt_buffers $::env(CARAVEL_ROOT)/spef/mgmt_protect.spef
+ read_spef -path \gpio_control_bidir_1[0] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_bidir_1[1] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_bidir_2[1] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_bidir_2[2] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1[0] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1[10] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1[1] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1[2] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1[3] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1[4] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1[5] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1[6] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1[7] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1[8] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1[9] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1a[0] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1a[1] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1a[2] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1a[3] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1a[4] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1a[5] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[0] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[10] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[11] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[12] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[13] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[14] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[15] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[1] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[2] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[3] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[4] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[5] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[6] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[7] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[8] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[9] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path gpio_defaults_block_0 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_1803.spef
+ read_spef -path gpio_defaults_block_1 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_1803.spef
+ read_spef -path gpio_defaults_block_2 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef
+ read_spef -path gpio_defaults_block_3 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef
+ read_spef -path gpio_defaults_block_4 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef
+ read_spef -path gpio_defaults_block_5 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_6 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_7 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_8 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_9 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_10 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_11 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_12 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_13 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_14 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_15 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_16 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_17 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_18 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_19 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_20 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_21 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_22 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_23 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_24 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_25 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_26 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_27 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_28 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_29 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_30 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_31 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_32 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_33 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_34 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_35 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_36 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_37 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+
+ ## User Project Spef
+ read_spef -path mprj/u_mbist1 $::env(USER_ROOT)/spef/mbist_top1.spef
+ read_spef -path mprj/u_mbist2 $::env(USER_ROOT)/spef/mbist_top1.spef
+ read_spef -path mprj/u_mbist3 $::env(USER_ROOT)/spef/mbist_top1.spef
+ read_spef -path mprj/u_mbist4 $::env(USER_ROOT)/spef/mbist_top1.spef
+
+ read_spef -path mprj/u_riscv_top $::env(USER_ROOT)/spef/scr1_top_wb.spef
+ read_spef -path mprj/u_pinmux $::env(USER_ROOT)/spef/pinmux.spef
+ read_spef -path mprj/u_qspi_master $::env(USER_ROOT)/spef/qspim_top.spef
+ read_spef -path mprj/u_uart_i2c_usb_spi $::env(USER_ROOT)/spef/uart_i2c_usb_spi_top.spef
+ read_spef -path mprj/u_wb_host $::env(USER_ROOT)/spef/wb_host.spef
+ read_spef -path mprj/u_intercon $::env(USER_ROOT)/spef/wb_interconnect.spef
+ read_spef -path mprj $::env(USER_ROOT)/spef/user_project_wrapper.spef
+
+
+ read_sdc -echo ./sdc/caravel.sdc
+ check_setup -verbose > unconstraints.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50
+ report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50
+ report_worst_slack -max
+ report_worst_slack -min
+ report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -slack_max 0.18 -group_count 10
+ report_check_types -max_slew -max_capacitance -max_fanout -violators > slew.cap.fanout.vio.rpt
+
+ echo "Wishbone Interface Timing.................." > wb.max.rpt
+ echo "Wishbone Interface Timing.................." > wb.min.rpt
+ set wb_port [get_pins {mprj/wbs_adr_i[*]}]
+ set wb_port [concat $wb_port [get_pins {mprj/wbs_cyc_i}]]
+ set wb_port [concat $wb_port [get_pins {mprj/wbs_dat_i[*]}]]
+ set wb_port [concat $wb_port [get_pins {mprj/wbs_sel_i[*]}]]
+ set wb_port [concat $wb_port [get_pins {mprj/wbs_stb_i}]]
+ set wb_port [concat $wb_port [get_pins {mprj/wbs_we_i}]]
+ set wb_port [concat $wb_port [get_pins {mprj/wbs_ack_o}]]
+ set wb_port [concat $wb_port [get_pins {mprj/wbs_dat_o[*]}]]
+ foreach pin $wb_port {
+ echo "Wishbone Interface Timing for : [get_full_name $pin]" >> wb.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through $pin >> wb.max.rpt
+ }
+ foreach pin $wb_port {
+ echo "Wishbone Interface Timing for [get_full_name $pin]" >> wb.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin >> wb.min.rpt
+ }
+
diff --git a/sta/sdc/caravel.sdc b/sta/sdc/caravel.sdc
new file mode 100644
index 0000000..10f37d4
--- /dev/null
+++ b/sta/sdc/caravel.sdc
@@ -0,0 +1,257 @@
+set ::env(IO_PCT) "0.2"
+set ::env(SYNTH_MAX_FANOUT) "5"
+set ::env(SYNTH_CAP_LOAD) "1"
+set ::env(SYNTH_TIMING_DERATE) 0.05
+set ::env(SYNTH_CLOCK_SETUP_UNCERTAINITY) 0.25
+set ::env(SYNTH_CLOCK_HOLD_UNCERTAINITY) 0.25
+set ::env(SYNTH_CLOCK_TRANSITION) 0.15
+
+## MASTER CLOCKS
+create_clock [get_ports {"clock"} ] -name "clock" -period 25
+create_clock [get_pins clocking/user_clk ] -name "user_clk2" -period 25
+#create_clock [get_pins housekeeping/_8847_/X ] -name "csclk" -period 25
+#create_clock [get_pins clocking/pll_clk ] -name "pll_clk" -period 25
+#create_clock [get_pins clocking/pll_clk90 ] -name "pll_clk90" -period 25
+
+create_generated_clock -name wb_clk -add -source [get_ports {clock}] -master_clock [get_clocks clock] -divide_by 1 -comment {Wishbone User Clock} [get_pins mprj/wb_clk_i]
+create_clock -name wbs_clk_i -period 15.0000 [get_pins {mprj/u_wb_host/wbs_clk_out}]
+create_clock -name cpu_clk -period 20.0000 [get_pins {mprj/u_wb_host/cpu_clk}]
+create_clock -name rtc_clk -period 50.0000 [get_pins {mprj/u_wb_host/rtc_clk}]
+create_clock -name usb_clk -period 20.0000 [get_pins {mprj/u_wb_host/usb_clk}]
+create_clock -name line_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart_core.u_lineclk_buf.u_buf/X}]
+
+
+## Case analysis
+
+set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[0]}]
+set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[1]}]
+set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[2]}]
+set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[3]}]
+
+set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[0]}]
+set_case_analysis 1 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[1]}]
+set_case_analysis 1 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[2]}]
+set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[3]}]
+
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[0]}]
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[1]}]
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[2]}]
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[3]}]
+
+set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[0]}]
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[1]}]
+set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[2]}]
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[3]}]
+
+set_case_analysis 1 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[0]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[1]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[2]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[3]}]
+set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[0]}]
+set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[1]}]
+set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[2]}]
+set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[3]}]
+
+set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[0]}]
+set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[2]}]
+set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[1]}]
+set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[3]}]
+
+set_case_analysis 1 [get_pins {mprj/u_mbist1/cfg_cska_mbist[0]}]
+set_case_analysis 1 [get_pins {mprj/u_mbist1/cfg_cska_mbist[1]}]
+set_case_analysis 1 [get_pins {mprj/u_mbist1/cfg_cska_mbist[2]}]
+set_case_analysis 0 [get_pins {mprj/u_mbist1/cfg_cska_mbist[3]}]
+
+set_case_analysis 1 [get_pins {mprj/u_mbist2/cfg_cska_mbist[0]}]
+set_case_analysis 1 [get_pins {mprj/u_mbist2/cfg_cska_mbist[1]}]
+set_case_analysis 1 [get_pins {mprj/u_mbist2/cfg_cska_mbist[2]}]
+set_case_analysis 0 [get_pins {mprj/u_mbist2/cfg_cska_mbist[3]}]
+
+set_case_analysis 1 [get_pins {mprj/u_mbist3/cfg_cska_mbist[0]}]
+set_case_analysis 1 [get_pins {mprj/u_mbist3/cfg_cska_mbist[1]}]
+set_case_analysis 1 [get_pins {mprj/u_mbist3/cfg_cska_mbist[2]}]
+set_case_analysis 0 [get_pins {mprj/u_mbist3/cfg_cska_mbist[3]}]
+
+set_case_analysis 1 [get_pins {mprj/u_mbist4/cfg_cska_mbist[0]}]
+set_case_analysis 1 [get_pins {mprj/u_mbist4/cfg_cska_mbist[1]}]
+set_case_analysis 1 [get_pins {mprj/u_mbist4/cfg_cska_mbist[2]}]
+set_case_analysis 0 [get_pins {mprj/u_mbist4/cfg_cska_mbist[3]}]
+
+#disable clock gating check at static clock select pins
+set_false_path -through [get_pins mprj/u_wb_host/u_wbs_clk_sel.u_mux/S]
+
+set_propagated_clock [all_clocks]
+
+set_clock_groups -name async_clock -asynchronous \
+ -group [get_clocks {clock wb_clk}]\
+ -group [get_clocks {user_clk2}]\
+ -group [get_clocks {wbs_clk_i}]\
+ -group [get_clocks {cpu_clk}]\
+ -group [get_clocks {rtc_clk}]\
+ -group [get_clocks {usb_clk}]\
+ -group [get_clocks {line_clk}]\
+ -comment {Async Clock group}
+
+## INPUT/OUTPUT DELAYS
+set input_delay_value 1
+set output_delay_value [expr 25 * $::env(IO_PCT)]
+puts "\[INFO\]: Setting output delay to: $output_delay_value"
+puts "\[INFO\]: Setting input delay to: $input_delay_value"
+
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {gpio}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[0]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[1]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[2]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[3]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[4]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[5]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[6]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[7]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[8]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[9]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[10]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[11]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[12]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[13]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[14]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[15]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[16]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[17]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[18]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[19]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[20]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[21]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[22]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[23]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[24]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[25]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[26]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[27]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[28]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[29]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[30]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[31]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[32]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[33]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[34]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[35]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[36]}]
+set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[37]}]
+
+set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_csb}]
+set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_clk}]
+set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_io0}]
+set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_io1}]
+
+set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
+
+## Set system monitoring mux select to zero so that the clock/user_clk monitoring is disabled
+set_case_analysis 0 [get_pins housekeeping/_4449_/S]
+set_case_analysis 0 [get_pins housekeeping/_4450_/S]
+
+## FALSE PATHS (ASYNCHRONOUS INPUTS)
+set_false_path -from [get_ports {resetb}]
+set_false_path -from [get_ports mprj_io[*]]
+set_false_path -from [get_ports gpio]
+
+# TODO set this as parameter
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load $cap_load [all_outputs]
+
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
+puts "\[INFO\]: Setting clock setup uncertainity to: $::env(SYNTH_CLOCK_SETUP_UNCERTAINITY)"
+puts "\[INFO\]: Setting clock hold uncertainity to: $::env(SYNTH_CLOCK_HOLD_UNCERTAINITY)"
+set_clock_uncertainty -setup $::env(SYNTH_CLOCK_SETUP_UNCERTAINITY) [all_clocks]
+set_clock_uncertainty -setup $::env(SYNTH_CLOCK_HOLD_UNCERTAINITY) [all_clocks]
+
+
+#set_output_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_adr_i[*]}]
+#set_output_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_cyc_i}]
+#set_output_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_i[*]}]
+#set_output_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_sel_i[*]}]
+#set_output_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_stb_i}]
+#set_output_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_we_i}]
+#
+#set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_adr_i[*]}]
+#set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_cyc_i}]
+#set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_i[*]}]
+#set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_sel_i[*]}]
+#set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_stb_i}]
+#set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_we_i}]
+#
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_ack_o}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[0]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[10]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[11]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[12]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[13]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[14]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[15]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[16]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[17]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[18]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[19]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[1]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[20]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[21]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[22]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[23]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[24]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[25]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[26]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[27]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[28]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[29]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[2]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[30]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[31]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[3]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[4]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[5]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[6]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[7]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[8]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[9]}]
+#
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_ack_o}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[0]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[10]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[11]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[12]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[13]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[14]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[15]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[16]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[17]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[18]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[19]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[1]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[20]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[21]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[22]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[23]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[24]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[25]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[26]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[27]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[28]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[29]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[2]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[30]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[31]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[3]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[4]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[5]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[6]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[7]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[8]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[9]}]
+
+
+
+puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
+set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {clock}]
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index 91e4e9b..a91211b 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@
.SUFFIXES:
.SILENT: clean all
-PATTERNS = wb_port risc_boot user_risc_boot user_uart user_spi user_i2cm riscv_regress user_basic
+PATTERNS = wb_port risc_boot user_risc_boot user_uart user_spi user_i2cm riscv_regress user_basic user_mbist_test1 user_risc_soft_boot
all: ${PATTERNS}
for i in ${PATTERNS}; do \
diff --git a/verilog/dv/risc_boot/Makefile b/verilog/dv/risc_boot/Makefile
index c52a974..da3fb1e 100644
--- a/verilog/dv/risc_boot/Makefile
+++ b/verilog/dv/risc_boot/Makefile
@@ -14,6 +14,9 @@
#
# SPDX-License-Identifier: Apache-2.0
+## PDK
+PDK_PATH = $(PDK_ROOT)/sky130A
+
## Caravel Pointers
CARAVEL_ROOT ?= ../../../caravel
CARAVEL_PATH ?= $(CARAVEL_ROOT)
@@ -22,7 +25,6 @@
CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
-
## User Project Pointers
UPRJ_VERILOG_PATH ?= ../../../verilog
UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
@@ -32,17 +34,17 @@
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
+UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include
## SYNTACORE FIRMWARE
SYNTACORE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/rtl/syntacore/scr1/sim/tests/common
-GCC64_PREFIX?=riscv64-unknown-elf
-
## RISCV GCC
GCC_PATH?=/ef/apps/bin
GCC_PREFIX?=riscv32-unknown-elf
-PDK_PATH?=/ef/tech/SW/sky130A
+GCC64_PREFIX?=riscv64-unknown-elf
## Simulation mode: RTL/GL
+SIM_DEFINES = -DFUNCTIONAL -DSIM
SIM?=RTL
DUMP?=OFF
@@ -70,7 +72,7 @@
-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
-I $(UPRJ_BEHAVIOURAL_AGENTS) \
-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
- -I $(UPRJ_INCLUDE_PATH4) \
+ -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \
$< -o $@
else
iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
@@ -78,11 +80,11 @@
-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
-I $(UPRJ_BEHAVIOURAL_AGENTS) \
-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
- -I $(UPRJ_INCLUDE_PATH4) \
+ -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \
$< -o $@
endif
else
- iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+ iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
-I $(UPRJ_BEHAVIOURAL_AGENTS) \
@@ -101,7 +103,7 @@
sed -i 's/@10000000/@00000000/g' $@
%.bin: %.elf
- ${GCC64_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
# ---- Clean ----
diff --git a/verilog/dv/risc_boot/risc_boot.c b/verilog/dv/risc_boot/risc_boot.c
index 3921642..f00f3bb 100644
--- a/verilog/dv/risc_boot/risc_boot.c
+++ b/verilog/dv/risc_boot/risc_boot.c
@@ -23,22 +23,22 @@
#define reg_mprj_wbhost_reg0 (*(volatile uint32_t*)0x30800000)
-#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x30030000)
-#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x30030004)
-#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x30030008)
-#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x3003000C)
-#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x30030010)
-#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x30030014)
-#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x30030018)
-#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x3003001C)
-#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x30030020)
-#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x30030024)
-#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x30030028)
-#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x3003002C)
-#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x30030030)
-#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x30030034)
-#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30030038)
-#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3003003C)
+#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x30020000)
+#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x30020004)
+#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x30020008)
+#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x3002000C)
+#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x30020010)
+#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x30020014)
+#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x30020018)
+#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x3002001C)
+#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x30020020)
+#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x30020024)
+#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x30020028)
+#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x3002002C)
+#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x30020030)
+#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x30020034)
+#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30020038)
+#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3002003C)
#define reg_mprj_uart_reg0 (*(volatile uint32_t*)0x30010000)
#define reg_mprj_uart_reg1 (*(volatile uint32_t*)0x30010004)
diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v
index 45e7603..38144e8 100644
--- a/verilog/dv/risc_boot/risc_boot_tb.v
+++ b/verilog/dv/risc_boot/risc_boot_tb.v
@@ -339,150 +339,7 @@
`ifndef GL // Drive Power for Hold Fix Buf
// All standard cell need power hook-up for functionality work
- initial begin
- force uut.mprj.u_qspi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay1_sdio0.VPB =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay1_sdio0.VGND =VSS;
- force uut.mprj.u_qspi_master.u_delay1_sdio0.VNB = VSS;
- force uut.mprj.u_qspi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay2_sdio0.VPB =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay2_sdio0.VGND =VSS;
- force uut.mprj.u_qspi_master.u_delay2_sdio0.VNB = VSS;
- force uut.mprj.u_qspi_master.u_buf_sdio0.VPWR =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_buf_sdio0.VPB =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_buf_sdio0.VGND =VSS;
- force uut.mprj.u_qspi_master.u_buf_sdio0.VNB =VSS;
-
-
- force uut.mprj.u_qspi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay1_sdio1.VPB =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay1_sdio1.VGND =VSS;
- force uut.mprj.u_qspi_master.u_delay1_sdio1.VNB = VSS;
- force uut.mprj.u_qspi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay2_sdio1.VPB =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay2_sdio1.VGND =VSS;
- force uut.mprj.u_qspi_master.u_delay2_sdio1.VNB = VSS;
- force uut.mprj.u_qspi_master.u_buf_sdio1.VPWR =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_buf_sdio1.VPB =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_buf_sdio1.VGND =VSS;
- force uut.mprj.u_qspi_master.u_buf_sdio1.VNB =VSS;
-
- force uut.mprj.u_qspi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay1_sdio2.VPB =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay1_sdio2.VGND =VSS;
- force uut.mprj.u_qspi_master.u_delay1_sdio2.VNB = VSS;
- force uut.mprj.u_qspi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay2_sdio2.VPB =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay2_sdio2.VGND =VSS;
- force uut.mprj.u_qspi_master.u_delay2_sdio2.VNB = VSS;
- force uut.mprj.u_qspi_master.u_buf_sdio2.VPWR =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_buf_sdio2.VPB =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_buf_sdio2.VGND =VSS;
- force uut.mprj.u_qspi_master.u_buf_sdio2.VNB =VSS;
-
- force uut.mprj.u_qspi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay1_sdio3.VPB =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay1_sdio3.VGND =VSS;
- force uut.mprj.u_qspi_master.u_delay1_sdio3.VNB = VSS;
- force uut.mprj.u_qspi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay2_sdio3.VPB =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay2_sdio3.VGND =VSS;
- force uut.mprj.u_qspi_master.u_delay2_sdio3.VNB = VSS;
- force uut.mprj.u_qspi_master.u_buf_sdio3.VPWR =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_buf_sdio3.VPB =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_buf_sdio3.VGND =VSS;
- force uut.mprj.u_qspi_master.u_buf_sdio3.VNB =VSS;
-
- force uut.mprj.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
- force uut.mprj.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VPB =USER_VDD1V8;
- force uut.mprj.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VGND =VSS;
- force uut.mprj.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_wb_rst.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_wb_rst.VGND =VSS;
- force uut.mprj.u_wb_host.u_buf_wb_rst.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_buf_cpu_rst.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_cpu_rst.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_cpu_rst.VGND =VSS;
- force uut.mprj.u_wb_host.u_buf_cpu_rst.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_buf_qspim_rst.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_qspim_rst.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_qspim_rst.VGND =VSS;
- force uut.mprj.u_wb_host.u_buf_qspim_rst.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_buf_sspim_rst.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_sspim_rst.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_sspim_rst.VGND =VSS;
- force uut.mprj.u_wb_host.u_buf_sspim_rst.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_buf_uart_rst.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_uart_rst.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_uart_rst.VGND =VSS;
- force uut.mprj.u_wb_host.u_buf_uart_rst.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_buf_i2cm_rst.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_i2cm_rst.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_i2cm_rst.VGND =VSS;
- force uut.mprj.u_wb_host.u_buf_i2cm_rst.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_buf_usb_rst.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_usb_rst.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_usb_rst.VGND =VSS;
- force uut.mprj.u_wb_host.u_buf_usb_rst.VNB = VSS;
-
-
- force uut.mprj.u_wb_host.u_clkbuf_cpu.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_clkbuf_cpu.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_clkbuf_cpu.VGND =VSS;
- force uut.mprj.u_wb_host.u_clkbuf_cpu.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_clkbuf_rtc.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_clkbuf_rtc.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_clkbuf_rtc.VGND =VSS;
- force uut.mprj.u_wb_host.u_clkbuf_rtc.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_clkbuf_usb.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_clkbuf_usb.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_clkbuf_usb.VGND =VSS;
- force uut.mprj.u_wb_host.u_clkbuf_usb.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_cpu_ref_sel.u_mux.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_cpu_ref_sel.u_mux.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_cpu_ref_sel.u_mux.VGND =VSS;
- force uut.mprj.u_wb_host.u_cpu_ref_sel.u_mux.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_cpu_clk_sel.u_mux.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_cpu_clk_sel.u_mux.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_cpu_clk_sel.u_mux.VGND =VSS;
- force uut.mprj.u_wb_host.u_cpu_clk_sel.u_mux.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_wbs_clk_sel.u_mux.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_wbs_clk_sel.u_mux.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_wbs_clk_sel.u_mux.VGND =VSS;
- force uut.mprj.u_wb_host.u_wbs_clk_sel.u_mux.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_usb_clk_sel.u_mux.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_usb_clk_sel.u_mux.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_usb_clk_sel.u_mux.VGND =VSS;
- force uut.mprj.u_wb_host.u_usb_clk_sel.u_mux.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_delay1_stb0.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_delay1_stb0.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_delay1_stb0.VGND =VSS;
- force uut.mprj.u_wb_host.u_delay1_stb0.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_delay2_stb1.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_delay2_stb1.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_delay2_stb1.VGND =VSS;
- force uut.mprj.u_wb_host.u_delay2_stb1.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_delay2_stb2.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_delay2_stb2.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_delay2_stb2.VGND =VSS;
- force uut.mprj.u_wb_host.u_delay2_stb2.VNB = VSS;
+initial begin
end
`endif
diff --git a/verilog/dv/user_basic/Makefile b/verilog/dv/user_basic/Makefile
index 1760e90..2c9b432 100644
--- a/verilog/dv/user_basic/Makefile
+++ b/verilog/dv/user_basic/Makefile
@@ -33,6 +33,7 @@
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
+UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include
## SYNTACORE FIRMWARE
SYNTACORE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/rtl/syntacore/scr1/sim/tests/common
@@ -65,7 +66,7 @@
-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
-I $(UPRJ_BEHAVIOURAL_AGENTS) \
-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
- -I $(UPRJ_INCLUDE_PATH4) \
+ -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \
$< -o $@
else
iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
@@ -73,7 +74,7 @@
-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
-I $(UPRJ_BEHAVIOURAL_AGENTS) \
-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
- -I $(UPRJ_INCLUDE_PATH4) \
+ -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \
$< -o $@
endif
else
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index 6dc6c1a..f645004 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -152,7 +152,7 @@
`ifdef WFDUMP
initial begin
$dumpfile("risc_boot.vcd");
- $dumpvars(2, user_basic_tb);
+ $dumpvars(3, user_basic_tb);
end
`endif
@@ -241,9 +241,9 @@
// Remove Wb/PinMux Reset
wb_user_core_write('h3080_0000,'h1);
- wb_user_core_read_check(32'h30030058,read_data,32'h8273_8343);
- wb_user_core_read_check(32'h3003005C,read_data,32'h2311_2021);
- wb_user_core_read_check(32'h30030060,read_data,32'h0001_8000);
+ wb_user_core_read_check(32'h30020058,read_data,32'h8273_8343);
+ wb_user_core_read_check(32'h3002005C,read_data,32'h1112_2021);
+ wb_user_core_read_check(32'h30020060,read_data,32'h0001_9000);
end
@@ -318,149 +318,7 @@
`ifndef GL // Drive Power for Hold Fix Buf
// All standard cell need power hook-up for functionality work
initial begin
- force u_top.u_qspi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio0.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio0.VGND =VSS;
- force u_top.u_qspi_master.u_delay1_sdio0.VNB = VSS;
- force u_top.u_qspi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio0.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio0.VGND =VSS;
- force u_top.u_qspi_master.u_delay2_sdio0.VNB = VSS;
- force u_top.u_qspi_master.u_buf_sdio0.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio0.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio0.VGND =VSS;
- force u_top.u_qspi_master.u_buf_sdio0.VNB =VSS;
- force u_top.u_qspi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio1.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio1.VGND =VSS;
- force u_top.u_qspi_master.u_delay1_sdio1.VNB = VSS;
- force u_top.u_qspi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio1.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio1.VGND =VSS;
- force u_top.u_qspi_master.u_delay2_sdio1.VNB = VSS;
- force u_top.u_qspi_master.u_buf_sdio1.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio1.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio1.VGND =VSS;
- force u_top.u_qspi_master.u_buf_sdio1.VNB =VSS;
-
- force u_top.u_qspi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio2.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio2.VGND =VSS;
- force u_top.u_qspi_master.u_delay1_sdio2.VNB = VSS;
- force u_top.u_qspi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio2.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio2.VGND =VSS;
- force u_top.u_qspi_master.u_delay2_sdio2.VNB = VSS;
- force u_top.u_qspi_master.u_buf_sdio2.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio2.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio2.VGND =VSS;
- force u_top.u_qspi_master.u_buf_sdio2.VNB =VSS;
-
- force u_top.u_qspi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio3.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio3.VGND =VSS;
- force u_top.u_qspi_master.u_delay1_sdio3.VNB = VSS;
- force u_top.u_qspi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio3.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio3.VGND =VSS;
- force u_top.u_qspi_master.u_delay2_sdio3.VNB = VSS;
- force u_top.u_qspi_master.u_buf_sdio3.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio3.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio3.VGND =VSS;
- force u_top.u_qspi_master.u_buf_sdio3.VNB =VSS;
-
- force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
- force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VPB =USER_VDD1V8;
- force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VGND =VSS;
- force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_wb_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_wb_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_wb_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_cpu_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_cpu_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_cpu_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_cpu_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_qspim_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_qspim_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_qspim_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_qspim_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_sspim_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_sspim_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_sspim_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_sspim_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_uart_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_uart_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_uart_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_uart_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_i2cm_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_i2cm_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_i2cm_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_i2cm_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_usb_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_usb_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_usb_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_usb_rst.VNB = VSS;
-
-
-
- force u_top.u_wb_host.u_clkbuf_cpu.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_cpu.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_cpu.VGND =VSS;
- force u_top.u_wb_host.u_clkbuf_cpu.VNB = VSS;
-
- force u_top.u_wb_host.u_clkbuf_rtc.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_rtc.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_rtc.VGND =VSS;
- force u_top.u_wb_host.u_clkbuf_rtc.VNB = VSS;
-
- force u_top.u_wb_host.u_clkbuf_usb.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_usb.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_usb.VGND =VSS;
- force u_top.u_wb_host.u_clkbuf_usb.VNB = VSS;
-
- force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VGND =VSS;
- force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VNB = VSS;
-
- force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VGND =VSS;
- force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VNB = VSS;
-
- force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VGND =VSS;
- force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VNB = VSS;
-
- force u_top.u_wb_host.u_usb_clk_sel.u_mux.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_usb_clk_sel.u_mux.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_usb_clk_sel.u_mux.VGND =VSS;
- force u_top.u_wb_host.u_usb_clk_sel.u_mux.VNB = VSS;
-
- force u_top.u_wb_host.u_delay1_stb0.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_delay1_stb0.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_delay1_stb0.VGND =VSS;
- force u_top.u_wb_host.u_delay1_stb0.VNB = VSS;
-
- force u_top.u_wb_host.u_delay2_stb1.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_delay2_stb1.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_delay2_stb1.VGND =VSS;
- force u_top.u_wb_host.u_delay2_stb1.VNB = VSS;
-
- force u_top.u_wb_host.u_delay2_stb2.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_delay2_stb2.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_delay2_stb2.VGND =VSS;
- force u_top.u_wb_host.u_delay2_stb2.VNB = VSS;
end
`endif
diff --git a/verilog/dv/user_i2cm/Makefile b/verilog/dv/user_i2cm/Makefile
index 39da3b4..854e8cf 100644
--- a/verilog/dv/user_i2cm/Makefile
+++ b/verilog/dv/user_i2cm/Makefile
@@ -33,6 +33,7 @@
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
+UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include
## SYNTACORE FIRMWARE
SYNTACORE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/rtl/syntacore/scr1/sim/tests/common
@@ -71,7 +72,7 @@
-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
-I $(UPRJ_BEHAVIOURAL_AGENTS) \
-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
- -I $(UPRJ_INCLUDE_PATH4) \
+ -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \
$< -o $@
else
iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
@@ -79,7 +80,7 @@
-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
-I $(UPRJ_BEHAVIOURAL_AGENTS) \
-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
- -I $(UPRJ_INCLUDE_PATH4) \
+ -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \
$< -o $@
endif
else
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v
index 80d92a9..1299479 100644
--- a/verilog/dv/user_i2cm/user_i2cm_tb.v
+++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -73,6 +73,7 @@
`define ADDR_SPACE_UART 32'h3001_0000
`define ADDR_SPACE_I2CM 32'h3001_0040
+`define ADDR_SPACE_PINMUX 32'h3002_0000
module tb_top;
@@ -153,7 +154,7 @@
wb_user_core_write('h3080_0000,'hA1);
// Enable I2C Multi Functional Ports
- wb_user_core_write('h3003_0038,'h200);
+ wb_user_core_write(`ADDR_SPACE_PINMUX+'h0038,'h200);
repeat (100) @(posedge clock);
@@ -345,149 +346,6 @@
`ifndef GL // Drive Power for Hold Fix Buf
// All standard cell need power hook-up for functionality work
initial begin
- force u_top.u_qspi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio0.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio0.VGND =VSS;
- force u_top.u_qspi_master.u_delay1_sdio0.VNB = VSS;
- force u_top.u_qspi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio0.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio0.VGND =VSS;
- force u_top.u_qspi_master.u_delay2_sdio0.VNB = VSS;
- force u_top.u_qspi_master.u_buf_sdio0.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio0.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio0.VGND =VSS;
- force u_top.u_qspi_master.u_buf_sdio0.VNB =VSS;
-
- force u_top.u_qspi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio1.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio1.VGND =VSS;
- force u_top.u_qspi_master.u_delay1_sdio1.VNB = VSS;
- force u_top.u_qspi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio1.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio1.VGND =VSS;
- force u_top.u_qspi_master.u_delay2_sdio1.VNB = VSS;
- force u_top.u_qspi_master.u_buf_sdio1.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio1.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio1.VGND =VSS;
- force u_top.u_qspi_master.u_buf_sdio1.VNB =VSS;
-
- force u_top.u_qspi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio2.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio2.VGND =VSS;
- force u_top.u_qspi_master.u_delay1_sdio2.VNB = VSS;
- force u_top.u_qspi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio2.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio2.VGND =VSS;
- force u_top.u_qspi_master.u_delay2_sdio2.VNB = VSS;
- force u_top.u_qspi_master.u_buf_sdio2.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio2.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio2.VGND =VSS;
- force u_top.u_qspi_master.u_buf_sdio2.VNB =VSS;
-
- force u_top.u_qspi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio3.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio3.VGND =VSS;
- force u_top.u_qspi_master.u_delay1_sdio3.VNB = VSS;
- force u_top.u_qspi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio3.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio3.VGND =VSS;
- force u_top.u_qspi_master.u_delay2_sdio3.VNB = VSS;
- force u_top.u_qspi_master.u_buf_sdio3.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio3.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio3.VGND =VSS;
- force u_top.u_qspi_master.u_buf_sdio3.VNB =VSS;
-
- force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
- force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VPB =USER_VDD1V8;
- force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VGND =VSS;
- force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_wb_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_wb_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_wb_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_cpu_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_cpu_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_cpu_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_cpu_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_qspim_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_qspim_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_qspim_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_qspim_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_sspim_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_sspim_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_sspim_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_sspim_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_uart_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_uart_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_uart_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_uart_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_i2cm_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_i2cm_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_i2cm_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_i2cm_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_usb_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_usb_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_usb_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_usb_rst.VNB = VSS;
-
-
-
- force u_top.u_wb_host.u_clkbuf_cpu.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_cpu.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_cpu.VGND =VSS;
- force u_top.u_wb_host.u_clkbuf_cpu.VNB = VSS;
-
- force u_top.u_wb_host.u_clkbuf_rtc.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_rtc.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_rtc.VGND =VSS;
- force u_top.u_wb_host.u_clkbuf_rtc.VNB = VSS;
-
- force u_top.u_wb_host.u_clkbuf_usb.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_usb.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_usb.VGND =VSS;
- force u_top.u_wb_host.u_clkbuf_usb.VNB = VSS;
-
- force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VGND =VSS;
- force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VNB = VSS;
-
- force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VGND =VSS;
- force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VNB = VSS;
-
- force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VGND =VSS;
- force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VNB = VSS;
-
- force u_top.u_wb_host.u_usb_clk_sel.u_mux.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_usb_clk_sel.u_mux.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_usb_clk_sel.u_mux.VGND =VSS;
- force u_top.u_wb_host.u_usb_clk_sel.u_mux.VNB = VSS;
-
- force u_top.u_wb_host.u_delay1_stb0.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_delay1_stb0.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_delay1_stb0.VGND =VSS;
- force u_top.u_wb_host.u_delay1_stb0.VNB = VSS;
-
- force u_top.u_wb_host.u_delay2_stb1.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_delay2_stb1.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_delay2_stb1.VGND =VSS;
- force u_top.u_wb_host.u_delay2_stb1.VNB = VSS;
-
- force u_top.u_wb_host.u_delay2_stb2.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_delay2_stb2.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_delay2_stb2.VGND =VSS;
- force u_top.u_wb_host.u_delay2_stb2.VNB = VSS;
end
`endif
diff --git a/verilog/dv/user_mbist_test1/Makefile b/verilog/dv/user_mbist_test1/Makefile
new file mode 100644
index 0000000..d6d34c6
--- /dev/null
+++ b/verilog/dv/user_mbist_test1/Makefile
@@ -0,0 +1,109 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+## Caravel Pointers
+CARAVEL_ROOT ?= ../../../caravel
+CARAVEL_PATH ?= $(CARAVEL_ROOT)
+CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
+CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog
+CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
+CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+
+## User Project Pointers
+UPRJ_VERILOG_PATH ?= ../../../verilog
+UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
+UPRJ_BEHAVIOURAL_MODELS = ../model
+UPRJ_BEHAVIOURAL_AGENTS = ../agents
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes
+UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
+UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
+UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
+UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include
+
+## SYNTACORE FIRMWARE
+SYNTACORE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/rtl/syntacore/scr1/sim/tests/common
+GCC64_PREFIX?=riscv64-unknown-elf
+
+## RISCV GCC
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/ef/tech/SW/sky130A
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+
+.SUFFIXES:
+
+PATTERN = user_mbist_test1
+
+all: ${PATTERN:=.vcd}
+
+vvp: ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
+ iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_AGENTS) \
+ -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
+ -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \
+ $< -o $@
+ else
+ iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_AGENTS) \
+ -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
+ -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \
+ $< -o $@
+ endif
+else
+ iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_AGENTS) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+#ifeq (,$(wildcard $(GCC64_PREFIX)-gcc ))
+# $(error $(GCC64_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+#endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+
+# ---- Clean ----
+
+clean:
+ rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
diff --git a/verilog/dv/user_mbist_test1/run_iverilog b/verilog/dv/user_mbist_test1/run_iverilog
new file mode 100755
index 0000000..e66b863
--- /dev/null
+++ b/verilog/dv/user_mbist_test1/run_iverilog
@@ -0,0 +1,31 @@
+# //////////////////////////////////////////////////////////////////////////////
+# // SPDX-FileCopyrightText: 2021, Dinesh Annayya
+# //
+# // Licensed under the Apache License, Version 2.0 (the "License");
+# // you may not use this file except in compliance with the License.
+# // You may obtain a copy of the License at
+# //
+# // http://www.apache.org/licenses/LICENSE-2.0
+# //
+# // Unless required by applicable law or agreed to in writing, software
+# // distributed under the License is distributed on an "AS IS" BASIS,
+# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# // See the License for the specific language governing permissions and
+# // limitations under the License.
+# // SPDX-License-Identifier: Apache-2.0
+# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+# // //////////////////////////////////////////////////////////////////////////
+
+#iverilog without Dump
+#
+iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I /home/dinesha/workarea/efabless/MPW-3/pdk/sky130A \
+-I /home/dinesha/workarea/opencore/git/riscduino/caravel/verilog/dv/caravel \
+-I /home/dinesha/workarea/opencore/git/riscduino/caravel/verilog/rtl \
+-I ../ -I ../../../verilog/rtl \
+-I ../../../verilog/rtl/mbist/include \
+user_mbist_test1_tb.v -o user_mbist_test1.vvp
+
+
+vvp user_mbist_test1.vvp | tee test.log
+
+\rm -rf user_mbist_test1.vvp
diff --git a/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v b/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v
new file mode 100644
index 0000000..8378213
--- /dev/null
+++ b/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v
@@ -0,0 +1,791 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Standalone User validation Test bench ////
+//// ////
+//// ////
+//// Description ////
+//// This is a standalone test bench to validate the ////
+//// Digital core MBIST logic through External WB i/F. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 18 Oct 2021, Dinesh A ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ns
+
+`include "uprj_netlists.v"
+
+`define WB_MAP `30080_0000
+`define GLBL_FUNC_MAP 'h3002_0000
+`define MBIST1_FUNC_MAP 'h3003_0000
+`define MBIST2_FUNC_MAP 'h3004_0000
+`define MBIST3_FUNC_MAP 'h3005_0000
+`define MBIST4_FUNC_MAP 'h3006_0000
+`define MBIST5_FUNC_MAP 'h3007_0000
+`define MBIST6_FUNC_MAP 'h3008_0000
+`define MBIST7_FUNC_MAP 'h3009_0000
+`define MBIST8_FUNC_MAP 'h300A_0000
+
+`define GLBL_BIST_CTRL1 'h3002_0070
+`define GLBL_BIST_STAT1 'h3002_0074
+`define GLBL_BIST_SWDATA 'h3002_0078
+`define GLBL_BIST_SRDATA 'h3002_007C
+`define GLBL_BIST_SPDATA 'h3002_0078 #
+
+`define WB_GLBL_CTRL 'h3080_0000
+
+`define NO_SRAM 2 // 8
+
+
+
+module user_mbist_test1_tb;
+ reg clock;
+ reg wb_rst_i;
+ reg power1, power2;
+ reg power3, power4;
+
+ reg wbd_ext_cyc_i; // strobe/request
+ reg wbd_ext_stb_i; // strobe/request
+ reg [31:0] wbd_ext_adr_i; // address
+ reg wbd_ext_we_i; // write
+ reg [31:0] wbd_ext_dat_i; // data output
+ reg [3:0] wbd_ext_sel_i; // byte enable
+
+ wire [31:0] wbd_ext_dat_o; // data input
+ wire wbd_ext_ack_o; // acknowlegement
+ wire wbd_ext_err_o; // error
+
+ // User I/O
+ wire [37:0] io_oeb;
+ wire [37:0] io_out;
+ wire [37:0] io_in;
+
+ wire gpio;
+ wire [37:0] mprj_io;
+ wire [7:0] mprj_io_0;
+ reg test_fail;
+ reg [31:0] read_data;
+ reg [31:0] writemem [0:511];
+ reg [8:0] faultaddr [0:7];
+ integer i;
+ event error_insert;
+
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #12.5 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ end
+
+ `ifdef WFDUMP
+ initial begin
+ $dumpfile("simx.vcd");
+ $dumpvars(5, user_mbist_test1_tb);
+ $dumpoff;
+ end
+ `endif
+
+ initial begin
+ wb_rst_i <= 1'b1;
+ #100;
+ wb_rst_i <= 1'b0; // Release reset
+
+ #200; // Wait for reset removal
+ repeat (10) @(posedge clock);
+ $display("Monitor: Standalone User Test Started");
+
+ test_fail = 0;
+ // Remove Wb Reset
+ wb_user_core_write(`WB_GLBL_CTRL,'h1);
+
+ $dumpoff;
+ $display("###################################################");
+ $display(" MBIST Test with Without Address Failure");
+ $display("###################################################");
+
+ // Check Is there is any BIST Error
+ // [0] - Bist Done - 1
+ // [1] - Bist Error - 0
+ // [2] - Bist Correct - 0
+ // [3] - Reserved - 0
+ // [7:4] - Bist Error Cnt - 4'h0
+ insert_fault(0,0,64'h01010101_01010101);
+
+ if(test_fail == 0) begin
+ $display("Monitor: Step-1: BIST Test without any Memory Error insertion test Passed");
+ end else begin
+ $display("Monitor: Step-1: BIST Test without any Memory Error insertion test Failed");
+ end
+ $dumpon;
+ $display("###################################################");
+ $display(" MBIST Test with Single Address Failure");
+ $display("###################################################");
+ // Check Is there is any BIST Error
+ // [0] - Bist Done - 1
+ // [1] - Bist Error - 0
+ // [2] - Bist Correct - 1
+ // [3] - Reserved - 0
+ // [7:4] - Bist Error Cnt - 4'h1
+ //if(read_data[6:0] != 7'b0001101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x1
+ faultaddr[0] = 9'h10;
+ insert_fault(1,1,64'h15151515_15151515);
+
+ if(test_fail == 0) begin
+ $display("Monitor: Step-2: BIST Test with One Memory Error insertion test Passed");
+ end else begin
+ $display("Monitor: Step-2: BIST Test with One Memory Error insertion test Failed");
+ end
+ $display("###################################################");
+ $dumpoff;
+ $display("###################################################");
+ $display(" MBIST Test with Two Address Failure");
+ $display("###################################################");
+ // Check Is there is any BIST Error
+ // [0] - Bist Done - 1
+ // [1] - Bist Error - 0
+ // [2] - Bist Correct - 1
+ // [3] - Reserved - 0
+ // [7:4] - Bist Error Cnt - 4'h2
+ //if(read_data[6:0] != 7'b0010101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x2
+ faultaddr[0] = 9'h10;
+ faultaddr[1] = 9'h20;
+ insert_fault(2,0,64'h25252525_25252525);
+
+ if(test_fail == 0) begin
+ $display("Monitor: Step-3: BIST Test with Two Memory Error insertion test Passed");
+ end else begin
+ $display("Monitor: Step-3: BIST Test with Two Memory Error insertion test Failed");
+ end
+ $display("###################################################");
+ $display(" MBIST Test with Three Address Failure");
+ $display("###################################################");
+
+ // Check Is there is any BIST Error
+ // [0] - Bist Done - 1
+ // [1] - Bist Error - 0
+ // [2] - Bist Correct - 1
+ // [3] - Reserved - 0
+ // [7:4] - Bist Error Cnt - 4'h3
+ //if(read_data[6:0] != 7'b0011101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x3
+ faultaddr[0] = 9'h10;
+ faultaddr[1] = 9'h20;
+ faultaddr[2] = 9'h30;
+ insert_fault(3,1,64'h35353535_35353535);
+
+ if(test_fail == 0) begin
+ $display("Monitor: Step-4: BIST Test with Three Memory Error insertion test Passed");
+ end else begin
+ $display("Monitor: Step-4: BIST Test with Three Memory Error insertion test Failed");
+ end
+ $dumpoff;
+ $display("###################################################");
+ $display(" MBIST Test with Fours Address Failure");
+ $display("###################################################");
+ // Check Is there is any BIST Error
+ // [0] - Bist Done - 1
+ // [1] - Bist Error - 0
+ // [2] - Bist Correct - 1
+ // [3] - Reserved - 0
+ // [7:4] - Bist Error Cnt - 4'h4
+ //if(read_data[6:0] != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4
+ faultaddr[0] = 9'h10;
+ faultaddr[1] = 9'h20;
+ faultaddr[2] = 9'h30;
+ faultaddr[3] = 9'h40;
+ insert_fault(4,0,64'h45454545_45454545);
+
+ if(test_fail == 0) begin
+ $display("Monitor: Step-5: BIST Test with Four Memory Error insertion test Passed");
+ end else begin
+ $display("Monitor: Step-5: BIST Test with Four Memory Error insertion test Failed");
+ end
+
+ $dumpon;
+ $display("###################################################");
+ $display(" MBIST Test with Fours Address(Continous Starting Addrsess) Failure");
+ $display("###################################################");
+ // Check Is there is any BIST Error
+ // [0] - Bist Done - 1
+ // [1] - Bist Error - 0
+ // [2] - Bist Correct - 1
+ // [3] - Reserved - 0
+ // [7:4] - Bist Error Cnt - 4'h4
+ //if(read_data[6:0] != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4
+ faultaddr[0] = 9'h0;
+ faultaddr[1] = 9'h1;
+ faultaddr[2] = 9'h2;
+ faultaddr[3] = 9'h3;
+ insert_fault(4,0,64'h45454545_45454545);
+
+ if(test_fail == 0) begin
+ $display("Monitor: Step-5.2: BIST Test with Four Memory Error insertion test Passed");
+ end else begin
+ $display("Monitor: Step-5.2: BIST Test with Four Memory Error insertion test Failed");
+ end
+
+ $display("###################################################");
+ $display(" MBIST Test with Fours Address(Last Addrsess) Failure");
+ $display("###################################################");
+ // Check Is there is any BIST Error
+ // [0] - Bist Done - 1
+ // [1] - Bist Error - 0
+ // [2] - Bist Correct - 1
+ // [3] - Reserved - 0
+ // [7:4] - Bist Error Cnt - 4'h4
+ //if(read_data[6:0] != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4
+ faultaddr[0] = 9'hF0;
+ faultaddr[1] = 9'hF1;
+ faultaddr[2] = 9'hF2;
+ faultaddr[3] = 9'hF3;
+ insert_fault(4,0,64'h45454545_45454545);
+
+ if(test_fail == 0) begin
+ $display("Monitor: Step-5.3: BIST Test with Four Memory Error insertion test Passed");
+ end else begin
+ $display("Monitor: Step-5.3: BIST Test with Four Memory Error insertion test Failed");
+ end
+ $display("###################################################");
+ $display(" MBIST Test with Five Address Failure");
+ $display("###################################################");
+ // Check Is there is any BIST Error
+ // [0] - Bist Done - 1
+ // [1] - Bist Error - 1
+ // [2] - Bist Correct - 1
+ // [3] - Reserved - 0
+ // [7:4] - Bist Error Cnt - 4'h4
+ //if(read_data[6:0] != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4
+ faultaddr[0] = 9'h10;
+ faultaddr[1] = 9'h20;
+ faultaddr[2] = 9'h30;
+ faultaddr[3] = 9'h40;
+ faultaddr[4] = 9'h50;
+ insert_fault(5,1,64'h47474747_47474747);
+
+ if(test_fail == 0) begin
+ $display("Monitor: Step-5: BIST Test with Five Memory Error insertion test Passed");
+ end else begin
+ $display("Monitor: Step-5: BIST Test with Five Memory Error insertion test Failed");
+ end
+
+ $dumpon;
+ $display("###################################################");
+ $display(" MBIST Test with Functional Access, continuation of previous MBIST Signature");
+ $display("###################################################");
+ $dumpon;
+ fork
+ begin
+ // Remove the Bist Enable and Bist Run
+ wb_user_core_write(`GLBL_BIST_CTRL1,'h000);
+
+ // Fill Random Data
+ for (i=0; i< 9'h1FC; i=i+1) begin
+ writemem[i] = $random;
+ wb_user_core_write(`MBIST1_FUNC_MAP+(i*4),writemem[i]);
+ wb_user_core_write(`MBIST2_FUNC_MAP+(i*4),writemem[i]);
+ wb_user_core_write(`MBIST3_FUNC_MAP+(i*4),writemem[i]);
+ wb_user_core_write(`MBIST4_FUNC_MAP+(i*4),writemem[i]);
+ //if(i < 9'h0FC) begin // SRAM5-SRAM8 are 1KB
+ // wb_user_core_write(`MBIST5_FUNC_MAP+(i*4),writemem[i]);
+ // wb_user_core_write(`MBIST6_FUNC_MAP+(i*4),writemem[i]);
+ // wb_user_core_write(`MBIST7_FUNC_MAP+(i*4),writemem[i]);
+ // wb_user_core_write(`MBIST8_FUNC_MAP+(i*4),writemem[i]);
+ //end
+ end
+ // Read back data
+ for (i=0; i< 9'h1FC; i=i+1) begin
+ wb_user_core_read_check(`MBIST1_FUNC_MAP+(i*4),read_data,writemem[i],32'hFFFFFFFF);
+ wb_user_core_read_check(`MBIST2_FUNC_MAP+(i*4),read_data,writemem[i],32'hFFFFFFFF);
+ wb_user_core_read_check(`MBIST3_FUNC_MAP+(i*4),read_data,writemem[i],32'hFFFFFFFF);
+ wb_user_core_read_check(`MBIST4_FUNC_MAP+(i*4),read_data,writemem[i],32'hFFFFFFFF);
+ //if(i < 9'h0FC) begin // SRAM5 - SRAM8 are 1KB
+ // wb_user_core_read_check(`MBIST5_FUNC_MAP+(i*4),read_data,writemem[i],32'hFFFFFFFF);
+ // wb_user_core_read_check(`MBIST6_FUNC_MAP+(i*4),read_data,writemem[i],32'hFFFFFFFF);
+ // wb_user_core_read_check(`MBIST7_FUNC_MAP+(i*4),read_data,writemem[i],32'hFFFFFFFF);
+ // wb_user_core_read_check(`MBIST8_FUNC_MAP+(i*4),read_data,writemem[i],32'hFFFFFFFF);
+ //end
+ end
+
+ // Cross-check Reducency address hold the failure address data
+ // Is last Error inserted address are 0x10,0x20,0x30,0x40
+ // So Address 0x1FC = Data[0x10], 0x1FD = Data[0x20]
+ // Address 0x1FE = Data[0x30], 0x1FF = Data[0x40]
+ // Check 2kb SRAM1
+ wb_user_core_read_check(`MBIST1_FUNC_MAP + (9'h1FC *4),read_data,writemem[9'h10],32'hFFFFFFFF);
+ wb_user_core_read_check(`MBIST1_FUNC_MAP + (9'h1FD *4),read_data,writemem[9'h20],32'hFFFFFFFF);
+ wb_user_core_read_check(`MBIST1_FUNC_MAP + (9'h1FE *4),read_data,writemem[9'h30],32'hFFFFFFFF);
+ wb_user_core_read_check(`MBIST1_FUNC_MAP + (9'h1FF *4),read_data,writemem[9'h40],32'hFFFFFFFF);
+
+ // Check 2kb SRAM2
+ wb_user_core_read_check(`MBIST2_FUNC_MAP + (9'h1FC *4),read_data,writemem[9'h11],32'hFFFFFFFF);
+ wb_user_core_read_check(`MBIST2_FUNC_MAP + (9'h1FD *4),read_data,writemem[9'h21],32'hFFFFFFFF);
+ wb_user_core_read_check(`MBIST2_FUNC_MAP + (9'h1FE *4),read_data,writemem[9'h31],32'hFFFFFFFF);
+ wb_user_core_read_check(`MBIST2_FUNC_MAP + (9'h1FF *4),read_data,writemem[9'h41],32'hFFFFFFFF);
+
+ //// Check 2kb SRAM3
+ wb_user_core_read_check(`MBIST3_FUNC_MAP + (9'h1FC *4),read_data,writemem[9'h12],32'hFFFFFFFF);
+ wb_user_core_read_check(`MBIST3_FUNC_MAP + (9'h1FD *4),read_data,writemem[9'h22],32'hFFFFFFFF);
+ wb_user_core_read_check(`MBIST3_FUNC_MAP + (9'h1FE *4),read_data,writemem[9'h32],32'hFFFFFFFF);
+ wb_user_core_read_check(`MBIST3_FUNC_MAP + (9'h1FF *4),read_data,writemem[9'h42],32'hFFFFFFFF);
+
+ //// Check 2kb SRAM4
+ wb_user_core_read_check(`MBIST4_FUNC_MAP + (9'h1FC *4),read_data,writemem[9'h13],32'hFFFFFFFF);
+ wb_user_core_read_check(`MBIST4_FUNC_MAP + (9'h1FD *4),read_data,writemem[9'h23],32'hFFFFFFFF);
+ wb_user_core_read_check(`MBIST4_FUNC_MAP + (9'h1FE *4),read_data,writemem[9'h33],32'hFFFFFFFF);
+ wb_user_core_read_check(`MBIST4_FUNC_MAP + (9'h1FF *4),read_data,writemem[9'h43],32'hFFFFFFFF);
+
+ //// Check 1kb SRAM5
+ //wb_user_core_read_check(`MBIST5_FUNC_MAP + (8'hFC *4),read_data,writemem[9'h14],32'hFFFFFFFF);
+ //wb_user_core_read_check(`MBIST5_FUNC_MAP + (8'hFD *4),read_data,writemem[9'h24],32'hFFFFFFFF);
+ //wb_user_core_read_check(`MBIST5_FUNC_MAP + (8'hFE *4),read_data,writemem[9'h34],32'hFFFFFFFF);
+ //wb_user_core_read_check(`MBIST5_FUNC_MAP + (8'hFF *4),read_data,writemem[9'h44],32'hFFFFFFFF);
+
+ //// Check 1kb SRAM6
+ //wb_user_core_read_check(`MBIST6_FUNC_MAP + (8'hFC *4),read_data,writemem[9'h15],32'hFFFFFFFF);
+ //wb_user_core_read_check(`MBIST6_FUNC_MAP + (8'hFD *4),read_data,writemem[9'h25],32'hFFFFFFFF);
+ //wb_user_core_read_check(`MBIST6_FUNC_MAP + (8'hFE *4),read_data,writemem[9'h35],32'hFFFFFFFF);
+ //wb_user_core_read_check(`MBIST6_FUNC_MAP + (8'hFF *4),read_data,writemem[9'h45],32'hFFFFFFFF);
+
+ //// Check 1kb SRAM7
+ //wb_user_core_read_check(`MBIST7_FUNC_MAP + (8'hFC *4),read_data,writemem[9'h16],32'hFFFFFFFF);
+ //wb_user_core_read_check(`MBIST7_FUNC_MAP + (8'hFD *4),read_data,writemem[9'h26],32'hFFFFFFFF);
+ //wb_user_core_read_check(`MBIST7_FUNC_MAP + (8'hFE *4),read_data,writemem[9'h36],32'hFFFFFFFF);
+ //wb_user_core_read_check(`MBIST7_FUNC_MAP + (8'hFF *4),read_data,writemem[9'h46],32'hFFFFFFFF);
+
+ //// Check 1kb SRAM8
+ //wb_user_core_read_check(`MBIST8_FUNC_MAP + (8'hFC *4),read_data,writemem[9'h17],32'hFFFFFFFF);
+ //wb_user_core_read_check(`MBIST8_FUNC_MAP + (8'hFD *4),read_data,writemem[9'h27],32'hFFFFFFFF);
+ //wb_user_core_read_check(`MBIST8_FUNC_MAP + (8'hFE *4),read_data,writemem[9'h37],32'hFFFFFFFF);
+ //wb_user_core_read_check(`MBIST8_FUNC_MAP + (8'hFF *4),read_data,writemem[9'h47],32'hFFFFFFFF);
+ end
+ begin
+ // Loop for BIST TimeOut
+ repeat (200000) @(posedge clock);
+ // $display("+1000 cycles");
+ test_fail = 1;
+ end
+ join_any
+ disable fork; //disable pending fork activity
+ if(test_fail == 0) begin
+ $display("Monitor: Step-5: BIST Test with Functional access test Passed");
+ end else begin
+ $display("Monitor: Step-5: BIST Test with Functional access test failed");
+ end
+
+ $display("###################################################");
+ $finish;
+ end
+
+wire USER_VDD1V8 = 1'b1;
+wire VSS = 1'b0;
+
+
+user_project_wrapper u_top(
+`ifdef USE_POWER_PINS
+ .vccd1(USER_VDD1V8), // User area 1 1.8V supply
+ .vssd1(VSS), // User area 1 digital ground
+`endif
+ .wb_clk_i (clock), // System clock
+ .user_clock2 (1'b1), // Real-time clock
+ .wb_rst_i (wb_rst_i), // Regular Reset signal
+
+ .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
+ .wbs_stb_i (wbd_ext_stb_i), // strobe/request
+ .wbs_adr_i (wbd_ext_adr_i), // address
+ .wbs_we_i (wbd_ext_we_i), // write
+ .wbs_dat_i (wbd_ext_dat_i), // data output
+ .wbs_sel_i (wbd_ext_sel_i), // byte enable
+
+ .wbs_dat_o (wbd_ext_dat_o), // data input
+ .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
+
+
+ // Logic Analyzer Signals
+ .la_data_in ('0) ,
+ .la_data_out (),
+ .la_oenb ('0),
+
+
+ // IOs
+ .io_in (io_in) ,
+ .io_out (io_out) ,
+ .io_oeb (io_oeb) ,
+
+ .user_irq ()
+
+);
+
+`ifndef GL // Drive Power for Hold Fix Buf
+ // All standard cell need power hook-up for functionality work
+ initial begin
+
+
+ end
+`endif
+
+
+//-------------------------------------
+// Insert user defined number of fault
+// -----------------------------------
+
+task insert_fault;
+input [3:0] num_fault;
+input fault_type; // 0 -> struck at 0 and 1 -> struck at 1
+input [63:0] mbist_signature;
+reg [31:0] datain;
+reg [8:0] fail_addr1;
+reg [8:0] fail_addr2;
+reg [8:0] fail_addr3;
+reg [8:0] fail_addr4;
+integer j;
+begin
+ repeat (2) @(posedge clock);
+ fork
+ begin
+ // Remove the Bist Enable and Bist Run
+ wb_user_core_write(`GLBL_BIST_CTRL1,'h000);
+ // Remove WB and BIST RESET
+ wb_user_core_write(`WB_GLBL_CTRL,'h001);
+ // Set the Bist Enable and Bist Run
+ wb_user_core_write(`GLBL_BIST_CTRL1,'h00003333);
+ // Remove WB and BIST RESET
+ wb_user_core_write(`WB_GLBL_CTRL,'h081);
+ // Check for MBIST Done
+ read_data = 'h0;
+ while (read_data[0] != 1'b1) begin
+ wb_user_core_read(`GLBL_BIST_STAT1,read_data);
+ end
+ // wait for some time for all the BIST to complete
+ repeat (1000) @(posedge clock);
+ // Check Is there is any BIST Error
+ // [0] - Bist Done
+ // [1] - Bist Error
+ // [2] - Bist Correct
+ // [3] - Reserved
+ // [7:4] - Bist Error Cnt
+ wb_user_core_read_check(`GLBL_BIST_STAT1,read_data,mbist_signature[31:0],32'hFFFFFFFF);
+ //wb_user_core_read_check(`GLBL_BIST_STAT2,read_data,mbist_signature[63:32],32'hFFFFFFFF);
+ end
+ // Insert Error Insertion
+ begin
+ while(1) begin
+ repeat (1) @(posedge clock);
+ #1;
+
+ if(u_top.u_sram1_2kb.web0 == 1'b0 &&
+ ((num_fault > 0 && u_top.u_sram1_2kb.addr0 == faultaddr[0]) ||
+ (num_fault > 1 && u_top.u_sram1_2kb.addr0 == faultaddr[1]) ||
+ (num_fault > 2 && u_top.u_sram1_2kb.addr0 == faultaddr[2]) ||
+ (num_fault > 3 && u_top.u_sram1_2kb.addr0 == faultaddr[3]) ||
+ (num_fault > 4 && u_top.u_sram1_2kb.addr0 == faultaddr[4]) ||
+ (num_fault > 5 && u_top.u_sram1_2kb.addr0 == faultaddr[5]) ||
+ (num_fault > 6 && u_top.u_sram1_2kb.addr0 == faultaddr[6]) ||
+ (num_fault > 7 && u_top.u_sram1_2kb.addr0 == faultaddr[7])))
+ begin
+ if(fault_type == 0) // Struck at 0
+ force u_top.u_sram1_2kb.din0 = u_top.mem1_din_b & 32'hFFFF_FFFE;
+ else
+ force u_top.u_sram1_2kb.din0 = u_top.mem1_din_b | 32'h1;
+ -> error_insert;
+ end else begin
+ release u_top.u_sram1_2kb.din0;
+ end
+
+ if(u_top.u_sram2_2kb.web0 == 1'b0 &&
+ ((num_fault > 0 && u_top.u_sram2_2kb.addr0 == faultaddr[0]+1) ||
+ (num_fault > 1 && u_top.u_sram2_2kb.addr0 == faultaddr[1]+1) ||
+ (num_fault > 2 && u_top.u_sram2_2kb.addr0 == faultaddr[2]+1) ||
+ (num_fault > 3 && u_top.u_sram2_2kb.addr0 == faultaddr[3]+1) ||
+ (num_fault > 4 && u_top.u_sram2_2kb.addr0 == faultaddr[4]+1) ||
+ (num_fault > 5 && u_top.u_sram2_2kb.addr0 == faultaddr[5]+1) ||
+ (num_fault > 6 && u_top.u_sram2_2kb.addr0 == faultaddr[6]+1) ||
+ (num_fault > 7 && u_top.u_sram2_2kb.addr0 == faultaddr[7]+1)))
+ begin
+ if(fault_type == 0) // Struck at 0
+ force u_top.u_sram2_2kb.din0 = u_top.mem2_din_b & 32'hFFFF_FFFE;
+ else
+ force u_top.u_sram2_2kb.din0 = u_top.mem2_din_b | 32'h1;
+ -> error_insert;
+ end else begin
+ release u_top.u_sram2_2kb.din0;
+ end
+
+ if(u_top.u_sram3_2kb.web0 == 1'b0 &&
+ ((num_fault > 0 && u_top.u_sram3_2kb.addr0 == faultaddr[0]+2) ||
+ (num_fault > 1 && u_top.u_sram3_2kb.addr0 == faultaddr[1]+2) ||
+ (num_fault > 2 && u_top.u_sram3_2kb.addr0 == faultaddr[2]+2) ||
+ (num_fault > 3 && u_top.u_sram3_2kb.addr0 == faultaddr[3]+2) ||
+ (num_fault > 4 && u_top.u_sram3_2kb.addr0 == faultaddr[4]+2) ||
+ (num_fault > 5 && u_top.u_sram3_2kb.addr0 == faultaddr[5]+2) ||
+ (num_fault > 6 && u_top.u_sram3_2kb.addr0 == faultaddr[6]+2) ||
+ (num_fault > 7 && u_top.u_sram3_2kb.addr0 == faultaddr[7]+2)))
+ begin
+ if(fault_type == 0) // Struck at 0
+ force u_top.u_sram3_2kb.din0 = u_top.mem3_din_b & 32'hFFFF_FFFE;
+ else
+ force u_top.u_sram3_2kb.din0 = u_top.mem3_din_b | 32'h1;
+ -> error_insert;
+ end else begin
+ release u_top.u_sram3_2kb.din0;
+ end
+
+ if(u_top.u_sram4_2kb.web0 == 1'b0 &&
+ ((num_fault > 0 && u_top.u_sram4_2kb.addr0 == faultaddr[0]+3) ||
+ (num_fault > 1 && u_top.u_sram4_2kb.addr0 == faultaddr[1]+3) ||
+ (num_fault > 2 && u_top.u_sram4_2kb.addr0 == faultaddr[2]+3) ||
+ (num_fault > 3 && u_top.u_sram4_2kb.addr0 == faultaddr[3]+3) ||
+ (num_fault > 4 && u_top.u_sram4_2kb.addr0 == faultaddr[4]+3) ||
+ (num_fault > 5 && u_top.u_sram4_2kb.addr0 == faultaddr[5]+3) ||
+ (num_fault > 6 && u_top.u_sram4_2kb.addr0 == faultaddr[6]+3) ||
+ (num_fault > 7 && u_top.u_sram4_2kb.addr0 == faultaddr[7]+3)))
+ begin
+ if(fault_type == 0) // Struck at 0
+ force u_top.u_sram4_2kb.din0 = u_top.mem4_din_b & 32'hFFFF_FFFE;
+ else
+ force u_top.u_sram4_2kb.din0 = u_top.mem4_din_b | 32'h1;
+ -> error_insert;
+ end else begin
+ release u_top.u_sram4_2kb.din0;
+ end
+
+ //if(u_top.u_sram5_1kb.web0 == 1'b0 &&
+ // ((num_fault > 0 && u_top.u_sram5_1kb.addr0 == faultaddr[0]+4) ||
+ // (num_fault > 1 && u_top.u_sram5_1kb.addr0 == faultaddr[1]+4) ||
+ // (num_fault > 2 && u_top.u_sram5_1kb.addr0 == faultaddr[2]+4) ||
+ // (num_fault > 3 && u_top.u_sram5_1kb.addr0 == faultaddr[3]+4) ||
+ // (num_fault > 4 && u_top.u_sram5_1kb.addr0 == faultaddr[4]+4) ||
+ // (num_fault > 5 && u_top.u_sram5_1kb.addr0 == faultaddr[5]+4) ||
+ // (num_fault > 6 && u_top.u_sram5_1kb.addr0 == faultaddr[6]+4) ||
+ // (num_fault > 7 && u_top.u_sram5_1kb.addr0 == faultaddr[7]+4)))
+ // begin
+ // if(fault_type == 0) // Struck at 0
+ // force u_top.u_sram5_1kb.din0 = u_top.mem5_din_b & 32'hFFFF_FFFE;
+ // else
+ // force u_top.u_sram5_1kb.din0 = u_top.mem5_din_b | 32'h1;
+ // -> error_insert;
+ //end else begin
+ // release u_top.u_sram5_1kb.din0;
+ //end
+
+ //if(u_top.u_sram6_1kb.web0 == 1'b0 &&
+ // ((num_fault > 0 && u_top.u_sram6_1kb.addr0 == faultaddr[0]+5) ||
+ // (num_fault > 1 && u_top.u_sram6_1kb.addr0 == faultaddr[1]+5) ||
+ // (num_fault > 2 && u_top.u_sram6_1kb.addr0 == faultaddr[2]+5) ||
+ // (num_fault > 3 && u_top.u_sram6_1kb.addr0 == faultaddr[3]+5) ||
+ // (num_fault > 4 && u_top.u_sram6_1kb.addr0 == faultaddr[4]+5) ||
+ // (num_fault > 5 && u_top.u_sram6_1kb.addr0 == faultaddr[5]+5) ||
+ // (num_fault > 6 && u_top.u_sram6_1kb.addr0 == faultaddr[6]+5) ||
+ // (num_fault > 7 && u_top.u_sram6_1kb.addr0 == faultaddr[7]+5)))
+ // begin
+ // if(fault_type == 0) // Struck at 0
+ // force u_top.u_sram6_1kb.din0 = u_top.mem6_din_b & 32'hFFFF_FFFE;
+ // else
+ // force u_top.u_sram6_1kb.din0 = u_top.mem6_din_b | 32'h1;
+ // -> error_insert;
+ //end else begin
+ // release u_top.u_sram6_1kb.din0;
+ //end
+
+ //if(u_top.u_sram7_1kb.web0 == 1'b0 &&
+ // ((num_fault > 0 && u_top.u_sram7_1kb.addr0 == faultaddr[0]+6) ||
+ // (num_fault > 1 && u_top.u_sram7_1kb.addr0 == faultaddr[1]+6) ||
+ // (num_fault > 2 && u_top.u_sram7_1kb.addr0 == faultaddr[2]+6) ||
+ // (num_fault > 3 && u_top.u_sram7_1kb.addr0 == faultaddr[3]+6) ||
+ // (num_fault > 4 && u_top.u_sram7_1kb.addr0 == faultaddr[4]+6) ||
+ // (num_fault > 5 && u_top.u_sram7_1kb.addr0 == faultaddr[5]+6) ||
+ // (num_fault > 6 && u_top.u_sram7_1kb.addr0 == faultaddr[6]+6) ||
+ // (num_fault > 7 && u_top.u_sram7_1kb.addr0 == faultaddr[7]+6)))
+ // begin
+ // if(fault_type == 0) // Struck at 0
+ // force u_top.u_sram7_1kb.din0 = u_top.mem7_din_b & 32'hFFFF_FFFE;
+ // else
+ // force u_top.u_sram7_1kb.din0 = u_top.mem7_din_b | 32'h1;
+ // -> error_insert;
+ //end else begin
+ // release u_top.u_sram7_1kb.din0;
+ //end
+
+ //if(u_top.u_sram8_1kb.web0 == 1'b0 &&
+ // ((num_fault > 0 && u_top.u_sram8_1kb.addr0 == faultaddr[0]+7) ||
+ // (num_fault > 1 && u_top.u_sram8_1kb.addr0 == faultaddr[1]+7) ||
+ // (num_fault > 2 && u_top.u_sram8_1kb.addr0 == faultaddr[2]+7) ||
+ // (num_fault > 3 && u_top.u_sram8_1kb.addr0 == faultaddr[3]+7) ||
+ // (num_fault > 4 && u_top.u_sram8_1kb.addr0 == faultaddr[4]+7) ||
+ // (num_fault > 5 && u_top.u_sram8_1kb.addr0 == faultaddr[5]+7) ||
+ // (num_fault > 6 && u_top.u_sram8_1kb.addr0 == faultaddr[6]+7) ||
+ // (num_fault > 7 && u_top.u_sram8_1kb.addr0 == faultaddr[7]+7)))
+ // begin
+ // if(fault_type == 0) // Struck at 0
+ // force u_top.u_sram8_1kb.din0 = u_top.mem8_din_b & 32'hFFFF_FFFE;
+ // else
+ // force u_top.u_sram8_1kb.din0 = u_top.mem8_din_b | 32'h1;
+ // -> error_insert;
+ //end else begin
+ // release u_top.u_sram8_1kb.din0;
+ //end
+
+ end
+ end
+ begin
+ // Loop for BIST TimeOut
+ repeat (200000) @(posedge clock);
+ // $display("+1000 cycles");
+ test_fail = 1;
+ end
+ join_any
+ disable fork; //disable pending fork activity
+
+ // Read Back the Failure Address and cross-check all the 8 MBIST
+ for(j=0; j < `NO_SRAM; j=j+1) begin
+ fail_addr1 = faultaddr[0]+j;
+ fail_addr2 = faultaddr[1]+j;
+ fail_addr3 = faultaddr[2]+j;
+ fail_addr4 = faultaddr[3]+j;
+
+ // Select the Serial SDI/SDO interface
+ wb_user_core_write(`GLBL_BIST_CTRL1,j << 28);
+ if(num_fault == 1)
+ wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{16'h0,7'h0,fail_addr1},32'h0000_FFFF);
+ if(num_fault == 2)
+ wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{7'h0,fail_addr2,7'h0,fail_addr1},32'hFFFF_FFFF);
+ if(num_fault == 3) begin
+ wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{7'h0,fail_addr2,7'h0,fail_addr1},32'hFFFF_FFFF);
+ wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{16'h0,7'h0,fail_addr3},32'h0000_FFFF);
+ end
+ if(num_fault >= 4) begin
+ wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{7'h0,fail_addr2,7'h0,fail_addr1},32'hFFFF_FFFF);
+ wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{7'h0,faultaddr[3]+j,7'h0,fail_addr3},32'hFFFF_FFFF);
+ end
+ end
+end
+endtask
+
+
+task wb_user_core_write;
+input [31:0] address;
+input [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h1; // write
+ wbd_ext_dat_i =data; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data);
+ repeat (2) @(posedge clock);
+end
+endtask
+
+task wb_user_core_read;
+input [31:0] address;
+output [31:0] data;
+reg [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='0; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ #1;
+ data = wbd_ext_dat_o;
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ //$display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
+ repeat (2) @(posedge clock);
+end
+endtask
+
+task wb_user_core_read_check;
+input [31:0] address;
+output [31:0] data;
+input [31:0] cmp_data;
+input [31:0] cmp_mask;
+reg [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='0; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ #1;
+ data = wbd_ext_dat_o;
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ if((data & cmp_mask) !== (cmp_data & cmp_mask) ) begin
+ $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,(cmp_data & cmp_mask),(data & cmp_mask));
+ test_fail = 1;
+ end else begin
+ $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,(data & cmp_mask));
+ end
+ repeat (2) @(posedge clock);
+end
+endtask
+
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/user_risc_boot/Makefile b/verilog/dv/user_risc_boot/Makefile
index fa32693..549a5e5 100644
--- a/verilog/dv/user_risc_boot/Makefile
+++ b/verilog/dv/user_risc_boot/Makefile
@@ -33,6 +33,7 @@
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
+UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include
## SYNTACORE FIRMWARE
SYNTACORE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/rtl/syntacore/scr1/sim/tests/common
@@ -71,7 +72,7 @@
-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
-I $(UPRJ_BEHAVIOURAL_AGENTS) \
-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
- -I $(UPRJ_INCLUDE_PATH4) \
+ -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \
$< -o $@
else
iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
@@ -79,7 +80,7 @@
-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
-I $(UPRJ_BEHAVIOURAL_AGENTS) \
-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
- -I $(UPRJ_INCLUDE_PATH4) \
+ -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \
$< -o $@
endif
else
diff --git a/verilog/dv/user_risc_boot/user_risc_boot.c b/verilog/dv/user_risc_boot/user_risc_boot.c
index 63b2e6a..37e424b 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot.c
+++ b/verilog/dv/user_risc_boot/user_risc_boot.c
@@ -18,34 +18,34 @@
#define SC_SIM_OUTPORT (0xf0000000)
#define uint32_t long
-#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10030000)
-#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10030004)
-#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10030008)
-#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1003000C)
-#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10030010)
-#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10030014)
-#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x10030018)
-#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x1003001C)
-#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x10030020)
-#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x10030024)
-#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x10030028)
-#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x1003002C)
-#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x10030030)
-#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x10030034)
-#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x10030038)
-#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x1003003C)
-#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x10030040)
-#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x10030044)
-#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x10030048)
-#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x1003004C)
-#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x10030050)
-#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x10030054)
-#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x10030058)
-#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x1003005C)
-#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x10030060)
-#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x10030064)
-#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x10030068)
-#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x1003006C)
+#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000)
+#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004)
+#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008)
+#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C)
+#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010)
+#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014)
+#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x10020018)
+#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x1002001C)
+#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x10020020)
+#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x10020024)
+#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x10020028)
+#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x1002002C)
+#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x10020030)
+#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x10020034)
+#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x10020038)
+#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x1002003C)
+#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x10020040)
+#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x10020044)
+#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x10020048)
+#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x1002004C)
+#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x10020050)
+#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x10020054)
+#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x10020058)
+#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x1002005C)
+#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x10020060)
+#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x10020064)
+#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x10020068)
+#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x1002006C)
int main()
{
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
index f755905..aba5643 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -164,22 +164,22 @@
// 0x3000002C = 0x66778899;
test_fail = 0;
- wb_user_core_read(32'h30030058,read_data);
+ wb_user_core_read(32'h30020058,read_data);
if(read_data != 32'h11223344) test_fail = 1;
- wb_user_core_read(32'h3003005C,read_data);
+ wb_user_core_read(32'h3002005C,read_data);
if(read_data != 32'h22334455) test_fail = 1;
- wb_user_core_read(32'h30030060,read_data);
+ wb_user_core_read(32'h30020060,read_data);
if(read_data != 32'h33445566) test_fail = 1;
- wb_user_core_read(32'h30030064,read_data);
+ wb_user_core_read(32'h30020064,read_data);
if(read_data!= 32'h44556677) test_fail = 1;
- wb_user_core_read(32'h30030068,read_data);
+ wb_user_core_read(32'h30020068,read_data);
if(read_data!= 32'h55667788) test_fail = 1;
- wb_user_core_read(32'h3003006C,read_data) ;
+ wb_user_core_read(32'h3002006C,read_data) ;
if(read_data != 32'h66778899) test_fail = 1;
@@ -247,149 +247,6 @@
`ifndef GL // Drive Power for Hold Fix Buf
// All standard cell need power hook-up for functionality work
initial begin
- force u_top.u_qspi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio0.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio0.VGND =VSS;
- force u_top.u_qspi_master.u_delay1_sdio0.VNB = VSS;
- force u_top.u_qspi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio0.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio0.VGND =VSS;
- force u_top.u_qspi_master.u_delay2_sdio0.VNB = VSS;
- force u_top.u_qspi_master.u_buf_sdio0.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio0.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio0.VGND =VSS;
- force u_top.u_qspi_master.u_buf_sdio0.VNB =VSS;
-
- force u_top.u_qspi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio1.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio1.VGND =VSS;
- force u_top.u_qspi_master.u_delay1_sdio1.VNB = VSS;
- force u_top.u_qspi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio1.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio1.VGND =VSS;
- force u_top.u_qspi_master.u_delay2_sdio1.VNB = VSS;
- force u_top.u_qspi_master.u_buf_sdio1.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio1.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio1.VGND =VSS;
- force u_top.u_qspi_master.u_buf_sdio1.VNB =VSS;
-
- force u_top.u_qspi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio2.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio2.VGND =VSS;
- force u_top.u_qspi_master.u_delay1_sdio2.VNB = VSS;
- force u_top.u_qspi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio2.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio2.VGND =VSS;
- force u_top.u_qspi_master.u_delay2_sdio2.VNB = VSS;
- force u_top.u_qspi_master.u_buf_sdio2.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio2.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio2.VGND =VSS;
- force u_top.u_qspi_master.u_buf_sdio2.VNB =VSS;
-
- force u_top.u_qspi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio3.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio3.VGND =VSS;
- force u_top.u_qspi_master.u_delay1_sdio3.VNB = VSS;
- force u_top.u_qspi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio3.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio3.VGND =VSS;
- force u_top.u_qspi_master.u_delay2_sdio3.VNB = VSS;
- force u_top.u_qspi_master.u_buf_sdio3.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio3.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio3.VGND =VSS;
- force u_top.u_qspi_master.u_buf_sdio3.VNB =VSS;
-
- force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
- force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VPB =USER_VDD1V8;
- force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VGND =VSS;
- force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_wb_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_wb_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_wb_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_cpu_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_cpu_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_cpu_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_cpu_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_qspim_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_qspim_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_qspim_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_qspim_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_sspim_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_sspim_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_sspim_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_sspim_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_uart_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_uart_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_uart_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_uart_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_i2cm_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_i2cm_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_i2cm_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_i2cm_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_usb_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_usb_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_usb_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_usb_rst.VNB = VSS;
-
-
-
- force u_top.u_wb_host.u_clkbuf_cpu.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_cpu.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_cpu.VGND =VSS;
- force u_top.u_wb_host.u_clkbuf_cpu.VNB = VSS;
-
- force u_top.u_wb_host.u_clkbuf_rtc.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_rtc.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_rtc.VGND =VSS;
- force u_top.u_wb_host.u_clkbuf_rtc.VNB = VSS;
-
- force u_top.u_wb_host.u_clkbuf_usb.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_usb.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_usb.VGND =VSS;
- force u_top.u_wb_host.u_clkbuf_usb.VNB = VSS;
-
- force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VGND =VSS;
- force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VNB = VSS;
-
- force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VGND =VSS;
- force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VNB = VSS;
-
- force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VGND =VSS;
- force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VNB = VSS;
-
- force u_top.u_wb_host.u_usb_clk_sel.u_mux.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_usb_clk_sel.u_mux.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_usb_clk_sel.u_mux.VGND =VSS;
- force u_top.u_wb_host.u_usb_clk_sel.u_mux.VNB = VSS;
-
- force u_top.u_wb_host.u_delay1_stb0.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_delay1_stb0.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_delay1_stb0.VGND =VSS;
- force u_top.u_wb_host.u_delay1_stb0.VNB = VSS;
-
- force u_top.u_wb_host.u_delay2_stb1.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_delay2_stb1.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_delay2_stb1.VGND =VSS;
- force u_top.u_wb_host.u_delay2_stb1.VNB = VSS;
-
- force u_top.u_wb_host.u_delay2_stb2.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_delay2_stb2.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_delay2_stb2.VGND =VSS;
- force u_top.u_wb_host.u_delay2_stb2.VNB = VSS;
end
`endif
diff --git a/verilog/dv/user_risc_soft_boot/Makefile b/verilog/dv/user_risc_soft_boot/Makefile
new file mode 100644
index 0000000..381b34a
--- /dev/null
+++ b/verilog/dv/user_risc_soft_boot/Makefile
@@ -0,0 +1,111 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+## Caravel Pointers
+CARAVEL_ROOT ?= ../../../caravel
+CARAVEL_PATH ?= $(CARAVEL_ROOT)
+CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
+CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog
+CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
+CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+
+## User Project Pointers
+UPRJ_VERILOG_PATH ?= ../../../verilog
+UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
+UPRJ_BEHAVIOURAL_MODELS = ../model
+UPRJ_BEHAVIOURAL_AGENTS = ../agents
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes
+UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
+UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
+UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
+UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include
+
+## SYNTACORE FIRMWARE
+SYNTACORE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/rtl/syntacore/scr1/sim/tests/common
+GCC64_PREFIX?=riscv64-unknown-elf
+
+## RISCV GCC
+GCC_PATH?=/ef/apps/bin
+GCC32_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/ef/tech/SW/sky130A
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+
+.SUFFIXES:
+
+PATTERN = user_risc_soft_boot
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+vvp: ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+ ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common user_risc_boot.c -o user_risc_boot.o
+ ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common/ ../../rtl/syntacore/scr1/sim/tests/common/crt_tcm.S -o crt_tcm.o
+ ${GCC64_PREFIX}-gcc -o user_risc_boot.elf -T ../../rtl/syntacore/scr1/sim/tests/common/link_tcm.ld user_risc_boot.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
+ ${GCC64_PREFIX}-objcopy -O verilog user_risc_boot.elf user_risc_boot.hex
+ ${GCC64_PREFIX}-objdump -D user_risc_boot.elf > user_risc_boot.dump
+ rm crt_tcm.o user_risc_boot.o
+ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
+ iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_AGENTS) \
+ -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
+ -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \
+ $< -o $@
+ else
+ iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_AGENTS) \
+ -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
+ -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \
+ $< -o $@
+ endif
+else
+ iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_AGENTS) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s
+ ${GCC64_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
+
+%.hex:
+ echo @"This is user boot test, noting to compile the mangment core code"
+
+%.bin: %.elf
+ ${GCC64_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump
+
+.PHONY: clean hex all
diff --git a/verilog/dv/user_risc_soft_boot/run_iverilog b/verilog/dv/user_risc_soft_boot/run_iverilog
new file mode 100755
index 0000000..56414f8
--- /dev/null
+++ b/verilog/dv/user_risc_soft_boot/run_iverilog
@@ -0,0 +1,49 @@
+# //////////////////////////////////////////////////////////////////////////////
+# // SPDX-FileCopyrightText: 2021, Dinesh Annayya
+# //
+# // Licensed under the Apache License, Version 2.0 (the "License");
+# // you may not use this file except in compliance with the License.
+# // You may obtain a copy of the License at
+# //
+# // http://www.apache.org/licenses/LICENSE-2.0
+# //
+# // Unless required by applicable law or agreed to in writing, software
+# // distributed under the License is distributed on an "AS IS" BASIS,
+# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# // See the License for the specific language governing permissions and
+# // limitations under the License.
+# // SPDX-License-Identifier: Apache-2.0
+# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+# // //////////////////////////////////////////////////////////////////////////
+
+riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common user_risc_boot.c -o user_risc_boot.o
+
+riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common/ ../../rtl/syntacore/scr1/sim/tests/common/crt_tcm.S -o crt_tcm.o
+
+riscv64-unknown-elf-gcc -o user_risc_boot.elf -T ../../rtl/syntacore/scr1/sim/tests/common/link_tcm.ld user_risc_boot.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32
+
+riscv64-unknown-elf-objcopy -O verilog user_risc_boot.elf user_risc_boot.hex
+
+riscv64-unknown-elf-objdump -D user_risc_boot.elf > user_risc_boot.dump
+
+rm crt_tcm.o user_risc_boot.o
+
+#iverilog with waveform dump
+
+iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $PDK_PATH \
+-I /home/dinesha/workarea/opencore/git/riscduino/caravel/verilog/dv/caravel -I /home/dinesha/workarea/opencore/git/riscduino/caravel/verilog/rtl \
+-I ../model -I ../../../verilog/rtl -I ../../../verilog \
+-I ../agents \
+-I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I ../../../verilog/rtl/i2cm/src/includes \
+-I ../../../verilog/rtl/usb1_host/src/includes -I ../../../verilog/rtl/mbist/include \
+user_risc_soft_boot_tb.v -o user_risc_soft_boot.vvp
+
+
+#iverilog -g2005-sv -I $PDK_PATH -DFUNCTIONAL -DSIM -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/rtl -I ../../../verilog -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_risc_boot_tb.v -o user_risc_boot_tb.vvp
+
+# GLS
+#iverilog -g2005-sv -DGL -I $PDK_PATH -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/rtl -I ../../../verilog -I /home/dinesha/workarea/pdk/sky130A -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_risc_boot_tb.vvp
+
+vvp user_risc_soft_boot.vvp | tee test.log
+
+\rm -rf user_risc_soft_boot.vvp
diff --git a/verilog/dv/user_risc_soft_boot/user_risc_boot.c b/verilog/dv/user_risc_soft_boot/user_risc_boot.c
new file mode 100644
index 0000000..37e424b
--- /dev/null
+++ b/verilog/dv/user_risc_soft_boot/user_risc_boot.c
@@ -0,0 +1,73 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021, Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+// //////////////////////////////////////////////////////////////////////////
+#define SC_SIM_OUTPORT (0xf0000000)
+#define uint32_t long
+
+#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000)
+#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004)
+#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008)
+#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C)
+#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010)
+#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014)
+#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x10020018)
+#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x1002001C)
+#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x10020020)
+#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x10020024)
+#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x10020028)
+#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x1002002C)
+#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x10020030)
+#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x10020034)
+#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x10020038)
+#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x1002003C)
+#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x10020040)
+#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x10020044)
+#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x10020048)
+#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x1002004C)
+#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x10020050)
+#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x10020054)
+#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x10020058)
+#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x1002005C)
+#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x10020060)
+#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x10020064)
+#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x10020068)
+#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x1002006C)
+
+int main()
+{
+
+ //volatile long *out_ptr = (volatile long*)SC_SIM_OUTPORT;
+ //*out_ptr = 0xAABBCCDD;
+ //*out_ptr = 0xBBCCDDEE;
+ //*out_ptr = 0xCCDDEEFF;
+ //*out_ptr = 0xDDEEFF00;
+
+ // Write software Write & Read Register
+ reg_mprj_globl_reg22 = 0x11223344;
+ reg_mprj_globl_reg23 = 0x22334455;
+ reg_mprj_globl_reg24 = 0x33445566;
+ reg_mprj_globl_reg25 = 0x44556677;
+ reg_mprj_globl_reg26 = 0x55667788;
+ reg_mprj_globl_reg27 = 0x66778899;
+ //reg_mprj_globl_reg12 = 0x778899AA;
+ //reg_mprj_globl_reg13 = 0x8899AABB;
+ //reg_mprj_globl_reg14 = 0x99AABBCC;
+ //reg_mprj_globl_reg15 = 0xAABBCCDD;
+
+ while(1) {}
+ return 0;
+}
diff --git a/verilog/dv/user_risc_soft_boot/user_risc_soft_boot_tb.v b/verilog/dv/user_risc_soft_boot/user_risc_soft_boot_tb.v
new file mode 100644
index 0000000..278e07f
--- /dev/null
+++ b/verilog/dv/user_risc_soft_boot/user_risc_soft_boot_tb.v
@@ -0,0 +1,383 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Standalone User validation Test bench ////
+//// ////
+//// This file is part of the YIFive cores project ////
+//// https://github.com/dineshannayya/yifive_r0.git ////
+//// http://www.opencores.org/cores/yifive/ ////
+//// ////
+//// Description ////
+//// This is a standalone test bench to validate the ////
+//// Digital core. ////
+//// 1. User Risc core is booted using compiled code of ////
+//// user_risc_boot.c ////
+//// 2. User Risc core uses Serial Flash and SDRAM to boot ////
+//// 3. After successful boot, Risc core will write signature ////
+//// in to user register from 0x1003_0058 to 0x1003_006C ////
+//// 4. Through the External Wishbone Interface we read back ////
+//// from 0x3003_0058 to 0x3003_006C ////
+//// and validate the user register to declared pass fail ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 16th Feb 2021, Dinesh A ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ns
+
+`include "uprj_netlists.v"
+
+module user_risc_soft_boot_tb;
+ reg clock;
+ reg wb_rst_i;
+ reg power1, power2;
+ reg power3, power4;
+
+ reg wbd_ext_cyc_i; // strobe/request
+ reg wbd_ext_stb_i; // strobe/request
+ reg [31:0] wbd_ext_adr_i; // address
+ reg wbd_ext_we_i; // write
+ reg [31:0] wbd_ext_dat_i; // data output
+ reg [3:0] wbd_ext_sel_i; // byte enable
+
+ wire [31:0] wbd_ext_dat_o; // data input
+ wire wbd_ext_ack_o; // acknowlegement
+ wire wbd_ext_err_o; // error
+
+ // User I/O
+ wire [37:0] io_oeb;
+ wire [37:0] io_out;
+ wire [37:0] io_in;
+
+ wire gpio;
+ wire [37:0] mprj_io;
+ wire [7:0] mprj_io_0;
+ reg test_fail;
+ reg [31:0] read_data;
+ logic [7:0] tem_mem[0:4095];
+ logic [31:0] tem_mem_32b[0:511];
+
+ `ifdef VERILATOR
+ logic [255:0] test_ram_file;
+ `else // VERILATOR
+
+ string test_ram_file;
+
+ `endif // VERILATOR
+
+ integer i;
+
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #12.5 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ end
+
+ `ifdef WFDUMP
+ initial begin
+ $dumpfile("simx.vcd");
+ $dumpvars(4, user_risc_soft_boot_tb);
+ end
+ `endif
+
+ initial begin
+
+ #200; // Wait for reset removal
+ repeat (10) @(posedge clock);
+ $display("Monitor: Standalone User Risc Boot Test Started");
+
+ // Remove Wb Reset
+ wb_user_core_write('h3080_0000,'h1);
+
+ $readmemh("user_risc_boot.hex",tem_mem);
+ // convert 8 bit 32 mem format
+ for(i =0; i < 511; i = i+1)
+ tem_mem_32b[i] = {tem_mem[(i*4)+3],tem_mem[(i*4)+2],tem_mem[(i*4)+1],tem_mem[(i*4)]};
+
+ $writememh("sram_bank0.hex",tem_mem_32b,0,511);
+ $readmemh("sram_bank0.hex",u_top.u_sram1_2kb.mem,0,511);
+
+ for(i =512; i < 1023; i = i+1)
+ tem_mem_32b[i-512] = {tem_mem[(i*4)+3],tem_mem[(i*4)+2],tem_mem[(i*4)+1],tem_mem[(i*4)]};
+
+ $writememh("sram_bank1.hex",tem_mem_32b,0,511);
+ $readmemh("sram_bank1.hex",u_top.u_sram2_2kb.mem,0,511);
+
+ // Enable the SRAM Remap to boot region
+ wb_user_core_write('h3080_000C,{4'b1111,28'h0});
+ repeat (2) @(posedge clock);
+ #1;
+ // Remove the reset, mbist, wishbone, riscv
+ wb_user_core_write('h3080_0000,'h83);
+
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (10) begin
+ repeat (400) @(posedge clock);
+ // $display("+1000 cycles");
+ end
+
+
+ $display("Monitor: Reading Back the expected value");
+ // User RISC core expect to write these value in global
+ // register, read back and decide on pass fail
+ // 0x30000018 = 0x11223344;
+ // 0x3000001C = 0x22334455;
+ // 0x30000020 = 0x33445566;
+ // 0x30000024 = 0x44556677;
+ // 0x30000028 = 0x55667788;
+ // 0x3000002C = 0x66778899;
+
+ test_fail = 0;
+ wb_user_core_read(32'h30020058,read_data);
+ if(read_data != 32'h11223344) test_fail = 1;
+
+ wb_user_core_read(32'h3002005C,read_data);
+ if(read_data != 32'h22334455) test_fail = 1;
+
+ wb_user_core_read(32'h30020060,read_data);
+ if(read_data != 32'h33445566) test_fail = 1;
+
+ wb_user_core_read(32'h30020064,read_data);
+ if(read_data!= 32'h44556677) test_fail = 1;
+
+ wb_user_core_read(32'h30020068,read_data);
+ if(read_data!= 32'h55667788) test_fail = 1;
+
+ wb_user_core_read(32'h3002006C,read_data) ;
+ if(read_data != 32'h66778899) test_fail = 1;
+
+
+ $display("###################################################");
+ if(test_fail == 0) begin
+ `ifdef GL
+ $display("Monitor: Standalone User Risc Boot (GL) Passed");
+ `else
+ $display("Monitor: Standalone User Risc Boot (RTL) Passed");
+ `endif
+ end else begin
+ `ifdef GL
+ $display("Monitor: Standalone User Risc Boot (GL) Failed");
+ `else
+ $display("Monitor: Standalone User Risc Boot (RTL) Failed");
+ `endif
+ end
+ $display("###################################################");
+ $finish;
+ end
+
+ initial begin
+ wb_rst_i <= 1'b1;
+ #100;
+ wb_rst_i <= 1'b0; // Release reset
+ end
+wire USER_VDD1V8 = 1'b1;
+wire VSS = 1'b0;
+
+user_project_wrapper u_top(
+`ifdef USE_POWER_PINS
+ .vccd1(USER_VDD1V8), // User area 1 1.8V supply
+ .vssd1(VSS), // User area 1 digital ground
+`endif
+ .wb_clk_i (clock), // System clock
+ .user_clock2 (1'b1), // Real-time clock
+ .wb_rst_i (wb_rst_i), // Regular Reset signal
+
+ .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
+ .wbs_stb_i (wbd_ext_stb_i), // strobe/request
+ .wbs_adr_i (wbd_ext_adr_i), // address
+ .wbs_we_i (wbd_ext_we_i), // write
+ .wbs_dat_i (wbd_ext_dat_i), // data output
+ .wbs_sel_i (wbd_ext_sel_i), // byte enable
+
+ .wbs_dat_o (wbd_ext_dat_o), // data input
+ .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
+
+
+ // Logic Analyzer Signals
+ .la_data_in ('0) ,
+ .la_data_out (),
+ .la_oenb ('0),
+
+
+ // IOs
+ .io_in (io_in) ,
+ .io_out (io_out) ,
+ .io_oeb (io_oeb) ,
+
+ .user_irq ()
+
+);
+
+`ifndef GL // Drive Power for Hold Fix Buf
+ // All standard cell need power hook-up for functionality work
+ initial begin
+
+ end
+`endif
+
+
+
+task wb_user_core_write;
+input [31:0] address;
+input [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h1; // write
+ wbd_ext_dat_i =data; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
+ repeat (2) @(posedge clock);
+end
+endtask
+
+task wb_user_core_read;
+input [31:0] address;
+output [31:0] data;
+reg [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='0; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ data = wbd_ext_dat_o;
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
+ repeat (2) @(posedge clock);
+end
+endtask
+
+`ifdef GL
+
+wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i;
+wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o;
+wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o;
+wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i;
+
+wire wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i;
+wire wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o;
+wire wbd_sdram_we_i = u_top.u_sdram_ctrl.wb_we_i;
+wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i;
+wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i;
+wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
+wire [3:0] wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;
+
+wire wbd_uart_stb_i = u_top.u_uart_i2c_usb.reg_cs;
+wire wbd_uart_ack_o = u_top.u_uart_i2c_usb.reg_ack;
+wire wbd_uart_we_i = u_top.u_uart_i2c_usb.reg_wr;
+wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb.reg_addr;
+wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb.reg_wdata;
+wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb.reg_rdata;
+wire wbd_uart_sel_i = u_top.u_uart_i2c_usb.reg_be;
+
+`endif
+
+/**
+`ifdef GL
+//-----------------------------------------------------------------------------
+// RISC IMEM amd DMEM Monitoring TASK
+//-----------------------------------------------------------------------------
+
+`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
+
+always@(posedge `RISC_CORE.wb_clk) begin
+ if(`RISC_CORE.wbd_imem_ack_i)
+ $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
+ if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
+ $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
+ if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
+ $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
+end
+
+`endif
+**/
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/user_spi/Makefile b/verilog/dv/user_spi/Makefile
index 054ec11..37f26fe 100644
--- a/verilog/dv/user_spi/Makefile
+++ b/verilog/dv/user_spi/Makefile
@@ -33,6 +33,7 @@
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
+UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include
## SYNTACORE FIRMWARE
SYNTACORE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/rtl/syntacore/scr1/sim/tests/common
@@ -71,7 +72,7 @@
-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
-I $(UPRJ_BEHAVIOURAL_AGENTS) \
-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
- -I $(UPRJ_INCLUDE_PATH4) \
+ -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \
$< -o $@
else
iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
@@ -79,7 +80,7 @@
-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
-I $(UPRJ_BEHAVIOURAL_AGENTS) \
-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
- -I $(UPRJ_INCLUDE_PATH4) \
+ -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \
$< -o $@
endif
else
diff --git a/verilog/dv/user_spi/user_spi_tb.v b/verilog/dv/user_spi/user_spi_tb.v
index 37105bd..0e662bf 100644
--- a/verilog/dv/user_spi/user_spi_tb.v
+++ b/verilog/dv/user_spi/user_spi_tb.v
@@ -1124,149 +1124,6 @@
`ifndef GL // Drive Power for Hold Fix Buf
// All standard cell need power hook-up for functionality work
initial begin
- force u_top.u_qspi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio0.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio0.VGND =VSS;
- force u_top.u_qspi_master.u_delay1_sdio0.VNB = VSS;
- force u_top.u_qspi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio0.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio0.VGND =VSS;
- force u_top.u_qspi_master.u_delay2_sdio0.VNB = VSS;
- force u_top.u_qspi_master.u_buf_sdio0.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio0.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio0.VGND =VSS;
- force u_top.u_qspi_master.u_buf_sdio0.VNB =VSS;
-
- force u_top.u_qspi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio1.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio1.VGND =VSS;
- force u_top.u_qspi_master.u_delay1_sdio1.VNB = VSS;
- force u_top.u_qspi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio1.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio1.VGND =VSS;
- force u_top.u_qspi_master.u_delay2_sdio1.VNB = VSS;
- force u_top.u_qspi_master.u_buf_sdio1.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio1.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio1.VGND =VSS;
- force u_top.u_qspi_master.u_buf_sdio1.VNB =VSS;
-
- force u_top.u_qspi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio2.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio2.VGND =VSS;
- force u_top.u_qspi_master.u_delay1_sdio2.VNB = VSS;
- force u_top.u_qspi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio2.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio2.VGND =VSS;
- force u_top.u_qspi_master.u_delay2_sdio2.VNB = VSS;
- force u_top.u_qspi_master.u_buf_sdio2.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio2.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio2.VGND =VSS;
- force u_top.u_qspi_master.u_buf_sdio2.VNB =VSS;
-
- force u_top.u_qspi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio3.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio3.VGND =VSS;
- force u_top.u_qspi_master.u_delay1_sdio3.VNB = VSS;
- force u_top.u_qspi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio3.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio3.VGND =VSS;
- force u_top.u_qspi_master.u_delay2_sdio3.VNB = VSS;
- force u_top.u_qspi_master.u_buf_sdio3.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio3.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio3.VGND =VSS;
- force u_top.u_qspi_master.u_buf_sdio3.VNB =VSS;
-
- force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
- force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VPB =USER_VDD1V8;
- force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VGND =VSS;
- force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_wb_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_wb_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_wb_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_cpu_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_cpu_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_cpu_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_cpu_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_qspim_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_qspim_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_qspim_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_qspim_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_sspim_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_sspim_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_sspim_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_sspim_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_uart_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_uart_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_uart_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_uart_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_i2cm_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_i2cm_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_i2cm_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_i2cm_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_usb_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_usb_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_usb_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_usb_rst.VNB = VSS;
-
-
-
- force u_top.u_wb_host.u_clkbuf_cpu.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_cpu.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_cpu.VGND =VSS;
- force u_top.u_wb_host.u_clkbuf_cpu.VNB = VSS;
-
- force u_top.u_wb_host.u_clkbuf_rtc.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_rtc.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_rtc.VGND =VSS;
- force u_top.u_wb_host.u_clkbuf_rtc.VNB = VSS;
-
- force u_top.u_wb_host.u_clkbuf_usb.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_usb.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_usb.VGND =VSS;
- force u_top.u_wb_host.u_clkbuf_usb.VNB = VSS;
-
- force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VGND =VSS;
- force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VNB = VSS;
-
- force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VGND =VSS;
- force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VNB = VSS;
-
- force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VGND =VSS;
- force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VNB = VSS;
-
- force u_top.u_wb_host.u_usb_clk_sel.u_mux.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_usb_clk_sel.u_mux.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_usb_clk_sel.u_mux.VGND =VSS;
- force u_top.u_wb_host.u_usb_clk_sel.u_mux.VNB = VSS;
-
- force u_top.u_wb_host.u_delay1_stb0.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_delay1_stb0.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_delay1_stb0.VGND =VSS;
- force u_top.u_wb_host.u_delay1_stb0.VNB = VSS;
-
- force u_top.u_wb_host.u_delay2_stb1.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_delay2_stb1.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_delay2_stb1.VGND =VSS;
- force u_top.u_wb_host.u_delay2_stb1.VNB = VSS;
-
- force u_top.u_wb_host.u_delay2_stb2.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_delay2_stb2.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_delay2_stb2.VGND =VSS;
- force u_top.u_wb_host.u_delay2_stb2.VNB = VSS;
end
`endif
diff --git a/verilog/dv/user_uart/Makefile b/verilog/dv/user_uart/Makefile
index fa0a9cf..401a399 100644
--- a/verilog/dv/user_uart/Makefile
+++ b/verilog/dv/user_uart/Makefile
@@ -33,6 +33,7 @@
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
+UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include
## SYNTACORE FIRMWARE
SYNTACORE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/rtl/syntacore/scr1/sim/tests/common
@@ -71,7 +72,7 @@
-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
-I $(UPRJ_BEHAVIOURAL_AGENTS) \
-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
- -I $(UPRJ_INCLUDE_PATH4) \
+ -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \
$< -o $@
else
iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
@@ -79,7 +80,7 @@
-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
-I $(UPRJ_BEHAVIOURAL_AGENTS) \
-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
- -I $(UPRJ_INCLUDE_PATH4) \
+ -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \
$< -o $@
endif
else
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index 5daa8e4..c459f5d 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -80,7 +80,8 @@
`include "uart_agent.v"
-`define ADDR_SPACE_UART 32'h3001_0000
+`define ADDR_SPACE_UART 32'h3001_0000
+`define ADDR_SPACE_PINMUX 32'h3002_0000
module user_uart_tb;
@@ -178,7 +179,7 @@
wb_user_core_write('h3080_0000,'h1);
// Enable UART Multi Functional Ports
- wb_user_core_write('h3003_0038,'h100);
+ wb_user_core_write(`ADDR_SPACE_PINMUX+'h0038,'h100);
repeat (2) @(posedge clock);
#1;
@@ -289,149 +290,6 @@
`ifndef GL // Drive Power for Hold Fix Buf
// All standard cell need power hook-up for functionality work
initial begin
- force u_top.u_qspi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio0.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio0.VGND =VSS;
- force u_top.u_qspi_master.u_delay1_sdio0.VNB = VSS;
- force u_top.u_qspi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio0.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio0.VGND =VSS;
- force u_top.u_qspi_master.u_delay2_sdio0.VNB = VSS;
- force u_top.u_qspi_master.u_buf_sdio0.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio0.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio0.VGND =VSS;
- force u_top.u_qspi_master.u_buf_sdio0.VNB =VSS;
-
- force u_top.u_qspi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio1.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio1.VGND =VSS;
- force u_top.u_qspi_master.u_delay1_sdio1.VNB = VSS;
- force u_top.u_qspi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio1.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio1.VGND =VSS;
- force u_top.u_qspi_master.u_delay2_sdio1.VNB = VSS;
- force u_top.u_qspi_master.u_buf_sdio1.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio1.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio1.VGND =VSS;
- force u_top.u_qspi_master.u_buf_sdio1.VNB =VSS;
-
- force u_top.u_qspi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio2.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio2.VGND =VSS;
- force u_top.u_qspi_master.u_delay1_sdio2.VNB = VSS;
- force u_top.u_qspi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio2.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio2.VGND =VSS;
- force u_top.u_qspi_master.u_delay2_sdio2.VNB = VSS;
- force u_top.u_qspi_master.u_buf_sdio2.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio2.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio2.VGND =VSS;
- force u_top.u_qspi_master.u_buf_sdio2.VNB =VSS;
-
- force u_top.u_qspi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio3.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio3.VGND =VSS;
- force u_top.u_qspi_master.u_delay1_sdio3.VNB = VSS;
- force u_top.u_qspi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio3.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio3.VGND =VSS;
- force u_top.u_qspi_master.u_delay2_sdio3.VNB = VSS;
- force u_top.u_qspi_master.u_buf_sdio3.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio3.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio3.VGND =VSS;
- force u_top.u_qspi_master.u_buf_sdio3.VNB =VSS;
-
- force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
- force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VPB =USER_VDD1V8;
- force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VGND =VSS;
- force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_wb_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_wb_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_wb_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_cpu_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_cpu_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_cpu_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_cpu_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_qspim_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_qspim_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_qspim_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_qspim_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_sspim_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_sspim_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_sspim_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_sspim_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_uart_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_uart_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_uart_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_uart_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_i2cm_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_i2cm_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_i2cm_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_i2cm_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_usb_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_usb_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_usb_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_usb_rst.VNB = VSS;
-
-
-
- force u_top.u_wb_host.u_clkbuf_cpu.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_cpu.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_cpu.VGND =VSS;
- force u_top.u_wb_host.u_clkbuf_cpu.VNB = VSS;
-
- force u_top.u_wb_host.u_clkbuf_rtc.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_rtc.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_rtc.VGND =VSS;
- force u_top.u_wb_host.u_clkbuf_rtc.VNB = VSS;
-
- force u_top.u_wb_host.u_clkbuf_usb.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_usb.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_usb.VGND =VSS;
- force u_top.u_wb_host.u_clkbuf_usb.VNB = VSS;
-
- force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VGND =VSS;
- force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VNB = VSS;
-
- force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VGND =VSS;
- force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VNB = VSS;
-
- force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VGND =VSS;
- force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VNB = VSS;
-
- force u_top.u_wb_host.u_usb_clk_sel.u_mux.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_usb_clk_sel.u_mux.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_usb_clk_sel.u_mux.VGND =VSS;
- force u_top.u_wb_host.u_usb_clk_sel.u_mux.VNB = VSS;
-
- force u_top.u_wb_host.u_delay1_stb0.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_delay1_stb0.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_delay1_stb0.VGND =VSS;
- force u_top.u_wb_host.u_delay1_stb0.VNB = VSS;
-
- force u_top.u_wb_host.u_delay2_stb1.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_delay2_stb1.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_delay2_stb1.VGND =VSS;
- force u_top.u_wb_host.u_delay2_stb1.VNB = VSS;
-
- force u_top.u_wb_host.u_delay2_stb2.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_delay2_stb2.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_delay2_stb2.VGND =VSS;
- force u_top.u_wb_host.u_delay2_stb2.VNB = VSS;
end
`endif
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile
index aecb8cf..6e144bf 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/wb_port/Makefile
@@ -14,6 +14,9 @@
#
# SPDX-License-Identifier: Apache-2.0
+## PDK
+PDK_PATH = $(PDK_ROOT)/sky130A
+
## Caravel Pointers
CARAVEL_ROOT ?= ../../../caravel
CARAVEL_PATH ?= $(CARAVEL_ROOT)
@@ -31,14 +34,14 @@
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
-
+UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include
## RISCV GCC
GCC_PATH?=/ef/apps/bin
GCC_PREFIX?=riscv32-unknown-elf
GCC64_PREFIX?=riscv64-unknown-elf
-PDK_PATH?=/ef/tech/SW/sky130A
## Simulation mode: RTL/GL
+SIM_DEFINES = -DFUNCTIONAL -DSIM
SIM?=RTL
DUMP?=OFF
@@ -55,22 +58,22 @@
%.vvp: %_tb.v %.hex
ifeq ($(SIM),RTL)
ifeq ($(DUMP),OFF)
- iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ iverilog -g2005-sv $(SIM_DEFINES) -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
- -I $(UPRJ_INCLUDE_PATH4) \
+ -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \
$< -o $@
else
- iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ iverilog -g2005-sv -DWFDUMP $(SIM_DEFINES) -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
- -I $(UPRJ_INCLUDE_PATH4) \
+ -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \
$< -o $@
endif
else
- iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+ iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_GL_PATH) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
$< -o $@
@@ -79,7 +82,7 @@
%.vcd: %.vvp
vvp $<
-%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s
+%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env
${GCC64_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
%.hex: %.elf
@@ -88,7 +91,22 @@
sed -i 's/@10000000/@00000000/g' $@
%.bin: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+ ${GCC64_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+#ifeq (,$(wildcard $(GCC64_PREFIX)-gcc ))
+# $(error $(GCC64_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+#endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
# ---- Clean ----
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c
index 28c72cd..cecab07 100644
--- a/verilog/dv/wb_port/wb_port.c
+++ b/verilog/dv/wb_port/wb_port.c
@@ -23,34 +23,34 @@
#define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
#define reg_mprj_wbhost_reg0 (*(volatile uint32_t*)0x30800000)
-#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x30030000)
-#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x30030004)
-#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x30030008)
-#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x3003000C)
-#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x30030010)
-#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x30030014)
-#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x30030018)
-#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x3003001C)
-#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x30030020)
-#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x30030024)
-#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x30030028)
-#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x3003002C)
-#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x30030030)
-#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x30030034)
-#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30030038)
-#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3003003C)
-#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x30030040)
-#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x30030044)
-#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x30030048)
-#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x3003004C)
-#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x30030050)
-#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x30030054)
-#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x30030058)
-#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x3003005C)
-#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x30030060)
-#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x30030064)
-#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x30030068)
-#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x3003006C)
+#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x30020000)
+#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x30020004)
+#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x30020008)
+#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x3002000C)
+#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x30020010)
+#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x30020014)
+#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x30020018)
+#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x3002001C)
+#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x30020020)
+#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x30020024)
+#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x30020028)
+#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x3002002C)
+#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x30020030)
+#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x30020034)
+#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30020038)
+#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3002003C)
+#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x30020040)
+#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x30020044)
+#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x30020048)
+#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x3002004C)
+#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x30020050)
+#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x30020054)
+#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x30020058)
+#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x3002005C)
+#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x30020060)
+#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x30020064)
+#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x30020068)
+#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x3002006C)
/*
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v
index ca9819f..88e8bee 100644
--- a/verilog/dv/wb_port/wb_port_tb.v
+++ b/verilog/dv/wb_port/wb_port_tb.v
@@ -169,148 +169,6 @@
`ifndef GL // Drive Power for Hold Fix Buf
// All standard cell need power hook-up for functionality work
initial begin
- force uut.mprj.u_qspi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay1_sdio0.VPB =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay1_sdio0.VGND =VSS;
- force uut.mprj.u_qspi_master.u_delay1_sdio0.VNB = VSS;
- force uut.mprj.u_qspi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay2_sdio0.VPB =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay2_sdio0.VGND =VSS;
- force uut.mprj.u_qspi_master.u_delay2_sdio0.VNB = VSS;
- force uut.mprj.u_qspi_master.u_buf_sdio0.VPWR =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_buf_sdio0.VPB =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_buf_sdio0.VGND =VSS;
- force uut.mprj.u_qspi_master.u_buf_sdio0.VNB =VSS;
-
-
- force uut.mprj.u_qspi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay1_sdio1.VPB =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay1_sdio1.VGND =VSS;
- force uut.mprj.u_qspi_master.u_delay1_sdio1.VNB = VSS;
- force uut.mprj.u_qspi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay2_sdio1.VPB =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay2_sdio1.VGND =VSS;
- force uut.mprj.u_qspi_master.u_delay2_sdio1.VNB = VSS;
- force uut.mprj.u_qspi_master.u_buf_sdio1.VPWR =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_buf_sdio1.VPB =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_buf_sdio1.VGND =VSS;
- force uut.mprj.u_qspi_master.u_buf_sdio1.VNB =VSS;
-
- force uut.mprj.u_qspi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay1_sdio2.VPB =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay1_sdio2.VGND =VSS;
- force uut.mprj.u_qspi_master.u_delay1_sdio2.VNB = VSS;
- force uut.mprj.u_qspi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay2_sdio2.VPB =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay2_sdio2.VGND =VSS;
- force uut.mprj.u_qspi_master.u_delay2_sdio2.VNB = VSS;
- force uut.mprj.u_qspi_master.u_buf_sdio2.VPWR =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_buf_sdio2.VPB =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_buf_sdio2.VGND =VSS;
- force uut.mprj.u_qspi_master.u_buf_sdio2.VNB =VSS;
-
- force uut.mprj.u_qspi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay1_sdio3.VPB =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay1_sdio3.VGND =VSS;
- force uut.mprj.u_qspi_master.u_delay1_sdio3.VNB = VSS;
- force uut.mprj.u_qspi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay2_sdio3.VPB =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_delay2_sdio3.VGND =VSS;
- force uut.mprj.u_qspi_master.u_delay2_sdio3.VNB = VSS;
- force uut.mprj.u_qspi_master.u_buf_sdio3.VPWR =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_buf_sdio3.VPB =USER_VDD1V8;
- force uut.mprj.u_qspi_master.u_buf_sdio3.VGND =VSS;
- force uut.mprj.u_qspi_master.u_buf_sdio3.VNB =VSS;
-
- force uut.mprj.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
- force uut.mprj.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VPB =USER_VDD1V8;
- force uut.mprj.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VGND =VSS;
- force uut.mprj.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_wb_rst.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_wb_rst.VGND =VSS;
- force uut.mprj.u_wb_host.u_buf_wb_rst.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_buf_cpu_rst.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_cpu_rst.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_cpu_rst.VGND =VSS;
- force uut.mprj.u_wb_host.u_buf_cpu_rst.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_buf_qspim_rst.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_qspim_rst.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_qspim_rst.VGND =VSS;
- force uut.mprj.u_wb_host.u_buf_qspim_rst.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_buf_sspim_rst.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_sspim_rst.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_sspim_rst.VGND =VSS;
- force uut.mprj.u_wb_host.u_buf_sspim_rst.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_buf_uart_rst.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_uart_rst.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_uart_rst.VGND =VSS;
- force uut.mprj.u_wb_host.u_buf_uart_rst.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_buf_i2cm_rst.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_i2cm_rst.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_i2cm_rst.VGND =VSS;
- force uut.mprj.u_wb_host.u_buf_i2cm_rst.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_buf_usb_rst.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_usb_rst.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_usb_rst.VGND =VSS;
- force uut.mprj.u_wb_host.u_buf_usb_rst.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_clkbuf_cpu.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_clkbuf_cpu.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_clkbuf_cpu.VGND =VSS;
- force uut.mprj.u_wb_host.u_clkbuf_cpu.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_clkbuf_rtc.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_clkbuf_rtc.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_clkbuf_rtc.VGND =VSS;
- force uut.mprj.u_wb_host.u_clkbuf_rtc.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_clkbuf_usb.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_clkbuf_usb.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_clkbuf_usb.VGND =VSS;
- force uut.mprj.u_wb_host.u_clkbuf_usb.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_cpu_ref_sel.u_mux.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_cpu_ref_sel.u_mux.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_cpu_ref_sel.u_mux.VGND =VSS;
- force uut.mprj.u_wb_host.u_cpu_ref_sel.u_mux.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_cpu_clk_sel.u_mux.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_cpu_clk_sel.u_mux.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_cpu_clk_sel.u_mux.VGND =VSS;
- force uut.mprj.u_wb_host.u_cpu_clk_sel.u_mux.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_wbs_clk_sel.u_mux.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_wbs_clk_sel.u_mux.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_wbs_clk_sel.u_mux.VGND =VSS;
- force uut.mprj.u_wb_host.u_wbs_clk_sel.u_mux.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_usb_clk_sel.u_mux.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_usb_clk_sel.u_mux.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_usb_clk_sel.u_mux.VGND =VSS;
- force uut.mprj.u_wb_host.u_usb_clk_sel.u_mux.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_delay1_stb0.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_delay1_stb0.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_delay1_stb0.VGND =VSS;
- force uut.mprj.u_wb_host.u_delay1_stb0.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_delay2_stb1.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_delay2_stb1.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_delay2_stb1.VGND =VSS;
- force uut.mprj.u_wb_host.u_delay2_stb1.VNB = VSS;
-
- force uut.mprj.u_wb_host.u_delay2_stb2.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_delay2_stb2.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_delay2_stb2.VGND =VSS;
- force uut.mprj.u_wb_host.u_delay2_stb2.VNB = VSS;
end
`endif
endmodule
diff --git a/verilog/rtl/lib/ctech_cells.sv b/verilog/rtl/lib/ctech_cells.sv
index fb61158..8e3b0de 100644
--- a/verilog/rtl/lib/ctech_cells.sv
+++ b/verilog/rtl/lib/ctech_cells.sv
@@ -5,6 +5,47 @@
input logic S ,
output logic X);
+`ifndef SYNTHESIS
+assign X = (S) ? A1 : A0;
+`else
sky130_fd_sc_hd__mux2_8 u_mux (.A0 (A0), .A1 (A1), .S (S), .X (X));
+`endif
endmodule
+
+module ctech_buf (
+ input logic A,
+ output logic X);
+
+`ifndef SYNTHESIS
+assign X = A;
+`else
+ sky130_fd_sc_hd__bufbuf_8 u_buf (.A(A),.X(X));
+`endif
+
+endmodule
+
+module ctech_clk_buf (
+ input logic A,
+ output logic X);
+
+`ifndef SYNTHESIS
+assign X = A;
+`else
+ sky130_fd_sc_hd__clkbuf_8 u_buf (.A(A),.X(X));
+`endif
+
+endmodule
+
+module ctech_delay_buf (
+ input logic A,
+ output logic X);
+
+`ifndef SYNTHESIS
+ assign X = A;
+`else
+ sky130_fd_sc_hd__dlygate4sd3_1 u_dly (.X(X),.A(A));
+`endif
+
+endmodule
+
diff --git a/verilog/rtl/lib/ser_inf_32b.sv b/verilog/rtl/lib/ser_inf_32b.sv
new file mode 100644
index 0000000..8228852
--- /dev/null
+++ b/verilog/rtl/lib/ser_inf_32b.sv
@@ -0,0 +1,121 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// ser_inf_32 ////
+//// ////
+//// This file is part of the mbist_ctrl cores project ////
+//// https://github.com/dineshannayya/mbist_ctrl.git ////
+//// ////
+//// Description ////
+//// This block manages the serial to Parallel conversion ////
+//// This block usefull for Bist SDI/SDO access ////
+//// Function: ////
+//// 1. When reg_wr=1, this block set shift=1 and shift ////
+//// reg_wdata serial through sdi for 32 cycles and ////
+//// asserts Reg Ack ////
+//// 2. When reg_rd=1, this block set shoft=1 and serial ////
+//// capture the sdo to reg_rdata for 32 cycles and ////
+//// asserts Reg Ack ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.0 - 20th Oct 2021, Dinesh A ////
+//// Initial integration ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+module ser_inf_32b
+ (
+
+ // Master Port
+ input logic rst_n , // Regular Reset signal
+ input logic clk , // System clock
+ input logic reg_wr , // Write Request
+ input logic reg_rd , // Read Request
+ input logic [31:0] reg_wdata , // data output
+ output logic [31:0] reg_rdata , // data input
+ output logic reg_ack , // acknowlegement
+
+ // Slave Port
+ output logic sdi , // Serial SDI
+ output logic shift , // Shift Signal
+ input logic sdo // Serial SDO
+
+ );
+
+
+ parameter IDLE = 1'b0;
+ parameter SHIFT_DATA = 1'b1;
+
+ logic state;
+ logic [5:0] bit_cnt;
+ logic [31:0] shift_data;
+
+
+always@(negedge rst_n or posedge clk)
+begin
+ if(rst_n == 0) begin
+ state <= IDLE;
+ reg_rdata <= 'h0;
+ reg_ack <= 1'b0;
+ sdi <= 1'b0;
+ bit_cnt <= 6'h0;
+ shift <= 'b0;
+ shift_data <= 32'h0;
+ end else begin
+ case(state)
+ IDLE: begin
+ reg_ack <= 1'b0;
+ bit_cnt <= 6'h0;
+ if(reg_wr) begin
+ shift <= 'b1;
+ shift_data <= reg_wdata;
+ state <= SHIFT_DATA;
+ end else if(reg_rd) begin
+ shift <= 'b1;
+ shift_data <= 'h0;
+ state <= SHIFT_DATA;
+ end
+ end
+ SHIFT_DATA: begin
+ shift_data <= {1'b0,shift_data[31:1]};
+ reg_rdata <= {sdo,reg_rdata[31:1]};
+ sdi <= shift_data[0];
+ if(bit_cnt < 31) begin
+ bit_cnt <= bit_cnt +1;
+ end else begin
+ reg_ack <= 1'b1;
+ shift <= 'b0;
+ state <= IDLE;
+ end
+ end
+ endcase
+ end
+end
+
+
+
+
+endmodule
diff --git a/verilog/rtl/mbist/include/mbist_def.svh b/verilog/rtl/mbist/include/mbist_def.svh
new file mode 100644
index 0000000..10fb2ea
--- /dev/null
+++ b/verilog/rtl/mbist/include/mbist_def.svh
@@ -0,0 +1,66 @@
+///////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+`ifndef BIST_DEFINE_SVH
+`define BIST_DEFINE_SVH
+
+// BIST ADDRESS CONTRL
+//
+//parameter BIST_ADDR_WD = 9 ;
+//parameter BIST_ADDR_START = 10'h000 ;
+//parameter BIST_ADDR_END = 10'h3FB ;
+
+// BIST DATA CONTRL
+//parameter BIST_DATA_WD = 32;
+parameter BIST_DATA_PAT_SIZE = 8;
+parameter BIST_DATA_PAT_TYPE1 = 64'h5555_5555_5555_5555;
+parameter BIST_DATA_PAT_TYPE2 = 64'h3333_3333_3333_3333;
+parameter BIST_DATA_PAT_TYPE3 = 64'h0F0F_0F0F_0F0F_0F0F;
+parameter BIST_DATA_PAT_TYPE4 = 64'h00FF_00FF_00FF_00FF;
+parameter BIST_DATA_PAT_TYPE5 = 64'h0000_FFFF_0000_FFFF;
+parameter BIST_DATA_PAT_TYPE6 = 64'h0000_0000_FFFF_FFFF;
+parameter BIST_DATA_PAT_TYPE7 = 64'hFFFF_FFFF_FFFF_FFFF;
+parameter BIST_DATA_PAT_TYPE8 = 64'h0000_0000_0000_0000;
+
+// BIST STIMULATION SELECT
+
+parameter BIST_STI_SIZE = 5;
+parameter BIST_STI_WD = 15;
+// Additional 3'b000 added at end of each stimulus to flush out the comparion
+// result + to handle error fix case
+parameter BIST_STIMULUS_TYPE1 = 15'b100100100100000;
+parameter BIST_STIMULUS_TYPE2 = 15'b100010101011000;
+parameter BIST_STIMULUS_TYPE3 = 15'b110011100010000;
+parameter BIST_STIMULUS_TYPE4 = 15'b000010101011000;
+parameter BIST_STIMULUS_TYPE5 = 15'b010011100010000;
+parameter BIST_STIMULUS_TYPE6 = 15'b000000000000000;
+parameter BIST_STIMULUS_TYPE7 = 15'b000000000000000;
+parameter BIST_STIMULUS_TYPE8 = 15'b000000000000000;
+
+
+// Operation
+parameter BIST_OP_SIZE = 4;
+
+// BIST ADDRESS REPAIR
+//parameter BIST_RAD_WD_I = BIST_ADDR_WD;
+//parameter BIST_RAD_WD_O = BIST_ADDR_WD;
+parameter BIST_ERR_LIMIT = 4;
+// Make Sure that this address in outside the valid address range
+//parameter BIST_REPAIR_ADDR_START = 10'h3FC ;
+
+`endif // BIST_DEFINE_SVH
diff --git a/verilog/rtl/mbist/run_iverilog b/verilog/rtl/mbist/run_iverilog
new file mode 100755
index 0000000..a88ada5
--- /dev/null
+++ b/verilog/rtl/mbist/run_iverilog
@@ -0,0 +1,18 @@
+iverilog -g2005-sv \
+src/top/mbist_top1.sv \
+src/core/mbist_addr_gen.sv \
+src/core/mbist_fsm.sv \
+src/core/mbist_op_sel.sv \
+src/core/mbist_repair_addr.sv \
+src/core/mbist_data_cmp.sv \
+src/core/mbist_mux.sv \
+src/core/mbist_pat_sel.sv \
+src/core/mbist_sti_sel.sv \
+src/core/mbist_mem_wrapper.sv \
+-I include/ \
+../lib/ctech_cells.sv \
+../lib/reset_sync.sv \
+$PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v \
+$PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v \
+--timescale 1ns/100ps \
+--bbox-unsup
diff --git a/verilog/rtl/mbist/run_verilator b/verilog/rtl/mbist/run_verilator
new file mode 100755
index 0000000..1dd5d6b
--- /dev/null
+++ b/verilog/rtl/mbist/run_verilator
@@ -0,0 +1,17 @@
+verilator -cc \
+src/top/mbist_top1.sv \
+src/core/mbist_addr_gen.sv \
+src/core/mbist_fsm.sv \
+src/core/mbist_op_sel.sv \
+src/core/mbist_repair_addr.sv \
+src/core/mbist_data_cmp.sv \
+src/core/mbist_mux.sv \
+src/core/mbist_pat_sel.sv \
+src/core/mbist_sti_sel.sv \
++incdir+include/ \
+../lib/ctech_cells.sv \
+../lib/reset_sync.sv \
+-v $PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v \
+-v $PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v \
+--timescale 1ns/100ps \
+--bbox-unsup
diff --git a/verilog/rtl/mbist/src/core/mbist_addr_gen.sv b/verilog/rtl/mbist/src/core/mbist_addr_gen.sv
new file mode 100644
index 0000000..584a2b6
--- /dev/null
+++ b/verilog/rtl/mbist/src/core/mbist_addr_gen.sv
@@ -0,0 +1,117 @@
+///////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// MBIST Address Generator ////
+//// ////
+//// This file is part of the mbist_ctrl cores project ////
+//// https://github.com/dineshannayya/mbist_ctrl.git ////
+//// ////
+//// Description ////
+//// This block integrate mbist address gen ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.0 - 11th Oct 2021, Dinesh A ////
+//// Initial integration ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+`include "mbist_def.svh"
+
+module mbist_addr_gen
+ #( parameter BIST_ADDR_WD = 9,
+ parameter BIST_DATA_WD = 32,
+ parameter BIST_ADDR_START = 9'h000,
+ parameter BIST_ADDR_END = 9'h1F8,
+ parameter BIST_REPAIR_ADDR_START = 9'h1FC,
+ parameter BIST_RAD_WD_I = BIST_ADDR_WD,
+ parameter BIST_RAD_WD_O = BIST_ADDR_WD) (
+
+ output logic last_addr, // Last address access
+ output logic [BIST_ADDR_WD-1:0] bist_addr, // Bist Address
+ output logic sdo, // scan data output
+ input logic clk, // clock input
+ input logic rst_n, // asynchronous reset
+ input logic run, // stop or start state machine
+ input logic updown, // count up or down
+ input logic scan_shift, // shift scan input
+ input logic scan_load, // load scan input
+ input logic sdi // scan data input
+
+);
+
+
+logic [BIST_ADDR_WD-1:0] next_addr; // Next Address
+logic [BIST_ADDR_WD-1:0] start_addr; // Address Start Address
+logic [BIST_ADDR_WD-1:0] end_addr; // Address Stop Address
+
+
+assign last_addr = (((updown == 1'b1)&&(bist_addr == end_addr))||((updown == 1'b0)&&(bist_addr == start_addr)))?1'b1:1'b0;
+
+
+/******************************
+ Address register
+ Basic Assumption: Allways counter start with upcounting
+*********************************/
+
+
+always @(posedge clk or negedge rst_n) begin
+ if(!rst_n) bist_addr <= BIST_ADDR_START ;
+ else if(scan_load) bist_addr <= start_addr;
+ else bist_addr <= next_addr;
+end
+
+/* Input combinational block */
+
+always_comb begin
+ if(run) begin
+ if((bist_addr == end_addr)&&(updown == 1'b1))
+ next_addr = start_addr ;
+ else if((bist_addr == start_addr)&&(updown == 1'b0))
+ next_addr = end_addr ;
+ else next_addr = (updown)?bist_addr+1'b1:bist_addr-1'b1;
+ end
+ else next_addr = bist_addr;
+end
+
+
+/* Start register */
+
+always @(posedge clk or negedge rst_n) begin
+ if(!rst_n) start_addr <= BIST_ADDR_START ;
+ else if(scan_shift) start_addr <= {sdi, start_addr[BIST_ADDR_WD-1:1]};
+end
+
+/* Start register */
+always @(posedge clk or negedge rst_n) begin
+ if(!rst_n) end_addr <= BIST_ADDR_END ;
+ else if(scan_shift) end_addr <= {start_addr[0], end_addr[BIST_ADDR_WD-1:1]};
+end
+
+
+
+assign sdo = end_addr[0];
+
+endmodule
+
diff --git a/verilog/rtl/mbist/src/core/mbist_data_cmp.sv b/verilog/rtl/mbist/src/core/mbist_data_cmp.sv
new file mode 100644
index 0000000..45dd343
--- /dev/null
+++ b/verilog/rtl/mbist/src/core/mbist_data_cmp.sv
@@ -0,0 +1,116 @@
+///////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// MBIST Data Comparator ////
+//// ////
+//// This file is part of the mbist_ctrl cores project ////
+//// https://github.com/dineshannayya/mbist_ctrl.git ////
+//// ////
+//// Description ////
+//// This block integrate mbist data comparator ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.0 - 11th Oct 2021, Dinesh A ////
+//// Initial integration ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+`include "mbist_def.svh"
+
+
+module mbist_data_cmp
+ #( parameter BIST_ADDR_WD = 9,
+ parameter BIST_DATA_WD = 32,
+ parameter BIST_ADDR_START = 9'h000,
+ parameter BIST_ADDR_END = 9'h1F8,
+ parameter BIST_REPAIR_ADDR_START = 9'h1FC,
+ parameter BIST_RAD_WD_I = BIST_ADDR_WD,
+ parameter BIST_RAD_WD_O = BIST_ADDR_WD) (
+
+ output logic error,
+ output logic error_correct,
+ output logic correct,
+ output logic [BIST_ADDR_WD-1:0] error_addr,
+ output logic [3:0] error_cnt,
+ input logic clk,
+ input logic rst_n,
+ input logic compare,
+ input logic addr_inc_phase,
+ input logic read_invert,
+ input logic [BIST_DATA_WD-1:0] comp_data,
+ input logic [BIST_DATA_WD-1:0] rxd_data,
+ input logic [BIST_ADDR_WD-1:0] addr
+
+ );
+
+logic mask_compare;
+logic [BIST_DATA_WD-1:0] exp_data;
+logic comp_status;
+
+assign exp_data = (read_invert) ? ~comp_data: comp_data;
+
+/* Comparison register */
+
+always @(posedge clk or negedge rst_n) begin
+ if(!rst_n) begin
+ comp_status <= 1'b0;
+ error_addr <= 'b0;
+ end else if(compare && !mask_compare) begin
+ comp_status <= |(exp_data ^ rxd_data);
+ error_addr <= addr;
+ end else begin
+ comp_status <= 1'b0;
+ end
+end
+
+// Due to cycle diference between compare and write opperation
+// There is chance two error reported for same address
+// To avoid this, once error is detected, comparision is masked
+// unit the next address phase
+always @(posedge clk or negedge rst_n) begin
+ if(!rst_n) begin
+ error_cnt <= 'b0;
+ correct <='b0;
+ mask_compare <= 'b0;
+ error <= '0;
+ end else if(mask_compare && addr_inc_phase) begin
+ mask_compare <= 1'b0;
+ end else if(comp_status && (error_cnt < BIST_ERR_LIMIT) ) begin
+ error_cnt <= error_cnt+1;
+ mask_compare <= 1'b1;
+ correct <='b1;
+ end else if(comp_status && (error_cnt == BIST_ERR_LIMIT) ) begin
+ error <= '1;
+ end
+end
+
+assign error_correct = (error_cnt < BIST_ERR_LIMIT) ? comp_status : 1'b0;
+
+endmodule
+
+
+
+
+
+
diff --git a/verilog/rtl/mbist/src/core/mbist_fsm.sv b/verilog/rtl/mbist/src/core/mbist_fsm.sv
new file mode 100644
index 0000000..7672ee7
--- /dev/null
+++ b/verilog/rtl/mbist/src/core/mbist_fsm.sv
@@ -0,0 +1,141 @@
+///////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// MBIST Main control FSM ////
+//// ////
+//// This file is part of the mbist_ctrl cores project ////
+//// https://github.com/dineshannayya/mbist_ctrl.git ////
+//// ////
+//// Description ////
+//// MBIST Main control FSM to control Command, Address, Write ////
+//// and Read compare phase ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.0 - 11th Oct 2021, Dinesh A ////
+//// Initial integration ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+module mbist_fsm
+ #( parameter BIST_ADDR_WD = 9,
+ parameter BIST_DATA_WD = 32,
+ parameter BIST_ADDR_START = 9'h000,
+ parameter BIST_ADDR_END = 9'h1F8,
+ parameter BIST_REPAIR_ADDR_START = 9'h1FC,
+ parameter BIST_RAD_WD_I = BIST_ADDR_WD,
+ parameter BIST_RAD_WD_O = BIST_ADDR_WD) (
+
+ output logic cmd_phase, // Command Phase
+ output logic cmp_phase, // Compare Phase
+ output logic run_op, // Move to Next Operation
+ output logic run_addr, // Move to Next Address
+ output logic run_sti, // Move to Next Stimulus
+ output logic run_pat, // Move to next pattern
+ output logic bist_done, // Bist Test Done
+
+
+ input logic clk, // Clock
+ input logic rst_n, // Reset
+ input logic bist_run, // Bist Run
+ input logic bist_error, // Bist Error
+ input logic op_reverse, // Address Reverse in Next Cycle
+ input logic last_op, // Last Operation
+ input logic last_addr, // Last Address
+ input logic last_sti, // Last Stimulus
+ input logic last_pat // Last Pattern
+
+
+);
+
+parameter FSM_PHASE1 = 2'b00;
+parameter FSM_PHASE2 = 2'b01;
+parameter FSM_EXIT = 2'b10;
+
+logic [1:0] state;
+
+
+
+always @(posedge clk or negedge rst_n)
+begin
+ if(!rst_n) begin
+ cmd_phase <= 0;
+ cmp_phase <= 0;
+ run_op <= 0;
+ run_addr <= 0;
+ run_sti <= 0;
+ run_pat <= 0;
+ bist_done <= 0;
+ state <= FSM_PHASE1;
+ end else if(bist_run) begin
+ case(state)
+ FSM_PHASE1 :
+ begin
+ cmd_phase <= 1;
+ cmp_phase <= 0;
+ run_op <= 0;
+ run_addr <= 0;
+ run_sti <= 0;
+ run_pat <= 0;
+ state <= FSM_PHASE2;
+ end
+ FSM_PHASE2 :
+ begin
+ if((last_addr && last_op && last_sti && last_pat) || bist_error) begin
+ cmd_phase <= 0;
+ cmp_phase <= 0;
+ run_op <= 0;
+ run_addr <= 0;
+ run_sti <= 0;
+ run_pat <= 0;
+ state <= FSM_EXIT;
+ end else begin
+ cmd_phase <= 0;
+ cmp_phase <= 1;
+ run_op <= 1;
+ if(last_op && !(last_addr && op_reverse))
+ run_addr <= 1;
+ if(last_addr && last_op)
+ run_sti <= 1;
+ if(last_addr && last_op && last_sti)
+ run_pat <= 1;
+ state <= FSM_PHASE1;
+ end
+ end
+ FSM_EXIT: bist_done <= 1;
+ default: state <= FSM_PHASE1;
+ endcase
+ end else begin
+ cmd_phase <= 0;
+ cmp_phase <= 0;
+ run_op <= 0;
+ run_addr <= 0;
+ run_sti <= 0;
+ run_pat <= 0;
+ state <= FSM_PHASE1;
+ end
+end
+
+
+
+endmodule
diff --git a/verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv b/verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv
new file mode 100644
index 0000000..b631626
--- /dev/null
+++ b/verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv
@@ -0,0 +1,120 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Memory wrapper ////
+//// ////
+//// This file is part of the mbist_ctrl project ////
+//// https://github.com/dineshannayya/mbist_ctrl.git ////
+//// ////
+//// Description ////
+//// This block does wishbone to SRAM signal mapping ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 18 Nov 2021, Dinesh A ////
+//// initial version ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+module mbist_mem_wrapper #(
+ parameter BIST_ADDR_WD=10,
+ parameter BIST_DATA_WD=32) (
+ input logic rst_n ,
+ // WB I/F
+ input logic wb_clk_i , // System clock
+ input logic wb_cyc_i , // strobe/request
+ input logic wb_stb_i , // strobe/request
+ input logic [BIST_ADDR_WD-1:0] wb_adr_i , // address
+ input logic wb_we_i , // write
+ input logic [BIST_DATA_WD-1:0] wb_dat_i , // data output
+ input logic [BIST_DATA_WD/8-1:0] wb_sel_i , // byte enable
+ output logic [BIST_DATA_WD-1:0] wb_dat_o , // data input
+ output logic wb_ack_o , // acknowlegement
+ output logic wb_err_o , // error
+ // MEM A PORT
+ output logic func_clk_a ,
+ output logic func_cen_a ,
+ output logic [BIST_ADDR_WD-1:0] func_addr_a ,
+ input logic [BIST_DATA_WD-1:0] func_dout_a ,
+
+ // Functional B Port
+ output logic func_clk_b ,
+ output logic func_cen_b ,
+ output logic func_web_b ,
+ output logic [BIST_DATA_WD/8-1:0] func_mask_b ,
+ output logic [BIST_ADDR_WD-1:0] func_addr_b ,
+ output logic [BIST_DATA_WD-1:0] func_din_b
+
+);
+
+
+// Memory Write PORT
+assign func_clk_b = wb_clk_i;
+assign func_cen_b = !wb_stb_i;
+assign func_web_b = !wb_we_i;
+assign func_mask_b = wb_sel_i;
+assign func_addr_b = wb_adr_i;
+assign func_din_b = wb_dat_i;
+
+assign func_clk_a = wb_clk_i;
+assign func_cen_a = (wb_stb_i == 1'b1 && wb_we_i == 1'b0 && wb_ack_o ==0) ? 1'b0 : 1'b1;
+assign func_addr_a = wb_adr_i;
+assign wb_dat_o = func_dout_a;
+
+assign wb_err_o = 1'b0;
+
+// Generate Once cycle delayed ACK to get the data from SRAM
+always_ff @(negedge rst_n or posedge wb_clk_i) begin
+ if ( rst_n == 1'b0 ) begin
+ wb_ack_o<= 'h0;
+ end else begin
+ wb_ack_o <= (wb_stb_i == 1'b1) & (wb_ack_o == 0);
+ end
+end
+
+
+endmodule
diff --git a/verilog/rtl/mbist/src/core/mbist_mux.sv b/verilog/rtl/mbist/src/core/mbist_mux.sv
new file mode 100755
index 0000000..754ea63
--- /dev/null
+++ b/verilog/rtl/mbist/src/core/mbist_mux.sv
@@ -0,0 +1,190 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// MBIST and MEMORY Mux Control Selection ////
+//// ////
+//// This file is part of the mbist_ctrl cores project ////
+//// https://github.com/dineshannayya/mbist_ctrl.git ////
+//// ////
+//// Description ////
+//// This block integrate MBIST and Memory control selection ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.0 - 11th Oct 2021, Dinesh A ////
+//// Initial integration
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+`include "mbist_def.svh"
+module mbist_mux
+ #( parameter BIST_ADDR_WD = 9,
+ parameter BIST_DATA_WD = 32,
+ parameter BIST_ADDR_START = 9'h000,
+ parameter BIST_ADDR_END = 9'h1F8,
+ parameter BIST_REPAIR_ADDR_START = 9'h1FC,
+ parameter BIST_RAD_WD_I = BIST_ADDR_WD,
+ parameter BIST_RAD_WD_O = BIST_ADDR_WD) (
+
+ input logic scan_mode,
+
+ input logic rst_n,
+ // MBIST CTRL SIGNAL
+ input logic bist_en,
+ input logic [BIST_ADDR_WD-1:0] bist_addr,
+ input logic [BIST_DATA_WD-1:0] bist_wdata,
+ input logic bist_clk,
+ input logic bist_wr,
+ input logic bist_rd,
+ input logic bist_error,
+ input logic [BIST_ADDR_WD-1:0] bist_error_addr,
+ output logic bist_correct,
+ input logic bist_sdi,
+ input logic bist_shift,
+ output logic bist_sdo,
+
+ // FUNCTIONAL CTRL SIGNAL
+ input logic func_clk_a,
+ input logic func_cen_a,
+ input logic [BIST_ADDR_WD-1:0] func_addr_a,
+ // Common for func and Mbist i/f
+ output logic [BIST_DATA_WD-1:0] func_dout_a,
+
+ input logic func_clk_b,
+ input logic func_cen_b,
+ input logic func_web_b,
+ input logic [BIST_DATA_WD/8-1:0] func_mask_b,
+ input logic [BIST_ADDR_WD-1:0] func_addr_b,
+ input logic [BIST_DATA_WD-1:0] func_din_b,
+
+
+ // towards memory
+ output logic mem_clk_a,
+ output logic mem_cen_a,
+ output logic [BIST_ADDR_WD-1:0] mem_addr_a,
+ input logic [BIST_DATA_WD-1:0] mem_dout_a,
+
+ output logic mem_clk_b,
+ output logic mem_cen_b,
+ output logic mem_web_b,
+ output logic [BIST_DATA_WD/8-1:0] mem_mask_b,
+ output logic [BIST_ADDR_WD-1:0] mem_addr_b,
+ output logic [BIST_DATA_WD-1:0] mem_din_b
+ );
+
+
+parameter BIST_MASK_WD = BIST_DATA_WD/8;
+
+wire [BIST_ADDR_WD-1:0] addr_a;
+wire [BIST_ADDR_WD-1:0] addr_b;
+wire mem_clk_a_cts; // used for internal clock tree
+wire mem_clk_b_cts; // usef for internal clock tree
+
+
+
+assign addr_a = (bist_en) ? bist_addr : func_addr_a;
+assign addr_b = (bist_en) ? bist_addr : func_addr_b;
+
+assign mem_cen_a = (bist_en) ? !bist_rd : func_cen_a;
+assign mem_cen_b = (bist_en) ? !bist_wr : func_cen_b;
+
+assign mem_web_b = (bist_en) ? !bist_wr : func_web_b;
+assign mem_mask_b = (bist_en) ? {{BIST_MASK_WD}{1'b1}} : func_mask_b;
+
+//assign mem_clk_a = (bist_en) ? bist_clk : func_clk_a;
+//assign mem_clk_b = (bist_en) ? bist_clk : func_clk_b;
+
+ctech_mux2x1 u_mem_clk_a_sel (.A0 (func_clk_a),.A1 (bist_clk),.S (bist_en), .X (mem_clk_a));
+ctech_mux2x1 u_mem_clk_b_sel (.A0 (func_clk_b),.A1 (bist_clk),.S (bist_en), .X (mem_clk_b));
+
+ctech_clk_buf u_cts_mem_clk_a (.A (mem_clk_a), . X(mem_clk_a_cts));
+ctech_clk_buf u_cts_mem_clk_b (.A (mem_clk_b), . X(mem_clk_b_cts));
+
+assign mem_din_b = (bist_en) ? bist_wdata : func_din_b;
+
+
+
+// During scan, SRAM data is unknown, feed data in back to avoid unknow
+// propagation
+assign func_dout_a = (scan_mode) ? mem_din_b : mem_dout_a;
+
+mbist_repair_addr
+ #(.BIST_ADDR_WD (BIST_ADDR_WD),
+ .BIST_DATA_WD (BIST_DATA_WD),
+ .BIST_ADDR_START (BIST_ADDR_START),
+ .BIST_ADDR_END (BIST_ADDR_END),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O))
+ u_repair_A(
+ .AddressOut (mem_addr_a ),
+ .Correct (bist_correct ),
+ .sdo (bist_sdo ),
+
+ .AddressIn (addr_a ),
+ .clk (mem_clk_a_cts ),
+ .rst_n (rst_n ),
+ .Error (bist_error ),
+ .ErrorAddr (bist_error_addr ),
+ .scan_shift (bist_shift ),
+ .sdi (bist_sdi )
+);
+
+mbist_repair_addr
+ #(.BIST_ADDR_WD (BIST_ADDR_WD),
+ .BIST_DATA_WD (BIST_DATA_WD),
+ .BIST_ADDR_START (BIST_ADDR_START),
+ .BIST_ADDR_END (BIST_ADDR_END),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O))
+ u_repair_B(
+ .AddressOut (mem_addr_b ),
+ .Correct ( ), // Both Bist Correct are same
+ .sdo ( ),
+
+ .AddressIn (addr_b ),
+ .clk (mem_clk_b_cts ),
+ .rst_n (rst_n ),
+ .Error (bist_error ),
+ .ErrorAddr (bist_error_addr ),
+ .scan_shift (1'b0 ), // Both Repair hold same address
+ .sdi (1'b0 )
+);
+
+
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
diff --git a/verilog/rtl/mbist/src/core/mbist_op_sel.sv b/verilog/rtl/mbist/src/core/mbist_op_sel.sv
new file mode 100644
index 0000000..a995b8e
--- /dev/null
+++ b/verilog/rtl/mbist/src/core/mbist_op_sel.sv
@@ -0,0 +1,132 @@
+///////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// MBIST Operation Selection ////
+//// ////
+//// This file is part of the mbist_ctrl cores project ////
+//// https://github.com/dineshannayya/mbist_ctrl.git ////
+//// ////
+//// Description ////
+//// This block integrate Operation Selection ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.0 - 11th Oct 2021, Dinesh A ////
+//// Initial integration ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+
+`include "mbist_def.svh"
+// bist stimulus selection
+
+module mbist_op_sel
+ #( parameter BIST_ADDR_WD = 9,
+ parameter BIST_DATA_WD = 32,
+ parameter BIST_ADDR_START = 9'h000,
+ parameter BIST_ADDR_END = 9'h1F8,
+ parameter BIST_REPAIR_ADDR_START = 9'h1FC,
+ parameter BIST_RAD_WD_I = BIST_ADDR_WD,
+ parameter BIST_RAD_WD_O = BIST_ADDR_WD) (
+
+ output logic op_read , // Opertion Read
+ output logic op_write , // Operation Write
+ output logic op_invert , // Opertaion Data Invert
+ output logic op_updown , // Operation Address Up Down
+ output logic op_reverse , // Operation Reverse
+ output logic op_repeatflag , // Operation Repeat flag
+ output logic sdo , // Scan Data Out
+ output logic last_op , // last operation
+
+ input logic clk , // Clock
+ input logic rst_n , // Reset
+ input logic scan_shift , // Scan Shift
+ input logic sdi , // Scan data in
+ input logic re_init , // Re-init when there is error correction
+ input logic run , // Run
+ input logic [BIST_STI_WD-1:0] stimulus
+
+);
+
+
+logic [BIST_OP_SIZE-1:0] op_sel ;// Actual Operation
+logic [7:0] tmp_op ;// Warning : Assming Max opertion is 8
+logic [7:0] tmpinvert ;// read control
+logic [7:0] tmpread ;// write control
+logic [7:0] tmpwrite ;// invertor control
+integer index ;// output index */
+integer loop ;// bit count
+
+
+/* Operation Selection Selection */
+
+always @(posedge clk or negedge rst_n) begin
+ if(!rst_n) op_sel <= {1'b1,{(BIST_OP_SIZE-1){1'b0}}};
+ else if(scan_shift) op_sel <= {sdi, op_sel[BIST_OP_SIZE-1:1]};
+ else if(re_init) op_sel <= {1'b1,{(BIST_OP_SIZE-1){1'b0}}}; // need fix for pmbist moode
+ else if(run) op_sel <= {op_sel[0],op_sel[BIST_OP_SIZE-1:1]};
+end
+
+assign op_updown = stimulus[BIST_STI_WD-1];
+assign op_reverse = stimulus[BIST_STI_WD-2];
+assign op_repeatflag = stimulus[BIST_STI_WD-3];
+// Re-wind the operation, when the is error correct
+assign last_op = (re_init) ? 1'b0 : op_sel[0];
+
+
+
+always_comb
+begin
+ loop=0;
+ tmpinvert = 8'h0;
+ tmpread = 8'h0;
+ tmpwrite = 8'h0;
+ for(index = 0 ; index < BIST_OP_SIZE ; index = index+1)begin
+ tmpinvert[index] = stimulus[loop];
+ tmpread[index] = stimulus[loop+1];
+ tmpwrite[index] = stimulus[loop+2];
+ loop = loop + 3;
+ end
+end
+
+
+always_comb
+begin
+ tmp_op = 8'b00000000;
+ tmp_op[BIST_OP_SIZE-1:0] = op_sel;
+ case(tmp_op)
+ 8'b10000000: {op_read,op_write,op_invert} = {tmpread[7],tmpwrite[7],tmpinvert[7]};
+ 8'b01000000: {op_read,op_write,op_invert} = {tmpread[6],tmpwrite[6],tmpinvert[6]};
+ 8'b00100000: {op_read,op_write,op_invert} = {tmpread[5],tmpwrite[5],tmpinvert[5]};
+ 8'b00010000: {op_read,op_write,op_invert} = {tmpread[4],tmpwrite[4],tmpinvert[4]};
+ 8'b00001000: {op_read,op_write,op_invert} = {tmpread[3],tmpwrite[3],tmpinvert[3]};
+ 8'b00000100: {op_read,op_write,op_invert} = {tmpread[2],tmpwrite[2],tmpinvert[2]};
+ 8'b00000010: {op_read,op_write,op_invert} = {tmpread[1],tmpwrite[1],tmpinvert[1]};
+ 8'b00000001: {op_read,op_write,op_invert} = {tmpread[0],tmpwrite[0],tmpinvert[0]};
+ default: {op_read,op_write,op_invert} = {tmpread[0],tmpwrite[0],tmpinvert[0]};
+ endcase
+end
+
+
+endmodule
diff --git a/verilog/rtl/mbist/src/core/mbist_pat_sel.sv b/verilog/rtl/mbist/src/core/mbist_pat_sel.sv
new file mode 100644
index 0000000..47a5c98
--- /dev/null
+++ b/verilog/rtl/mbist/src/core/mbist_pat_sel.sv
@@ -0,0 +1,116 @@
+///////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// MBIST Pattern Selection ////
+//// ////
+//// This file is part of the mbist_ctrl cores project ////
+//// https://github.com/dineshannayya/mbist_ctrl.git ////
+//// ////
+//// Description ////
+//// This block integrate mbist pattern selection ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.0 - 11th Oct 2021, Dinesh A ////
+//// Initial integration ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+`include "mbist_def.svh"
+//-----------------------------------
+// MBIST Data Pattern Selection Logic
+//-----------------------------------
+module mbist_pat_sel
+ #( parameter BIST_ADDR_WD = 9,
+ parameter BIST_DATA_WD = 32,
+ parameter BIST_ADDR_START = 9'h000,
+ parameter BIST_ADDR_END = 9'h1F8,
+ parameter BIST_REPAIR_ADDR_START = 9'h1FC,
+ parameter BIST_RAD_WD_I = BIST_ADDR_WD,
+ parameter BIST_RAD_WD_O = BIST_ADDR_WD) (
+
+ output logic pat_last, // Last pattern
+ output logic [BIST_DATA_WD-1:0] pat_data, // pattern data
+ output logic sdo, // scan data output
+ input logic clk, // clock
+ input logic rst_n, // reset
+ input logic run, // stop or start state machine
+ input logic scan_shift, // scan shift
+ input logic sdi // scan input
+
+);
+
+
+logic [BIST_DATA_PAT_SIZE-1:0] pat_sel ;/* Pattern Select */
+logic [63:0] pattern;
+
+integer index ;/* output index */
+
+
+
+// last pattern
+assign pat_last = pat_sel[0];
+
+
+/* Pattern Selection */
+
+always @(posedge clk or negedge rst_n) begin
+ if(!rst_n) pat_sel <= {1'b1,{(BIST_DATA_PAT_SIZE-1){1'b0}}};
+ else if(scan_shift) pat_sel <= {sdi, pat_sel[BIST_DATA_PAT_SIZE-1:1]};
+ else if(run) pat_sel <= {pat_sel[0],pat_sel[BIST_DATA_PAT_SIZE-1:1]};
+end
+
+
+/* Pattern Selection */
+logic [7:0] tmp_pat;
+always_comb
+begin
+ tmp_pat = 8'b00000000;
+ tmp_pat[7:8-BIST_DATA_PAT_SIZE] = pat_sel;
+ case(tmp_pat)
+ 8'b10000000: pattern = BIST_DATA_PAT_TYPE1;
+ 8'b01000000: pattern = BIST_DATA_PAT_TYPE2;
+ 8'b00100000: pattern = BIST_DATA_PAT_TYPE3;
+ 8'b00010000: pattern = BIST_DATA_PAT_TYPE4;
+ 8'b00001000: pattern = BIST_DATA_PAT_TYPE5;
+ 8'b00000100: pattern = BIST_DATA_PAT_TYPE6;
+ 8'b00000010: pattern = BIST_DATA_PAT_TYPE7;
+ 8'b00000001: pattern = BIST_DATA_PAT_TYPE8;
+ default: pattern = BIST_DATA_PAT_TYPE1;
+ endcase
+end
+
+/* Data distributor */
+
+always_comb
+begin
+ for(index = 0 ; index < BIST_DATA_WD ; index = index + 1) begin
+ pat_data[index] = pattern[index%64];
+ end
+end
+
+assign sdo = pat_sel[0];
+
+endmodule
+
+
diff --git a/verilog/rtl/mbist/src/core/mbist_repair_addr.sv b/verilog/rtl/mbist/src/core/mbist_repair_addr.sv
new file mode 100644
index 0000000..70eb7c1
--- /dev/null
+++ b/verilog/rtl/mbist/src/core/mbist_repair_addr.sv
@@ -0,0 +1,152 @@
+///////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// MBIST Address Repair ////
+//// ////
+//// This file is part of the mbist_ctrl cores project ////
+//// https://github.com/dineshannayya/mbist_ctrl.git ////
+//// ////
+//// Description ////
+//// This block integrate mbist address repair ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.0 - 11th Oct 2021, Dinesh A ////
+//// Initial integration ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+
+// BIST address Repair Logic
+
+`include "mbist_def.svh"
+
+module mbist_repair_addr
+ #( parameter BIST_ADDR_WD = 9,
+ parameter BIST_DATA_WD = 32,
+ parameter BIST_ADDR_START = 9'h000,
+ parameter BIST_ADDR_END = 9'h1F8,
+ parameter BIST_REPAIR_ADDR_START = 9'h1FC,
+ parameter BIST_RAD_WD_I = BIST_ADDR_WD,
+ parameter BIST_RAD_WD_O = BIST_ADDR_WD) (
+
+ output logic [BIST_RAD_WD_O-1:0] AddressOut,
+ output logic Correct,
+ output logic sdo, // scan data output
+
+ input logic [BIST_RAD_WD_I-1:0] AddressIn,
+ input logic clk,
+ input logic rst_n,
+ input logic Error,
+ input logic [BIST_RAD_WD_I-1:0] ErrorAddr,
+ input logic scan_shift, // shift scan input
+ input logic sdi // scan data input
+
+
+);
+
+logic [3:0] ErrorCnt; // Assumed Maximum Error correction is less than 16
+logic [15:0] shift_reg;
+logic [15:0] shift_load;
+logic [7:0] shift_cnt;
+logic scan_shift_d;
+logic shift_pos_edge;
+
+logic [BIST_RAD_WD_I-1:0] RepairMem [0:BIST_ERR_LIMIT-1];
+integer i;
+
+
+always@(posedge clk or negedge rst_n)
+begin
+ if(!rst_n) begin
+ ErrorCnt <= '0;
+ Correct <= '0;
+ // Initialize the Repair RAM for SCAN purpose
+ for(i =0; i < BIST_ERR_LIMIT; i = i+1) begin
+ RepairMem[i] = 'h0;
+ end
+ end else if(Error) begin
+ if(ErrorCnt <= BIST_ERR_LIMIT) begin
+ ErrorCnt <= ErrorCnt+1;
+ RepairMem[ErrorCnt] <= ErrorAddr;
+ Correct <= 1'b1;
+ end else begin
+ Correct <= 1'b0;
+ end
+ end
+end
+
+integer index;
+
+always_comb
+begin
+ AddressOut = AddressIn;
+ for(index=0; index < BIST_ERR_LIMIT; index=index+1) begin
+ if(ErrorCnt > index && AddressIn == RepairMem[index]) AddressOut = BIST_REPAIR_ADDR_START+index;
+ end
+end
+
+/********************************************
+* Serial shifting the Repair address
+* *******************************************/
+
+always@(posedge clk or negedge rst_n)
+begin
+ if(!rst_n) begin
+ shift_reg <= '0;
+ shift_cnt <= '0;
+ scan_shift_d <= 1'b0;
+ end else begin
+ if(scan_shift && (shift_cnt[7:4] < BIST_ERR_LIMIT)) begin
+ shift_cnt <= shift_cnt+1;
+ end
+ scan_shift_d <= scan_shift;
+ shift_reg <= shift_load;
+ end
+end
+
+// Detect scan_shift pos edge
+assign shift_pos_edge = (scan_shift_d ==0) && (scan_shift);
+
+always_comb
+begin
+ shift_load = shift_reg;
+ // Block the data reloading every pos edge of shift
+ if(scan_shift && ((shift_cnt[7:4]+1) < BIST_ERR_LIMIT) && (shift_cnt[3:0] == 4'b1111))
+ shift_load = {RepairMem[shift_cnt[7:4]+1]};
+ else if(scan_shift)
+ shift_load = {sdi,shift_reg[15:1]};
+ else
+ shift_load = {RepairMem[shift_cnt[7:4]]};
+
+end
+
+assign sdo = shift_reg[0];
+endmodule
+
+
+
+
+
+
diff --git a/verilog/rtl/mbist/src/core/mbist_sti_sel.sv b/verilog/rtl/mbist/src/core/mbist_sti_sel.sv
new file mode 100644
index 0000000..459dc9f
--- /dev/null
+++ b/verilog/rtl/mbist/src/core/mbist_sti_sel.sv
@@ -0,0 +1,105 @@
+///////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// MBIST Stimulus Selection ////
+//// ////
+//// This file is part of the mbist_ctrl cores project ////
+//// https://github.com/dineshannayya/mbist_ctrl.git ////
+//// ////
+//// Description ////
+//// This block integrate stimulus slectiion ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.0 - 11th Oct 2021, Dinesh A ////
+//// Initial integration ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+
+`include "mbist_def.svh"
+// bist stimulus selection
+
+module mbist_sti_sel
+ #( parameter BIST_ADDR_WD = 9,
+ parameter BIST_DATA_WD = 32,
+ parameter BIST_ADDR_START = 9'h000,
+ parameter BIST_ADDR_END = 9'h1F8,
+ parameter BIST_REPAIR_ADDR_START = 9'h1FC,
+ parameter BIST_RAD_WD_I = BIST_ADDR_WD,
+ parameter BIST_RAD_WD_O = BIST_ADDR_WD) (
+
+ output logic sdo , // Scan Data Out
+ output logic last_stimulus , // last stimulus
+ output logic [BIST_STI_WD-1:0] stimulus ,
+
+ input logic clk , // Clock
+ input logic rst_n , // Reset
+ input logic scan_shift , // Scan Shift
+ input logic sdi , // Scan data in
+ input logic run // Run
+
+);
+
+logic [BIST_STI_SIZE-1:0] sti_sel ; // Stimulation Selection
+logic [7:0] tmp_sti ; // Warning: Max Stimulus assmed is 8
+
+
+
+/* Pattern Selection */
+
+always @(posedge clk or negedge rst_n) begin
+ if(!rst_n) sti_sel <= {1'b1,{(BIST_STI_SIZE-1){1'b0}}};
+ else if(scan_shift) sti_sel <= {sdi, sti_sel[BIST_STI_SIZE-1:1]};
+ else if(run) sti_sel <= {sti_sel[0],sti_sel[BIST_STI_SIZE-1:1]};
+end
+
+
+/* Pattern Selection */
+always_comb
+begin
+ tmp_sti = 8'b00000000;
+ tmp_sti[7:8-BIST_STI_SIZE] = sti_sel;
+ case(tmp_sti)
+ 8'b10000000: stimulus = BIST_STIMULUS_TYPE1;
+ 8'b01000000: stimulus = BIST_STIMULUS_TYPE2;
+ 8'b00100000: stimulus = BIST_STIMULUS_TYPE3;
+ 8'b00010000: stimulus = BIST_STIMULUS_TYPE4;
+ 8'b00001000: stimulus = BIST_STIMULUS_TYPE5;
+ 8'b00000100: stimulus = BIST_STIMULUS_TYPE6;
+ 8'b00000010: stimulus = BIST_STIMULUS_TYPE7;
+ 8'b00000001: stimulus = BIST_STIMULUS_TYPE8;
+ default: stimulus = BIST_STIMULUS_TYPE1;
+ endcase
+end
+
+
+/* Assign output */
+
+assign sdo = sti_sel[0];
+assign last_stimulus = sti_sel[0];
+
+
+
+endmodule
diff --git a/verilog/rtl/mbist/src/top/mbist_top1.sv b/verilog/rtl/mbist/src/top/mbist_top1.sv
new file mode 100644
index 0000000..10fdbfd
--- /dev/null
+++ b/verilog/rtl/mbist/src/top/mbist_top1.sv
@@ -0,0 +1,469 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// MBIST TOP ////
+//// ////
+//// This file is part of the mbist_ctrl cores project ////
+//// https://github.com/dineshannayya/mbist_ctrl.git ////
+//// ////
+//// Description ////
+//// This block integrate mbist controller with row ////
+//// redendency feature ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.0 - 11th Oct 2021, Dinesh A ////
+//// Initial integration ////
+//// 0.1 - 26th Oct 2021, Dinesh A ////
+//// Fixed Error Address are serial shifted through ////
+//// sdi/sdo ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+`include "mbist_def.svh"
+module mbist_top1
+ #(
+ parameter BIST_ADDR_WD = 9,
+ parameter BIST_DATA_WD = 32,
+ parameter BIST_ADDR_START = 9'h000,
+ parameter BIST_ADDR_END = 9'h1FB,
+ parameter BIST_REPAIR_ADDR_START = 9'h1FC,
+ parameter BIST_RAD_WD_I = BIST_ADDR_WD,
+ parameter BIST_RAD_WD_O = BIST_ADDR_WD) (
+
+`ifdef USE_POWER_PINS
+ inout vccd1, // User area 1 1.8V supply
+ inout vssd1, // User area 1 digital ground
+`endif
+
+ // Clock Skew Adjust
+ input logic wbd_clk_int,
+ output logic wbd_clk_mbist,
+ input logic [3:0] cfg_cska_mbist, // clock skew adjust for web host
+
+ input logic rst_n,
+
+ // MBIST I/F
+ input logic bist_en,
+ input logic bist_run,
+ input logic bist_shift,
+ input logic bist_load,
+ input logic bist_sdi,
+
+ output logic [3:0] bist_error_cnt,
+ output logic bist_correct,
+ output logic bist_error,
+ output logic bist_done,
+ output logic bist_sdo,
+
+
+ // WB I/F
+ input logic wb_clk_i, // System clock
+ input logic wb_cyc_i, // strobe/request
+ input logic wb_stb_i, // strobe/request
+ input logic [BIST_ADDR_WD-1:0] wb_adr_i, // address
+ input logic wb_we_i , // write
+ input logic [BIST_DATA_WD-1:0] wb_dat_i, // data output
+ input logic [BIST_DATA_WD/8-1:0] wb_sel_i, // byte enable
+ output logic [BIST_DATA_WD-1:0] wb_dat_o, // data input
+ output logic wb_ack_o, // acknowlegement
+ output logic wb_err_o, // error
+
+ // towards memory
+ // PORT-A
+ output logic mem_clk_a,
+ output logic [BIST_ADDR_WD-1:0]mem_addr_a,
+ output logic mem_cen_a,
+ output logic [BIST_DATA_WD-1:0]mem_din_b,
+ // PORT-B
+ output logic mem_clk_b,
+ output logic mem_cen_b,
+ output logic mem_web_b,
+ output logic [BIST_DATA_WD/8-1:0]mem_mask_b,
+ output logic [BIST_ADDR_WD-1:0]mem_addr_b,
+ input logic [BIST_DATA_WD-1:0]mem_dout_a
+
+
+
+
+);
+
+// FUNCTIONAL A PORT
+logic func_clk_a;
+logic func_cen_a;
+logic [BIST_ADDR_WD-1:0]func_addr_a;
+logic [BIST_DATA_WD-1:0]func_dout_a;
+
+// Functional B Port
+logic func_clk_b;
+logic func_cen_b;
+logic func_web_b;
+logic [BIST_DATA_WD/8-1:0]func_mask_b;
+logic [BIST_ADDR_WD-1:0]func_addr_b;
+logic [BIST_DATA_WD-1:0]func_din_b;
+//----------------------------------------------------
+// Local variable defination
+// ---------------------------------------------------
+//
+logic srst_n ; // sync reset w.r.t bist_clk
+logic cmd_phase ; // Command Phase
+logic cmp_phase ; // Compare Phase
+logic run_op ; // Run next Operation
+logic run_addr ; // Run Next Address
+logic run_sti ; // Run Next Stimulus
+logic run_pat ; // Run Next Pattern
+logic op_updown ; // Adress updown direction
+logic last_addr ; // last address indication
+logic last_sti ; // last stimulus
+logic last_op ; // last operation
+logic last_pat ; // last pattern
+logic [BIST_DATA_WD-1:0] pat_data ; // Selected Data Pattern
+logic [BIST_STI_WD-1:0] stimulus ; // current stimulus
+logic compare ; // compare data
+logic op_repeatflag;
+logic op_reverse;
+logic op_read ;
+logic op_write ;
+logic op_invert ;
+
+//---------------------------------
+// SDI => SDO diasy chain
+// bist_sdi => bist_addr_sdo => bist_sti_sdo => bist_op_sdo => bist_pat_sdo => bist_sdo
+// ---------------------------------
+logic bist_addr_sdo ;
+logic bist_sti_sdo ;
+logic bist_op_sdo ;
+logic bist_pat_sdo ;
+
+logic bist_error_correct ;
+logic [BIST_ADDR_WD-1:0]bist_error_addr ; // bist address
+
+logic [BIST_ADDR_WD-1:0]bist_addr ; // bist address
+logic [BIST_DATA_WD-1:0] bist_wdata ; // bist write data
+logic bist_wr ;
+logic bist_rd ;
+
+
+assign bist_wr = (cmd_phase && op_write);
+assign bist_rd = (cmd_phase && op_read);
+
+assign compare = (cmp_phase && op_read);
+assign bist_wdata = (op_invert) ? ~pat_data : pat_data;
+
+// Clock Tree branching to avoid clock latency towards SRAM path
+wire wb_clk_b1,wb_clk_b2;
+ctech_clk_buf u_cts_wb_clk_b1 (.A (wb_clk_i), . X(wb_clk_b1));
+ctech_clk_buf u_cts_wb_clk_b2 (.A (wb_clk_i), . X(wb_clk_b2));
+
+// wb_host clock skew control
+clk_skew_adjust u_skew_mbist
+ (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ .clk_in (wbd_clk_int ),
+ .sel (cfg_cska_mbist ),
+ .clk_out (wbd_clk_mbist )
+ );
+
+reset_sync u_reset_sync (
+ .scan_mode (1'b0 ),
+ .dclk (wb_clk_b1 ), // Destination clock domain
+ .arst_n (rst_n ), // active low async reset
+ .srst_n (srst_n )
+ );
+
+
+
+// bist main control FSM
+
+mbist_fsm
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+ u_fsm (
+
+ .cmd_phase (cmd_phase ),
+ .cmp_phase (cmp_phase ),
+ .run_op (run_op ),
+ .run_addr (run_addr ),
+ .run_sti (run_sti ),
+ .run_pat (run_pat ),
+ .bist_done (bist_done ),
+
+
+ .clk (wb_clk_b1 ),
+ .rst_n (srst_n ),
+ .bist_run (bist_run ),
+ .last_op (last_op ),
+ .last_addr (last_addr ),
+ .last_sti (last_sti ),
+ .last_pat (last_pat ),
+ .op_reverse (op_reverse ),
+ .bist_error (bist_error )
+);
+
+
+// bist address generation
+mbist_addr_gen
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+ u_addr_gen(
+ .last_addr (last_addr ),
+ .bist_addr (bist_addr ),
+ .sdo (bist_addr_sdo ),
+
+ .clk (wb_clk_b1 ),
+ .rst_n (srst_n ),
+ .run (run_addr ),
+ .updown (op_updown ),
+ .scan_shift (bist_shift ),
+ .scan_load (bist_load ),
+ .sdi (bist_sdi )
+
+);
+
+
+// BIST current stimulus selection
+mbist_sti_sel
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+ u_sti_sel(
+
+ .sdo (bist_sti_sdo ),
+ .last_stimulus (last_sti ),
+ .stimulus (stimulus ),
+
+ .clk (wb_clk_b1 ),
+ .rst_n (srst_n ),
+ .scan_shift (bist_shift ),
+ .sdi (bist_addr_sdo ),
+ .run (run_sti )
+
+);
+
+
+// Bist Operation selection
+mbist_op_sel
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+ u_op_sel (
+
+ .op_read (op_read ),
+ .op_write (op_write ),
+ .op_invert (op_invert ),
+ .op_updown (op_updown ),
+ .op_reverse (op_reverse ),
+ .op_repeatflag (op_repeatflag ),
+ .sdo (bist_op_sdo ),
+ .last_op (last_op ),
+
+ .clk (wb_clk_b1 ),
+ .rst_n (srst_n ),
+ .scan_shift (bist_shift ),
+ .sdi (bist_sti_sdo ),
+ .re_init (bist_error_correct ),
+ .run (run_op ),
+ .stimulus (stimulus )
+
+ );
+
+
+
+mbist_pat_sel
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+ u_pat_sel (
+ .pat_last (last_pat ),
+ .pat_data (pat_data ),
+ .sdo (bist_pat_sdo ),
+ .clk (wb_clk_b1 ),
+ .rst_n (srst_n ),
+ .run (run_pat ),
+ .scan_shift (bist_shift ),
+ .sdi (bist_op_sdo )
+
+ );
+
+
+mbist_data_cmp
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+
+
+ u_cmp (
+ .error (bist_error ),
+ .error_correct (bist_error_correct ),
+ .correct ( ), // same signal available at bist mux
+ .error_addr (bist_error_addr ),
+ .error_cnt (bist_error_cnt ),
+ .clk (wb_clk_b1 ),
+ .rst_n (srst_n ),
+ .addr_inc_phase (run_addr ),
+ .compare (compare ),
+ .read_invert (op_invert ),
+ .comp_data (pat_data ),
+ .rxd_data (func_dout_a ),
+ .addr (bist_addr )
+
+ );
+
+
+mbist_mem_wrapper #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD )
+ ) u_mem_wrapper(
+ .rst_n (srst_n ),
+ // WB I/F
+ .wb_clk_i (wb_clk_b2 ), // System clock
+ .wb_cyc_i (wb_cyc_i ), // strobe/request
+ .wb_stb_i (wb_stb_i ), // strobe/request
+ .wb_adr_i (wb_adr_i ), // address
+ .wb_we_i (wb_we_i ), // write
+ .wb_dat_i (wb_dat_i ), // data output
+ .wb_sel_i (wb_sel_i ), // byte enable
+ .wb_dat_o (wb_dat_o ), // data input
+ .wb_ack_o (wb_ack_o ), // acknowlegement
+ .wb_err_o (wb_err_o ), // error
+ // MEM A PORT
+ .func_clk_a (func_clk_a ),
+ .func_cen_a (func_cen_a ),
+ .func_addr_a (func_addr_a ),
+ .func_dout_a (func_dout_a ),
+
+ // Functional B Port
+ .func_clk_b (func_clk_b ),
+ .func_cen_b (func_cen_b ),
+ .func_web_b (func_web_b ),
+ .func_mask_b (func_mask_b ),
+ .func_addr_b (func_addr_b ),
+ .func_din_b (func_din_b )
+ );
+
+
+mbist_mux
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+ u_mem_sel (
+
+ .scan_mode (1'b0 ),
+
+ .rst_n (srst_n ),
+ // MBIST CTRL SIGNAL
+ .bist_en (bist_en ),
+ .bist_addr (bist_addr ),
+ .bist_wdata (bist_wdata ),
+ .bist_clk (wb_clk_b2 ),
+ .bist_wr (bist_wr ),
+ .bist_rd (bist_rd ),
+ .bist_error (bist_error_correct),
+ .bist_error_addr (bist_error_addr),
+ .bist_correct (bist_correct ),
+ .bist_sdi (bist_pat_sdo),
+ .bist_shift (bist_shift),
+ .bist_sdo (bist_sdo),
+
+ // FUNCTIONAL CTRL SIGNAL
+ .func_clk_a (func_clk_a ),
+ .func_cen_a (func_cen_a ),
+ .func_addr_a (func_addr_a ),
+ // Common for func and Mbist i/f
+ .func_dout_a (func_dout_a ),
+
+ .func_clk_b (func_clk_b ),
+ .func_cen_b (func_cen_b ),
+ .func_web_b (func_web_b ),
+ .func_mask_b (func_mask_b ),
+ .func_addr_b (func_addr_b ),
+ .func_din_b (func_din_b ),
+
+
+ // towards memory
+ // Memory Out Port
+ .mem_clk_a (mem_clk_a ),
+ .mem_cen_a (mem_cen_a ),
+ .mem_addr_a (mem_addr_a ),
+ .mem_dout_a (mem_dout_a ),
+
+ // Memory Input Port
+ .mem_clk_b (mem_clk_b ),
+ .mem_cen_b (mem_cen_b ),
+ .mem_web_b (mem_web_b ),
+ .mem_mask_b (mem_mask_b ),
+ .mem_addr_b (mem_addr_b ),
+ .mem_din_b (mem_din_b )
+ );
+
+
+endmodule
+
diff --git a/verilog/rtl/mbist/src/top/mbist_top2.sv b/verilog/rtl/mbist/src/top/mbist_top2.sv
new file mode 100644
index 0000000..89433df
--- /dev/null
+++ b/verilog/rtl/mbist/src/top/mbist_top2.sv
@@ -0,0 +1,479 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// MBIST TOP ////
+//// ////
+//// This file is part of the mbist_ctrl cores project ////
+//// https://github.com/dineshannayya/mbist_ctrl.git ////
+//// ////
+//// Description ////
+//// This block integrate mbist controller with row ////
+//// redendency feature ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.0 - 11th Oct 2021, Dinesh A ////
+//// Initial integration ////
+//// 0.1 - 26th Oct 2021, Dinesh A ////
+//// Fixed Error Address are serial shifted through ////
+//// sdi/sdo ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+`include "mbist_def.svh"
+module mbist_top2
+ #( parameter SCW = 8, // SCAN CHAIN WIDTH
+ parameter BIST_ADDR_WD = 8,
+ parameter BIST_DATA_WD = 32,
+ parameter BIST_ADDR_START = 8'h00,
+ parameter BIST_ADDR_END = 8'hFB,
+ parameter BIST_REPAIR_ADDR_START = 8'hFC,
+ parameter BIST_RAD_WD_I = BIST_ADDR_WD,
+ parameter BIST_RAD_WD_O = BIST_ADDR_WD) (
+
+`ifdef USE_POWER_PINS
+ inout vccd1, // User area 1 1.8V supply
+ inout vssd1, // User area 1 digital ground
+`endif
+
+ // Scan I/F
+ input logic scan_en,
+ input logic scan_mode,
+ input logic [SCW-1:0] scan_si,
+ output logic [SCW-1:0] scan_so,
+ output logic scan_en_o,
+ output logic scan_mode_o,
+
+ // Clock Skew Adjust
+ input logic wbd_clk_int,
+ output logic wbd_clk_mbist,
+ input logic [3:0] cfg_cska_mbist, // clock skew adjust for web host
+
+ input logic rst_n,
+
+ // MBIST I/F
+ input logic bist_en,
+ input logic bist_run,
+ input logic bist_shift,
+ input logic bist_load,
+ input logic bist_sdi,
+
+ output logic [3:0] bist_error_cnt,
+ output logic bist_correct,
+ output logic bist_error,
+ output logic bist_done,
+ output logic bist_sdo,
+
+
+ // WB I/F
+ input logic wb_clk_i, // System clock
+ input logic wb_cyc_i, // strobe/request
+ input logic wb_stb_i, // strobe/request
+ input logic [BIST_ADDR_WD-1:0] wb_adr_i, // address
+ input logic wb_we_i , // write
+ input logic [BIST_DATA_WD-1:0] wb_dat_i, // data output
+ input logic [BIST_DATA_WD/8-1:0] wb_sel_i, // byte enable
+ output logic [BIST_DATA_WD-1:0] wb_dat_o, // data input
+ output logic wb_ack_o, // acknowlegement
+ output logic wb_err_o, // error
+
+ // towards memory
+ // PORT-A
+ output logic mem_clk_a,
+ output logic [BIST_ADDR_WD-1:0]mem_addr_a,
+ output logic mem_cen_a,
+ output logic [BIST_DATA_WD-1:0]mem_din_b,
+ // PORT-B
+ output logic mem_clk_b,
+ output logic mem_cen_b,
+ output logic mem_web_b,
+ output logic [BIST_DATA_WD/8-1:0]mem_mask_b,
+ output logic [BIST_ADDR_WD-1:0]mem_addr_b,
+ input logic [BIST_DATA_WD-1:0]mem_dout_a
+
+
+
+
+);
+
+// FUNCTIONAL A PORT
+logic func_clk_a;
+logic func_cen_a;
+logic [BIST_ADDR_WD-1:0]func_addr_a;
+logic [BIST_DATA_WD-1:0]func_dout_a;
+
+// Functional B Port
+logic func_clk_b;
+logic func_cen_b;
+logic func_web_b;
+logic [BIST_DATA_WD/8-1:0]func_mask_b;
+logic [BIST_ADDR_WD-1:0]func_addr_b;
+logic [BIST_DATA_WD-1:0]func_din_b;
+//----------------------------------------------------
+// Local variable defination
+// ---------------------------------------------------
+//
+logic srst_n ; // sync reset w.r.t bist_clk
+logic cmd_phase ; // Command Phase
+logic cmp_phase ; // Compare Phase
+logic run_op ; // Run next Operation
+logic run_addr ; // Run Next Address
+logic run_sti ; // Run Next Stimulus
+logic run_pat ; // Run Next Pattern
+logic op_updown ; // Adress updown direction
+logic last_addr ; // last address indication
+logic last_sti ; // last stimulus
+logic last_op ; // last operation
+logic last_pat ; // last pattern
+logic [BIST_DATA_WD-1:0] pat_data ; // Selected Data Pattern
+logic [BIST_STI_WD-1:0] stimulus ; // current stimulus
+logic compare ; // compare data
+logic op_repeatflag;
+logic op_reverse;
+logic op_read ;
+logic op_write ;
+logic op_invert ;
+
+//---------------------------------
+// SDI => SDO diasy chain
+// bist_sdi => bist_addr_sdo => bist_sti_sdo => bist_op_sdo => bist_pat_sdo => bist_sdo
+// ---------------------------------
+logic bist_addr_sdo ;
+logic bist_sti_sdo ;
+logic bist_op_sdo ;
+logic bist_pat_sdo ;
+
+logic bist_error_correct ;
+logic [BIST_ADDR_WD-1:0]bist_error_addr ; // bist address
+
+logic [BIST_ADDR_WD-1:0]bist_addr ; // bist address
+logic [BIST_DATA_WD-1:0] bist_wdata ; // bist write data
+logic bist_wr ;
+logic bist_rd ;
+
+assign scan_en_o = scan_en;
+assign scan_mode_o = scan_mode;
+
+assign bist_wr = (cmd_phase && op_write);
+assign bist_rd = (cmd_phase && op_read);
+
+assign compare = (cmp_phase && op_read);
+assign bist_wdata = (op_invert) ? ~pat_data : pat_data;
+
+// Clock Tree branching to avoid clock latency towards SRAM path
+wire wb_clk_b1,wb_clk_b2;
+ctech_clk_buf u_cts_wb_clk_b1 (.A (wb_clk_i), . X(wb_clk_b1));
+ctech_clk_buf u_cts_wb_clk_b2 (.A (wb_clk_i), . X(wb_clk_b2));
+
+// wb_host clock skew control
+clk_skew_adjust u_skew_mbist
+ (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ .clk_in (wbd_clk_int ),
+ .sel (cfg_cska_mbist ),
+ .clk_out (wbd_clk_mbist )
+ );
+
+reset_sync u_reset_sync (
+ .scan_mode (scan_mode ),
+ .dclk (wb_clk_b1 ), // Destination clock domain
+ .arst_n (rst_n ), // active low async reset
+ .srst_n (srst_n )
+ );
+
+
+
+// bist main control FSM
+
+mbist_fsm
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+ u_fsm (
+
+ .cmd_phase (cmd_phase ),
+ .cmp_phase (cmp_phase ),
+ .run_op (run_op ),
+ .run_addr (run_addr ),
+ .run_sti (run_sti ),
+ .run_pat (run_pat ),
+ .bist_done (bist_done ),
+
+
+ .clk (wb_clk_b1 ),
+ .rst_n (srst_n ),
+ .bist_run (bist_run ),
+ .last_op (last_op ),
+ .last_addr (last_addr ),
+ .last_sti (last_sti ),
+ .last_pat (last_pat ),
+ .op_reverse (op_reverse ),
+ .bist_error (bist_error )
+);
+
+
+// bist address generation
+mbist_addr_gen
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+ u_addr_gen(
+ .last_addr (last_addr ),
+ .bist_addr (bist_addr ),
+ .sdo (bist_addr_sdo ),
+
+ .clk (wb_clk_b1 ),
+ .rst_n (srst_n ),
+ .run (run_addr ),
+ .updown (op_updown ),
+ .scan_shift (bist_shift ),
+ .scan_load (bist_load ),
+ .sdi (bist_sdi )
+
+);
+
+
+// BIST current stimulus selection
+mbist_sti_sel
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+ u_sti_sel(
+
+ .sdo (bist_sti_sdo ),
+ .last_stimulus (last_sti ),
+ .stimulus (stimulus ),
+
+ .clk (wb_clk_b1 ),
+ .rst_n (srst_n ),
+ .scan_shift (bist_shift ),
+ .sdi (bist_addr_sdo ),
+ .run (run_sti )
+
+);
+
+
+// Bist Operation selection
+mbist_op_sel
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+ u_op_sel (
+
+ .op_read (op_read ),
+ .op_write (op_write ),
+ .op_invert (op_invert ),
+ .op_updown (op_updown ),
+ .op_reverse (op_reverse ),
+ .op_repeatflag (op_repeatflag ),
+ .sdo (bist_op_sdo ),
+ .last_op (last_op ),
+
+ .clk (wb_clk_b1 ),
+ .rst_n (srst_n ),
+ .scan_shift (bist_shift ),
+ .sdi (bist_sti_sdo ),
+ .re_init (bist_error_correct ),
+ .run (run_op ),
+ .stimulus (stimulus )
+
+ );
+
+
+
+mbist_pat_sel
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+ u_pat_sel (
+ .pat_last (last_pat ),
+ .pat_data (pat_data ),
+ .sdo (bist_pat_sdo ),
+ .clk (wb_clk_b1 ),
+ .rst_n (srst_n ),
+ .run (run_pat ),
+ .scan_shift (bist_shift ),
+ .sdi (bist_op_sdo )
+
+ );
+
+
+mbist_data_cmp
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+
+
+ u_cmp (
+ .error (bist_error ),
+ .error_correct (bist_error_correct ),
+ .correct ( ), // same signal available at bist mux
+ .error_addr (bist_error_addr ),
+ .error_cnt (bist_error_cnt ),
+ .clk (wb_clk_b1 ),
+ .rst_n (srst_n ),
+ .addr_inc_phase (run_addr ),
+ .compare (compare ),
+ .read_invert (op_invert ),
+ .comp_data (pat_data ),
+ .rxd_data (func_dout_a ),
+ .addr (bist_addr )
+
+ );
+
+
+mbist_mem_wrapper #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD )
+ ) u_mem_wrapper(
+ .rst_n (srst_n ),
+ // WB I/F
+ .wb_clk_i (wb_clk_b2 ), // System clock
+ .wb_cyc_i (wb_cyc_i ), // strobe/request
+ .wb_stb_i (wb_stb_i ), // strobe/request
+ .wb_adr_i (wb_adr_i ), // address
+ .wb_we_i (wb_we_i ), // write
+ .wb_dat_i (wb_dat_i ), // data output
+ .wb_sel_i (wb_sel_i ), // byte enable
+ .wb_dat_o (wb_dat_o ), // data input
+ .wb_ack_o (wb_ack_o ), // acknowlegement
+ .wb_err_o (wb_err_o ), // error
+ // MEM A PORT
+ .func_clk_a (func_clk_a ),
+ .func_cen_a (func_cen_a ),
+ .func_addr_a (func_addr_a ),
+ .func_dout_a (func_dout_a ),
+
+ // Functional B Port
+ .func_clk_b (func_clk_b ),
+ .func_cen_b (func_cen_b ),
+ .func_web_b (func_web_b ),
+ .func_mask_b (func_mask_b ),
+ .func_addr_b (func_addr_b ),
+ .func_din_b (func_din_b )
+ );
+
+
+mbist_mux
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+ u_mem_sel (
+
+ .scan_mode (scan_mode ),
+
+ .rst_n (srst_n ),
+ // MBIST CTRL SIGNAL
+ .bist_en (bist_en ),
+ .bist_addr (bist_addr ),
+ .bist_wdata (bist_wdata ),
+ .bist_clk (wb_clk_b2 ),
+ .bist_wr (bist_wr ),
+ .bist_rd (bist_rd ),
+ .bist_error (bist_error_correct),
+ .bist_error_addr (bist_error_addr),
+ .bist_correct (bist_correct ),
+ .bist_sdi (bist_pat_sdo),
+ .bist_shift (bist_shift),
+ .bist_sdo (bist_sdo),
+
+ // FUNCTIONAL CTRL SIGNAL
+ .func_clk_a (func_clk_a ),
+ .func_cen_a (func_cen_a ),
+ .func_addr_a (func_addr_a ),
+ // Common for func and Mbist i/f
+ .func_dout_a (func_dout_a ),
+
+ .func_clk_b (func_clk_b ),
+ .func_cen_b (func_cen_b ),
+ .func_web_b (func_web_b ),
+ .func_mask_b (func_mask_b ),
+ .func_addr_b (func_addr_b ),
+ .func_din_b (func_din_b ),
+
+
+ // towards memory
+ // Memory Out Port
+ .mem_clk_a (mem_clk_a ),
+ .mem_cen_a (mem_cen_a ),
+ .mem_addr_a (mem_addr_a ),
+ .mem_dout_a (mem_dout_a ),
+
+ // Memory Input Port
+ .mem_clk_b (mem_clk_b ),
+ .mem_cen_b (mem_cen_b ),
+ .mem_web_b (mem_web_b ),
+ .mem_mask_b (mem_mask_b ),
+ .mem_addr_b (mem_addr_b ),
+ .mem_din_b (mem_din_b )
+ );
+
+
+endmodule
+
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv
index 4337738..518ceaa 100755
--- a/verilog/rtl/pinmux/src/pinmux.sv
+++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -76,7 +76,24 @@
output logic spim_mosi,
output logic pulse1m_mclk,
- output logic [31:0] pinmux_debug
+ output logic [31:0] pinmux_debug,
+
+ // BIST I/F
+ output logic [3:0] bist_en,
+ output logic [3:0] bist_run,
+ output logic [3:0] bist_load,
+
+ output logic [3:0] bist_sdi,
+ output logic [3:0] bist_shift,
+ input logic [3:0] bist_sdo,
+
+ input logic [3:0] bist_done,
+ input logic [3:0] bist_error,
+ input logic [3:0] bist_correct,
+ input logic [3:0] bist_error_cnt0,
+ input logic [3:0] bist_error_cnt1,
+ input logic [3:0] bist_error_cnt2,
+ input logic [3:0] bist_error_cnt3
);
@@ -277,7 +294,25 @@
// Outputs
- .gpio_prev_indata (gpio_prev_indata )
+ .gpio_prev_indata (gpio_prev_indata ) ,
+
+ // BIST I/F
+ .bist_en (bist_en ),
+ .bist_run (bist_run ),
+ .bist_load (bist_load ),
+
+ .bist_sdi (bist_sdi ),
+ .bist_shift (bist_shift ),
+ .bist_sdo (bist_sdo ),
+
+ .bist_done (bist_done ),
+ .bist_error (bist_error ),
+ .bist_correct (bist_correct ),
+ .bist_error_cnt0 (bist_error_cnt0 ),
+ .bist_error_cnt1 (bist_error_cnt1 ),
+ .bist_error_cnt2 (bist_error_cnt2 ),
+ .bist_error_cnt3 (bist_error_cnt3 )
+
);
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv
index 357cad1..4ed5fbc 100644
--- a/verilog/rtl/pinmux/src/pinmux_reg.sv
+++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -61,7 +61,25 @@
output logic [31:0] cfg_multi_func_sel ,// multifunction pins
// Outputs
- output logic [31:0] gpio_prev_indata // prv data from GPIO I/P pins
+ output logic [31:0] gpio_prev_indata, // prv data from GPIO I/P pins
+
+ // BIST I/F
+ output logic [3:0] bist_en,
+ output logic [3:0] bist_run,
+ output logic [3:0] bist_load,
+
+ output logic [3:0] bist_sdi,
+ output logic [3:0] bist_shift,
+ input logic [3:0] bist_sdo,
+
+ input logic [3:0] bist_done,
+ input logic [3:0] bist_error,
+ input logic [3:0] bist_correct,
+ input logic [3:0] bist_error_cnt0,
+ input logic [3:0] bist_error_cnt1,
+ input logic [3:0] bist_error_cnt2,
+ input logic [3:0] bist_error_cnt3
+
);
@@ -70,97 +88,102 @@
// Internal Wire Declarations
//-----------------------------------------------------------------------
-reg sw_rd_en ;
-reg sw_wr_en;
-reg [4:0] sw_addr; // addressing 16 registers
-reg [31:0] sw_reg_wdata;
-reg [3:0] wr_be ;
-reg reg_cs_l;
-reg reg_cs_2l;
+logic sw_rd_en ;
+logic sw_wr_en;
+logic [4:0] sw_addr; // addressing 16 registers
+logic [31:0] sw_reg_wdata;
+logic [3:0] wr_be ;
-reg [31:0] reg_out;
-
-wire [31:0] reg_0; // Chip ID
-wire [31:0] reg_1; // Risc Fuse Id
-reg [31:0] reg_2; // GPIO Read Data
-reg [31:0] reg_3; // GPIO Output Data
-reg [31:0] reg_4; // GPIO Dir Sel
-reg [31:0] reg_5; // GPIO Type
-reg [31:0] reg_6; // Interrupt
-reg [31:0] reg_7; //
-reg [31:0] reg_8; //
-reg [31:0] reg_9; // GPIO Interrupt Status
-wire [31:0] reg_10; // GPIO Interrupt Status
-reg [31:0] reg_11; // GPIO Interrupt Mask
-reg [31:0] reg_12; // GPIO Posedge Interrupt Select
-reg [31:0] reg_13; // GPIO Negedge Interrupt Select
-reg [31:0] reg_14; // Software-Reg_14
-reg [31:0] reg_15; // Software-Reg_15
-reg [31:0] reg_16; // PWN-0 Config
-reg [31:0] reg_17; // PWN-1 Config
-reg [31:0] reg_18; // PWN-2 Config
-reg [31:0] reg_19; // PWN-3 Config
-reg [31:0] reg_20; // PWN-4 Config
-reg [31:0] reg_21; // PWN-5 Config
-reg [31:0] reg_22; // Software-Reg1
-reg [31:0] reg_23; // Software-Reg2
-reg [31:0] reg_24; // Software-Reg3
-reg [31:0] reg_25; // Software-Reg4
-reg [31:0] reg_26; // Software-Reg5
-reg [31:0] reg_27; // Software-Reg6
+logic [31:0] reg_out;
+logic [31:0] reg_0; // Chip ID
+logic [31:0] reg_1; // Risc Fuse Id
+logic [31:0] reg_2; // GPIO Read Data
+logic [31:0] reg_3; // GPIO Output Data
+logic [31:0] reg_4; // GPIO Dir Sel
+logic [31:0] reg_5; // GPIO Type
+logic [31:0] reg_6; // Interrupt
+logic [31:0] reg_7; //
+logic [31:0] reg_8; //
+logic [31:0] reg_9; // GPIO Interrupt Status
+logic [31:0] reg_10; // GPIO Interrupt Status
+logic [31:0] reg_11; // GPIO Interrupt Mask
+logic [31:0] reg_12; // GPIO Posedge Interrupt Select
+logic [31:0] reg_13; // GPIO Negedge Interrupt Select
+logic [31:0] reg_14; // Software-Reg_14
+logic [31:0] reg_15; // Software-Reg_15
+logic [31:0] reg_16; // PWN-0 Config
+logic [31:0] reg_17; // PWN-1 Config
+logic [31:0] reg_18; // PWN-2 Config
+logic [31:0] reg_19; // PWN-3 Config
+logic [31:0] reg_20; // PWN-4 Config
+logic [31:0] reg_21; // PWN-5 Config
+logic [31:0] reg_22; // Software-Reg1
+logic [31:0] reg_23; // Software-Reg2
+logic [31:0] reg_24; // Software-Reg3
+logic [31:0] reg_25; // Software-Reg4
+logic [31:0] reg_26; // Software-Reg5
+logic [31:0] reg_27; // Software-Reg6
-reg cs_int;
-wire gpio_intr;
+logic cs_int;
+logic gpio_intr;
+assign sw_addr = reg_addr [6:2];
+assign sw_rd_en = reg_cs & !reg_wr;
+assign sw_wr_en = reg_cs & reg_wr;
+assign wr_be = reg_be;
+assign sw_reg_wdata = reg_wdata;
-//-----------------------------------------------------------------------
-// To avoid interface timing, all the content are registered
-//-----------------------------------------------------------------------
-always @ (posedge mclk or negedge h_reset_n)
-begin
- if (h_reset_n == 1'b0)
- begin
- sw_addr <= '0;
- sw_rd_en <= '0;
- sw_wr_en <= '0;
- sw_reg_wdata <= '0;
- wr_be <= '0;
- reg_cs_l <= '0;
- reg_cs_2l <= '0;
- end else begin
- sw_addr <= reg_addr [6:2];
- sw_rd_en <= reg_cs & !reg_wr;
- sw_wr_en <= reg_cs & reg_wr;
- sw_reg_wdata <= reg_wdata;
- wr_be <= reg_be;
- reg_cs_l <= reg_cs;
- reg_cs_2l <= reg_cs_l;
- end
+
+//-----------------------------------
+// Edge detection for Logic Bist
+// ----------------------------------
+
+logic wb_req;
+logic wb_req_d;
+logic wb_req_pedge;
+
+always_ff @(negedge h_reset_n or posedge mclk) begin
+ if ( h_reset_n == 1'b0 ) begin
+ wb_req <= '0;
+ wb_req_d <= '0;
+ end else begin
+ wb_req <= reg_cs && (reg_ack == 0) ;
+ wb_req_d <= wb_req;
+ end
end
+// Detect pos edge of request
+assign wb_req_pedge = (wb_req_d ==0) && (wb_req==1'b1);
-//-----------------------------------------------------------------------
-// Read path mux
-//-----------------------------------------------------------------------
+
+//-----------------------------------------------------------------
+// Reg 4/5 are BIST Serial I/F register and it takes minimum 32
+// cycle to respond ACK back
+// ----------------------------------------------------------------
+wire ser_acc = sw_wr_en_30 | sw_rd_en_31;
+wire non_ser_acc = reg_cs ? !ser_acc : 1'b0;
+wire serial_ack;
always @ (posedge mclk or negedge h_reset_n)
begin : preg_out_Seq
if (h_reset_n == 1'b0) begin
- reg_rdata [31:0] <= 32'h0000_0000;
- reg_ack <= 1'b0;
- end else if (sw_rd_en && !reg_ack && !reg_cs_2l) begin
- reg_rdata [31:0] <= reg_out [31:0];
- reg_ack <= 1'b1;
- end else if (sw_wr_en && !reg_ack && !reg_cs_2l) begin
- reg_ack <= 1'b1;
+ reg_rdata <= 'h0;
+ reg_ack <= 1'b0;
+ end else if (ser_acc && serial_ack) begin
+ reg_rdata <= serail_dout ;
+ reg_ack <= 1'b1;
+ end else if (non_ser_acc && !reg_ack) begin
+ reg_rdata <= reg_out ;
+ reg_ack <= 1'b1;
end else begin
reg_ack <= 1'b0;
end
end
+
//-----------------------------------------------------------------------
// register read enable and write enable decoding logic
//-----------------------------------------------------------------------
@@ -193,6 +216,15 @@
wire sw_wr_en_25 = sw_wr_en & (sw_addr == 5'h19);
wire sw_wr_en_26 = sw_wr_en & (sw_addr == 5'h1A);
wire sw_wr_en_27 = sw_wr_en & (sw_addr == 5'h1B);
+wire sw_wr_en_28 = sw_wr_en & (sw_addr == 5'h1C);
+wire sw_wr_en_29 = sw_wr_en & (sw_addr == 5'h1D);
+wire sw_wr_en_30 = sw_wr_en & (sw_addr == 5'h1E);
+wire sw_wr_en_31 = sw_wr_en & (sw_addr == 5'h1F);
+
+wire sw_rd_en_28 = sw_rd_en & (sw_addr == 5'h1C);
+wire sw_rd_en_29 = sw_rd_en & (sw_addr == 5'h1D);
+wire sw_rd_en_30 = sw_rd_en & (sw_addr == 5'h1E);
+wire sw_rd_en_31 = sw_rd_en & (sw_addr == 5'h1F);
//-----------------------------------------------------------------------
@@ -636,7 +668,7 @@
//-----------------------------------------
// Software Reg-2, Release date: <DAY><MONTH><YEAR>
// ----------------------------------------
-gen_32b_reg #(32'h2311_2021) u_reg_23 (
+gen_32b_reg #(32'h1312_2021) u_reg_23 (
//List of Inputs
.reset_n (h_reset_n ),
.clk (mclk ),
@@ -649,9 +681,9 @@
);
//-----------------------------------------
-// Software Reg-3: Poject Revison 1.8 = 0001800
+// Software Reg-3: Poject Revison 2.0 = 0002000
// ----------------------------------------
-gen_32b_reg #(32'h0001_8000) u_reg_24 (
+gen_32b_reg #(32'h0002_0000) u_reg_24 (
//List of Inputs
.reset_n (h_reset_n ),
.clk (mclk ),
@@ -708,6 +740,102 @@
.data_out (reg_27 )
);
+
+//-----------------------------------------------------------------------
+// reg-28
+// -----------------------------------------------------------------
+logic [31:0] cfg_bist_ctrl_1;
+
+gen_32b_reg #(32'h0) u_reg_28 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_28 ),
+ .we (wr_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (cfg_bist_ctrl_1[31:0] )
+ );
+
+
+wire [3:0] bist_serial_sel = cfg_bist_ctrl_1[31:28];
+
+assign bist_en[0] = cfg_bist_ctrl_1[0];
+assign bist_run[0] = cfg_bist_ctrl_1[1];
+assign bist_load[0] = cfg_bist_ctrl_1[2];
+
+assign bist_en[1] = cfg_bist_ctrl_1[4];
+assign bist_run[1] = cfg_bist_ctrl_1[5];
+assign bist_load[1] = cfg_bist_ctrl_1[6];
+
+assign bist_en[2] = cfg_bist_ctrl_1[8];
+assign bist_run[2] = cfg_bist_ctrl_1[9];
+assign bist_load[2] = cfg_bist_ctrl_1[10];
+
+assign bist_en[3] = cfg_bist_ctrl_1[12];
+assign bist_run[3] = cfg_bist_ctrl_1[13];
+assign bist_load[3] = cfg_bist_ctrl_1[14];
+
+//-----------------------------------------------------------------------
+// reg-29
+//-----------------------------------------------------------------
+logic [31:0] cfg_bist_status_1;
+
+assign cfg_bist_status_1 = { 16'h0,
+ bist_error_cnt3, 1'b0, bist_correct[3], bist_error[3], bist_done[3],
+ bist_error_cnt2, 1'b0, bist_correct[2], bist_error[2], bist_done[2],
+ bist_error_cnt1, 1'b0, bist_correct[1], bist_error[1], bist_done[1],
+ bist_error_cnt0, 1'b0, bist_correct[0], bist_error[0], bist_done[0]
+ };
+
+//-----------------------------------------------------------------------
+// reg-30 => Write to Serail I/F
+// reg-31 => READ from Serail I/F
+//-----------------------------------------------------------------
+logic bist_sdi_int;
+logic bist_shift_int;
+logic bist_sdo_int;
+logic [31:0] serail_dout;
+
+assign bist_sdo_int = (bist_serial_sel == 4'b0000) ? bist_sdo[0] :
+ (bist_serial_sel == 4'b0001) ? bist_sdo[1] :
+ (bist_serial_sel == 4'b0010) ? bist_sdo[2] :
+ (bist_serial_sel == 4'b0011) ? bist_sdo[3] :
+ 1'b0;
+
+assign bist_shift[0] = (bist_serial_sel == 4'b0000) ? bist_shift_int : 1'b0;
+assign bist_shift[1] = (bist_serial_sel == 4'b0001) ? bist_shift_int : 1'b0;
+assign bist_shift[2] = (bist_serial_sel == 4'b0010) ? bist_shift_int : 1'b0;
+assign bist_shift[3] = (bist_serial_sel == 4'b0011) ? bist_shift_int : 1'b0;
+
+assign bist_sdi[0] = (bist_serial_sel == 4'b0000) ? bist_sdi_int : 1'b0;
+assign bist_sdi[1] = (bist_serial_sel == 4'b0001) ? bist_sdi_int : 1'b0;
+assign bist_sdi[2] = (bist_serial_sel == 4'b0010) ? bist_sdi_int : 1'b0;
+assign bist_sdi[3] = (bist_serial_sel == 4'b0011) ? bist_sdi_int : 1'b0;
+
+ser_inf_32b u_ser_intf
+ (
+
+ // Master Port
+ .rst_n (h_reset_n), // Regular Reset signal
+ .clk (mclk), // System clock
+ .reg_wr (sw_wr_en_30 & wb_req_pedge), // Write Request
+ .reg_rd (sw_rd_en_31 & wb_req_pedge), // Read Request
+ .reg_wdata (sw_reg_wdata) , // data output
+ .reg_rdata (serail_dout), // data input
+ .reg_ack (serial_ack), // acknowlegement
+
+ // Slave Port
+ .sdi (bist_sdi_int), // Serial SDI
+ .shift (bist_shift_int), // Shift Signal
+ .sdo (bist_sdo_int) // Serial SDO
+
+ );
+
+
+
+
//-----------------------------------------------------------------------
// Register Read Path Multiplexer instantiation
//-----------------------------------------------------------------------
@@ -745,6 +873,10 @@
5'b11001 : reg_out [31:0] = reg_25 [31:0];
5'b11010 : reg_out [31:0] = reg_26 [31:0];
5'b11011 : reg_out [31:0] = reg_27 [31:0];
+ 5'b11100 : reg_out [31:0] = cfg_bist_ctrl_1 [31:0];
+ 5'b11101 : reg_out [31:0] = cfg_bist_status_1 [31:0];
+ 5'b11110 : reg_out [31:0] = serail_dout [31:0]; // Previous Shift Data
+ 5'b11111 : reg_out [31:0] = serail_dout [31:0]; // Latest Shift Data
default : reg_out [31:0] = 32'h0;
endcase
end
diff --git a/verilog/rtl/qspim/src/qspim_top.sv b/verilog/rtl/qspim/src/qspim_top.sv
index d4aede1..ec7eb7c 100644
--- a/verilog/rtl/qspim/src/qspim_top.sv
+++ b/verilog/rtl/qspim/src/qspim_top.sv
@@ -236,21 +236,21 @@
// ADDing Delay cells for Interface hold fix
-sky130_fd_sc_hd__dlygate4sd3_1 u_delay1_sdio0 (.X(spi_sdo0_d1),.A(spi_sdo_int[0]));
-sky130_fd_sc_hd__dlygate4sd3_1 u_delay2_sdio0 (.X(spi_sdo0_d2),.A(spi_sdo0_d1));
-sky130_fd_sc_hd__clkbuf_16 u_buf_sdio0 (.X(spi_sdo[0]),.A(spi_sdo0_d2));
+ctech_delay_buf u_delay1_sdio0 (.X(spi_sdo0_d1),.A(spi_sdo_int[0]));
+ctech_delay_buf u_delay2_sdio0 (.X(spi_sdo0_d2),.A(spi_sdo0_d1));
+ctech_buf u_buf_sdio0 (.X(spi_sdo[0]),.A(spi_sdo0_d2));
-sky130_fd_sc_hd__dlygate4sd3_1 u_delay1_sdio1 (.X(spi_sdo1_d1),.A(spi_sdo_int[1]));
-sky130_fd_sc_hd__dlygate4sd3_1 u_delay2_sdio1 (.X(spi_sdo1_d2),.A(spi_sdo1_d1));
-sky130_fd_sc_hd__clkbuf_16 u_buf_sdio1 (.X(spi_sdo[1]),.A(spi_sdo1_d2));
+ctech_delay_buf u_delay1_sdio1 (.X(spi_sdo1_d1),.A(spi_sdo_int[1]));
+ctech_delay_buf u_delay2_sdio1 (.X(spi_sdo1_d2),.A(spi_sdo1_d1));
+ctech_buf u_buf_sdio1 (.X(spi_sdo[1]),.A(spi_sdo1_d2));
-sky130_fd_sc_hd__dlygate4sd3_1 u_delay1_sdio2 (.X(spi_sdo2_d1),.A(spi_sdo_int[2]));
-sky130_fd_sc_hd__dlygate4sd3_1 u_delay2_sdio2 (.X(spi_sdo2_d2),.A(spi_sdo2_d1));
-sky130_fd_sc_hd__clkbuf_16 u_buf_sdio2 (.X(spi_sdo[2]),.A(spi_sdo2_d2));
+ctech_delay_buf u_delay1_sdio2 (.X(spi_sdo2_d1),.A(spi_sdo_int[2]));
+ctech_delay_buf u_delay2_sdio2 (.X(spi_sdo2_d2),.A(spi_sdo2_d1));
+ctech_buf u_buf_sdio2 (.X(spi_sdo[2]),.A(spi_sdo2_d2));
-sky130_fd_sc_hd__dlygate4sd3_1 u_delay1_sdio3 (.X(spi_sdo3_d1),.A(spi_sdo_int[3]));
-sky130_fd_sc_hd__dlygate4sd3_1 u_delay2_sdio3 (.X(spi_sdo3_d2),.A(spi_sdo3_d1));
-sky130_fd_sc_hd__clkbuf_16 u_buf_sdio3 (.X(spi_sdo[3]),.A(spi_sdo3_d2));
+ctech_delay_buf u_delay1_sdio3 (.X(spi_sdo3_d1),.A(spi_sdo_int[3]));
+ctech_delay_buf u_delay2_sdio3 (.X(spi_sdo3_d2),.A(spi_sdo3_d1));
+ctech_buf u_buf_sdio3 (.X(spi_sdo[3]),.A(spi_sdo3_d2));
assign #1 spi_oen[0] = !spi_en_tx; // SPI_DIO0
diff --git a/verilog/rtl/uart/src/uart_core.sv b/verilog/rtl/uart/src/uart_core.sv
index 15cb568..b3eefab 100644
--- a/verilog/rtl/uart/src/uart_core.sv
+++ b/verilog/rtl/uart/src/uart_core.sv
@@ -192,7 +192,7 @@
wire line_clk_16x_in;
-sky130_fd_sc_hd__clkbuf_16 u_lineclk_buf (.A(line_clk_16x_in), .X(line_clk_16x));
+ctech_clk_buf u_lineclk_buf (.A(line_clk_16x_in), .X(line_clk_16x));
clk_ctl #(11) u_clk_ctl (
// Outputs
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 554170d..b140722 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -98,6 +98,7 @@
`include "lib/async_fifo.sv"
`include "lib/registers.v"
`include "lib/clk_ctl.v"
+ `include "lib/ser_inf_32b.sv"
`include "digital_core/src/glbl_cfg.sv"
`include "wb_host/src/wb_host.sv"
@@ -143,6 +144,18 @@
`include "syntacore/scr1/src/top/scr1_top_wb.sv"
`include "lib/sync_fifo.sv"
+ `include "mbist/src/core/mbist_addr_gen.sv"
+ `include "mbist/src/core/mbist_fsm.sv"
+ `include "mbist/src/core/mbist_op_sel.sv"
+ `include "mbist/src/core/mbist_repair_addr.sv"
+ `include "mbist/src/core/mbist_sti_sel.sv"
+ `include "mbist/src/core/mbist_pat_sel.sv"
+ `include "mbist/src/core/mbist_mux.sv"
+ `include "mbist/src/core/mbist_data_cmp.sv"
+ `include "mbist/src/core/mbist_mem_wrapper.sv"
+
+ `include "mbist/src/top/mbist_top1.sv"
+
`include "user_project_wrapper.v"
// we are using netlist file for clk_skew_adjust as it has
// standard cell + power pin
diff --git a/verilog/rtl/usb1_host/src/phy/usb_transceiver.v b/verilog/rtl/usb1_host/src/phy/usb_transceiver.v
index 45b9912..6a3575b 100644
--- a/verilog/rtl/usb1_host/src/phy/usb_transceiver.v
+++ b/verilog/rtl/usb1_host/src/phy/usb_transceiver.v
@@ -120,8 +120,11 @@
// 0 1 Differential Logic '1'
// 1 0 Differential Logic '0'
// 1 1 Illegal State
-always @ (mode_i or usb_phy_tx_dp_i or usb_phy_tx_dn_i)
+always_comb
begin : MUX
+// Logic "0"
+out_dp = 1'b0;
+out_dn = 1'b1;
case(mode_i)
1'b0:
begin
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 2f805ce..bb64ea6 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -126,6 +126,11 @@
//// 1.8 Nov 23, 2021, Dinesh A ////
//// Three Chip Specific Signature added at PinMux Reg ////
//// reg_22,reg_23,reg_24 ////
+//// 1.9 Dec 11, 2021, Dinesh A ////
+//// 2 x 2K SRAM added into Wishbone Interface ////
+//// Temporary ADC block removed ////
+//// 0.0 Dec 14, 2021, Dinesh A ////
+//// Added two more 2K SRAM added into Wishbone Interface ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
@@ -203,9 +208,11 @@
// Local Parameter Declaration
// --------------------------------------------------
-parameter SDR_DW = 8; // SDR Data Width
-parameter SDR_BW = 1; // SDR Byte Width
-parameter WB_WIDTH = 32; // WB ADDRESS/DARA WIDTH
+parameter SDR_DW = 8; // SDR Data Width
+parameter SDR_BW = 1; // SDR Byte Width
+parameter WB_WIDTH = 32; // WB ADDRESS/DARA WIDTH
+parameter BIST1_ADDR_WD = 11; // 512x32 SRAM
+parameter BIST_DATA_WD = 32;
//---------------------------------------------------------------------
// Wishbone Risc V Instruction Memory Interface
@@ -286,7 +293,7 @@
// Global Register Wishbone Interface
//---------------------------------------------------------------------
wire wbd_uart_stb_o; // strobe/request
-wire [31:0] wbd_uart_adr_o; // address
+wire [7:0] wbd_uart_adr_o; // address
wire wbd_uart_we_o; // write
wire [31:0] wbd_uart_dat_o; // data output
wire [3:0] wbd_uart_sel_o; // byte enable
@@ -295,6 +302,57 @@
wire wbd_uart_ack_i; // acknowlegement
wire wbd_uart_err_i; // error
+//---------------------------------------------------------------------
+// MBIST1
+//---------------------------------------------------------------------
+wire wbd_mbist1_stb_o; // strobe/request
+wire [BIST1_ADDR_WD-1:0] wbd_mbist1_adr_o; // address
+wire wbd_mbist1_we_o; // write
+wire [WB_WIDTH-1:0] wbd_mbist1_dat_o; // data output
+wire [3:0] wbd_mbist1_sel_o; // byte enable
+wire wbd_mbist1_cyc_o ;
+wire [WB_WIDTH-1:0] wbd_mbist1_dat_i; // data input
+wire wbd_mbist1_ack_i; // acknowlegement
+wire wbd_mbist1_err_i; // error
+
+//---------------------------------------------------------------------
+// MBIST2
+//---------------------------------------------------------------------
+wire wbd_mbist2_stb_o; // strobe/request
+wire [BIST1_ADDR_WD-1:0] wbd_mbist2_adr_o; // address
+wire wbd_mbist2_we_o; // write
+wire [WB_WIDTH-1:0] wbd_mbist2_dat_o; // data output
+wire [3:0] wbd_mbist2_sel_o; // byte enable
+wire wbd_mbist2_cyc_o ;
+wire [WB_WIDTH-1:0] wbd_mbist2_dat_i; // data input
+wire wbd_mbist2_ack_i; // acknowlegement
+wire wbd_mbist2_err_i; // error
+
+//---------------------------------------------------------------------
+// MBIST2
+//---------------------------------------------------------------------
+wire wbd_mbist3_stb_o; // strobe/request
+wire [BIST1_ADDR_WD-1:0] wbd_mbist3_adr_o; // address
+wire wbd_mbist3_we_o; // write
+wire [WB_WIDTH-1:0] wbd_mbist3_dat_o; // data output
+wire [3:0] wbd_mbist3_sel_o; // byte enable
+wire wbd_mbist3_cyc_o ;
+wire [WB_WIDTH-1:0] wbd_mbist3_dat_i; // data input
+wire wbd_mbist3_ack_i; // acknowlegement
+wire wbd_mbist3_err_i; // error
+
+//---------------------------------------------------------------------
+// MBIST2
+//---------------------------------------------------------------------
+wire wbd_mbist4_stb_o; // strobe/request
+wire [BIST1_ADDR_WD-1:0] wbd_mbist4_adr_o; // address
+wire wbd_mbist4_we_o; // write
+wire [WB_WIDTH-1:0] wbd_mbist4_dat_o; // data output
+wire [3:0] wbd_mbist4_sel_o; // byte enable
+wire wbd_mbist4_cyc_o ;
+wire [WB_WIDTH-1:0] wbd_mbist4_dat_i; // data input
+wire wbd_mbist4_ack_i; // acknowlegement
+wire wbd_mbist4_err_i; // error
//----------------------------------------------------
// CPU Configuration
//----------------------------------------------------
@@ -304,11 +362,12 @@
wire uart_rst_n ;// uart reset
wire i2c_rst_n ;// i2c reset
wire usb_rst_n ;// i2c reset
-wire [1:0] uart_i2c_usb_sel ;// 0 - uart, 1 - I2C, 2- USb
+wire [3:0] boot_remap ;// Boot Remap
wire cpu_clk ;
wire rtc_clk ;
wire usb_clk ;
wire wbd_clk_int ;
+
wire wbd_clk_pinmux ;
//wire wbd_clk_int1 ;
//wire wbd_clk_int2 ;
@@ -320,24 +379,58 @@
wire [15:0] irq_lines ;
wire soft_irq ;
+
wire [7:0] cfg_glb_ctrl ;
wire [31:0] cfg_clk_ctrl1 ;
wire [31:0] cfg_clk_ctrl2 ;
wire [3:0] cfg_cska_wi ; // clock skew adjust for wishbone interconnect
-wire [3:0] cfg_cska_riscv; // clock skew adjust for riscv
-wire [3:0] cfg_cska_uart ; // clock skew adjust for uart
-wire [3:0] cfg_cska_spi ; // clock skew adjust for spi
-wire [3:0] cfg_cska_pinmux; // clock skew adjust for pinmux
-wire [3:0] cfg_cska_sp_co ; // clock skew adjust for global reg
wire [3:0] cfg_cska_wh ; // clock skew adjust for web host
+wire [3:0] cfg_cska_riscv; // clock skew adjust for riscv
+wire [3:0] cfg_cska_uart ; // clock skew adjust for uart
+wire [3:0] cfg_cska_qspi ; // clock skew adjust for spi
+wire [3:0] cfg_cska_pinmux; // clock skew adjust for pinmux
+wire [3:0] cfg_cska_qspi_co ; // clock skew adjust for global reg
+wire [3:0] cfg_cska_mbist1;
+wire [3:0] cfg_cska_mbist2;
+wire [3:0] cfg_cska_mbist3;
+wire [3:0] cfg_cska_mbist4;
-wire wbd_clk_wi ; // clock for wishbone interconnect
-wire wbd_clk_riscv ; // clock for riscv
-wire wbd_clk_uart ; // clock for uart
-wire wbd_clk_spi ; // clock for spi
-wire wbd_clk_glbl ; // clock for global reg
-wire wbd_clk_wh ; // clock for global reg
+// Bus Repeater Signals output from Wishbone Interface
+wire [3:0] cfg_cska_riscv_rp ; // clock skew adjust for riscv
+wire [3:0] cfg_cska_uart_rp ; // clock skew adjust for uart
+wire [3:0] cfg_cska_qspi_rp ; // clock skew adjust for spi
+wire [3:0] cfg_cska_pinmux_rp ; // clock skew adjust for pinmux
+wire [3:0] cfg_cska_qspi_co_rp; // clock skew adjust for global reg
+wire [3:0] cfg_cska_mbist1_rp ;
+wire [3:0] cfg_cska_mbist2_rp ;
+wire [3:0] cfg_cska_mbist3_rp ;
+wire [3:0] cfg_cska_mbist4_rp ;
+
+wire [31:0] fuse_mhartid_rp ; // Repeater
+wire [15:0] irq_lines_rp ; // Repeater
+wire soft_irq_rp ; // Repeater
+
+wire wbd_clk_risc_rp ;
+wire wbd_clk_qspi_rp ;
+wire wbd_clk_uart_rp ;
+wire wbd_clk_pinmux_rp ;
+wire wbd_clk_mbist1_rp ;
+wire wbd_clk_mbist2_rp ;
+wire wbd_clk_mbist3_rp ;
+wire wbd_clk_mbist4_rp ;
+
+// Progammable Clock Skew inserted signals
+wire wbd_clk_wi_skew ; // clock for wishbone interconnect with clock skew
+wire wbd_clk_riscv_skew ; // clock for riscv with clock skew
+wire wbd_clk_uart_skew ; // clock for uart with clock skew
+wire wbd_clk_spi_skew ; // clock for spi with clock skew
+wire wbd_clk_glbl_skew ; // clock for global reg with clock skew
+wire wbd_clk_wh_skew ; // clock for global reg
+wire wbd_clk_mbist1_skew; // clock for global reg
+wire wbd_clk_mbist2_skew; // clock for global reg
+wire wbd_clk_mbist3_skew; // clock for global reg
+wire wbd_clk_mbist4_skew; // clock for global reg
@@ -413,18 +506,120 @@
wire usb_intr_o ;
wire i2cm_intr_o ;
+
+//----------------------------------------------------------
+// BIST I/F
+// ---------------------------------------------------------
+wire [3:0] bist_en ;
+wire [3:0] bist_run ;
+wire [3:0] bist_load ;
+
+wire [3:0] bist_sdi ;
+wire [3:0] bist_shift ;
+wire [3:0] bist_sdo ;
+
+wire [3:0] bist_done ;
+wire [3:0] bist_error ;
+wire [3:0] bist_correct ;
+wire [3:0] bist_error_cnt0 ;
+wire [3:0] bist_error_cnt1 ;
+wire [3:0] bist_error_cnt2 ;
+wire [3:0] bist_error_cnt3 ;
+
+// With Repeater Buffer
+wire [3:0] bist_en_rp ;
+wire [3:0] bist_run_rp ;
+wire [3:0] bist_load_rp ;
+
+wire [3:0] bist_sdi_rp ;
+wire [3:0] bist_shift_rp ;
+wire [3:0] bist_sdo_rp ;
+
+wire [3:0] bist_done_rp ;
+wire [3:0] bist_error_rp ;
+wire [3:0] bist_correct_rp ;
+wire [3:0] bist_error_cnt0_rp ;
+wire [3:0] bist_error_cnt1_rp ;
+wire [3:0] bist_error_cnt2_rp ;
+wire [3:0] bist_error_cnt3_rp ;
+
+// towards memory MBIST1
+// PORT-A
+wire mem1_clk_a;
+wire [BIST1_ADDR_WD-1:2] mem1_addr_a;
+wire mem1_cen_a;
+wire [BIST_DATA_WD-1:0] mem1_din_b;
+
+// PORT-B
+wire mem1_clk_b;
+wire mem1_cen_b;
+wire mem1_web_b;
+wire [BIST_DATA_WD/8-1:0] mem1_mask_b;
+wire [BIST1_ADDR_WD-1:2] mem1_addr_b;
+wire [BIST_DATA_WD-1:0] mem1_dout_a;
+
+// towards memory MBIST2
+// PORT-A
+wire mem2_clk_a;
+wire [BIST1_ADDR_WD-1:2] mem2_addr_a;
+wire mem2_cen_a;
+wire [BIST_DATA_WD-1:0] mem2_din_b;
+
+// PORT-B
+wire mem2_clk_b;
+wire mem2_cen_b;
+wire mem2_web_b;
+wire [BIST_DATA_WD/8-1:0] mem2_mask_b;
+wire [BIST1_ADDR_WD-1:2] mem2_addr_b;
+wire [BIST_DATA_WD-1:0] mem2_dout_a;
+
+// towards memory MBIST3
+// PORT-A
+wire mem3_clk_a;
+wire [BIST1_ADDR_WD-1:2] mem3_addr_a;
+wire mem3_cen_a;
+wire [BIST_DATA_WD-1:0] mem3_din_b;
+
+// PORT-B
+wire mem3_clk_b;
+wire mem3_cen_b;
+wire mem3_web_b;
+wire [BIST_DATA_WD/8-1:0] mem3_mask_b;
+wire [BIST1_ADDR_WD-1:2] mem3_addr_b;
+wire [BIST_DATA_WD-1:0] mem3_dout_a;
+
+// towards memory MBIST4
+// PORT-A
+wire mem4_clk_a;
+wire [BIST1_ADDR_WD-1:2] mem4_addr_a;
+wire mem4_cen_a;
+wire [BIST_DATA_WD-1:0] mem4_din_b;
+
+// PORT-B
+wire mem4_clk_b;
+wire mem4_cen_b;
+wire mem4_web_b;
+wire [BIST_DATA_WD/8-1:0] mem4_mask_b;
+wire [BIST1_ADDR_WD-1:2] mem4_addr_b;
+wire [BIST_DATA_WD-1:0] mem4_dout_a;
+
/////////////////////////////////////////////////////////
// Clock Skew Ctrl
////////////////////////////////////////////////////////
assign cfg_cska_wi = cfg_clk_ctrl1[3:0];
-assign cfg_cska_riscv = cfg_clk_ctrl1[7:4];
-assign cfg_cska_uart = cfg_clk_ctrl1[11:8];
-assign cfg_cska_spi = cfg_clk_ctrl1[15:12];
-assign cfg_cska_pinmux = cfg_clk_ctrl1[19:16];
-assign cfg_cska_wh = cfg_clk_ctrl1[23:20];
-assign cfg_cska_sp_co = cfg_clk_ctrl1[27:24];
+assign cfg_cska_wh = cfg_clk_ctrl1[7:4];
+assign cfg_cska_riscv = cfg_clk_ctrl1[11:8];
+assign cfg_cska_qspi = cfg_clk_ctrl1[15:12];
+assign cfg_cska_uart = cfg_clk_ctrl1[19:16];
+assign cfg_cska_pinmux = cfg_clk_ctrl1[23:20];
+assign cfg_cska_qspi_co = cfg_clk_ctrl1[27:24];
+assign cfg_cska_mbist1 = cfg_clk_ctrl2[3:0];
+assign cfg_cska_mbist2 = cfg_clk_ctrl2[7:4];
+assign cfg_cska_mbist3 = cfg_clk_ctrl2[11:8];
+assign cfg_cska_mbist4 = cfg_clk_ctrl2[15:12];
+assign boot_remap = cfg_clk_ctrl2[31:28];
//assign la_data_out = {riscv_debug,spi_debug,sdram_debug};
assign la_data_out[127:0] = {pinmux_debug,spi_debug,riscv_debug};
@@ -454,7 +649,7 @@
.uart_rst_n (uart_rst_n ), // uart reset
.i2cm_rst_n (i2c_rst_n ), // i2c reset
.usb_rst_n (usb_rst_n ), // usb reset
- .uart_i2c_usb_sel (uart_i2c_usb_sel ), // 0 - uart, 1 - I2C, 2- USB
+ .bist_rst_n (bist_rst_n ), // BIST Reset
// Master Port
.wbm_rst_i (wb_rst_i ),
@@ -503,9 +698,9 @@
.vccd1 (vccd1 ),// User area 1 1.8V supply
.vssd1 (vssd1 ),// User area 1 digital ground
`endif
- .wbd_clk_int (wbd_clk_int ),
- .cfg_cska_riscv (cfg_cska_riscv ),
- .wbd_clk_riscv (wbd_clk_riscv ),
+ .wbd_clk_int (wbd_clk_risc_rp ),
+ .cfg_cska_riscv (cfg_cska_riscv_rp ),
+ .wbd_clk_riscv (wbd_clk_riscv_skew ),
// Reset
.pwrup_rst_n (wbd_int_rst_n ),
@@ -518,11 +713,11 @@
.rtc_clk (rtc_clk ),
// Fuses
- .fuse_mhartid (fuse_mhartid ),
+ .fuse_mhartid (fuse_mhartid_rp ),
// IRQ
- .irq_lines (irq_lines ),
- .soft_irq (soft_irq ), // TODO - Interrupts
+ .irq_lines (irq_lines_rp ),
+ .soft_irq (soft_irq_rp ), // TODO - Interrupts
// DFT
// .test_mode (1'b0 ), // Moved inside IP
@@ -544,7 +739,7 @@
`endif
.wb_rst_n (wbd_int_rst_n ),
- .wb_clk (wbd_clk_riscv ),
+ .wb_clk (wbd_clk_riscv_skew ),
// Instruction memory interface
.wbd_imem_stb_o (wbd_riscv_imem_stb_i ),
.wbd_imem_adr_o (wbd_riscv_imem_adr_i ),
@@ -612,9 +807,9 @@
.rst_n (qspim_rst_n ),
// Clock Skew Adjust
- .cfg_cska_sp_co (cfg_cska_sp_co ),
- .cfg_cska_spi (cfg_cska_spi ),
- .wbd_clk_int (wbd_clk_int ),
+ .cfg_cska_sp_co (cfg_cska_qspi_co_rp ),
+ .cfg_cska_spi (cfg_cska_qspi_rp ),
+ .wbd_clk_int (wbd_clk_qspi_rp ),
.wbd_clk_spi (wbd_clk_spi ),
.wbd_stb_i (wbd_spim_stb_o ),
@@ -639,18 +834,161 @@
-wb_interconnect u_intercon (
+wb_interconnect #(
+ `ifndef SYNTHESIS
+ .CH_CLK_WD(8),
+ .CH_DATA_WD(137)
+ `endif
+ ) u_intercon (
`ifdef USE_POWER_PINS
.vccd1 (vccd1 ),// User area 1 1.8V supply
.vssd1 (vssd1 ),// User area 1 digital ground
`endif
+ .ch_clk_in ({
+ wbd_clk_int,
+ wbd_clk_int,
+ wbd_clk_int,
+ wbd_clk_int,
+ wbd_clk_int,
+ wbd_clk_int,
+ wbd_clk_int,
+ wbd_clk_int}),
+ .ch_clk_out ({
+ wbd_clk_mbist4_rp,
+ wbd_clk_mbist3_rp,
+ wbd_clk_mbist2_rp,
+ wbd_clk_mbist1_rp,
+ wbd_clk_pinmux_rp,
+ wbd_clk_uart_rp,
+ wbd_clk_qspi_rp,
+ wbd_clk_risc_rp}),
+ .ch_data_in ({
+ bist_error_cnt3[3:0],
+ bist_correct[3],
+ bist_error[3],
+ bist_done[3],
+ bist_sdo[3],
+ bist_shift[3],
+ bist_sdi[3],
+ bist_load[3],
+ bist_run[3],
+ bist_en[3],
+
+ bist_error_cnt2[3:0],
+ bist_correct[2],
+ bist_error[2],
+ bist_done[2],
+ bist_sdo[2],
+ bist_shift[2],
+ bist_sdi[2],
+ bist_load[2],
+ bist_run[2],
+ bist_en[2],
+
+ bist_error_cnt1[3:0],
+ bist_correct[1],
+ bist_error[1],
+ bist_done[1],
+ bist_sdo[1],
+ bist_shift[1],
+ bist_sdi[1],
+ bist_load[1],
+ bist_run[1],
+ bist_en[1],
+
+ bist_error_cnt0[3:0],
+ bist_correct[0],
+ bist_error[0],
+ bist_done[0],
+ bist_sdo[0],
+ bist_shift[0],
+ bist_sdi[0],
+ bist_load[0],
+ bist_run[0],
+ bist_en[0],
+
+
+ soft_irq,
+ irq_lines[15:0],
+ fuse_mhartid[31:0],
+
+ cfg_cska_mbist4[3:0],
+ cfg_cska_mbist3[3:0],
+ cfg_cska_mbist2[3:0],
+ cfg_cska_mbist1[3:0],
+ cfg_cska_qspi_co[3:0],
+ cfg_cska_pinmux[3:0],
+ cfg_cska_uart[3:0],
+ cfg_cska_qspi[3:0],
+ cfg_cska_riscv[3:0]
+ } ),
+ .ch_data_out ({
+ bist_error_cnt3_rp[3:0],
+ bist_correct_rp[3],
+ bist_error_rp[3],
+ bist_done_rp[3],
+ bist_sdo_rp[3],
+ bist_shift_rp[3],
+ bist_sdi_rp[3],
+ bist_load_rp[3],
+ bist_run_rp[3],
+ bist_en_rp[3],
+
+ bist_error_cnt2_rp[3:0],
+ bist_correct_rp[2],
+ bist_error_rp[2],
+ bist_done_rp[2],
+ bist_sdo_rp[2],
+ bist_shift_rp[2],
+ bist_sdi_rp[2],
+ bist_load_rp[2],
+ bist_run_rp[2],
+ bist_en_rp[2],
+
+ bist_error_cnt1_rp[3:0],
+ bist_correct_rp[1],
+ bist_error_rp[1],
+ bist_done_rp[1],
+ bist_sdo_rp[1],
+ bist_shift_rp[1],
+ bist_sdi_rp[1],
+ bist_load_rp[1],
+ bist_run_rp[1],
+ bist_en_rp[1],
+
+ bist_error_cnt0_rp[3:0],
+ bist_correct_rp[0],
+ bist_error_rp[0],
+ bist_done_rp[0],
+ bist_sdo_rp[0],
+ bist_shift_rp[0],
+ bist_sdi_rp[0],
+ bist_load_rp[0],
+ bist_run_rp[0],
+ bist_en_rp[0],
+
+ soft_irq_rp,
+ irq_lines_rp[15:0],
+ fuse_mhartid_rp[31:0],
+
+ cfg_cska_mbist4_rp[3:0],
+ cfg_cska_mbist3_rp[3:0],
+ cfg_cska_mbist2_rp[3:0],
+ cfg_cska_mbist1_rp[3:0],
+ cfg_cska_qspi_co_rp[3:0],
+ cfg_cska_pinmux_rp[3:0],
+ cfg_cska_uart_rp[3:0],
+ cfg_cska_qspi_rp[3:0],
+ cfg_cska_riscv_rp[3:0]
+ }),
// Clock Skew adjust
.wbd_clk_int (wbd_clk_int ),
.cfg_cska_wi (cfg_cska_wi ),
- .wbd_clk_wi (wbd_clk_wi ),
+ .wbd_clk_wi (wbd_clk_wi_skew ),
- .clk_i (wbd_clk_wi ),
+ .clk_i (wbd_clk_wi_skew ),
.rst_n (wbd_int_rst_n ),
+ .boot_remap (boot_remap ),
// Master 0 Interface
.m0_wbd_dat_i (wbd_int_dat_i ),
@@ -710,25 +1048,58 @@
// Slave 2 Interface
// .s2_wbd_err_i (1'b0 ), - Moved inside IP
- .s2_wbd_dat_i (wbd_adc_dat_i ),
- .s2_wbd_ack_i (wbd_adc_ack_i ),
- .s2_wbd_dat_o (wbd_adc_dat_o ),
- .s2_wbd_adr_o (wbd_adc_adr_o ),
- .s2_wbd_sel_o (wbd_adc_sel_o ),
- .s2_wbd_we_o (wbd_adc_we_o ),
- .s2_wbd_cyc_o (wbd_adc_cyc_o ),
- .s2_wbd_stb_o (wbd_adc_stb_o ),
+ .s2_wbd_dat_i (wbd_glbl_dat_i ),
+ .s2_wbd_ack_i (wbd_glbl_ack_i ),
+ .s2_wbd_dat_o (wbd_glbl_dat_o ),
+ .s2_wbd_adr_o (wbd_glbl_adr_o ),
+ .s2_wbd_sel_o (wbd_glbl_sel_o ),
+ .s2_wbd_we_o (wbd_glbl_we_o ),
+ .s2_wbd_cyc_o (wbd_glbl_cyc_o ),
+ .s2_wbd_stb_o (wbd_glbl_stb_o ),
// Slave 3 Interface
- // .s3_wbd_err_i (1'b0 ), - Moved inside IP
- .s3_wbd_dat_i (wbd_glbl_dat_i ),
- .s3_wbd_ack_i (wbd_glbl_ack_i ),
- .s3_wbd_dat_o (wbd_glbl_dat_o ),
- .s3_wbd_adr_o (wbd_glbl_adr_o ),
- .s3_wbd_sel_o (wbd_glbl_sel_o ),
- .s3_wbd_we_o (wbd_glbl_we_o ),
- .s3_wbd_cyc_o (wbd_glbl_cyc_o ),
- .s3_wbd_stb_o (wbd_glbl_stb_o )
+ // .s3_wbd_err_i (1'b0 ), - Moved inside IP
+ .s3_wbd_dat_i (wbd_mbist1_dat_i ),
+ .s3_wbd_ack_i (wbd_mbist1_ack_i ),
+ .s3_wbd_dat_o (wbd_mbist1_dat_o ),
+ .s3_wbd_adr_o (wbd_mbist1_adr_o ),
+ .s3_wbd_sel_o (wbd_mbist1_sel_o ),
+ .s3_wbd_we_o (wbd_mbist1_we_o ),
+ .s3_wbd_cyc_o (wbd_mbist1_cyc_o ),
+ .s3_wbd_stb_o (wbd_mbist1_stb_o ),
+
+ // Slave 4 Interface
+ // .s4_wbd_err_i (1'b0 ), - Moved inside IP
+ .s4_wbd_dat_i (wbd_mbist2_dat_i ),
+ .s4_wbd_ack_i (wbd_mbist2_ack_i ),
+ .s4_wbd_dat_o (wbd_mbist2_dat_o ),
+ .s4_wbd_adr_o (wbd_mbist2_adr_o ),
+ .s4_wbd_sel_o (wbd_mbist2_sel_o ),
+ .s4_wbd_we_o (wbd_mbist2_we_o ),
+ .s4_wbd_cyc_o (wbd_mbist2_cyc_o ),
+ .s4_wbd_stb_o (wbd_mbist2_stb_o ),
+
+ // Slave 5 Interface
+ // .s5_wbd_err_i (1'b0 ), - Moved inside IP
+ .s5_wbd_dat_i (wbd_mbist3_dat_i ),
+ .s5_wbd_ack_i (wbd_mbist3_ack_i ),
+ .s5_wbd_dat_o (wbd_mbist3_dat_o ),
+ .s5_wbd_adr_o (wbd_mbist3_adr_o ),
+ .s5_wbd_sel_o (wbd_mbist3_sel_o ),
+ .s5_wbd_we_o (wbd_mbist3_we_o ),
+ .s5_wbd_cyc_o (wbd_mbist3_cyc_o ),
+ .s5_wbd_stb_o (wbd_mbist3_stb_o ),
+
+ // Slave 6 Interface
+ // .s6_wbd_err_i (1'b0 ), - Moved inside IP
+ .s6_wbd_dat_i (wbd_mbist4_dat_i ),
+ .s6_wbd_ack_i (wbd_mbist4_ack_i ),
+ .s6_wbd_dat_o (wbd_mbist4_dat_o ),
+ .s6_wbd_adr_o (wbd_mbist4_adr_o ),
+ .s6_wbd_sel_o (wbd_mbist4_sel_o ),
+ .s6_wbd_we_o (wbd_mbist4_we_o ),
+ .s6_wbd_cyc_o (wbd_mbist4_cyc_o ),
+ .s6_wbd_stb_o (wbd_mbist4_stb_o )
);
@@ -737,15 +1108,15 @@
.vccd1 (vccd1 ),// User area 1 1.8V supply
.vssd1 (vssd1 ),// User area 1 digital ground
`endif
- .wbd_clk_int (wbd_clk_int ),
- .cfg_cska_uart (cfg_cska_uart ),
- .wbd_clk_uart (wbd_clk_uart ),
+ .wbd_clk_int (wbd_clk_uart_rp ),
+ .cfg_cska_uart (cfg_cska_uart_rp ),
+ .wbd_clk_uart (wbd_clk_uart_skew ),
.uart_rstn (uart_rst_n ), // uart reset
.i2c_rstn (i2c_rst_n ), // i2c reset
.usb_rstn (usb_rst_n ), // USB reset
.spi_rstn (sspim_rst_n ), // SPI reset
- .app_clk (wbd_clk_uart ),
+ .app_clk (wbd_clk_uart_skew ),
.usb_clk (usb_clk ),
// Reg Bus Interface Signal
@@ -797,13 +1168,13 @@
.vssd1 (vssd1 ),// User area 1 digital ground
`endif
//clk skew adjust
- .cfg_cska_pinmux (cfg_cska_pinmux ),
- .wbd_clk_int (wbd_clk_int ),
- .wbd_clk_pinmux (wbd_clk_pinmux ),
+ .cfg_cska_pinmux (cfg_cska_pinmux_rp ),
+ .wbd_clk_int (wbd_clk_pinmux_rp ),
+ .wbd_clk_pinmux (wbd_clk_pinmux_skew ),
// System Signals
// Inputs
- .mclk (wbd_clk_pinmux ),
+ .mclk (wbd_clk_pinmux_skew ),
.h_reset_n (wbd_int_rst_n ),
// Reg Bus Interface Signal
@@ -866,9 +1237,382 @@
.pulse1m_mclk (pulse1m_mclk ),
- .pinmux_debug (pinmux_debug )
- );
+ .pinmux_debug (pinmux_debug ),
+ // BIST I/F
+ .bist_en (bist_en ),
+ .bist_run (bist_run ),
+ .bist_load (bist_load ),
+
+ .bist_sdi (bist_sdi ),
+ .bist_shift (bist_shift ),
+ .bist_sdo (bist_sdo_rp ),
+
+ .bist_done (bist_done_rp ),
+ .bist_error (bist_error_rp ),
+ .bist_correct (bist_correct_rp ),
+ .bist_error_cnt0 (bist_error_cnt0_rp ),
+ .bist_error_cnt1 (bist_error_cnt1_rp ),
+ .bist_error_cnt2 (bist_error_cnt2_rp ),
+ .bist_error_cnt3 (bist_error_cnt3_rp )
+
+
+ );
+//------------- MBIST1 - 512x32 ----
+
+mbist_top1 #(
+ `ifndef SYNTHESIS
+ .BIST_ADDR_WD (BIST1_ADDR_WD-2 ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (9'h000 ),
+ .BIST_ADDR_END (9'h1FB ),
+ .BIST_REPAIR_ADDR_START (9'h1FC ),
+ .BIST_RAD_WD_I (BIST1_ADDR_WD-2 ),
+ .BIST_RAD_WD_O (BIST1_ADDR_WD-2 )
+ `endif
+ )
+ u_mbist1 (
+
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+
+ // Clock Skew adjust
+ .wbd_clk_int (wbd_clk_mbist1_rp ),
+ .cfg_cska_mbist (cfg_cska_mbist1_rp ),
+ .wbd_clk_mbist (wbd_clk_mbist1_skew ),
+
+ // WB I/F
+ .wb_clk_i (wbd_clk_mbist1_skew ),
+ .wb_cyc_i (wbd_mbist1_cyc_o),
+ .wb_stb_i (wbd_mbist1_stb_o),
+ .wb_adr_i (wbd_mbist1_adr_o[BIST1_ADDR_WD-1:2]),
+ .wb_we_i (wbd_mbist1_we_o ),
+ .wb_dat_i (wbd_mbist1_dat_o),
+ .wb_sel_i (wbd_mbist1_sel_o),
+ .wb_dat_o (wbd_mbist1_dat_i),
+ .wb_ack_o (wbd_mbist1_ack_i),
+ .wb_err_o ( ),
+
+ .rst_n (bist_rst_n ),
+
+
+ .bist_en (bist_en_rp[0] ),
+ .bist_run (bist_run_rp[0] ),
+ .bist_shift (bist_shift_rp[0] ),
+ .bist_load (bist_load_rp[0] ),
+ .bist_sdi (bist_sdi_rp[0] ),
+
+ .bist_error_cnt (bist_error_cnt0 ),
+ .bist_correct (bist_correct[0] ),
+ .bist_error (bist_error[0] ),
+ .bist_done (bist_done[0] ),
+ .bist_sdo (bist_sdo[0] ),
+
+ // towards memory
+ // PORT-A
+ .mem_clk_a (mem1_clk_a ),
+ .mem_addr_a (mem1_addr_a ),
+ .mem_cen_a (mem1_cen_a ),
+ .mem_dout_a (mem1_dout_a ),
+ // PORT-B
+ .mem_clk_b (mem1_clk_b ),
+ .mem_cen_b (mem1_cen_b ),
+ .mem_web_b (mem1_web_b ),
+ .mem_mask_b (mem1_mask_b ),
+ .mem_addr_b (mem1_addr_b ),
+ .mem_din_b (mem1_din_b )
+
+
+);
+
+sky130_sram_2kbyte_1rw1r_32x512_8 u_sram1_2kb(
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1),// User area 1 1.8V supply
+ .vssd1 (vssd1),// User area 1 digital ground
+`endif
+// Port 0: RW
+ .clk0 (mem1_clk_b),
+ .csb0 (mem1_cen_b),
+ .web0 (mem1_web_b),
+ .wmask0 (mem1_mask_b),
+ .addr0 (mem1_addr_b),
+ .din0 (mem1_din_b),
+ .dout0 (),
+// Port 1: R
+ .clk1 (mem1_clk_a),
+ .csb1 (mem1_cen_a),
+ .addr1 (mem1_addr_a),
+ .dout1 (mem1_dout_a)
+ );
+
+//------------- MBIST2 - 512x32 ----
+
+mbist_top1 #(
+ `ifndef SYNTHESIS
+ .BIST_ADDR_WD (BIST1_ADDR_WD-2 ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (9'h000 ),
+ .BIST_ADDR_END (9'h1FB ),
+ .BIST_REPAIR_ADDR_START (9'h1FC ),
+ .BIST_RAD_WD_I (BIST1_ADDR_WD-2 ),
+ .BIST_RAD_WD_O (BIST1_ADDR_WD-2 )
+ `endif
+ )
+ u_mbist2 (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+
+ // Clock Skew adjust
+ .wbd_clk_int (wbd_clk_mbist2_rp),
+ .cfg_cska_mbist (cfg_cska_mbist2_rp),
+ .wbd_clk_mbist (wbd_clk_mbist2_skew),
+
+ // WB I/F
+ .wb_clk_i (wbd_clk_mbist2_skew),
+ .wb_cyc_i (wbd_mbist2_cyc_o),
+ .wb_stb_i (wbd_mbist2_stb_o),
+ .wb_adr_i (wbd_mbist2_adr_o[BIST1_ADDR_WD-1:2]),
+ .wb_we_i (wbd_mbist2_we_o ),
+ .wb_dat_i (wbd_mbist2_dat_o),
+ .wb_sel_i (wbd_mbist2_sel_o),
+ .wb_dat_o (wbd_mbist2_dat_i),
+ .wb_ack_o (wbd_mbist2_ack_i),
+ .wb_err_o ( ),
+
+ .rst_n (bist_rst_n ),
+
+
+ .bist_en (bist_en_rp[1] ),
+ .bist_run (bist_run_rp[1] ),
+ .bist_shift (bist_shift_rp[1] ),
+ .bist_load (bist_load_rp[1] ),
+ .bist_sdi (bist_sdi_rp[1] ),
+
+ .bist_error_cnt (bist_error_cnt1 ),
+ .bist_correct (bist_correct[1] ),
+ .bist_error (bist_error[1] ),
+ .bist_done (bist_done[1] ),
+ .bist_sdo (bist_sdo[1] ),
+
+ // towards memory
+ // PORT-A
+ .mem_clk_a (mem2_clk_a ),
+ .mem_addr_a (mem2_addr_a ),
+ .mem_cen_a (mem2_cen_a ),
+ .mem_dout_a (mem2_dout_a ),
+ // PORT-B
+ .mem_clk_b (mem2_clk_b ),
+ .mem_cen_b (mem2_cen_b ),
+ .mem_web_b (mem2_web_b ),
+ .mem_mask_b (mem2_mask_b ),
+ .mem_addr_b (mem2_addr_b ),
+ .mem_din_b (mem2_din_b )
+
+
+);
+
+sky130_sram_2kbyte_1rw1r_32x512_8 u_sram2_2kb(
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1),// User area 1 1.8V supply
+ .vssd1 (vssd1),// User area 1 digital ground
+`endif
+// Port 0: RW
+ .clk0 (mem2_clk_b),
+ .csb0 (mem2_cen_b),
+ .web0 (mem2_web_b),
+ .wmask0 (mem2_mask_b),
+ .addr0 (mem2_addr_b),
+ .din0 (mem2_din_b),
+ .dout0 (),
+// Port 1: R
+ .clk1 (mem2_clk_a),
+ .csb1 (mem2_cen_a),
+ .addr1 (mem2_addr_a),
+ .dout1 (mem2_dout_a)
+ );
+
+
+//------------- MBIST3 - 512x32 ----
+
+mbist_top1 #(
+ `ifndef SYNTHESIS
+ .BIST_ADDR_WD (BIST1_ADDR_WD-2 ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (9'h000 ),
+ .BIST_ADDR_END (9'h1FB ),
+ .BIST_REPAIR_ADDR_START (9'h1FC ),
+ .BIST_RAD_WD_I (BIST1_ADDR_WD-2 ),
+ .BIST_RAD_WD_O (BIST1_ADDR_WD-2 )
+ `endif
+ )
+ u_mbist3 (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+
+ // Clock Skew adjust
+ .wbd_clk_int (wbd_clk_mbist3_rp),
+ .cfg_cska_mbist (cfg_cska_mbist3_rp),
+ .wbd_clk_mbist (wbd_clk_mbist3_skew),
+
+ // WB I/F
+ .wb_clk_i (wbd_clk_mbist3_skew),
+ .wb_cyc_i (wbd_mbist3_cyc_o),
+ .wb_stb_i (wbd_mbist3_stb_o),
+ .wb_adr_i (wbd_mbist3_adr_o[BIST1_ADDR_WD-1:2]),
+ .wb_we_i (wbd_mbist3_we_o ),
+ .wb_dat_i (wbd_mbist3_dat_o),
+ .wb_sel_i (wbd_mbist3_sel_o),
+ .wb_dat_o (wbd_mbist3_dat_i),
+ .wb_ack_o (wbd_mbist3_ack_i),
+ .wb_err_o ( ),
+
+ .rst_n (bist_rst_n ),
+
+
+ .bist_en (bist_en_rp[2] ),
+ .bist_run (bist_run_rp[2] ),
+ .bist_shift (bist_shift_rp[2] ),
+ .bist_load (bist_load_rp[2] ),
+ .bist_sdi (bist_sdi_rp[2] ),
+
+ .bist_error_cnt (bist_error_cnt2 ),
+ .bist_correct (bist_correct[2] ),
+ .bist_error (bist_error[2] ),
+ .bist_done (bist_done[2] ),
+ .bist_sdo (bist_sdo[2] ),
+
+ // towards memory
+ // PORT-A
+ .mem_clk_a (mem3_clk_a ),
+ .mem_addr_a (mem3_addr_a ),
+ .mem_cen_a (mem3_cen_a ),
+ .mem_dout_a (mem3_dout_a ),
+ // PORT-B
+ .mem_clk_b (mem3_clk_b ),
+ .mem_cen_b (mem3_cen_b ),
+ .mem_web_b (mem3_web_b ),
+ .mem_mask_b (mem3_mask_b ),
+ .mem_addr_b (mem3_addr_b ),
+ .mem_din_b (mem3_din_b )
+
+
+);
+
+sky130_sram_2kbyte_1rw1r_32x512_8 u_sram3_2kb(
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1),// User area 1 1.8V supply
+ .vssd1 (vssd1),// User area 1 digital ground
+`endif
+// Port 0: RW
+ .clk0 (mem3_clk_b),
+ .csb0 (mem3_cen_b),
+ .web0 (mem3_web_b),
+ .wmask0 (mem3_mask_b),
+ .addr0 (mem3_addr_b),
+ .din0 (mem3_din_b),
+ .dout0 (),
+// Port 1: R
+ .clk1 (mem3_clk_a),
+ .csb1 (mem3_cen_a),
+ .addr1 (mem3_addr_a),
+ .dout1 (mem3_dout_a)
+ );
+
+//------------- MBIST4 - 512x32 ----
+
+mbist_top1 #(
+ `ifndef SYNTHESIS
+ .BIST_ADDR_WD (BIST1_ADDR_WD-2 ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (9'h000 ),
+ .BIST_ADDR_END (9'h1FB ),
+ .BIST_REPAIR_ADDR_START (9'h1FC ),
+ .BIST_RAD_WD_I (BIST1_ADDR_WD-2 ),
+ .BIST_RAD_WD_O (BIST1_ADDR_WD-2 )
+ `endif
+ )
+ u_mbist4 (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+
+ // Clock Skew adjust
+ .wbd_clk_int (wbd_clk_mbist4_rp),
+ .cfg_cska_mbist (cfg_cska_mbist4_rp),
+ .wbd_clk_mbist (wbd_clk_mbist4_skew),
+
+ // WB I/F
+ .wb_clk_i (wbd_clk_mbist4_skew),
+ .wb_cyc_i (wbd_mbist4_cyc_o),
+ .wb_stb_i (wbd_mbist4_stb_o),
+ .wb_adr_i (wbd_mbist4_adr_o[BIST1_ADDR_WD-1:2]),
+ .wb_we_i (wbd_mbist4_we_o ),
+ .wb_dat_i (wbd_mbist4_dat_o),
+ .wb_sel_i (wbd_mbist4_sel_o),
+ .wb_dat_o (wbd_mbist4_dat_i),
+ .wb_ack_o (wbd_mbist4_ack_i),
+ .wb_err_o ( ),
+
+ .rst_n (bist_rst_n ),
+
+
+ .bist_en (bist_en_rp[3] ),
+ .bist_run (bist_run_rp[3] ),
+ .bist_shift (bist_shift_rp[3] ),
+ .bist_load (bist_load_rp[3] ),
+ .bist_sdi (bist_sdi_rp[3] ),
+
+ .bist_error_cnt (bist_error_cnt3 ),
+ .bist_correct (bist_correct[3] ),
+ .bist_error (bist_error[3] ),
+ .bist_done (bist_done[3] ),
+ .bist_sdo (bist_sdo[3] ),
+
+ // towards memory
+ // PORT-A
+ .mem_clk_a (mem4_clk_a ),
+ .mem_addr_a (mem4_addr_a ),
+ .mem_cen_a (mem4_cen_a ),
+ .mem_dout_a (mem4_dout_a ),
+ // PORT-B
+ .mem_clk_b (mem4_clk_b ),
+ .mem_cen_b (mem4_cen_b ),
+ .mem_web_b (mem4_web_b ),
+ .mem_mask_b (mem4_mask_b ),
+ .mem_addr_b (mem4_addr_b ),
+ .mem_din_b (mem4_din_b )
+
+
+);
+
+sky130_sram_2kbyte_1rw1r_32x512_8 u_sram4_2kb(
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1),// User area 1 1.8V supply
+ .vssd1 (vssd1),// User area 1 digital ground
+`endif
+// Port 0: RW
+ .clk0 (mem4_clk_b),
+ .csb0 (mem4_cen_b),
+ .web0 (mem4_web_b),
+ .wmask0 (mem4_mask_b),
+ .addr0 (mem4_addr_b),
+ .din0 (mem4_din_b),
+ .dout0 (),
+// Port 1: R
+ .clk1 (mem4_clk_a),
+ .csb1 (mem4_cen_a),
+ .addr1 (mem4_addr_a),
+ .dout1 (mem4_dout_a)
+ );
+
+/***
sar_adc u_adc (
`ifdef USE_POWER_PINS
.vccd1 (vccd1),// User area 1 1.8V supply
@@ -878,8 +1622,8 @@
`endif
- .clk (wbd_clk_int),// The clock (digital)
- .reset_n (wbd_int_rst_n),// Active low reset (digital)
+ .clk (wbd_clk_adc_rp ),// The clock (digital)
+ .reset_n (wbd_int_rst_n ),// Active low reset (digital)
// Reg Bus Interface Signal
.reg_cs (wbd_adc_stb_o ),
@@ -904,6 +1648,7 @@
.analog_din(analog_io[5:0]) // (Analog)
);
+***/
/****
* TODO: Need to uncomment the DAC
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv
index 259a94f..988f9eb 100644
--- a/verilog/rtl/wb_host/src/wb_host.sv
+++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -88,7 +88,7 @@
output logic uart_rst_n ,
output logic i2cm_rst_n ,
output logic usb_rst_n ,
- output logic [1:0] uart_i2c_usb_sel ,
+ output logic bist_rst_n ,
// Master Port
input logic wbm_rst_i , // Regular Reset signal
@@ -160,19 +160,20 @@
logic [3:0] cfg_cpu_clk_ctrl;
logic [7:0] cfg_rtc_clk_ctrl;
logic [3:0] cfg_usb_clk_ctrl;
-logic [6:0] cfg_glb_ctrl;
+logic [8:0] cfg_glb_ctrl;
assign wbm_rst_n = !wbm_rst_i;
assign wbs_rst_n = !wbm_rst_i;
-sky130_fd_sc_hd__bufbuf_16 u_buf_wb_rst (.A(cfg_glb_ctrl[0]),.X(wbd_int_rst_n));
-sky130_fd_sc_hd__bufbuf_16 u_buf_cpu_rst (.A(cfg_glb_ctrl[1]),.X(cpu_rst_n));
-sky130_fd_sc_hd__bufbuf_16 u_buf_qspim_rst (.A(cfg_glb_ctrl[2]),.X(qspim_rst_n));
-sky130_fd_sc_hd__bufbuf_16 u_buf_sspim_rst (.A(cfg_glb_ctrl[3]),.X(sspim_rst_n));
-sky130_fd_sc_hd__bufbuf_16 u_buf_uart_rst (.A(cfg_glb_ctrl[4]),.X(uart_rst_n));
-sky130_fd_sc_hd__bufbuf_16 u_buf_i2cm_rst (.A(cfg_glb_ctrl[5]),.X(i2cm_rst_n));
-sky130_fd_sc_hd__bufbuf_16 u_buf_usb_rst (.A(cfg_glb_ctrl[6]),.X(usb_rst_n));
+ctech_buf u_buf_wb_rst (.A(cfg_glb_ctrl[0]),.X(wbd_int_rst_n));
+ctech_buf u_buf_cpu_rst (.A(cfg_glb_ctrl[1]),.X(cpu_rst_n));
+ctech_buf u_buf_qspim_rst (.A(cfg_glb_ctrl[2]),.X(qspim_rst_n));
+ctech_buf u_buf_sspim_rst (.A(cfg_glb_ctrl[3]),.X(sspim_rst_n));
+ctech_buf u_buf_uart_rst (.A(cfg_glb_ctrl[4]),.X(uart_rst_n));
+ctech_buf u_buf_i2cm_rst (.A(cfg_glb_ctrl[5]),.X(i2cm_rst_n));
+ctech_buf u_buf_usb_rst (.A(cfg_glb_ctrl[6]),.X(usb_rst_n));
+ctech_buf u_buf_bist_rst (.A(cfg_glb_ctrl[7]),.X(bist_rst_n));
// wb_host clock skew control
clk_skew_adjust u_skew_wh
@@ -196,9 +197,9 @@
logic wb_req;
// Hold fix for STROBE
wire wbm_stb_d1,wbm_stb_d2,wbm_stb_d3;
-sky130_fd_sc_hd__dlygate4sd3_1 u_delay1_stb0 (.X(wbm_stb_d1),.A(wbm_stb_i));
-sky130_fd_sc_hd__dlygate4sd3_1 u_delay2_stb1 (.X(wbm_stb_d2),.A(wbm_stb_d1));
-sky130_fd_sc_hd__dlygate4sd3_1 u_delay2_stb2 (.X(wbm_stb_d3),.A(wbm_stb_d2));
+ctech_delay_buf u_delay1_stb0 (.X(wbm_stb_d1),.A(wbm_stb_i));
+ctech_delay_buf u_delay2_stb1 (.X(wbm_stb_d2),.A(wbm_stb_d1));
+ctech_delay_buf u_delay2_stb2 (.X(wbm_stb_d3),.A(wbm_stb_d2));
always_ff @(negedge wbm_rst_n or posedge wbm_clk_i) begin
if ( wbm_rst_n == 1'b0 ) begin
wb_req <= '0;
@@ -262,8 +263,7 @@
//-------------------------------------
// Global + Clock Control
// -------------------------------------
-assign cfg_glb_ctrl = reg_0[6:0];
-assign uart_i2c_usb_sel = reg_0[8:7];
+assign cfg_glb_ctrl = reg_0[8:0];
assign cfg_wb_clk_ctrl = reg_0[11:9];
assign cfg_rtc_clk_ctrl = reg_0[19:12];
assign cfg_cpu_clk_ctrl = reg_0[23:20];
@@ -405,7 +405,7 @@
ctech_mux2x1 u_cpu_ref_sel (.A0 (user_clock1), .A1 (user_clock2), .S (cfg_cpu_clk_src_sel), .X (cpu_ref_clk));
ctech_mux2x1 u_cpu_clk_sel (.A0 (cpu_ref_clk), .A1 (cpu_clk_div), .S (cfg_cpu_clk_div), .X (cpu_clk_int));
-sky130_fd_sc_hd__clkbuf_16 u_clkbuf_cpu (.A (cpu_clk_int), . X(cpu_clk));
+ctech_clk_buf u_clkbuf_cpu (.A (cpu_clk_int), . X(cpu_clk));
clk_ctl #(1) u_cpuclk (
// Outputs
@@ -423,7 +423,7 @@
wire [7:0] cfg_rtc_clk_ratio = cfg_rtc_clk_ctrl[7:0];
-sky130_fd_sc_hd__clkbuf_16 u_clkbuf_rtc (.A (rtc_clk_div), . X(rtc_clk));
+ctech_clk_buf u_clkbuf_rtc (.A (rtc_clk_div), . X(rtc_clk));
clk_ctl #(7) u_rtcclk (
// Outputs
@@ -450,7 +450,7 @@
ctech_mux2x1 u_usb_clk_sel (.A0 (usb_ref_clk), .A1 (usb_clk_div), .S (cfg_usb_clk_div), .X (usb_clk_int));
-sky130_fd_sc_hd__clkbuf_16 u_clkbuf_usb (.A (usb_clk_int), . X(usb_clk));
+ctech_clk_buf u_clkbuf_usb (.A (usb_clk_int), . X(usb_clk));
clk_ctl #(2) u_usbclk (
// Outputs
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
index ae60de7..ebd1fcd 100644
--- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
+++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -56,6 +56,14 @@
//// Push the clock skew logic inside the block due to ////
//// global power hooking challanges for small block at ////
//// top level ////
+//// 0.7 - 07 Dec 2021, Dinesh A ////
+//// Buffer channel are added insider wb_inter to simply ////
+//// global routing ////
+//// 0.8 -10 Dec 2021 , Dinesh A ////
+//// two more slave port added for MBIST and ADC port ////
+//// removed ////
+//// Memory remap added to move the RISC Program memory ////
+//// to SRAM Memory ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
@@ -86,11 +94,20 @@
-module wb_interconnect(
+module wb_interconnect #(
+ parameter CH_CLK_WD = 7,
+ parameter CH_DATA_WD = 103
+ ) (
`ifdef USE_POWER_PINS
input logic vccd1, // User area 1 1.8V supply
input logic vssd1, // User area 1 digital ground
`endif
+ // Bus repeaters
+ input [CH_CLK_WD-1:0] ch_clk_in,
+ output [CH_CLK_WD-1:0] ch_clk_out,
+ input [CH_DATA_WD-1:0] ch_data_in,
+ output [CH_DATA_WD-1:0]ch_data_out,
+
// Clock Skew Adjust
input logic [3:0] cfg_cska_wi,
input logic wbd_clk_int,
@@ -99,6 +116,10 @@
input logic clk_i,
input logic rst_n,
+
+ input logic [3:0] boot_remap, // When remap is enabled
+ // [0] - 0x0000_0000 - 0x0000_07FF Map to MBIST1
+ // [1] - 0x0000_0800 - 0x0000_0FFF Map to MBIST2
// Master 0 Interface
input logic [31:0] m0_wbd_dat_i,
@@ -150,7 +171,7 @@
input logic s1_wbd_ack_i,
// input logic s1_wbd_err_i, - unused
output logic [31:0] s1_wbd_dat_o,
- output logic [31:0] s1_wbd_adr_o,
+ output logic [7:0] s1_wbd_adr_o,
output logic [3:0] s1_wbd_sel_o,
output logic s1_wbd_we_o,
output logic s1_wbd_cyc_o,
@@ -168,16 +189,52 @@
output logic s2_wbd_stb_o,
// Slave 3 Interface
- // Uart is 8bit interface
+ // MBIST
input logic [31:0] s3_wbd_dat_i,
input logic s3_wbd_ack_i,
// input logic s3_wbd_err_i,
output logic [31:0] s3_wbd_dat_o,
- output logic [7:0] s3_wbd_adr_o,
+ output logic [10:0] s3_wbd_adr_o,
output logic [3:0] s3_wbd_sel_o,
output logic s3_wbd_we_o,
output logic s3_wbd_cyc_o,
- output logic s3_wbd_stb_o
+ output logic s3_wbd_stb_o,
+
+ // Slave 4 Interface
+ // MBIST2
+ input logic [31:0] s4_wbd_dat_i,
+ input logic s4_wbd_ack_i,
+ // input logic s4_wbd_err_i,
+ output logic [31:0] s4_wbd_dat_o,
+ output logic [10:0] s4_wbd_adr_o,
+ output logic [3:0] s4_wbd_sel_o,
+ output logic s4_wbd_we_o,
+ output logic s4_wbd_cyc_o,
+ output logic s4_wbd_stb_o,
+
+ // Slave 5 Interface
+ // MBIST3
+ input logic [31:0] s5_wbd_dat_i,
+ input logic s5_wbd_ack_i,
+ // input logic s5_wbd_err_i,
+ output logic [31:0] s5_wbd_dat_o,
+ output logic [10:0] s5_wbd_adr_o,
+ output logic [3:0] s5_wbd_sel_o,
+ output logic s5_wbd_we_o,
+ output logic s5_wbd_cyc_o,
+ output logic s5_wbd_stb_o,
+
+ // Slave 6 Interface
+ // MBIST4
+ input logic [31:0] s6_wbd_dat_i,
+ input logic s6_wbd_ack_i,
+ // input logic s6_wbd_err_i,
+ output logic [31:0] s6_wbd_dat_o,
+ output logic [10:0] s6_wbd_adr_o,
+ output logic [3:0] s6_wbd_sel_o,
+ output logic s6_wbd_we_o,
+ output logic s6_wbd_cyc_o,
+ output logic s6_wbd_stb_o
);
////////////////////////////////////////////////////////////////////
@@ -185,6 +242,14 @@
// Type define
//
+parameter TARGET_SPI_MEM = 4'b0000;
+parameter TARGET_SPI_REG = 4'b0000;
+parameter TARGET_UART = 4'b0001;
+parameter TARGET_PINMUX = 4'b0010;
+parameter TARGET_MBIST1 = 4'b0011;
+parameter TARGET_MBIST2 = 4'b0100;
+parameter TARGET_MBIST3 = 4'b0101;
+parameter TARGET_MBIST4 = 4'b0110;
// WishBone Wr Interface
typedef struct packed {
@@ -220,12 +285,18 @@
type_wb_wr_intf s1_wb_wr;
type_wb_wr_intf s2_wb_wr;
type_wb_wr_intf s3_wb_wr;
+type_wb_wr_intf s4_wb_wr;
+type_wb_wr_intf s5_wb_wr;
+type_wb_wr_intf s6_wb_wr;
// Slave Read Interface
type_wb_rd_intf s0_wb_rd;
type_wb_rd_intf s1_wb_rd;
type_wb_rd_intf s2_wb_rd;
type_wb_rd_intf s3_wb_rd;
+type_wb_rd_intf s4_wb_rd;
+type_wb_rd_intf s5_wb_rd;
+type_wb_rd_intf s6_wb_rd;
type_wb_wr_intf m_bus_wr; // Multiplexed Master I/F
@@ -234,6 +305,10 @@
type_wb_wr_intf s_bus_wr; // Multiplexed Master I/F
type_wb_rd_intf s_bus_rd; // Multiplexed Slave I/F
+// channel repeater
+assign ch_clk_out = ch_clk_in;
+assign ch_data_out = ch_data_in;
+
// Wishbone interconnect clock skew control
clk_skew_adjust u_skew_wi
(
@@ -254,16 +329,22 @@
// 0x1001_0040 to 0x1001_007F - I2C
// 0x1001_0080 to 0x1001_00BF - USB
// 0x1001_00C0 to 0x1001_00FF - SSPIM
-// 0x1002_0000 to 0x1002_00FF - ADC
-// 0x1003_0000 to 0x1003_00FF - PINMUX
+// 0x1002_0000 to 0x1002_00FF - PINMUX
+// 0x1003_0000 to 0x1003_07FF - MBIST1
+// 0x1004_0000 to 0x1004_07FF - MBIST2
+// 0x1005_0000 to 0x1005_07FF - MBIST3
+// 0x1006_0000 to 0x1006_07FF - MBIST4
// 0x3080_0000 to 0x3080_00FF - WB HOST (This decoding happens at wb_host block)
// ---------------------------------------------------------------------------
//
-wire [3:0] m0_wbd_tid_i = (m0_wbd_adr_i[31:28] == 4'b0000 ) ? 4'b0000 : // SPI
- (m0_wbd_adr_i[31:16] == 16'h1000 ) ? 4'b0000 : // SPI REG
- (m0_wbd_adr_i[31:16] == 16'h1001 ) ? 4'b0001 : // UART/I2C/USB/SPI
- (m0_wbd_adr_i[31:16] == 16'h1002 ) ? 4'b0010 : // ADC
- (m0_wbd_adr_i[31:16] == 16'h1003 ) ? 4'b0011 : // PINMUX
+wire [3:0] m0_wbd_tid_i = (m0_wbd_adr_i[31:28] == 4'b0000 ) ? TARGET_SPI_MEM : // SPI
+ (m0_wbd_adr_i[31:16] == 16'h1000 ) ? TARGET_SPI_REG : // SPI REG
+ (m0_wbd_adr_i[31:16] == 16'h1001 ) ? TARGET_UART : // UART/I2C/USB/SPI
+ (m0_wbd_adr_i[31:16] == 16'h1002 ) ? TARGET_PINMUX : // PINMUX
+ (m0_wbd_adr_i[31:16] == 16'h1003 ) ? TARGET_MBIST1 : // MBIST1
+ (m0_wbd_adr_i[31:16] == 16'h1004 ) ? TARGET_MBIST2 : // MBIST2
+ (m0_wbd_adr_i[31:16] == 16'h1005 ) ? TARGET_MBIST3 : // MBIST3
+ (m0_wbd_adr_i[31:16] == 16'h1006 ) ? TARGET_MBIST4 : // MBIST4
4'b0000;
//------------------------------
@@ -274,21 +355,40 @@
// 0x1001_0040 to 0x1001_007F - I2
// 0x1001_0080 to 0x1001_00BF - USB
// 0x1001_00C0 to 0x1001_00FF - SSPIM
-// 0x1002_0000 to 0x1002_00FF - ADC
-// 0x1003_0000 to 0x1003_00FF - PINMUX
+// 0x1002_0000 to 0x1002_00FF - PINMUX
+// 0x1003_0000 to 0x1003_07FF - MBIST1
+// 0x1004_0000 to 0x1004_07FF - MBIST2
+// 0x1005_0000 to 0x1005_07FF - MBIST3
+// 0x1006_0000 to 0x1006_07FF - MBIST4
//-----------------------------
//
-wire [3:0] m1_wbd_tid_i = (m1_wbd_adr_i[31:28] == 4'b0000 ) ? 4'b0000 :
- (m1_wbd_adr_i[31:16] == 16'h1000 ) ? 4'b0000 :
- (m1_wbd_adr_i[31:16] == 16'h1001 ) ? 4'b0001 :
- (m1_wbd_adr_i[31:16] == 16'h1002 ) ? 4'b0010 :
- (m1_wbd_adr_i[31:16] == 16'h1003 ) ? 4'b0011 : 4'b0000;
+wire [3:0] m1_wbd_tid_i = (boot_remap[0] && m1_wbd_adr_i[31:11] == 21'h0) ? TARGET_MBIST1:
+ (boot_remap[1] && m1_wbd_adr_i[31:11] == 21'h1) ? TARGET_MBIST2:
+ (boot_remap[2] && m1_wbd_adr_i[31:11] == 21'h2) ? TARGET_MBIST3:
+ (boot_remap[3] && m1_wbd_adr_i[31:11] == 21'h3) ? TARGET_MBIST4:
+ (m1_wbd_adr_i[31:28] == 4'b0000 ) ? TARGET_SPI_MEM :
+ (m1_wbd_adr_i[31:16] == 16'h1000 ) ? TARGET_SPI_REG :
+ (m1_wbd_adr_i[31:16] == 16'h1001 ) ? TARGET_UART :
+ (m1_wbd_adr_i[31:16] == 16'h1002 ) ? TARGET_PINMUX :
+ (m1_wbd_adr_i[31:16] == 16'h1003 ) ? TARGET_MBIST1 :
+ (m1_wbd_adr_i[31:16] == 16'h1004 ) ? TARGET_MBIST2 :
+ (m1_wbd_adr_i[31:16] == 16'h1005 ) ? TARGET_MBIST3 :
+ (m1_wbd_adr_i[31:16] == 16'h1006 ) ? TARGET_MBIST4 :
+ 4'b0000;
-wire [3:0] m2_wbd_tid_i = (m2_wbd_adr_i[31:28] == 4'b0000 ) ? 4'b0000 :
- (m2_wbd_adr_i[31:16] == 16'h1000 ) ? 4'b0000 :
- (m2_wbd_adr_i[31:16] == 16'h1001 ) ? 4'b0001 :
- (m2_wbd_adr_i[31:16] == 16'h1002 ) ? 4'b0010 :
- (m2_wbd_adr_i[31:16] == 16'h1003 ) ? 4'b0011 : 4'b0000;
+wire [3:0] m2_wbd_tid_i = (boot_remap[0] && m2_wbd_adr_i[31:11] == 21'h0) ? TARGET_MBIST1:
+ (boot_remap[1] && m2_wbd_adr_i[31:11] == 21'h1) ? TARGET_MBIST2:
+ (boot_remap[2] && m2_wbd_adr_i[31:11] == 21'h2) ? TARGET_MBIST3:
+ (boot_remap[3] && m2_wbd_adr_i[31:11] == 21'h3) ? TARGET_MBIST4:
+ (m2_wbd_adr_i[31:28] == 4'b0000 ) ? TARGET_SPI_MEM :
+ (m2_wbd_adr_i[31:16] == 16'h1000 ) ? TARGET_SPI_REG :
+ (m2_wbd_adr_i[31:16] == 16'h1001 ) ? TARGET_UART :
+ (m2_wbd_adr_i[31:16] == 16'h1002 ) ? TARGET_PINMUX :
+ (m2_wbd_adr_i[31:16] == 16'h1003 ) ? TARGET_MBIST1 :
+ (m2_wbd_adr_i[31:16] == 16'h1004 ) ? TARGET_MBIST2 :
+ (m2_wbd_adr_i[31:16] == 16'h1005 ) ? TARGET_MBIST3 :
+ (m2_wbd_adr_i[31:16] == 16'h1006 ) ? TARGET_MBIST4 :
+ 4'b0000;
//----------------------------------------
// Master Mapping
// -------------------------------------
@@ -340,7 +440,7 @@
assign s0_wbd_stb_o = s0_wb_wr.wbd_stb ;
assign s1_wbd_dat_o = s1_wb_wr.wbd_dat ;
- assign s1_wbd_adr_o = {4'b0,s1_wb_wr.wbd_adr[27:0]} ;
+ assign s1_wbd_adr_o = s1_wb_wr.wbd_adr[7:0] ;
assign s1_wbd_sel_o = s1_wb_wr.wbd_sel ;
assign s1_wbd_we_o = s1_wb_wr.wbd_we ;
assign s1_wbd_cyc_o = s1_wb_wr.wbd_cyc ;
@@ -354,12 +454,33 @@
assign s2_wbd_stb_o = s2_wb_wr.wbd_stb ;
assign s3_wbd_dat_o = s3_wb_wr.wbd_dat[31:0] ;
- assign s3_wbd_adr_o = s3_wb_wr.wbd_adr[7:0] ; // Global Reg Need 8 bit
+ assign s3_wbd_adr_o = s3_wb_wr.wbd_adr[10:0] ; // MBIST Need 11 bit
assign s3_wbd_sel_o = s3_wb_wr.wbd_sel[3:0] ;
assign s3_wbd_we_o = s3_wb_wr.wbd_we ;
assign s3_wbd_cyc_o = s3_wb_wr.wbd_cyc ;
assign s3_wbd_stb_o = s3_wb_wr.wbd_stb ;
+ assign s4_wbd_dat_o = s4_wb_wr.wbd_dat[31:0] ;
+ assign s4_wbd_adr_o = s4_wb_wr.wbd_adr[10:0] ; // MBIST Need 11 bit
+ assign s4_wbd_sel_o = s4_wb_wr.wbd_sel[3:0] ;
+ assign s4_wbd_we_o = s4_wb_wr.wbd_we ;
+ assign s4_wbd_cyc_o = s4_wb_wr.wbd_cyc ;
+ assign s4_wbd_stb_o = s4_wb_wr.wbd_stb ;
+
+ assign s5_wbd_dat_o = s5_wb_wr.wbd_dat[31:0] ;
+ assign s5_wbd_adr_o = s5_wb_wr.wbd_adr[10:0] ; // MBIST Need 11 bit
+ assign s5_wbd_sel_o = s5_wb_wr.wbd_sel[3:0] ;
+ assign s5_wbd_we_o = s5_wb_wr.wbd_we ;
+ assign s5_wbd_cyc_o = s5_wb_wr.wbd_cyc ;
+ assign s5_wbd_stb_o = s5_wb_wr.wbd_stb ;
+
+ assign s6_wbd_dat_o = s6_wb_wr.wbd_dat[31:0] ;
+ assign s6_wbd_adr_o = s6_wb_wr.wbd_adr[10:0] ; // MBIST Need 11 bit
+ assign s6_wbd_sel_o = s6_wb_wr.wbd_sel[3:0] ;
+ assign s6_wbd_we_o = s6_wb_wr.wbd_we ;
+ assign s6_wbd_cyc_o = s6_wb_wr.wbd_cyc ;
+ assign s6_wbd_stb_o = s6_wb_wr.wbd_stb ;
+
assign s0_wb_rd.wbd_dat = s0_wbd_dat_i ;
assign s0_wb_rd.wbd_ack = s0_wbd_ack_i ;
assign s0_wb_rd.wbd_err = 1'b0; // s0_wbd_err_i ; - unused
@@ -376,6 +497,17 @@
assign s3_wb_rd.wbd_ack = s3_wbd_ack_i ;
assign s3_wb_rd.wbd_err = 1'b0; // s3_wbd_err_i ; - unused
+ assign s4_wb_rd.wbd_dat = s4_wbd_dat_i ;
+ assign s4_wb_rd.wbd_ack = s4_wbd_ack_i ;
+ assign s4_wb_rd.wbd_err = 1'b0; // s4_wbd_err_i ; - unused
+
+ assign s5_wb_rd.wbd_dat = s5_wbd_dat_i ;
+ assign s5_wb_rd.wbd_ack = s5_wbd_ack_i ;
+ assign s5_wb_rd.wbd_err = 1'b0; // s5_wbd_err_i ; - unused
+
+ assign s6_wb_rd.wbd_dat = s6_wbd_dat_i ;
+ assign s6_wb_rd.wbd_ack = s6_wbd_ack_i ;
+ assign s6_wb_rd.wbd_err = 1'b0; // s6_wbd_err_i ; - unused
//
// arbitor
//
@@ -406,20 +538,26 @@
wire [3:0] s_wbd_tid = s_bus_wr.wbd_tid; // to fix iverilog warning
always_comb begin
case(s_wbd_tid)
- 3'h0: s_bus_rd = s0_wb_rd;
- 3'h1: s_bus_rd = s1_wb_rd;
- 3'h2: s_bus_rd = s2_wb_rd;
- 3'h3: s_bus_rd = s3_wb_rd;
+ 4'h0: s_bus_rd = s0_wb_rd;
+ 4'h1: s_bus_rd = s1_wb_rd;
+ 4'h2: s_bus_rd = s2_wb_rd;
+ 4'h3: s_bus_rd = s3_wb_rd;
+ 4'h4: s_bus_rd = s4_wb_rd;
+ 4'h5: s_bus_rd = s5_wb_rd;
+ 4'h6: s_bus_rd = s6_wb_rd;
default: s_bus_rd = s0_wb_rd;
endcase
end
// Connect Master => Slave
-assign s0_wb_wr = (s_wbd_tid == 2'b00) ? s_bus_wr : 'h0;
-assign s1_wb_wr = (s_wbd_tid == 2'b01) ? s_bus_wr : 'h0;
-assign s2_wb_wr = (s_wbd_tid == 2'b10) ? s_bus_wr : 'h0;
-assign s3_wb_wr = (s_wbd_tid == 2'b11) ? s_bus_wr : 'h0;
+assign s0_wb_wr = (s_wbd_tid == 3'b000) ? s_bus_wr : 'h0;
+assign s1_wb_wr = (s_wbd_tid == 3'b001) ? s_bus_wr : 'h0;
+assign s2_wb_wr = (s_wbd_tid == 3'b010) ? s_bus_wr : 'h0;
+assign s3_wb_wr = (s_wbd_tid == 3'b011) ? s_bus_wr : 'h0;
+assign s4_wb_wr = (s_wbd_tid == 3'b100) ? s_bus_wr : 'h0;
+assign s5_wb_wr = (s_wbd_tid == 3'b101) ? s_bus_wr : 'h0;
+assign s6_wb_wr = (s_wbd_tid == 3'b110) ? s_bus_wr : 'h0;
// Connect Slave to Master
assign m0_wb_rd = (gnt == 2'b00) ? m_bus_rd : 'h0;
@@ -429,24 +567,24 @@
// Stagging FF to break write and read timing path
wb_stagging u_m_wb_stage(
- .clk_i (clk_i ),
- .rst_n (rst_n ),
+ .clk_i (clk_i ),
+ .rst_n (rst_n ),
// WishBone Input master I/P
- .m_wbd_dat_i (m_bus_wr.wbd_dat ),
- .m_wbd_adr_i (m_bus_wr.wbd_adr ),
- .m_wbd_sel_i (m_bus_wr.wbd_sel ),
- .m_wbd_we_i (m_bus_wr.wbd_we ),
- .m_wbd_cyc_i (m_bus_wr.wbd_cyc ),
- .m_wbd_stb_i (m_bus_wr.wbd_stb ),
- .m_wbd_tid_i (m_bus_wr.wbd_tid ),
- .m_wbd_dat_o (m_bus_rd.wbd_dat ),
- .m_wbd_ack_o (m_bus_rd.wbd_ack ),
- .m_wbd_err_o (m_bus_rd.wbd_err ),
+ .m_wbd_dat_i (m_bus_wr.wbd_dat ),
+ .m_wbd_adr_i (m_bus_wr.wbd_adr ),
+ .m_wbd_sel_i (m_bus_wr.wbd_sel ),
+ .m_wbd_we_i (m_bus_wr.wbd_we ),
+ .m_wbd_cyc_i (m_bus_wr.wbd_cyc ),
+ .m_wbd_stb_i (m_bus_wr.wbd_stb ),
+ .m_wbd_tid_i (m_bus_wr.wbd_tid ),
+ .m_wbd_dat_o (m_bus_rd.wbd_dat ),
+ .m_wbd_ack_o (m_bus_rd.wbd_ack ),
+ .m_wbd_err_o (m_bus_rd.wbd_err ),
// Slave Interface
- .s_wbd_dat_i (s_bus_rd.wbd_dat ),
- .s_wbd_ack_i (s_bus_rd.wbd_ack ),
- .s_wbd_err_i (s_bus_rd.wbd_err ),
+ .s_wbd_dat_i (s_bus_rd.wbd_dat ),
+ .s_wbd_ack_i (s_bus_rd.wbd_ack ),
+ .s_wbd_err_i (s_bus_rd.wbd_err ),
.s_wbd_dat_o (s_bus_wr.wbd_dat ),
.s_wbd_adr_o (s_bus_wr.wbd_adr ),
.s_wbd_sel_o (s_bus_wr.wbd_sel ),
