database update
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 03c3409..0a4f516 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -30,7 +30,7 @@
## Source Verilog Files
set ::env(VERILOG_FILES) "\
$script_dir/../../caravel/verilog/rtl/defines.v \
- $script_dir/../../verilog/gl/digital_core.v \
+ $script_dir/../../verilog/rtl/digital_core/src/digital_core.sv \
$script_dir/../../verilog/rtl/user_project_wrapper.v"
## Clock configurations
@@ -42,12 +42,11 @@
## Internal Macros
### Macro Placement
set ::env(FP_SIZING) "absolute"
-set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
+set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
set ::env(SDC_FILE) "$script_dir/base.sdc"
set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
-set ::env(SYNTH_READ_BLACKBOX_LIB) "1"
### Black-box verilog and views
set ::env(VERILOG_FILES_BLACKBOX) "\
@@ -81,15 +80,6 @@
set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore/scr1/src/includes $script_dir/../../verilog/rtl/sdram_ctrl/src/defs ]
-set ::env(GLB_RT_MAXLAYER) 5
-
-set ::env(FP_PDN_CHECK_NODES) 0
-
-set ::env(GLB_RT_OBS) "met1 0 0 $::env(DIE_AREA),\
- met2 0 0 $::env(DIE_AREA),\
- met3 0 0 $::env(DIE_AREA),\
- met4 0 0 $::env(DIE_AREA),\
- met5 0 0 $::env(DIE_AREA)"
# The following is because there are no std cells in the example wrapper project.
@@ -100,5 +90,52 @@
set ::env(PL_DIAMOND_SEARCH_HEIGHT) "400"
set ::env(ROUTING_OPT_ITERS) "20"
+set ::env(GLB_RT_ALLOW_CONGESTION) 1
+set ::env(GLB_RT_MAXLAYER) 5
+set ::env(GLB_RT_MINLAYER) 2
+set ::env(GLB_RT_ADJUSTMENT) 0.45
+set ::env(GENERATE_FINAL_SUMMARY_REPORT) 1
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(FP_PDN_CHECK_NODES) 0
+# This makes sure that the core rings are outside the boundaries
+# of your block.
+set ::env(MAGIC_ZEROIZE_ORIGIN) 0
+# Area Configurations. DON'T TOUCH.
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 2920 3520"
+set ::env(RUN_CVC) 0
+
+# Pin Configurations. DON'T TOUCH
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+
+set ::unit 2.4
+set ::env(FP_IO_VEXTEND) [expr 2*$::unit]
+set ::env(FP_IO_HEXTEND) [expr 2*$::unit]
+set ::env(FP_IO_VLENGTH) $::unit
+set ::env(FP_IO_HLENGTH) $::unit
+
+set ::env(FP_IO_VTHICKNESS_MULT) 4
+set ::env(FP_IO_HTHICKNESS_MULT) 4
+
+# Power & Pin Configurations. DON'T TOUCH.
+set ::env(FP_PDN_CORE_RING) 1
+set ::env(FP_PDN_CORE_RING_VWIDTH) 3
+set ::env(FP_PDN_CORE_RING_HWIDTH) $::env(FP_PDN_CORE_RING_VWIDTH)
+set ::env(FP_PDN_CORE_RING_VOFFSET) 14
+set ::env(FP_PDN_CORE_RING_HOFFSET) $::env(FP_PDN_CORE_RING_VOFFSET)
+set ::env(FP_PDN_CORE_RING_VSPACING) 1.7
+set ::env(FP_PDN_CORE_RING_HSPACING) $::env(FP_PDN_CORE_RING_VSPACING)
+
+set ::env(FP_PDN_VWIDTH) 3
+set ::env(FP_PDN_HWIDTH) 3
+set ::env(FP_PDN_VOFFSET) 5
+set ::env(FP_PDN_HOFFSET) $::env(FP_PDN_VOFFSET)
+set ::env(FP_PDN_VPITCH) 180
+set ::env(FP_PDN_HPITCH) $::env(FP_PDN_VPITCH)
+set ::env(FP_PDN_VSPACING) [expr 5*$::env(FP_PDN_CORE_RING_VWIDTH)]
+set ::env(FP_PDN_HSPACING) [expr 5*$::env(FP_PDN_CORE_RING_HWIDTH)]
+set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
+set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
+set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl
new file mode 100644
index 0000000..6249330
--- /dev/null
+++ b/openlane/user_project_wrapper/interactive.tcl
@@ -0,0 +1,34 @@
+package require openlane
+set script_dir [file dirname [file normalize [info script]]]
+
+prep -design $script_dir -tag 24June2021 -overwrite
+set save_path $script_dir/../..
+
+run_synthesis
+run_floorplan
+run_placement
+run_cts
+run_routing
+
+write_powered_verilog
+set_netlist $::env(lvs_result_file_tag).powered.v
+run_magic
+run_magic_drc
+puts $::env(CURRENT_NETLIST)
+run_magic_spice_export
+
+save_views -lef_path $::env(magic_result_file_tag).lef \
+ -def_path $::env(tritonRoute_result_file_tag).def \
+ -gds_path $::env(magic_result_file_tag).gds \
+ -mag_path $::env(magic_result_file_tag).mag \
+ -maglef_path $::env(magic_result_file_tag).lef.mag \
+ -spice_path $::env(magic_result_file_tag).spice \
+ -verilog_path $::env(CURRENT_NETLIST)\
+ -save_path $save_path \
+ -tag $::env(RUN_TAG)
+
+run_lvs
+run_antenna_check
+calc_total_runtime
+generate_final_summary_report
+puts_success "Flow Completed Without Fatal Errors."
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index a7365ab..901e853 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1,7 @@
-mprj 1175 1690 N
+u_core.u_riscv_top 300 300 N
+u_core.u_glbl_cfg 2000 2200 N
+u_core.u_uart_core 2000 1100 N
+u_core.u_intercon 300 1800 N
+u_core.u_spi_master 300 2200 N
+u_core.u_sdram_ctrl 1000 2200 N
+u_core.u_glbl_cfg 2000 2200 N
diff --git a/openlane/user_project_wrapper/macro_placement.cfg b/openlane/user_project_wrapper/macro_placement.cfg
deleted file mode 100644
index cc8a2a9..0000000
--- a/openlane/user_project_wrapper/macro_placement.cfg
+++ /dev/null
@@ -1,6 +0,0 @@
-u_core.u_riscv_top 300 300 N
-u_core.u_intercon 300 1800 N
-u_core.u_spi_master 300 2200 N
-u_core.u_sdram_ctrl 1000 2200 N
-u_core.u_glbl_cfg 2000 2200 N
-u_core.u_uart_core 2000 1100 N
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index 36a0857..b7f7a50 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl
@@ -38,7 +38,7 @@
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 2300 200"
+set ::env(DIE_AREA) "0 0 2000 200"
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg
index c32dce4..ae72f2a 100644
--- a/openlane/wb_interconnect/pin_order.cfg
+++ b/openlane/wb_interconnect/pin_order.cfg
@@ -220,114 +220,7 @@
m1_wbd_err_o
m1_wbd_cyc_i
-m2_wbd_stb_i 1500 0 2
-m2_wbd_we_i
-m2_wbd_adr_i\[31\]
-m2_wbd_adr_i\[30\]
-m2_wbd_adr_i\[29\]
-m2_wbd_adr_i\[28\]
-m2_wbd_adr_i\[27\]
-m2_wbd_adr_i\[26\]
-m2_wbd_adr_i\[25\]
-m2_wbd_adr_i\[24\]
-m2_wbd_adr_i\[23\]
-m2_wbd_adr_i\[22\]
-m2_wbd_adr_i\[21\]
-m2_wbd_adr_i\[20\]
-m2_wbd_adr_i\[19\]
-m2_wbd_adr_i\[18\]
-m2_wbd_adr_i\[17\]
-m2_wbd_adr_i\[16\]
-m2_wbd_adr_i\[15\]
-m2_wbd_adr_i\[14\]
-m2_wbd_adr_i\[13\]
-m2_wbd_adr_i\[12\]
-m2_wbd_adr_i\[11\]
-m2_wbd_adr_i\[10\]
-m2_wbd_adr_i\[9\]
-m2_wbd_adr_i\[8\]
-m2_wbd_adr_i\[7\]
-m2_wbd_adr_i\[6\]
-m2_wbd_adr_i\[5\]
-m2_wbd_adr_i\[4\]
-m2_wbd_adr_i\[3\]
-m2_wbd_adr_i\[2\]
-m2_wbd_adr_i\[1\]
-m2_wbd_adr_i\[0\]
-m2_wbd_sel_i\[3\]
-m2_wbd_sel_i\[2\]
-m2_wbd_sel_i\[1\]
-m2_wbd_sel_i\[0\]
-m2_wbd_dat_i\[31\]
-m2_wbd_dat_i\[30\]
-m2_wbd_dat_i\[29\]
-m2_wbd_dat_i\[28\]
-m2_wbd_dat_i\[27\]
-m2_wbd_dat_i\[26\]
-m2_wbd_dat_i\[25\]
-m2_wbd_dat_i\[24\]
-m2_wbd_dat_i\[23\]
-m2_wbd_dat_i\[22\]
-m2_wbd_dat_i\[21\]
-m2_wbd_dat_i\[20\]
-m2_wbd_dat_i\[19\]
-m2_wbd_dat_i\[18\]
-m2_wbd_dat_i\[17\]
-m2_wbd_dat_i\[16\]
-m2_wbd_dat_i\[15\]
-m2_wbd_dat_i\[14\]
-m2_wbd_dat_i\[13\]
-m2_wbd_dat_i\[12\]
-m2_wbd_dat_i\[11\]
-m2_wbd_dat_i\[10\]
-m2_wbd_dat_i\[9\]
-m2_wbd_dat_i\[8\]
-m2_wbd_dat_i\[7\]
-m2_wbd_dat_i\[6\]
-m2_wbd_dat_i\[5\]
-m2_wbd_dat_i\[4\]
-m2_wbd_dat_i\[3\]
-m2_wbd_dat_i\[2\]
-m2_wbd_dat_i\[1\]
-m2_wbd_dat_i\[0\]
-m2_wbd_dat_o\[31\]
-m2_wbd_dat_o\[30\]
-m2_wbd_dat_o\[29\]
-m2_wbd_dat_o\[28\]
-m2_wbd_dat_o\[27\]
-m2_wbd_dat_o\[26\]
-m2_wbd_dat_o\[25\]
-m2_wbd_dat_o\[24\]
-m2_wbd_dat_o\[23\]
-m2_wbd_dat_o\[22\]
-m2_wbd_dat_o\[21\]
-m2_wbd_dat_o\[20\]
-m2_wbd_dat_o\[19\]
-m2_wbd_dat_o\[18\]
-m2_wbd_dat_o\[17\]
-m2_wbd_dat_o\[16\]
-m2_wbd_dat_o\[15\]
-m2_wbd_dat_o\[14\]
-m2_wbd_dat_o\[13\]
-m2_wbd_dat_o\[12\]
-m2_wbd_dat_o\[11\]
-m2_wbd_dat_o\[10\]
-m2_wbd_dat_o\[9\]
-m2_wbd_dat_o\[8\]
-m2_wbd_dat_o\[7\]
-m2_wbd_dat_o\[6\]
-m2_wbd_dat_o\[5\]
-m2_wbd_dat_o\[4\]
-m2_wbd_dat_o\[3\]
-m2_wbd_dat_o\[2\]
-m2_wbd_dat_o\[1\]
-m2_wbd_dat_o\[0\]
-m2_wbd_ack_o
-m2_wbd_err_o
-m2_wbd_cyc_i
-
-
-s3_wbd_stb_o 2000 0 2
+s3_wbd_stb_o 1700 0 2
s3_wbd_we_o
s3_wbd_adr_o\[7\]
s3_wbd_adr_o\[6\]
@@ -653,3 +546,109 @@
s2_wbd_err_i
s2_wbd_cyc_o
+#W
+m2_wbd_stb_i 0 0 2
+m2_wbd_we_i
+m2_wbd_adr_i\[31\]
+m2_wbd_adr_i\[30\]
+m2_wbd_adr_i\[29\]
+m2_wbd_adr_i\[28\]
+m2_wbd_adr_i\[27\]
+m2_wbd_adr_i\[26\]
+m2_wbd_adr_i\[25\]
+m2_wbd_adr_i\[24\]
+m2_wbd_adr_i\[23\]
+m2_wbd_adr_i\[22\]
+m2_wbd_adr_i\[21\]
+m2_wbd_adr_i\[20\]
+m2_wbd_adr_i\[19\]
+m2_wbd_adr_i\[18\]
+m2_wbd_adr_i\[17\]
+m2_wbd_adr_i\[16\]
+m2_wbd_adr_i\[15\]
+m2_wbd_adr_i\[14\]
+m2_wbd_adr_i\[13\]
+m2_wbd_adr_i\[12\]
+m2_wbd_adr_i\[11\]
+m2_wbd_adr_i\[10\]
+m2_wbd_adr_i\[9\]
+m2_wbd_adr_i\[8\]
+m2_wbd_adr_i\[7\]
+m2_wbd_adr_i\[6\]
+m2_wbd_adr_i\[5\]
+m2_wbd_adr_i\[4\]
+m2_wbd_adr_i\[3\]
+m2_wbd_adr_i\[2\]
+m2_wbd_adr_i\[1\]
+m2_wbd_adr_i\[0\]
+m2_wbd_sel_i\[3\]
+m2_wbd_sel_i\[2\]
+m2_wbd_sel_i\[1\]
+m2_wbd_sel_i\[0\]
+m2_wbd_dat_i\[31\]
+m2_wbd_dat_i\[30\]
+m2_wbd_dat_i\[29\]
+m2_wbd_dat_i\[28\]
+m2_wbd_dat_i\[27\]
+m2_wbd_dat_i\[26\]
+m2_wbd_dat_i\[25\]
+m2_wbd_dat_i\[24\]
+m2_wbd_dat_i\[23\]
+m2_wbd_dat_i\[22\]
+m2_wbd_dat_i\[21\]
+m2_wbd_dat_i\[20\]
+m2_wbd_dat_i\[19\]
+m2_wbd_dat_i\[18\]
+m2_wbd_dat_i\[17\]
+m2_wbd_dat_i\[16\]
+m2_wbd_dat_i\[15\]
+m2_wbd_dat_i\[14\]
+m2_wbd_dat_i\[13\]
+m2_wbd_dat_i\[12\]
+m2_wbd_dat_i\[11\]
+m2_wbd_dat_i\[10\]
+m2_wbd_dat_i\[9\]
+m2_wbd_dat_i\[8\]
+m2_wbd_dat_i\[7\]
+m2_wbd_dat_i\[6\]
+m2_wbd_dat_i\[5\]
+m2_wbd_dat_i\[4\]
+m2_wbd_dat_i\[3\]
+m2_wbd_dat_i\[2\]
+m2_wbd_dat_i\[1\]
+m2_wbd_dat_i\[0\]
+m2_wbd_dat_o\[31\]
+m2_wbd_dat_o\[30\]
+m2_wbd_dat_o\[29\]
+m2_wbd_dat_o\[28\]
+m2_wbd_dat_o\[27\]
+m2_wbd_dat_o\[26\]
+m2_wbd_dat_o\[25\]
+m2_wbd_dat_o\[24\]
+m2_wbd_dat_o\[23\]
+m2_wbd_dat_o\[22\]
+m2_wbd_dat_o\[21\]
+m2_wbd_dat_o\[20\]
+m2_wbd_dat_o\[19\]
+m2_wbd_dat_o\[18\]
+m2_wbd_dat_o\[17\]
+m2_wbd_dat_o\[16\]
+m2_wbd_dat_o\[15\]
+m2_wbd_dat_o\[14\]
+m2_wbd_dat_o\[13\]
+m2_wbd_dat_o\[12\]
+m2_wbd_dat_o\[11\]
+m2_wbd_dat_o\[10\]
+m2_wbd_dat_o\[9\]
+m2_wbd_dat_o\[8\]
+m2_wbd_dat_o\[7\]
+m2_wbd_dat_o\[6\]
+m2_wbd_dat_o\[5\]
+m2_wbd_dat_o\[4\]
+m2_wbd_dat_o\[3\]
+m2_wbd_dat_o\[2\]
+m2_wbd_dat_o\[1\]
+m2_wbd_dat_o\[0\]
+m2_wbd_ack_o
+m2_wbd_err_o
+m2_wbd_cyc_i
diff --git a/signoff/wb_interconnect/final_summary_report.csv b/signoff/wb_interconnect/final_summary_report.csv
index 7b4b696..3eb297f 100644
--- a/signoff/wb_interconnect/final_summary_report.csv
+++ b/signoff/wb_interconnect/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,Flow_completed,0h6m41s,0h2m46s,5652.173913043478,0.46,2826.086956521739,5,561.93,1300,0,0,0,0,0,0,0,8,0,0,0,561231,17243,0.0,0.0,0.0,0.0,-0.22,0.0,0.0,0.0,0.0,-0.4,511843016,0.0,47.22,10.06,35.71,0.16,-1,1054,1627,210,783,0,0,0,1300,247,0,75,14,115,0,0,181,436,422,10,130,5454,0,5584,97.84735812133071,10.22,10,AREA 0,4,50,1,50,153.18,0.32,0,sky130_fd_sc_hd,4,4
+0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,Flow_completed,0h6m17s,0h2m46s,6500.0,0.4,3250.0,6,540.84,1300,0,0,0,0,0,0,0,9,0,0,0,465926,16959,0.0,0.0,0.0,0.0,-0.04,0.0,0.0,0.0,0.0,-0.04,407751231,0.0,46.13,11.88,29.14,0.34,-1,1054,1627,210,783,0,0,0,1300,247,0,75,14,115,0,0,181,436,422,10,130,4719,0,4849,99.60159362549801,10.04,10,AREA 0,4,50,1,50,153.18,0.32,0,sky130_fd_sc_hd,4,4
diff --git a/verilog/rtl/digital_core/src/digital_core.sv b/verilog/rtl/digital_core/src/digital_core.sv
index 5d37e27..d80af75 100644
--- a/verilog/rtl/digital_core/src/digital_core.sv
+++ b/verilog/rtl/digital_core/src/digital_core.sv
@@ -84,14 +84,8 @@
parameter WB_WIDTH = 32 // WB ADDRESS/DARA WIDTH
) (
`ifdef USE_POWER_PINS
- inout vdda1, // User area 1 3.3V supply
- inout vdda2, // User area 2 3.3V supply
- inout vssa1, // User area 1 analog ground
- inout vssa2, // User area 2 analog ground
inout vccd1, // User area 1 1.8V supply
- inout vccd2, // User area 2 1.8v supply
inout vssd1, // User area 1 digital ground
- inout vssd2, // User area 2 digital ground
`endif
input logic wb_clk_i , // System clock
input logic user_clock2 , // user Clock
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 8e7547b..303a53d 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -85,14 +85,8 @@
digital_core u_core (
`ifdef USE_POWER_PINS
- .vdda1(vdda1), // User area 1 3.3V power
- .vdda2(vdda2), // User area 2 3.3V power
- .vssa1(vssa1), // User area 1 analog ground
- .vssa2(vssa2), // User area 2 analog ground
.vccd1(vccd1), // User area 1 1.8V power
- .vccd2(vccd2), // User area 2 1.8V power
.vssd1(vssd1), // User area 1 digital ground
- .vssd2(vssd2), // User area 2 digital ground
`endif
.wb_clk_i(wb_clk_i),
