def,lef,gds,mag,spi,magled added
diff --git a/checks/.full_log.log.swp b/checks/.full_log.log.swp
new file mode 100644
index 0000000..7b64fd1
--- /dev/null
+++ b/checks/.full_log.log.swp
Binary files differ
diff --git a/checks/full_log.log b/checks/full_log.log
new file mode 100644
index 0000000..26e484c
--- /dev/null
+++ b/checks/full_log.log
@@ -0,0 +1,22 @@
+FULL RUN LOG:
+ Executing Step 0 of 8: Extracting GDS Files
+Step 0 done without fatal errors.
+ Executing Step 1 of 8: Project License Check
+{{LICENSE COMPLIANCE PASSED}} Apache-2.0 LICENSE file was found in project root
+ No third party libraries found.
+Step 1 done without fatal errors.
+{{SPDX COMPLIANCE WARNING}} Found 527 non-compliant files with the SPDX Standard. Check full log for more information
+SPDX COMPLIANCE: NON-COMPLIANT FILES PREVIEW: ['/home/dinesha/workarea/opencore/git/yifive_r0/read.me', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/openlane/user_analog_project_wrapper_empty/or_ioplace.tcl', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/tbuart.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/spiflash.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/qspi/qspi_tb.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/caravan/caravan_tb.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl/simpleuart.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl/picorv32.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl/mgmt_soc.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl/spimemio.v', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/default.cvcrc', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/config.1.tcl', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/config.tcl']
+ Executing Step 2 of 8: YAML File Check
+ YAML file valid!
+Step 2 done without fatal errors.
+ Detected Project Type is "digital"
+ Executing Step 3 of 8: Project Compliance Checks
+b'Going into /home/dinesha/workarea/efabless/caravel'
+b'Removing manifest'
+b'Fetching manifest'
+b'Running sha1sum checks'
+ Manifest Checks Failed. Please rebase your Repository to the latest Caravel master.
+verilog/rtl/mgmt_core.v: FAILED
+verilog/rtl/mgmt_soc.v: FAILED
+verilog/rtl/wb_intercon.v: FAILED
diff --git a/checks/manifest_check.log b/checks/manifest_check.log
new file mode 100644
index 0000000..94c2d81
--- /dev/null
+++ b/checks/manifest_check.log
@@ -0,0 +1,47 @@
+verilog/rtl/DFFRAM.v: OK
+verilog/rtl/DFFRAMBB.v: OK
+verilog/rtl/__uprj_analog_netlists.v: OK
+verilog/rtl/__uprj_netlists.v: OK
+verilog/rtl/__user_analog_project_wrapper.v: OK
+verilog/rtl/__user_project_wrapper.v: OK
+verilog/rtl/caravan.v: OK
+verilog/rtl/caravan_netlists.v: OK
+verilog/rtl/caravel.v: OK
+verilog/rtl/caravel_clocking.v: OK
+verilog/rtl/chip_io.v: OK
+verilog/rtl/chip_io_alt.v: OK
+verilog/rtl/clock_div.v: OK
+verilog/rtl/convert_gpio_sigs.v: OK
+verilog/rtl/counter_timer_high.v: OK
+verilog/rtl/counter_timer_low.v: OK
+verilog/rtl/digital_pll.v: OK
+verilog/rtl/digital_pll_controller.v: OK
+verilog/rtl/gpio_control_block.v: OK
+verilog/rtl/gpio_wb.v: OK
+verilog/rtl/housekeeping_spi.v: OK
+verilog/rtl/la_wb.v: OK
+verilog/rtl/mem_wb.v: OK
+verilog/rtl/mgmt_core.v: FAILED
+verilog/rtl/mgmt_protect.v: OK
+verilog/rtl/mgmt_protect_hv.v: OK
+verilog/rtl/mgmt_soc.v: FAILED
+verilog/rtl/mprj2_logic_high.v: OK
+verilog/rtl/mprj_ctrl.v: OK
+verilog/rtl/mprj_io.v: OK
+verilog/rtl/mprj_logic_high.v: OK
+verilog/rtl/pads.v: OK
+verilog/rtl/picorv32.v: OK
+verilog/rtl/ring_osc2x13.v: OK
+verilog/rtl/simple_por.v: OK
+verilog/rtl/simple_spi_master.v: OK
+verilog/rtl/simpleuart.v: OK
+verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v: OK
+verilog/rtl/spimemio.v: OK
+verilog/rtl/sram_1rw1r_32_256_8_sky130.v: OK
+verilog/rtl/storage.v: OK
+verilog/rtl/storage_bridge_wb.v: OK
+verilog/rtl/sysctrl.v: OK
+verilog/rtl/wb_intercon.v: FAILED
+scripts/set_user_id.py: OK
+scripts/generate_fill.py: OK
+scripts/compositor.py: OK
diff --git a/checks/spdx_compliance_report.log b/checks/spdx_compliance_report.log
new file mode 100644
index 0000000..0f040f1
--- /dev/null
+++ b/checks/spdx_compliance_report.log
@@ -0,0 +1,529 @@
+FULL RUN LOG:
+SPDX NON-COMPLIANT FILES
+/home/dinesha/workarea/opencore/git/yifive_r0/read.me
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/openlane/user_analog_project_wrapper_empty/or_ioplace.tcl
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/tbuart.v
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/spiflash.v
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/qspi/qspi_tb.v
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/caravan/caravan_tb.v
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl/simpleuart.v
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl/picorv32.v
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl/mgmt_soc.v
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl/spimemio.v
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/default.cvcrc
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/config.1.tcl
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/config.tcl
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/config.tcl
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic_spice.tcl
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/opt.lib
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/trimmed.lib
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+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/sky130_fd_sc_hd__tt_025C_1v80.no_pg.lib
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+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/20-tritonRoute.guide
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+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__conb_1.ext
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