icache and dcache bypass added
diff --git a/openlane/pinmux/config.tcl b/openlane/pinmux/config.tcl index 7650732..21b155d 100755 --- a/openlane/pinmux/config.tcl +++ b/openlane/pinmux/config.tcl
@@ -85,6 +85,9 @@ set ::env(PL_TARGET_DENSITY) "0.30" set ::env(CELL_PAD) "4" +set ::env(FP_IO_VEXTEND) {6} +set ::env(FP_IO_HEXTEND) {6} + # helps in anteena fix set ::env(USE_ARC_ANTENNA_CHECK) "0"
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index 19757e8..774a95c 100644 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl
@@ -142,6 +142,14 @@ met1 150 750 833.1 1166.54,\ met2 150 750 833.1 1166.54,\ met3 150 750 833.1 1166.54,\ + + met1 2250 2150 2800 2600,\ + met2 2250 2150 2800 2600,\ + met3 2250 2150 2800 2600,\ + met1 950 650 1760 1290,\ + met2 950 650 1760 1290,\ + met3 950 650 1760 1290,\ + met5 0 0 2920 3520" set ::env(FP_PDN_POWER_STRAPS) "vccd1 vssd1 1, vccd2 vssd2 0, vdda1 vssa1 0, vdda2 vssa2 0"
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl index 0d8ff81..6bc107d 100755 --- a/openlane/wb_host/config.tcl +++ b/openlane/wb_host/config.tcl
@@ -24,6 +24,8 @@ set ::env(DESIGN_IS_CORE) "0" +set ::env(OPENLANE_VERBOSE) {10} + # Timing configuration set ::env(CLOCK_PERIOD) "10" set ::env(CLOCK_PORT) "wbm_clk_i wbs_clk_i u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X"
diff --git a/openlane/ycr_intf/config.tcl b/openlane/ycr_intf/config.tcl index 831ef54..a0d9839 100644 --- a/openlane/ycr_intf/config.tcl +++ b/openlane/ycr_intf/config.tcl
@@ -70,6 +70,8 @@ set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg set ::env(PL_TARGET_DENSITY) 0.37 +set ::env(FP_IO_VEXTEND) {6} +set ::env(FP_IO_HEXTEND) {6} set ::env(RT_MAX_LAYER) {met4} #set ::env(GLB_RT_MAXLAYER) "5"
diff --git a/openlane/ycr_intf/pin_order.cfg b/openlane/ycr_intf/pin_order.cfg index fb87e40..016df72 100644 --- a/openlane/ycr_intf/pin_order.cfg +++ b/openlane/ycr_intf/pin_order.cfg
@@ -344,7 +344,7 @@ icache_mem_din0\[30\] icache_mem_din0\[31\] -icache_mem_clk1 100 0 2 +icache_mem_clk1 100 0 4 icache_mem_csb1 icache_mem_addr1\[8\] icache_mem_addr1\[7\]
diff --git a/verilog/dv/riscv_regress/Makefile b/verilog/dv/riscv_regress/Makefile index 21064f9..15194cc 100644 --- a/verilog/dv/riscv_regress/Makefile +++ b/verilog/dv/riscv_regress/Makefile
@@ -1,10 +1,32 @@ -#------------------------------------------------------------------------------ -# Makefile for SCR1 -#------------------------------------------------------------------------------ -SIM ?= RTL -DUMP ?= OFF -TOOLS?=/opt/riscv64i/ +# ---- Include Partitioned Makefiles ---- + +CONFIG = caravel_user_project + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### + +export root_dir := $(shell pwd) +export bld_dir := $(root_dir)/build/$(current_goal)_$(BUS)_$(CFG)_$(ARCH)_IPIC_$(IPIC)_TCM_$(TCM)_VIRQ_$(VECT_IRQ)_TRACE_$(TRACE) +DESIGNS?=${root_dir}/../../.. + +UPRJ_TESTS_PATH = $(root_dir) + +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog +## YIFIVE FIRMWARE +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware +GCC64_PREFIX?=riscv64-unknown-elf + + +## Simulation mode: RTL/GL +SIM?=RTL +DUMP?=OFF +RISC_CORE?=0 + +### To Enable IVERILOG FST DUMP +export IVERILOG_DUMPER = fst + # PARAMETERS @@ -48,7 +70,7 @@ VECT_IRQ ?= 0 IPIC ?= 0 TCM ?= 0 - SIM_CFG_DEF = YCR1_CFG_$(CFG) + SIM_CFG_DEF = YCR_CFG_$(CFG) endif endif endif @@ -118,38 +140,16 @@ endif -export root_dir := $(shell pwd) -export bld_dir := $(root_dir)/build/$(current_goal)_$(BUS)_$(CFG)_$(ARCH)_IPIC_$(IPIC)_TCM_$(TCM)_VIRQ_$(VECT_IRQ)_TRACE_$(TRACE) - -## Caravel Pointers related to build directory -CARAVEL_ROOT ?= $(root_dir)/../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel - ## User Project Pointers -UPRJ_VERILOG_PATH ?= $(root_dir)/../../../verilog -UPRJ_TESTS_PATH = $(root_dir) -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl -UPRJ_BEHAVIOURAL_MODELS = $(root_dir)/../model -UPRJ_BEHAVIOURAL_AGENTS = $(root_dir)/../agents -UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes -UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs -UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes -UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes -UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include -sv_list = ../../user_risc_regress_tb.v +sv_list = $(root_dir)/user_risc_regress_tb.v top_module = user_risc_regress_tb # TB Paths -export sim_dir := $(UPRJ_TESTS_PATH) +export sim_dir := $(root_dir) export tst_dir := $(sim_dir)/tests -export inc_dir := $(UPRJ_VERILOG_PATH)/dv/firmware +export inc_dir := $(sim_dir)/../firmware test_results := $(bld_dir)/test_results.txt test_info := $(bld_dir)/test_info @@ -168,10 +168,6 @@ export RISCV_RAM_OBJCOPY ?= $(CROSS_PREFIX)objcopy -R .text.init -R .text -R .rodata -R .rodata.str1.4 -O verilog export RISCV_READELF ?= $(CROSS_PREFIX)readelf -s - -### To Enable IVERILOG FST DUMP -export IVERILOG_DUMPER = fst - ifneq (,$(findstring e,$(ARCH_lowercase))) # Tests can be compiled for RVE only if gcc version 8.0.0 or higher GCCVERSIONGT7 := $(shell expr `$(RISCV_GCC) -dumpfullversion | cut -f1 -d'.'` \> 7) @@ -204,7 +200,7 @@ # Targets -.PHONY: tests run_iverilog run_iverilog_wf run_modelsim run_modelsim_wlf run_vcs run_ncsim run_verilator run_verilator_wf +.PHONY: tests run_iverilog run_modelsim run_modelsim_wlf run_vcs run_ncsim run_verilator run_verilator_wf default: clean_test_list run_iverilog @@ -276,18 +272,73 @@ printf "$$(cat $(test_results)) \n" run_iverilog: $(test_info) +ifeq ($(SIM),RTL) + ifeq ($(DUMP),OFF) cd $(bld_dir); \ iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) -I $(UPRJ_TESTS_PATH) \ + -I $(UPRJ_TESTS_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $(sv_list) \ -o $(top_module).vvp; \ printf "" > $(test_results); \ iverilog-vpi ../../../vpi/system/system.c; \ vvp -M. -msystem $(top_module).vvp \ + +risc_core_id=$(RISC_CORE) \ + +test_info=$(test_info) \ + +test_results=$(test_results) \ + | tee $(sim_results) ;\ + printf "Simulation performed on $$(vvp -V) \n" ;\ + printf " Test | build | simulation \n" ; \ + printf "$$(cat $(test_results)) \n" + else + cd $(bld_dir); \ + iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -I $(UPRJ_TESTS_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ + $(sv_list) \ + -o $(top_module).vvp; \ + printf "" > $(test_results); \ + iverilog-vpi ../../../vpi/system/system.c; \ + vvp -M. -msystem $(top_module).vvp \ + +risc_core_id=$(RISC_CORE) \ + +test_info=$(test_info) \ + +test_results=$(test_results) \ + | tee $(sim_results) ;\ + printf "Simulation performed on $$(vvp -V) \n" ;\ + printf " Test | build | simulation \n" ; \ + printf "$$(cat $(test_results)) \n" + endif +else + ifeq ($(DUMP),OFF) + cd $(bld_dir); \ + iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -I $(UPRJ_TESTS_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + $(sv_list) \ + -o $(top_module).vvp; \ + printf "" > $(test_results); \ + iverilog-vpi ../../../vpi/system/system.c; \ + vvp -M. -msystem $(top_module).vvp \ + +risc_core_id=$(RISC_CORE) \ + +test_info=$(test_info) \ + +test_results=$(test_results) \ + | tee $(sim_results) ;\ + printf "Simulation performed on $$(vvp -V) \n" ;\ + printf " Test | build | simulation \n" ; \ + printf "$$(cat $(test_results)) \n" + else + cd $(bld_dir); \ + iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -I $(UPRJ_TESTS_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + $(sv_list) \ + -o $(top_module).vvp; \ + printf "" > $(test_results); \ + iverilog-vpi ../../../vpi/system/system.c; \ + vvp -M. -msystem $(top_module).vvp \ + +risc_core_id=$(RISC_CORE) \ +test_info=$(test_info) \ +test_results=$(test_results) \ | tee $(sim_results) ;\ @@ -295,25 +346,8 @@ printf " Test | build | simulation \n" ; \ printf "$$(cat $(test_results)) \n" -run_iverilog_wf: $(test_info) - cd $(bld_dir); \ - iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) -I $(UPRJ_TESTS_PATH) \ - $(sv_list) \ - -o $(top_module).vvp; \ - printf "" > $(test_results); \ - iverilog-vpi ../../../vpi/system/system.c; \ - vvp -M. -msystem $(top_module).vvp \ - +test_info=$(test_info) \ - +test_results=$(test_results) \ - | tee $(sim_results) ;\ - printf "Simulation performed on $$(vvp -V) \n" ;\ - printf " Test | build | simulation \n" ; \ - printf "$$(cat $(test_results)) \n" + endif +endif run_modelsim_wlf: $(test_info) $(MAKE) -C $(root_dir)/sim build_modelsim_wlf SIM_CFG_DEF=$(SIM_CFG_DEF) SIM_TRACE_DEF=$(SIM_TRACE_DEF) SIM_BUILD_OPTS=$(SIM_BUILD_OPTS); \
diff --git a/verilog/dv/riscv_regress/user_risc_regress_tb.v b/verilog/dv/riscv_regress/user_risc_regress_tb.v index b1a0b63..8b2dd41 100644 --- a/verilog/dv/riscv_regress/user_risc_regress_tb.v +++ b/verilog/dv/riscv_regress/user_risc_regress_tb.v
@@ -71,11 +71,10 @@ `default_nettype wire -`timescale 1 ns / 1 ns +`timescale 1 ns/1 ps -`include "uprj_netlists.v" +`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" `include "is62wvs1288.v" -`include "user_reg_map.v"
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v index 400e4ad..236eb33 100644 --- a/verilog/rtl/uprj_netlists.v +++ b/verilog/rtl/uprj_netlists.v
@@ -108,7 +108,6 @@ `include "wb_interconnect/src/wb_slave_port.sv" `include "wb_interconnect/src/wb_interconnect.sv" - `include "yifive/ycr1c/src/core/pipeline/ycr_pipe_hdu.sv" `include "yifive/ycr1c/src/core/pipeline/ycr_pipe_tdu.sv" `include "yifive/ycr1c/src/core/pipeline/ycr_ipic.sv"