backand cleanup
diff --git a/openlane/glbl_cfg/config.tcl b/openlane/glbl_cfg/config.tcl
index fd5bda6..7040413 100755
--- a/openlane/glbl_cfg/config.tcl
+++ b/openlane/glbl_cfg/config.tcl
@@ -29,6 +29,10 @@
set ::env(LEC_ENABLE) 0
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+
# Floorplanning
# -------------
@@ -41,7 +45,7 @@
set ::env(FP_PDN_VPITCH) 50
-set ::env(PDN_CFG) $script_dir/pdn.tcl
+#set ::env(PDN_CFG) $script_dir/pdn.tcl
set ::env(FP_VERTICAL_HALO) 6
set ::env(PL_TARGET_DENSITY) 0.52
diff --git a/openlane/glbl_cfg/pin_order.cfg b/openlane/glbl_cfg/pin_order.cfg
index 8f9547a..5867718 100644
--- a/openlane/glbl_cfg/pin_order.cfg
+++ b/openlane/glbl_cfg/pin_order.cfg
@@ -3,240 +3,237 @@
#MANUAL_PLACE
#E
cpu_clk 0000 0
-rtc_clk 0000 1
-cpu_rst_n 0000 2
-irq_lines\[15\] 0000 3
-irq_lines\[14\] 0000 4
-irq_lines\[13\] 0000 5
-irq_lines\[12\] 0000 6
-irq_lines\[11\] 0000 7
-irq_lines\[10\] 0000 8
-irq_lines\[9\] 0000 9
-irq_lines\[8\] 0000 10
-irq_lines\[7\] 0000 11
-irq_lines\[6\] 0000 12
-irq_lines\[5\] 0000 13
-irq_lines\[4\] 0000 14
-irq_lines\[3\] 0000 15
-irq_lines\[2\] 0000 16
-irq_lines\[1\] 0000 17
-irq_lines\[0\] 0000 18
-soft_irq 0000 19
-fuse_mhartid\[31\] 0000 20
-fuse_mhartid\[30\] 0000 21
-fuse_mhartid\[29\] 0000 22
-fuse_mhartid\[28\] 0000 23
-fuse_mhartid\[27\] 0000 24
-fuse_mhartid\[26\] 0000 25
-fuse_mhartid\[25\] 0000 26
-fuse_mhartid\[24\] 0000 27
-fuse_mhartid\[23\] 0000 28
-fuse_mhartid\[22\] 0000 29
-fuse_mhartid\[21\] 0000 30
-fuse_mhartid\[20\] 0000 31
-fuse_mhartid\[19\] 0000 32
-fuse_mhartid\[18\] 0000 33
-fuse_mhartid\[17\] 0000 34
-fuse_mhartid\[16\] 0000 35
-fuse_mhartid\[15\] 0000 36
-fuse_mhartid\[14\] 0000 37
-fuse_mhartid\[13\] 0000 38
-fuse_mhartid\[12\] 0000 39
-fuse_mhartid\[11\] 0000 40
-fuse_mhartid\[10\] 0000 41
-fuse_mhartid\[9\] 0000 42
-fuse_mhartid\[8\] 0000 43
-fuse_mhartid\[7\] 0000 44
-fuse_mhartid\[6\] 0000 45
-fuse_mhartid\[5\] 0000 46
-fuse_mhartid\[4\] 0000 47
-fuse_mhartid\[3\] 0000 48
-fuse_mhartid\[2\] 0000 49
-fuse_mhartid\[1\] 0000 50
-fuse_mhartid\[0\] 0000 51
+rtc_clk
+irq_lines\[15\]
+irq_lines\[14\]
+irq_lines\[13\]
+irq_lines\[12\]
+irq_lines\[11\]
+irq_lines\[10\]
+irq_lines\[9\]
+irq_lines\[8\]
+irq_lines\[7\]
+irq_lines\[6\]
+irq_lines\[5\]
+irq_lines\[4\]
+irq_lines\[3\]
+irq_lines\[2\]
+irq_lines\[1\]
+irq_lines\[0\]
+soft_irq
+fuse_mhartid\[31\]
+fuse_mhartid\[30\]
+fuse_mhartid\[29\]
+fuse_mhartid\[28\]
+fuse_mhartid\[27\]
+fuse_mhartid\[26\]
+fuse_mhartid\[25\]
+fuse_mhartid\[24\]
+fuse_mhartid\[23\]
+fuse_mhartid\[22\]
+fuse_mhartid\[21\]
+fuse_mhartid\[20\]
+fuse_mhartid\[19\]
+fuse_mhartid\[18\]
+fuse_mhartid\[17\]
+fuse_mhartid\[16\]
+fuse_mhartid\[15\]
+fuse_mhartid\[14\]
+fuse_mhartid\[13\]
+fuse_mhartid\[12\]
+fuse_mhartid\[11\]
+fuse_mhartid\[10\]
+fuse_mhartid\[9\]
+fuse_mhartid\[8\]
+fuse_mhartid\[7\]
+fuse_mhartid\[6\]
+fuse_mhartid\[5\]
+fuse_mhartid\[4\]
+fuse_mhartid\[3\]
+fuse_mhartid\[2\]
+fuse_mhartid\[1\]
+fuse_mhartid\[0\]
#N
mclk 0000 0
-reset_n 0000 1
-user_clock2 0000 2
-spi_rst_n 0000 3
-user_irq\[2\] 0000 4
-user_irq\[1\] 0000 5
-user_irq\[0\] 0000 6
-device_idcode\[31\] 0000 7
-device_idcode\[30\] 0000 8
-device_idcode\[29\] 0000 9
-device_idcode\[28\] 0000 10
-device_idcode\[27\] 0000 11
-device_idcode\[26\] 0000 12
-device_idcode\[25\] 0000 13
-device_idcode\[24\] 0000 14
-device_idcode\[23\] 0000 15
-device_idcode\[22\] 0000 16
-device_idcode\[21\] 0000 17
-device_idcode\[20\] 0000 18
-device_idcode\[19\] 0000 19
-device_idcode\[18\] 0000 20
-device_idcode\[17\] 0000 21
-device_idcode\[16\] 0000 22
-device_idcode\[15\] 0000 23
-device_idcode\[14\] 0000 24
-device_idcode\[13\] 0000 25
-device_idcode\[12\] 0000 26
-device_idcode\[11\] 0000 27
-device_idcode\[10\] 0000 28
-device_idcode\[9\] 0000 29
-device_idcode\[8\] 0000 30
-device_idcode\[7\] 0000 31
-device_idcode\[6\] 0000 32
-device_idcode\[5\] 0000 33
-device_idcode\[4\] 0000 34
-device_idcode\[3\] 0000 35
-device_idcode\[2\] 0000 36
-device_idcode\[1\] 0000 37
-device_idcode\[0\] 0000 38
+reset_n
+user_clock2
+user_irq\[2\]
+user_irq\[1\]
+user_irq\[0\]
+device_idcode\[31\]
+device_idcode\[30\]
+device_idcode\[29\]
+device_idcode\[28\]
+device_idcode\[27\]
+device_idcode\[26\]
+device_idcode\[25\]
+device_idcode\[24\]
+device_idcode\[23\]
+device_idcode\[22\]
+device_idcode\[21\]
+device_idcode\[20\]
+device_idcode\[19\]
+device_idcode\[18\]
+device_idcode\[17\]
+device_idcode\[16\]
+device_idcode\[15\]
+device_idcode\[14\]
+device_idcode\[13\]
+device_idcode\[12\]
+device_idcode\[11\]
+device_idcode\[10\]
+device_idcode\[9\]
+device_idcode\[8\]
+device_idcode\[7\]
+device_idcode\[6\]
+device_idcode\[5\]
+device_idcode\[4\]
+device_idcode\[3\]
+device_idcode\[2\]
+device_idcode\[1\]
+device_idcode\[0\]
#W
sdram_clk 0000 0
-sdram_rst_n 0000 1
-sdr_init_done 0000 2
-cfg_sdr_width\[1] 0000 3
-cfg_sdr_width\[0] 0000 4
-cfg_colbits\[1\] 0000 5
-cfg_colbits\[0\] 0000 6
-cfg_sdr_tras_d\[3\] 0000 7
-cfg_sdr_tras_d\[2\] 0000 8
-cfg_sdr_tras_d\[1\] 0000 9
-cfg_sdr_tras_d\[0\] 0000 10
-cfg_sdr_trp_d\[3\] 0000 11
-cfg_sdr_trp_d\[2\] 0000 12
-cfg_sdr_trp_d\[1\] 0000 13
-cfg_sdr_trp_d\[0\] 0000 14
-cfg_sdr_trcd_d\[3\] 0000 15
-cfg_sdr_trcd_d\[2\] 0000 16
-cfg_sdr_trcd_d\[1\] 0000 17
-cfg_sdr_trcd_d\[0\] 0000 18
-cfg_sdr_en 0000 19
-cfg_req_depth\[1\] 0000 20
-cfg_req_depth\[0\] 0000 21
-cfg_sdr_mode_reg\[12\] 0000 22
-cfg_sdr_mode_reg\[11\] 0000 23
-cfg_sdr_mode_reg\[10\] 0000 24
-cfg_sdr_mode_reg\[9\] 0000 25
-cfg_sdr_mode_reg\[8\] 0000 26
-cfg_sdr_mode_reg\[7\] 0000 27
-cfg_sdr_mode_reg\[6\] 0000 28
-cfg_sdr_mode_reg\[5\] 0000 29
-cfg_sdr_mode_reg\[4\] 0000 30
-cfg_sdr_mode_reg\[3\] 0000 31
-cfg_sdr_mode_reg\[2\] 0000 32
-cfg_sdr_mode_reg\[1\] 0000 33
-cfg_sdr_mode_reg\[0\] 0000 34
-cfg_sdr_cas\[2\] 0000 35
-cfg_sdr_cas\[1\] 0000 36
-cfg_sdr_cas\[0\] 0000 37
-cfg_sdr_trcar_d\[3\] 0000 38
-cfg_sdr_trcar_d\[2\] 0000 39
-cfg_sdr_trcar_d\[1\] 0000 40
-cfg_sdr_trcar_d\[0\] 0000 41
-cfg_sdr_twr_d\[3\] 0000 42
-cfg_sdr_twr_d\[2\] 0000 43
-cfg_sdr_twr_d\[1\] 0000 44
-cfg_sdr_twr_d\[0\] 0000 45
-cfg_sdr_rfsh\[11\] 0000 46
-cfg_sdr_rfsh\[10\] 0000 47
-cfg_sdr_rfsh\[9\] 0000 48
-cfg_sdr_rfsh\[8\] 0000 49
-cfg_sdr_rfsh\[7\] 0000 50
-cfg_sdr_rfsh\[6\] 0000 51
-cfg_sdr_rfsh\[5\] 0000 52
-cfg_sdr_rfsh\[4\] 0000 53
-cfg_sdr_rfsh\[3\] 0000 54
-cfg_sdr_rfsh\[2\] 0000 55
-cfg_sdr_rfsh\[1\] 0000 56
-cfg_sdr_rfsh\[0\] 0000 57
-cfg_sdr_rfmax\[2\] 0000 58
-cfg_sdr_rfmax\[1\] 0000 59
-cfg_sdr_rfmax\[0\] 0000 60
+sdr_init_done
+cfg_sdr_width\[1]
+cfg_sdr_width\[0]
+cfg_colbits\[1\]
+cfg_colbits\[0\]
+cfg_sdr_tras_d\[3\]
+cfg_sdr_tras_d\[2\]
+cfg_sdr_tras_d\[1\]
+cfg_sdr_tras_d\[0\]
+cfg_sdr_trp_d\[3\]
+cfg_sdr_trp_d\[2\]
+cfg_sdr_trp_d\[1\]
+cfg_sdr_trp_d\[0\]
+cfg_sdr_trcd_d\[3\]
+cfg_sdr_trcd_d\[2\]
+cfg_sdr_trcd_d\[1\]
+cfg_sdr_trcd_d\[0\]
+cfg_sdr_en
+cfg_req_depth\[1\]
+cfg_req_depth\[0\]
+cfg_sdr_mode_reg\[12\]
+cfg_sdr_mode_reg\[11\]
+cfg_sdr_mode_reg\[10\]
+cfg_sdr_mode_reg\[9\]
+cfg_sdr_mode_reg\[8\]
+cfg_sdr_mode_reg\[7\]
+cfg_sdr_mode_reg\[6\]
+cfg_sdr_mode_reg\[5\]
+cfg_sdr_mode_reg\[4\]
+cfg_sdr_mode_reg\[3\]
+cfg_sdr_mode_reg\[2\]
+cfg_sdr_mode_reg\[1\]
+cfg_sdr_mode_reg\[0\]
+cfg_sdr_cas\[2\]
+cfg_sdr_cas\[1\]
+cfg_sdr_cas\[0\]
+cfg_sdr_trcar_d\[3\]
+cfg_sdr_trcar_d\[2\]
+cfg_sdr_trcar_d\[1\]
+cfg_sdr_trcar_d\[0\]
+cfg_sdr_twr_d\[3\]
+cfg_sdr_twr_d\[2\]
+cfg_sdr_twr_d\[1\]
+cfg_sdr_twr_d\[0\]
+cfg_sdr_rfsh\[11\]
+cfg_sdr_rfsh\[10\]
+cfg_sdr_rfsh\[9\]
+cfg_sdr_rfsh\[8\]
+cfg_sdr_rfsh\[7\]
+cfg_sdr_rfsh\[6\]
+cfg_sdr_rfsh\[5\]
+cfg_sdr_rfsh\[4\]
+cfg_sdr_rfsh\[3\]
+cfg_sdr_rfsh\[2\]
+cfg_sdr_rfsh\[1\]
+cfg_sdr_rfsh\[0\]
+cfg_sdr_rfmax\[2\]
+cfg_sdr_rfmax\[1\]
+cfg_sdr_rfmax\[0\]
#S
reg_cs 0000 0
-reg_wr 0000 1
-reg_addr\[7\] 0000 2
-reg_addr\[6\] 0000 3
-reg_addr\[5\] 0000 4
-reg_addr\[4\] 0000 5
-reg_addr\[3\] 0000 6
-reg_addr\[2\] 0000 7
-reg_addr\[1\] 0000 8
-reg_addr\[0\] 0000 9
-reg_be\[3\] 0000 10
-reg_be\[2\] 0000 11
-reg_be\[1\] 0000 12
-reg_be\[0\] 0000 13
-reg_wdata\[31\] 0000 14
-reg_wdata\[30\] 0000 15
-reg_wdata\[29\] 0000 16
-reg_wdata\[28\] 0000 17
-reg_wdata\[27\] 0000 18
-reg_wdata\[26\] 0000 19
-reg_wdata\[25\] 0000 20
-reg_wdata\[24\] 0000 21
-reg_wdata\[23\] 0000 22
-reg_wdata\[22\] 0000 23
-reg_wdata\[21\] 0000 24
-reg_wdata\[20\] 0000 25
-reg_wdata\[19\] 0000 26
-reg_wdata\[18\] 0000 27
-reg_wdata\[17\] 0000 28
-reg_wdata\[16\] 0000 29
-reg_wdata\[15\] 0000 30
-reg_wdata\[14\] 0000 31
-reg_wdata\[13\] 0000 32
-reg_wdata\[12\] 0000 33
-reg_wdata\[11\] 0000 34
-reg_wdata\[10\] 0000 35
-reg_wdata\[9\] 0000 36
-reg_wdata\[8\] 0000 37
-reg_wdata\[7\] 0000 38
-reg_wdata\[6\] 0000 39
-reg_wdata\[5\] 0000 40
-reg_wdata\[4\] 0000 41
-reg_wdata\[3\] 0000 42
-reg_wdata\[2\] 0000 43
-reg_wdata\[1\] 0000 44
-reg_wdata\[0\] 0000 45
-reg_rdata\[31\] 0000 46
-reg_rdata\[30\] 0000 47
-reg_rdata\[29\] 0000 48
-reg_rdata\[28\] 0000 49
-reg_rdata\[27\] 0000 50
-reg_rdata\[26\] 0000 51
-reg_rdata\[25\] 0000 52
-reg_rdata\[24\] 0000 53
-reg_rdata\[23\] 0000 54
-reg_rdata\[22\] 0000 55
-reg_rdata\[21\] 0000 56
-reg_rdata\[20\] 0000 57
-reg_rdata\[19\] 0000 58
-reg_rdata\[18\] 0000 59
-reg_rdata\[17\] 0000 60
-reg_rdata\[16\] 0000 61
-reg_rdata\[15\] 0000 62
-reg_rdata\[14\] 0000 63
-reg_rdata\[13\] 0000 64
-reg_rdata\[12\] 0000 65
-reg_rdata\[11\] 0000 66
-reg_rdata\[10\] 0000 67
-reg_rdata\[9\] 0000 68
-reg_rdata\[8\] 0000 69
-reg_rdata\[7\] 0000 70
-reg_rdata\[6\] 0000 71
-reg_rdata\[5\] 0000 72
-reg_rdata\[4\] 0000 73
-reg_rdata\[3\] 0000 74
-reg_rdata\[2\] 0000 75
-reg_rdata\[1\] 0000 76
-reg_rdata\[0\] 0000 77
-reg_ack 0000 78
+reg_wr
+reg_addr\[7\]
+reg_addr\[6\]
+reg_addr\[5\]
+reg_addr\[4\]
+reg_addr\[3\]
+reg_addr\[2\]
+reg_addr\[1\]
+reg_addr\[0\]
+reg_be\[3\]
+reg_be\[2\]
+reg_be\[1\]
+reg_be\[0\]
+reg_wdata\[31\]
+reg_wdata\[30\]
+reg_wdata\[29\]
+reg_wdata\[28\]
+reg_wdata\[27\]
+reg_wdata\[26\]
+reg_wdata\[25\]
+reg_wdata\[24\]
+reg_wdata\[23\]
+reg_wdata\[22\]
+reg_wdata\[21\]
+reg_wdata\[20\]
+reg_wdata\[19\]
+reg_wdata\[18\]
+reg_wdata\[17\]
+reg_wdata\[16\]
+reg_wdata\[15\]
+reg_wdata\[14\]
+reg_wdata\[13\]
+reg_wdata\[12\]
+reg_wdata\[11\]
+reg_wdata\[10\]
+reg_wdata\[9\]
+reg_wdata\[8\]
+reg_wdata\[7\]
+reg_wdata\[6\]
+reg_wdata\[5\]
+reg_wdata\[4\]
+reg_wdata\[3\]
+reg_wdata\[2\]
+reg_wdata\[1\]
+reg_wdata\[0\]
+reg_rdata\[31\]
+reg_rdata\[30\]
+reg_rdata\[29\]
+reg_rdata\[28\]
+reg_rdata\[27\]
+reg_rdata\[26\]
+reg_rdata\[25\]
+reg_rdata\[24\]
+reg_rdata\[23\]
+reg_rdata\[22\]
+reg_rdata\[21\]
+reg_rdata\[20\]
+reg_rdata\[19\]
+reg_rdata\[18\]
+reg_rdata\[17\]
+reg_rdata\[16\]
+reg_rdata\[15\]
+reg_rdata\[14\]
+reg_rdata\[13\]
+reg_rdata\[12\]
+reg_rdata\[11\]
+reg_rdata\[10\]
+reg_rdata\[9\]
+reg_rdata\[8\]
+reg_rdata\[7\]
+reg_rdata\[6\]
+reg_rdata\[5\]
+reg_rdata\[4\]
+reg_rdata\[3\]
+reg_rdata\[2\]
+reg_rdata\[1\]
+reg_rdata\[0\]
+reg_ack
diff --git a/openlane/sdram/base.sdc b/openlane/sdram/base.sdc
index 0b59edd..117c0f4 100644
--- a/openlane/sdram/base.sdc
+++ b/openlane/sdram/base.sdc
@@ -6,7 +6,7 @@
set ::env(SDRAM_CLOCK_PORT) "sdram_clk"
set ::env(PAD_SDRAM_CLOCK_PERIOD) "20"
-set ::env(PAD_SDRAM_CLOCK_PORT) "sdram_pad_clk"
+set ::env(PAD_SDRAM_CLOCK_PORT) "io_in\[29\]"
######################################
# WB Clock domain input output
######################################
@@ -17,7 +17,7 @@
puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
-set_input_delay 2.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] {wb_rst_i}
+set_input_delay 2.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] {wb_rst_n}
set_input_delay 3.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_stb_i*]
set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_addr_i*]
@@ -52,16 +52,8 @@
puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
-set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port sdr_cke*]
-set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port sdr_cs_n*]
-set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port sdr_ras_n*]
-set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port sdr_cas_n*]
-set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port sdr_we_n*]
-set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port sdr_dqm*]
-set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port sdr_ba*]
-set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port sdr_addr*]
-set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port sdr_dout*]
-set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port sdr_den_n*]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out*]
+set_output_delay $sdram_output_delay_value -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_oeb*]
################################################
# PAD SDRAM Clock domain input output
@@ -70,7 +62,7 @@
################################################
create_clock [get_ports $::env(PAD_SDRAM_CLOCK_PORT)] -name $::env(PAD_SDRAM_CLOCK_PORT) -period $::env(SDRAM_CLOCK_PERIOD)
-set_input_delay $sdram_input_delay_value -clock [get_clocks $::env(PAD_SDRAM_CLOCK_PORT)] [get_port pad_sdr_din*]
+set_input_delay $sdram_input_delay_value -clock [get_clocks $::env(PAD_SDRAM_CLOCK_PORT)] [get_port io_in*]
set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks $::env(WB_CLOCK_PORT)] -group [get_clocks $::env(SDRAM_CLOCK_PORT)]
diff --git a/openlane/sdram/config.tcl b/openlane/sdram/config.tcl
index 879a9ae..6d25773 100755
--- a/openlane/sdram/config.tcl
+++ b/openlane/sdram/config.tcl
@@ -9,7 +9,7 @@
# Timing configuration
set ::env(CLOCK_PERIOD) "10"
-set ::env(CLOCK_PORT) "wb_clk_i sdram_clk sdram_pad_clk"
+set ::env(CLOCK_PORT) "wb_clk_i sdram_clk"
# Sources
@@ -34,6 +34,10 @@
set ::env(LEC_ENABLE) 0
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+
# Floorplanning
# -------------
@@ -45,7 +49,7 @@
set ::env(FP_PDN_VPITCH) 50
-set ::env(PDN_CFG) $script_dir/pdn.tcl
+#set ::env(PDN_CFG) $script_dir/pdn.tcl
set ::env(FP_VERTICAL_HALO) 6
set ::env(PL_TARGET_DENSITY) 0.52
diff --git a/openlane/sdram/pin_order.cfg b/openlane/sdram/pin_order.cfg
index 08d9668..8f3bcb1 100644
--- a/openlane/sdram/pin_order.cfg
+++ b/openlane/sdram/pin_order.cfg
@@ -3,50 +3,101 @@
#W
wb_clk_i 0000 0
-wb_rst_i 0000 1
+wb_rst_n 0000 1
#N
-sdr_cas_n 0000 0
-sdr_cke 0000 1
-sdr_cs_n 0000 2
-sdr_dqm 0000 3
-sdr_ras_n 0000 4
-sdr_we_n 0000 5
-sdr_addr\[12\] 0000 6
-sdr_addr\[11\] 0000 7
-sdr_addr\[10\] 0000 8
-sdr_addr\[9\] 0000 9
-sdr_addr\[8\] 0000 10
-sdr_addr\[7\] 0000 11
-sdr_addr\[6\] 0000 12
-sdr_addr\[5\] 0000 13
-sdr_addr\[4\] 0000 14
-sdr_addr\[3\] 0000 15
-sdr_addr\[2\] 0000 16
-sdr_addr\[1\] 0000 17
-sdr_addr\[0\] 0000 18
-sdr_ba\[1\] 0000 19
-sdr_ba\[0\] 0000 20
-pad_sdr_din\[7\] 0000 21
-pad_sdr_din\[6\] 0000 22
-pad_sdr_din\[5\] 0000 23
-pad_sdr_din\[4\] 0000 24
-pad_sdr_din\[3\] 0000 25
-pad_sdr_din\[2\] 0000 26
-pad_sdr_din\[1\] 0000 27
-pad_sdr_din\[0\] 0000 28
-sdr_dout\[7\] 0000 29
-sdr_dout\[6\] 0000 30
-sdr_dout\[5\] 0000 31
-sdr_dout\[4\] 0000 32
-sdr_dout\[3\] 0000 33
-sdr_dout\[2\] 0000 34
-sdr_dout\[1\] 0000 35
-sdr_dout\[0\] 0000 36
-sdr_den_n 0000 37
-sdram_pad_clk 0000 38
+io_oeb\[29\]
+io_out\[29\]
+io_in\[29\]
+io_oeb\[28\]
+io_out\[28\]
+io_in\[28\]
+io_oeb\[27\]
+io_out\[27\]
+io_in\[27\]
+io_oeb\[26\]
+io_out\[26\]
+io_in\[26\]
+io_oeb\[25\]
+io_out\[25\]
+io_in\[25\]
+io_oeb\[24\]
+io_out\[24\]
+io_in\[24\]
+io_oeb\[23\]
+io_out\[23\]
+io_in\[23\]
+io_oeb\[22\]
+io_out\[22\]
+io_in\[22\]
+io_oeb\[21\]
+io_out\[21\]
+io_in\[21\]
+io_oeb\[20\]
+io_out\[20\]
+io_in\[20\]
+io_oeb\[19\]
+io_out\[19\]
+io_in\[19\]
+io_oeb\[18\]
+io_out\[18\]
+io_in\[18\]
+io_oeb\[17\]
+io_out\[17\]
+io_in\[17\]
+io_oeb\[16\]
+io_out\[16\]
+io_in\[16\]
+io_oeb\[15\]
+io_out\[15\]
+io_in\[15\]
+io_oeb\[14\]
+io_out\[14\]
+io_in\[14\]
+io_oeb\[13\]
+io_out\[13\]
+io_in\[13\]
+io_oeb\[12\]
+io_out\[12\]
+io_in\[12\]
+io_oeb\[11\]
+io_out\[11\]
+io_in\[11\]
+io_oeb\[10\]
+io_out\[10\]
+io_in\[10\]
+io_oeb\[9\]
+io_out\[9\]
+io_in\[9\]
+io_oeb\[8\]
+io_out\[8\]
+io_in\[8\]
+io_oeb\[7\]
+io_out\[7\]
+io_in\[7\]
+io_oeb\[6\]
+io_out\[6\]
+io_in\[6\]
+io_oeb\[5\]
+io_out\[5\]
+io_in\[5\]
+io_oeb\[4\]
+io_out\[4\]
+io_in\[4\]
+io_oeb\[3\]
+io_out\[3\]
+io_in\[3\]
+io_oeb\[2\]
+io_out\[2\]
+io_in\[2\]
+io_oeb\[1\]
+io_out\[1\]
+io_in\[1\]
+io_oeb\[0\]
+io_out\[0\]
+io_in\[0\]
#E
@@ -218,6 +269,3 @@
wb_dat_o\[0\] 0000 101
wb_ack_o 0000 102
wb_cyc_i 0000 103
-wb_cti_i\[2] 0000 104
-wb_cti_i\[1] 0000 105
-wb_cti_i\[0] 0000 106
diff --git a/openlane/spi_master/config.tcl b/openlane/spi_master/config.tcl
index 4308ae6..c7cb2cb 100755
--- a/openlane/spi_master/config.tcl
+++ b/openlane/spi_master/config.tcl
@@ -29,6 +29,10 @@
set ::env(LEC_ENABLE) 0
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+
# Floorplanning
# -------------
@@ -40,7 +44,7 @@
set ::env(FP_PDN_VPITCH) 50
-set ::env(PDN_CFG) $script_dir/pdn.tcl
+#set ::env(PDN_CFG) $script_dir/pdn.tcl
set ::env(FP_VERTICAL_HALO) 6
set ::env(PL_TARGET_DENSITY) 0.52
diff --git a/openlane/spi_master/pin_order.cfg b/openlane/spi_master/pin_order.cfg
index 99a192d..6d3c721 100644
--- a/openlane/spi_master/pin_order.cfg
+++ b/openlane/spi_master/pin_order.cfg
@@ -1,7 +1,7 @@
#BUS_SORT
#MANUAL_PLACE
-#E
+#W
mclk 0000 0
rst_n 0000 1
events_o\[1\] 0000 2
@@ -9,22 +9,24 @@
#N
-spi_mode\[1\] 0000 0
-spi_mode\[0\] 0000 1
-spi_clk 0000 2
-spi_csn0 0000 3
-spi_csn1 0000 4
-spi_csn2 0000 5
-spi_csn3 0000 6
-spi_en_tx 0000 7
-spi_sdi0 0000 8
-spi_sdi1 0000 9
-spi_sdi2 0000 10
-spi_sdi3 0000 11
-spi_sdo0 0000 12
-spi_sdo1 0000 13
-spi_sdo2 0000 14
-spi_sdo3 0000 15
+io_in\[5\] 0000 0
+io_out\[5\]
+io_oeb\[5\]
+io_in\[4\]
+io_out\[4\]
+io_oeb\[4\]
+io_in\[3\]
+io_out\[3\]
+io_oeb\[3\]
+io_in\[2\]
+io_out\[2\]
+io_oeb\[2\]
+io_in\[1\]
+io_out\[1\]
+io_oeb\[1\]
+io_in\[0\]
+io_out\[0\]
+io_oeb\[0\]
#S
diff --git a/openlane/syntacore/config.tcl b/openlane/syntacore/config.tcl
index 1b74046..1b4c673 100755
--- a/openlane/syntacore/config.tcl
+++ b/openlane/syntacore/config.tcl
@@ -55,6 +55,10 @@
set ::env(LEC_ENABLE) 0
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+
# --------
# Floorplanning
# -------------
@@ -68,7 +72,7 @@
set ::env(FP_PDN_VPITCH) 50
-set ::env(PDN_CFG) $script_dir/pdn.tcl
+#set ::env(PDN_CFG) $script_dir/pdn.tcl
set ::env(FP_VERTICAL_HALO) 6
set ::env(PL_TARGET_DENSITY) 0.52
diff --git a/openlane/syntacore/pin_order.cfg b/openlane/syntacore/pin_order.cfg
index 9a84238..5f52899 100644
--- a/openlane/syntacore/pin_order.cfg
+++ b/openlane/syntacore/pin_order.cfg
@@ -60,8 +60,6 @@
wb_rst_n 0000 1
pwrup_rst_n 0000 2
rst_n 0000 3
-test_mode 0000 4
-test_rst_n 0000 5
#N
wbd_imem_stb_o 0000 0
diff --git a/openlane/uart/config.tcl b/openlane/uart/config.tcl
index fd726c7..b0d2b84 100644
--- a/openlane/uart/config.tcl
+++ b/openlane/uart/config.tcl
@@ -35,6 +35,10 @@
set ::env(LEC_ENABLE) 0
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+
# Floorplanning
# -------------
@@ -46,7 +50,7 @@
set ::env(FP_PDN_VPITCH) 50
-set ::env(PDN_CFG) $script_dir/pdn.tcl
+#set ::env(PDN_CFG) $script_dir/pdn.tcl
set ::env(FP_VERTICAL_HALO) 6
set ::env(PL_TARGET_DENSITY) 0.52
diff --git a/openlane/uart/pin_order.cfg b/openlane/uart/pin_order.cfg
index 218a647..248595c 100644
--- a/openlane/uart/pin_order.cfg
+++ b/openlane/uart/pin_order.cfg
@@ -3,9 +3,13 @@
#S
app_clk 0000 0
-arst_n 0000 1
-si 0000 2
-so 0000 3
+arst_n
+io_in\[1\]
+io_out\[1\]
+io_oeb\[1\]
+io_in\[0\]
+io_out\[0\]
+io_oeb\[0\]
#N
reg_cs 0000 0
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 5a67c33..eee22e7 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -55,6 +55,7 @@
$script_dir/../../verilog/gl/glbl_cfg.v \
$script_dir/../../verilog/gl/uart.v \
$script_dir/../../verilog/gl/sdram.v \
+ $script_dir/../../verilog/gl/wb_host.v \
$script_dir/../../verilog/gl/syntacore.v \
"
@@ -64,6 +65,7 @@
$lef_root/wb_interconnect.lef \
$lef_root/sdram.lef \
$lef_root/uart.lef \
+ $lef_root/wb_host.lef \
$lef_root/syntacore.lef \
"
@@ -73,6 +75,7 @@
$gds_root/wb_interconnect.gds \
$gds_root/uart.gds \
$gds_root/sdram.gds \
+ $gds_root/wb_host.gds \
$gds_root/syntacore.gds \
"
@@ -80,67 +83,26 @@
set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore/scr1/src/includes $script_dir/../../verilog/rtl/sdram_ctrl/src/defs ]
+set ::env(GLB_RT_MAXLAYER) 4
+
+set ::env(FP_PDN_CHECK_NODES) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
# The following is because there are no std cells in the example wrapper project.
#set ::env(SYNTH_TOP_LEVEL) 1
-set ::env(PL_BASIC_PLACEMENT) 1
+set ::env(PL_RANDOM_GLB_PLACEMENT) 1
-# Important for large macro placement
-set ::env(PL_DIAMOND_SEARCH_HEIGHT) "400"
-set ::env(ROUTING_OPT_ITERS) "20"
-
-set ::env(GLB_RT_ALLOW_CONGESTION) 1
-set ::env(GLB_RT_MAXLAYER) 5
-set ::env(GLB_RT_MINLAYER) 2
-set ::env(GLB_RT_ADJUSTMENT) 0.45
-set ::env(GENERATE_FINAL_SUMMARY_REPORT) 1
-set ::env(SYNTH_READ_BLACKBOX_LIB) 1
-set ::env(FP_PDN_CHECK_NODES) 0
-# This makes sure that the core rings are outside the boundaries
-# of your block.
-set ::env(MAGIC_ZEROIZE_ORIGIN) 0
-
-# Area Configurations. DON'T TOUCH.
-set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 2920 3520"
-
-set ::env(RUN_CVC) 0
-
-# Pin Configurations. DON'T TOUCH
-set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
-
-set ::unit 2.4
-set ::env(FP_IO_VEXTEND) [expr 2*$::unit]
-set ::env(FP_IO_HEXTEND) [expr 2*$::unit]
-set ::env(FP_IO_VLENGTH) $::unit
-set ::env(FP_IO_HLENGTH) $::unit
-
-set ::env(FP_IO_VTHICKNESS_MULT) 4
-set ::env(FP_IO_HTHICKNESS_MULT) 4
-
-# Power & Pin Configurations. DON'T TOUCH.
-set ::env(FP_PDN_CORE_RING) 1
-set ::env(FP_PDN_CORE_RING_VWIDTH) 3
-set ::env(FP_PDN_CORE_RING_HWIDTH) $::env(FP_PDN_CORE_RING_VWIDTH)
-set ::env(FP_PDN_CORE_RING_VOFFSET) 14
-set ::env(FP_PDN_CORE_RING_HOFFSET) $::env(FP_PDN_CORE_RING_VOFFSET)
-set ::env(FP_PDN_CORE_RING_VSPACING) 1.7
-set ::env(FP_PDN_CORE_RING_HSPACING) $::env(FP_PDN_CORE_RING_VSPACING)
-
-set ::env(FP_PDN_VWIDTH) 3
-set ::env(FP_PDN_HWIDTH) 3
-set ::env(FP_PDN_VOFFSET) 5
-set ::env(FP_PDN_HOFFSET) $::env(FP_PDN_VOFFSET)
-set ::env(FP_PDN_VPITCH) 180
-set ::env(FP_PDN_HPITCH) $::env(FP_PDN_VPITCH)
-set ::env(FP_PDN_VSPACING) [expr 5*$::env(FP_PDN_CORE_RING_VWIDTH)]
-set ::env(FP_PDN_HSPACING) [expr 5*$::env(FP_PDN_CORE_RING_HWIDTH)]
-set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
-set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
-set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
set ::env(DIODE_INSERTION_STRATEGY) 0
set ::env(FILL_INSERTION) 0
set ::env(TAP_DECAP_INSERTION) 0
set ::env(CLOCK_TREE_SYNTH) 0
+
+set ::env(PL_DIAMOND_SEARCH_HEIGHT) "250"
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index 901e853..26d4b30 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,7 +1,7 @@
-u_core.u_riscv_top 300 300 N
-u_core.u_glbl_cfg 2000 2200 N
-u_core.u_uart_core 2000 1100 N
-u_core.u_intercon 300 1800 N
-u_core.u_spi_master 300 2200 N
-u_core.u_sdram_ctrl 1000 2200 N
-u_core.u_glbl_cfg 2000 2200 N
+u_core.u_riscv_top 300 800 N
+u_core.u_glbl_cfg 2000 2700 N
+u_core.u_uart_core 2000 1600 N
+u_core.u_intercon 300 2300 N
+u_core.u_spi_master 300 2700 N
+u_core.u_sdram_ctrl 1000 2700 N
+u_core.u_wb_host 300 300 N
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index b7f7a50..144a5f2 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl
@@ -30,6 +30,10 @@
set ::env(LEC_ENABLE) 0
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+
# Floorplanning
# -------------
@@ -43,7 +47,7 @@
set ::env(FP_PDN_VPITCH) 50
-set ::env(PDN_CFG) $script_dir/pdn.tcl
+#set ::env(PDN_CFG) $script_dir/pdn.tcl
set ::env(FP_VERTICAL_HALO) 6
set ::env(PL_TARGET_DENSITY) 0.32
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg
index ae72f2a..120e132 100644
--- a/openlane/wb_interconnect/pin_order.cfg
+++ b/openlane/wb_interconnect/pin_order.cfg
@@ -248,7 +248,6 @@
s3_wbd_dat_i\[1\]
s3_wbd_dat_i\[0\]
s3_wbd_ack_i
-s3_wbd_err_i
s3_wbd_cyc_o
#N
@@ -355,7 +354,6 @@
s0_wbd_dat_i\[1\]
s0_wbd_dat_i\[0\]
s0_wbd_ack_i
-s0_wbd_err_i
s0_wbd_cyc_o
s1_wbd_stb_o 0700 0 2
@@ -461,7 +459,6 @@
s1_wbd_dat_i\[1\]
s1_wbd_dat_i\[0\]
s1_wbd_ack_i
-s1_wbd_err_i
s1_wbd_cyc_o
s2_wbd_stb_o 1700 0 2
@@ -543,7 +540,6 @@
s2_wbd_dat_i\[1\]
s2_wbd_dat_i\[0\]
s2_wbd_ack_i
-s2_wbd_err_i
s2_wbd_cyc_o
#W
diff --git a/signoff/glbl_cfg/final_summary_report.csv b/signoff/glbl_cfg/final_summary_report.csv
index 5c5c658..f364c36 100644
--- a/signoff/glbl_cfg/final_summary_report.csv
+++ b/signoff/glbl_cfg/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/glbl_cfg,glbl_cfg,glbl_cfg,Flow_completed,0h4m40s,0h2m46s,47033.33333333334,0.12,23516.66666666667,42,522.13,2822,0,0,0,0,0,0,0,1,0,0,0,164974,23877,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,130499422,0.0,42.48,45.14,4.0,3.21,-1,2676,2872,476,672,0,0,0,2822,1,0,3,9,474,0,3,571,588,548,10,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,50,153.18,0.52,0,sky130_fd_sc_hd,4,4
+0,/project/openlane/glbl_cfg,glbl_cfg,glbl_cfg,Flow_completed,0h4m54s,0h2m58s,47033.33333333334,0.12,23516.66666666667,42,525.0,2822,0,0,0,0,0,0,0,3,0,0,0,164082,23983,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,130105462,0.0,39.84,44.17,6.3,5.77,-1,2676,2872,476,672,0,0,0,2822,1,0,3,9,474,0,3,571,588,548,10,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,50,153.18,0.52,0,sky130_fd_sc_hd,4,4
diff --git a/signoff/sdram/final_summary_report.csv b/signoff/sdram/final_summary_report.csv
index 5551aa2..7679060 100644
--- a/signoff/sdram/final_summary_report.csv
+++ b/signoff/sdram/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/sdram,sdrc_top,sdram,Flow_completed,0h8m17s,0h4m3s,37154.28571428572,0.35,18577.14285714286,29,627.36,6502,0,0,0,0,0,0,0,3,0,0,0,319648,53184,-0.56,-0.56,-0.51,-0.51,-0.52,-16.15,-16.15,-67.68,-67.68,-85.83,250181986,0.0,36.08,22.35,5.09,1.65,-1,6477,6647,1150,1320,0,0,0,6502,131,107,82,107,352,213,29,2197,1190,1123,28,350,4248,0,4598,95.05703422053233,10.52,10,AREA 0,5,50,1,50,153.18,0.52,0,sky130_fd_sc_hd,4,4
+0,/project/openlane/sdram,sdrc_top,sdram,Flow_completed,0h9m0s,0h4m10s,37194.28571428572,0.35,18597.14285714286,29,615.55,6509,0,0,0,0,0,0,0,1,0,0,0,317021,52641,-3.59,-3.59,-3.59,-3.59,-4.69,-3.59,-3.59,-3.59,-3.59,-4.69,248911505,0.0,35.34,22.72,5.59,0.95,-1,6444,6672,1140,1368,0,0,0,6509,132,107,80,108,350,212,30,2197,1189,1088,29,350,4248,0,4598,68.07351940095302,14.690000000000001,10,AREA 0,5,50,1,50,153.18,0.52,0,sky130_fd_sc_hd,4,4
diff --git a/signoff/spi_master/final_summary_report.csv b/signoff/spi_master/final_summary_report.csv
index 542e54d..4cb3b80 100644
--- a/signoff/spi_master/final_summary_report.csv
+++ b/signoff/spi_master/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/spi_master,spim_top,spi_master,Flow_completed,0h7m25s,0h4m9s,25650.0,0.24,12825.0,22,565.22,3078,0,0,0,0,0,0,0,0,0,0,0,192520,29838,-3.48,-3.48,-4.12,-4.12,-4.63,-122.15,-122.15,-1022.65,-1022.65,-1261.37,148845920,0.0,20.22,26.73,1.11,10.26,-1,3056,3154,447,545,0,0,0,3078,85,0,94,81,1122,89,19,921,527,463,28,424,2889,0,3313,68.35269993164731,14.629999999999999,10,AREA 0,4,50,1,50,153.18,0.52,0,sky130_fd_sc_hd,4,4
+0,/project/openlane/spi_master,spim_top,spi_master,Flow_completed,0h6m23s,0h3m50s,25416.66666666667,0.24,12708.333333333336,22,570.17,3050,0,0,0,0,0,0,0,1,0,0,0,180296,28569,-1.48,-1.48,-1.98,-1.98,-2.67,-86.69,-86.69,-451.23,-451.23,-670.86,140719500,0.0,19.19,26.08,0.87,7.44,-1,3016,3128,433,545,0,0,0,3050,83,0,92,79,1118,89,19,920,527,458,28,424,2889,0,3313,78.92659826361484,12.67,10,AREA 0,4,50,1,50,153.18,0.52,0,sky130_fd_sc_hd,4,4
diff --git a/signoff/syntacore/final_summary_report.csv b/signoff/syntacore/final_summary_report.csv
index 03edd3a..e34d613 100644
--- a/signoff/syntacore/final_summary_report.csv
+++ b/signoff/syntacore/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/syntacore,scr1_top_wb,syntacore,Flow_completed,0h49m35s,0h23m51s,34500.0,1.8,17250.0,25,1233.35,31050,0,0,0,0,0,0,0,17,2,0,0,1859813,273688,-0.26,-0.26,-0.4,-0.4,-0.54,-9.62,-9.62,-22.88,-22.88,-28.71,1563068607,0.0,35.03,24.43,12.75,3.82,-1,30938,31176,2811,3049,0,0,0,31050,619,0,692,2059,4036,2095,1327,7438,2842,2789,96,866,22836,0,23702,94.87666034155599,10.54,10,AREA 0,4,50,1,50,153.18,0.52,0,sky130_fd_sc_hd,4,4
+0,/project/openlane/syntacore,scr1_top_wb,syntacore,Flow_completed,0h51m0s,0h23m39s,34493.333333333336,1.8,17246.666666666668,25,1236.48,31044,0,0,0,0,0,0,0,7,2,0,0,1867015,273721,-0.26,-0.26,-0.42,-0.42,-0.49,-9.62,-9.62,-26.28,-26.28,-27.81,1569371612,0.0,34.83,24.33,13.44,3.98,-1,30930,31168,2806,3044,0,0,0,31044,619,0,692,2060,4036,2095,1327,7433,2838,2786,95,866,22836,0,23702,95.32888465204957,10.49,10,AREA 0,4,50,1,50,153.18,0.52,0,sky130_fd_sc_hd,4,4
diff --git a/signoff/uart/final_summary_report.csv b/signoff/uart/final_summary_report.csv
index 2c9f3d3..d32ec61 100644
--- a/signoff/uart/final_summary_report.csv
+++ b/signoff/uart/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/uart,uart_core,uart,Flow_completed,0h4m18s,0h2m37s,43383.333333333336,0.12,21691.666666666668,35,514.21,2603,0,0,0,0,0,0,0,0,0,0,0,95167,20189,-0.54,-0.54,-0.48,-0.48,-0.73,-37.39,-37.39,-32.51,-32.51,-55.78,71078085,0.0,24.29,28.78,0.57,1.17,-1,2604,2621,453,470,0,0,0,2603,56,0,29,41,183,125,26,685,435,396,18,278,1410,0,1688,93.19664492078284,10.73,10,AREA 0,5,50,1,50,153.18,0.52,0,sky130_fd_sc_hd,4,4
+0,/project/openlane/uart,uart_core,uart,Flow_completed,0h5m14s,0h3m20s,43433.333333333336,0.12,21716.666666666668,35,511.72,2606,0,0,0,0,0,0,0,0,0,0,0,95298,20096,-0.57,-0.57,-0.5,-0.5,-0.71,-40.55,-40.55,-33.82,-33.82,-56.54,70681058,0.0,25.01,28.03,0.33,2.03,-1,2605,2625,454,474,0,0,0,2606,59,0,30,41,182,125,26,685,435,396,16,278,1410,0,1688,93.37068160597572,10.71,10,AREA 0,5,50,1,50,153.18,0.52,0,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 7e4defc..1eda607 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h42m47s,0h4m57s,38.33281444582815,10.2784,19.166407222914074,0,578.02,197,0,0,0,0,0,0,98674,15,225,-1,13,661124,2948,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,655217497,0.0,1.25,5.09,0.4,2.03,-1,693,1311,684,1302,0,0,0,197,0,0,0,0,0,0,0,0,2,2,1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0.45,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h48m32s,0h6m22s,3.1133250311332503,10.2784,1.5566625155666252,0,574.53,16,0,0,0,0,0,0,65,0,23,-1,6,1272729,5759,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,2.81,4.04,0.21,1.09,-1,852,1470,843,1461,0,0,0,16,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_interconnect/final_summary_report.csv b/signoff/wb_interconnect/final_summary_report.csv
index 3eb297f..fcbedf8 100644
--- a/signoff/wb_interconnect/final_summary_report.csv
+++ b/signoff/wb_interconnect/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,Flow_completed,0h6m17s,0h2m46s,6500.0,0.4,3250.0,6,540.84,1300,0,0,0,0,0,0,0,9,0,0,0,465926,16959,0.0,0.0,0.0,0.0,-0.04,0.0,0.0,0.0,0.0,-0.04,407751231,0.0,46.13,11.88,29.14,0.34,-1,1054,1627,210,783,0,0,0,1300,247,0,75,14,115,0,0,181,436,422,10,130,4719,0,4849,99.60159362549801,10.04,10,AREA 0,4,50,1,50,153.18,0.32,0,sky130_fd_sc_hd,4,4
+0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,Flow_completed,0h7m29s,0h3m50s,6465.0,0.4,3232.5,6,563.65,1293,0,0,0,0,0,0,0,9,0,0,0,468040,17506,0.0,0.0,0.0,0.0,-1.15,0.0,0.0,0.0,0.0,-29.57,415332616,0.0,44.92,11.38,31.98,0.1,-1,1043,1616,204,777,0,0,0,1293,244,0,75,15,111,0,0,180,431,418,11,130,4719,0,4849,89.68609865470852,11.15,10,AREA 0,4,50,1,50,153.18,0.32,0,sky130_fd_sc_hd,4,4
diff --git a/verilog/dv/risc_boot/risc_boot.c b/verilog/dv/risc_boot/risc_boot.c
index 1ceec26..dadfcab 100644
--- a/verilog/dv/risc_boot/risc_boot.c
+++ b/verilog/dv/risc_boot/risc_boot.c
@@ -20,7 +20,8 @@
#include "verilog/dv/caravel/stub.c"
// User Project Slaves (0x3000_0000)
-#define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
+
+#define reg_mprj_wbhost_reg0 (*(volatile uint32_t*)0x30800000)
#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x30000000)
#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x30000004)
@@ -167,6 +168,10 @@
/* Apply configuration */
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
+
+ // Remove Wishbone Reset
+ reg_mprj_wbhost_reg0 = 0x1;
+
// SDRAM Config-2
reg_mprj_globl_reg5 = 0x100019E;
@@ -174,8 +179,9 @@
// SDRAM Config-1
reg_mprj_globl_reg4 = 0x2F172242;
- // Wake Up CPU Core
- reg_mprj_globl_reg0 = 0x07;
+ // Remove All Reset
+ reg_mprj_wbhost_reg0 = 0xF;
+
// configure the user uart
reg_mprj_uart_reg0 = 0x7;
diff --git a/verilog/dv/user_risc_boot/Makefile b/verilog/dv/user_risc_boot/Makefile
index d2bccea..8c55f5e 100644
--- a/verilog/dv/user_risc_boot/Makefile
+++ b/verilog/dv/user_risc_boot/Makefile
@@ -54,12 +54,12 @@
vvp: ${PATTERN:=.vvp}
%.vvp: %_tb.v
- riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common user_uart.c -o user_uart.o
+ riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common user_risc_boot.c -o user_risc_boot.o
riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common/ ../../rtl/syntacore/scr1/sim/tests/common/crt_tcm.S -o crt_tcm.o
- riscv64-unknown-elf-gcc -o user_uart.elf -T ../../rtl/syntacore/scr1/sim/tests/common/link_tcm.ld user_uart.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32
- riscv64-unknown-elf-objcopy -O verilog user_uart.elf user_uart.hex
- riscv64-unknown-elf-objdump -D user_uart.elf > user_uart.dump
- rm crt_tcm.o user_uart.o
+ riscv64-unknown-elf-gcc -o user_risc_boot.elf -T ../../rtl/syntacore/scr1/sim/tests/common/link_tcm.ld user_risc_boot.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32
+ riscv64-unknown-elf-objcopy -O verilog user_risc_boot.elf user_risc_boot.hex
+ riscv64-unknown-elf-objdump -D user_risc_boot.elf > user_risc_boot.dump
+ rm crt_tcm.o user_risc_boot.o
ifeq ($(SIM),RTL)
iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
diff --git a/verilog/dv/user_risc_boot/run_iverilog b/verilog/dv/user_risc_boot/run_iverilog
index 1d8298d..d2520fa 100755
--- a/verilog/dv/user_risc_boot/run_iverilog
+++ b/verilog/dv/user_risc_boot/run_iverilog
@@ -11,7 +11,7 @@
rm crt_tcm.o user_risc_boot.o
#iverilog with waveform dump
-#iverilog -g2005-sv -DWFDUMP -I $PDK_PATH -I ../ -I ../../../verilog/rtl -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $$CARAVEL_ROOT/verilog/dv/caravel -I ../model user_risc_boot_tb.v -o user_risc_boot_tb.vvp
+#iverilog -g2005-sv -DWFDUMP -I $PDK_PATH -I ../ -I ../../../verilog/rtl -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model user_risc_boot_tb.v -o user_risc_boot_tb.vvp
iverilog -g2005-sv -I $PDK_PATH -I ../ -I ../../../verilog/rtl -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model user_risc_boot_tb.v -o user_risc_boot_tb.vvp
diff --git a/verilog/dv/user_risc_boot/uprj_netlists.v b/verilog/dv/user_risc_boot/uprj_netlists.v
index 598170e..1668caa 100644
--- a/verilog/dv/user_risc_boot/uprj_netlists.v
+++ b/verilog/dv/user_risc_boot/uprj_netlists.v
@@ -14,8 +14,58 @@
// SPDX-License-Identifier: Apache-2.0
// Include caravel global defines for the number of the user project IO pads
+`include "defines.v"
`define USE_POWER_PINS
+`ifdef GL
+ `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+ `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+ `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
+ `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
+
+ `include "digital_core/src/digital_core.sv"
+ `include "glbl_cfg.v"
+ `include "sdram.v"
+ `include "spi_master.v"
+ `include "uart.v"
+ `include "wb_interconnect.v"
+
+ `include "wb_host/src/wb_host.sv"
+ `include "lib/async_wb.sv"
+ `include "lib/registers.v"
+
+ `include "syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv"
+ `include "syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv"
+ `include "syntacore/scr1/src/core/pipeline/scr1_ipic.sv"
+ `include "syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv"
+ `include "syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv"
+ `include "syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv"
+ `include "syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv"
+ `include "syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv"
+ `include "syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv"
+ `include "syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv"
+ `include "syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv"
+ `include "syntacore/scr1/src/core/primitives/scr1_reset_cells.sv"
+ `include "syntacore/scr1/src/core/primitives/scr1_cg.sv"
+ `include "syntacore/scr1/src/core/scr1_clk_ctrl.sv"
+ `include "syntacore/scr1/src/core/scr1_tapc_shift_reg.sv"
+ `include "syntacore/scr1/src/core/scr1_tapc.sv"
+ `include "syntacore/scr1/src/core/scr1_tapc_synchronizer.sv"
+ `include "syntacore/scr1/src/core/scr1_core_top.sv"
+ `include "syntacore/scr1/src/core/scr1_dm.sv"
+ `include "syntacore/scr1/src/core/scr1_dmi.sv"
+ `include "syntacore/scr1/src/core/scr1_scu.sv"
+
+ `include "syntacore/scr1/src/top/scr1_dmem_router.sv"
+ `include "syntacore/scr1/src/top/scr1_dp_memory.sv"
+ `include "syntacore/scr1/src/top/scr1_tcm.sv"
+ `include "syntacore/scr1/src/top/scr1_timer.sv"
+ `include "syntacore/scr1/src/top/scr1_dmem_wb.sv"
+ `include "syntacore/scr1/src/top/scr1_imem_wb.sv"
+ `include "syntacore/scr1/src/top/scr1_top_wb.sv"
+ `include "lib/sync_fifo.sv"
+ `include "lib/async_fifo.sv"
+`else
`include "spi_master/src/spim_top.sv"
`include "spi_master/src/spim_regs.sv"
`include "spi_master/src/spim_clkgen.sv"
@@ -46,6 +96,9 @@
`include "digital_core/src/glbl_cfg.sv"
`include "digital_core/src/digital_core.sv"
+ `include "wb_host/src/wb_host.sv"
+ `include "lib/async_wb.sv"
+
`include "lib/wb_stagging.sv"
`include "wb_interconnect/src/wb_arb.sv"
`include "wb_interconnect/src/wb_interconnect.sv"
@@ -81,3 +134,6 @@
`include "syntacore/scr1/src/top/scr1_imem_wb.sv"
`include "syntacore/scr1/src/top/scr1_top_wb.sv"
`include "lib/sync_fifo.sv"
+
+ `include "user_project_wrapper.v"
+`endif
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
index ea56e6b..fa08ddc 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -54,7 +54,7 @@
`default_nettype none
-`timescale 1 ns / 1 ps
+`timescale 1 ns / 1 ns
`include "uprj_netlists.v"
`include "spiflash.v"
@@ -119,6 +119,9 @@
repeat (10) @(posedge clock);
$display("Monitor: Standalone User Risc Boot Test Started");
+ // Remove Wb Reset
+ wb_user_core_write('h3080_0000,'h1);
+
#1;
//------------ SDRAM Config - 2
wb_user_core_write('h3000_0014,'h100_019E);
@@ -131,7 +134,7 @@
repeat (2) @(posedge clock);
#1;
// Remove all the reset
- wb_user_core_write('h3000_0000,'h7);
+ wb_user_core_write('h3080_0000,'hF);
// Repeat cycles of 1000 clock edges as needed to complete testbench
@@ -194,33 +197,27 @@
#100;
wb_rst_i <= 1'b0; // Release reset
end
+wire USER_VDD1V8 = 1'b1;
+wire VSS = 1'b0;
-
- digital_core u_core(
+user_project_wrapper u_top(
`ifdef USE_POWER_PINS
- .vdda1(), // User area 1 3.3V supply
- .vdda2(), // User area 2 3.3V supply
- .vssa1(), // User area 1 analog ground
- .vssa2(), // User area 2 analog ground
- .vccd1(), // User area 1 1.8V supply
- .vccd2(), // User area 2 1.8v supply
- .vssd1(), // User area 1 digital ground
- .vssd2(), // User area 2 digital ground
+ .vccd1(USER_VDD1V8), // User area 1 1.8V supply
+ .vssd1(VSS), // User area 1 digital ground
`endif
.wb_clk_i (clock), // System clock
.user_clock2 (1'b1), // Real-time clock
.wb_rst_i (wb_rst_i), // Regular Reset signal
- .wbd_ext_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbd_ext_stb_i (wbd_ext_stb_i), // strobe/request
- .wbd_ext_adr_i (wbd_ext_adr_i), // address
- .wbd_ext_we_i (wbd_ext_we_i), // write
- .wbd_ext_dat_i (wbd_ext_dat_i), // data output
- .wbd_ext_sel_i (wbd_ext_sel_i), // byte enable
+ .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
+ .wbs_stb_i (wbd_ext_stb_i), // strobe/request
+ .wbs_adr_i (wbd_ext_adr_i), // address
+ .wbs_we_i (wbd_ext_we_i), // write
+ .wbs_dat_i (wbd_ext_dat_i), // data output
+ .wbs_sel_i (wbd_ext_sel_i), // byte enable
- .wbd_ext_dat_o (wbd_ext_dat_o), // data input
- .wbd_ext_ack_o (wbd_ext_ack_o), // acknowlegement
- .wbd_ext_err_o (wbd_ext_err_o), // error
+ .wbs_dat_o (wbd_ext_dat_o), // data input
+ .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
// Logic Analyzer Signals
@@ -320,6 +317,7 @@
input [31:0] data;
begin
repeat (1) @(posedge clock);
+ #1;
wbd_ext_adr_i =address; // address
wbd_ext_we_i ='h1; // write
wbd_ext_dat_i =data; // data output
@@ -328,6 +326,7 @@
wbd_ext_stb_i ='h1; // strobe/request
wait(wbd_ext_ack_o == 1);
repeat (1) @(posedge clock);
+ #1;
wbd_ext_cyc_i ='h0; // strobe/request
wbd_ext_stb_i ='h0; // strobe/request
wbd_ext_adr_i ='h0; // address
@@ -345,6 +344,7 @@
reg [31:0] data;
begin
repeat (1) @(posedge clock);
+ #1;
wbd_ext_adr_i =address; // address
wbd_ext_we_i ='h0; // write
wbd_ext_dat_i ='0; // data output
@@ -354,6 +354,7 @@
wait(wbd_ext_ack_o == 1);
data = wbd_ext_dat_o;
repeat (1) @(posedge clock);
+ #1;
wbd_ext_cyc_i ='h0; // strobe/request
wbd_ext_stb_i ='h0; // strobe/request
wbd_ext_adr_i ='h0; // address
@@ -368,30 +369,22 @@
-////-----------------------------------------------------------------------------
-//// RISC IMEM amd DMEM Monitoring TASK
-////-----------------------------------------------------------------------------
-//logic [`SCR1_DMEM_AWIDTH-1:0] core2imem_addr_o_r; // DMEM address
-//logic [`SCR1_DMEM_AWIDTH-1:0] core2dmem_addr_o_r; // DMEM address
-//logic core2dmem_cmd_o_r;
-//
-//`define RISC_CORE user_risc_boot_tb.u_core.u_riscv_top.i_core_top
-//
-//always@(posedge `RISC_CORE.clk) begin
-// if(`RISC_CORE.imem2core_req_ack_i && `RISC_CORE.core2imem_req_o)
-// core2imem_addr_o_r <= `RISC_CORE.core2imem_addr_o;
-//
-// if(`RISC_CORE.dmem2core_req_ack_i && `RISC_CORE.core2dmem_req_o) begin
-// core2dmem_addr_o_r <= `RISC_CORE.core2dmem_addr_o;
-// core2dmem_cmd_o_r <= `RISC_CORE.core2dmem_cmd_o;
-// end
-//
-// if(`RISC_CORE.imem2core_resp_i !=0)
-// $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x Resonse: %x", core2imem_addr_o_r,`RISC_CORE.imem2core_rdata_i,`RISC_CORE.imem2core_resp_i);
-// if((`RISC_CORE.dmem2core_resp_i !=0) && core2dmem_cmd_o_r)
-// $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", core2dmem_addr_o_r,`RISC_CORE.core2dmem_wdata_o,`RISC_CORE.dmem2core_resp_i);
-// if((`RISC_CORE.dmem2core_resp_i !=0) && !core2dmem_cmd_o_r)
-// $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", core2dmem_addr_o_r,`RISC_CORE.dmem2core_rdata_i,`RISC_CORE.dmem2core_resp_i);
-//end
+`ifdef GL
+//-----------------------------------------------------------------------------
+// RISC IMEM amd DMEM Monitoring TASK
+//-----------------------------------------------------------------------------
+
+`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
+
+always@(posedge `RISC_CORE.wb_clk) begin
+ if(`RISC_CORE.wbd_imem_ack_i)
+ $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
+ if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
+ $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
+ if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
+ $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
+end
+
+`endif
endmodule
`default_nettype wire
diff --git a/verilog/dv/user_uart/run_iverilog b/verilog/dv/user_uart/run_iverilog
index af95096..1badece 100755
--- a/verilog/dv/user_uart/run_iverilog
+++ b/verilog/dv/user_uart/run_iverilog
@@ -11,13 +11,13 @@
rm crt_tcm.o user_uart.o
#iverilog with waveform dump
-#iverilog -g2005-sv -DWFDUMP -I $PDK_PATH -I ../ -I ../../../verilog/rtl -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_uart_tb.vvp
+iverilog -g2005-sv -DWFDUMP -I $PDK_PATH -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/rtl -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_uart_tb.vvp
-iverilog -g2005-sv -I $PDK_PATH -I ../ -I ../../../verilog/rtl -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_uart_tb.vvp
+#iverilog -g2005-sv -I $PDK_PATH -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/rtl -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_uart_tb.vvp
# GLS
-#iverilog -g2005-sv -DGL -I $PDK_PATH -I ../../gl -I ../ -I ../../../verilog/rtl -I /home/dinesha/workarea/pdk/sky130A -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_uart_tb.vvp
+#iverilog -g2005-sv -DGL -I $PDK_PATH -I ../../../caravel/verilog/rtl -I ../../gl -I ../ -I ../../../verilog/rtl -I /home/dinesha/workarea/pdk/sky130A -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_uart_tb.vvp
vvp user_uart_tb.vvp | tee test.log
diff --git a/verilog/dv/user_uart/uprj_netlists.v b/verilog/dv/user_uart/uprj_netlists.v
index 5572f55..1668caa 100644
--- a/verilog/dv/user_uart/uprj_netlists.v
+++ b/verilog/dv/user_uart/uprj_netlists.v
@@ -14,6 +14,7 @@
// SPDX-License-Identifier: Apache-2.0
// Include caravel global defines for the number of the user project IO pads
+`include "defines.v"
`define USE_POWER_PINS
`ifdef GL
@@ -26,9 +27,44 @@
`include "glbl_cfg.v"
`include "sdram.v"
`include "spi_master.v"
- `include "syntacore.v"
`include "uart.v"
`include "wb_interconnect.v"
+
+ `include "wb_host/src/wb_host.sv"
+ `include "lib/async_wb.sv"
+ `include "lib/registers.v"
+
+ `include "syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv"
+ `include "syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv"
+ `include "syntacore/scr1/src/core/pipeline/scr1_ipic.sv"
+ `include "syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv"
+ `include "syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv"
+ `include "syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv"
+ `include "syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv"
+ `include "syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv"
+ `include "syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv"
+ `include "syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv"
+ `include "syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv"
+ `include "syntacore/scr1/src/core/primitives/scr1_reset_cells.sv"
+ `include "syntacore/scr1/src/core/primitives/scr1_cg.sv"
+ `include "syntacore/scr1/src/core/scr1_clk_ctrl.sv"
+ `include "syntacore/scr1/src/core/scr1_tapc_shift_reg.sv"
+ `include "syntacore/scr1/src/core/scr1_tapc.sv"
+ `include "syntacore/scr1/src/core/scr1_tapc_synchronizer.sv"
+ `include "syntacore/scr1/src/core/scr1_core_top.sv"
+ `include "syntacore/scr1/src/core/scr1_dm.sv"
+ `include "syntacore/scr1/src/core/scr1_dmi.sv"
+ `include "syntacore/scr1/src/core/scr1_scu.sv"
+
+ `include "syntacore/scr1/src/top/scr1_dmem_router.sv"
+ `include "syntacore/scr1/src/top/scr1_dp_memory.sv"
+ `include "syntacore/scr1/src/top/scr1_tcm.sv"
+ `include "syntacore/scr1/src/top/scr1_timer.sv"
+ `include "syntacore/scr1/src/top/scr1_dmem_wb.sv"
+ `include "syntacore/scr1/src/top/scr1_imem_wb.sv"
+ `include "syntacore/scr1/src/top/scr1_top_wb.sv"
+ `include "lib/sync_fifo.sv"
+ `include "lib/async_fifo.sv"
`else
`include "spi_master/src/spim_top.sv"
`include "spi_master/src/spim_regs.sv"
@@ -60,6 +96,9 @@
`include "digital_core/src/glbl_cfg.sv"
`include "digital_core/src/digital_core.sv"
+ `include "wb_host/src/wb_host.sv"
+ `include "lib/async_wb.sv"
+
`include "lib/wb_stagging.sv"
`include "wb_interconnect/src/wb_arb.sv"
`include "wb_interconnect/src/wb_interconnect.sv"
@@ -95,4 +134,6 @@
`include "syntacore/scr1/src/top/scr1_imem_wb.sv"
`include "syntacore/scr1/src/top/scr1_top_wb.sv"
`include "lib/sync_fifo.sv"
+
+ `include "user_project_wrapper.v"
`endif
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index fbb254e..5a647ba 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -132,7 +132,8 @@
`ifdef WFDUMP
initial begin
$dumpfile("risc_boot.vcd");
- $dumpvars(4, user_uart_tb);
+ $dumpvars(2, user_uart_tb);
+ $dumpvars(4, user_uart_tb.u_top.u_core);
end
`endif
@@ -156,6 +157,9 @@
repeat (10) @(posedge clock);
$display("Monitor: Standalone User Uart Test Started");
+ // Remove Wb Reset
+ wb_user_core_write('h3080_0000,'h1);
+
#1;
//------------ SDRAM Config - 2
wb_user_core_write('h3000_0014,'h100_019E);
@@ -168,7 +172,7 @@
repeat (2) @(posedge clock);
#1;
// Remove all the reset
- wb_user_core_write('h3000_0000,'h7);
+ wb_user_core_write('h3080_0000,'hF);
repeat (20000) @(posedge clock); // wait for Processor Get Ready
tb_uart.uart_init;
@@ -232,31 +236,28 @@
end
-digital_core u_core(
+wire USER_VDD1V8 = 1'b1;
+wire VSS = 1'b0;
+
+
+user_project_wrapper u_top(
`ifdef USE_POWER_PINS
- .vdda1(), // User area 1 3.3V supply
- .vdda2(), // User area 2 3.3V supply
- .vssa1(), // User area 1 analog ground
- .vssa2(), // User area 2 analog ground
- .vccd1(), // User area 1 1.8V supply
- .vccd2(), // User area 2 1.8v supply
- .vssd1(), // User area 1 digital ground
- .vssd2(), // User area 2 digital ground
+ .vccd1(USER_VDD1V8), // User area 1 1.8V supply
+ .vssd1(VSS), // User area 1 digital ground
`endif
.wb_clk_i (clock), // System clock
.user_clock2 (1'b1), // Real-time clock
.wb_rst_i (wb_rst_i), // Regular Reset signal
- .wbd_ext_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbd_ext_stb_i (wbd_ext_stb_i), // strobe/request
- .wbd_ext_adr_i (wbd_ext_adr_i), // address
- .wbd_ext_we_i (wbd_ext_we_i), // write
- .wbd_ext_dat_i (wbd_ext_dat_i), // data output
- .wbd_ext_sel_i (wbd_ext_sel_i), // byte enable
+ .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
+ .wbs_stb_i (wbd_ext_stb_i), // strobe/request
+ .wbs_adr_i (wbd_ext_adr_i), // address
+ .wbs_we_i (wbd_ext_we_i), // write
+ .wbs_dat_i (wbd_ext_dat_i), // data output
+ .wbs_sel_i (wbd_ext_sel_i), // byte enable
- .wbd_ext_dat_o (wbd_ext_dat_o), // data input
- .wbd_ext_ack_o (wbd_ext_ack_o), // acknowlegement
- .wbd_ext_err_o (wbd_ext_err_o), // error
+ .wbs_dat_o (wbd_ext_dat_o), // data input
+ .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
// Logic Analyzer Signals
@@ -371,6 +372,7 @@
input [31:0] data;
begin
repeat (1) @(posedge clock);
+ #1;
wbd_ext_adr_i =address; // address
wbd_ext_we_i ='h1; // write
wbd_ext_dat_i =data; // data output
@@ -379,6 +381,7 @@
wbd_ext_stb_i ='h1; // strobe/request
wait(wbd_ext_ack_o == 1);
repeat (1) @(posedge clock);
+ #1;
wbd_ext_cyc_i ='h0; // strobe/request
wbd_ext_stb_i ='h0; // strobe/request
wbd_ext_adr_i ='h0; // address
@@ -396,6 +399,7 @@
reg [31:0] data;
begin
repeat (1) @(posedge clock);
+ #1;
wbd_ext_adr_i =address; // address
wbd_ext_we_i ='h0; // write
wbd_ext_dat_i ='0; // data output
@@ -405,6 +409,7 @@
wait(wbd_ext_ack_o == 1);
data = wbd_ext_dat_o;
repeat (1) @(posedge clock);
+ #1;
wbd_ext_cyc_i ='h0; // strobe/request
wbd_ext_stb_i ='h0; // strobe/request
wbd_ext_adr_i ='h0; // address
@@ -419,30 +424,22 @@
-////-----------------------------------------------------------------------------
-//// RISC IMEM amd DMEM Monitoring TASK
-////-----------------------------------------------------------------------------
-//logic [`SCR1_DMEM_AWIDTH-1:0] core2imem_addr_o_r; // DMEM address
-//logic [`SCR1_DMEM_AWIDTH-1:0] core2dmem_addr_o_r; // DMEM address
-//logic core2dmem_cmd_o_r;
-//
-//`define RISC_CORE user_uart_tb.u_core.u_riscv_top.i_core_top
-//
-//always@(posedge `RISC_CORE.clk) begin
-// if(`RISC_CORE.imem2core_req_ack_i && `RISC_CORE.core2imem_req_o)
-// core2imem_addr_o_r <= `RISC_CORE.core2imem_addr_o;
-//
-// if(`RISC_CORE.dmem2core_req_ack_i && `RISC_CORE.core2dmem_req_o) begin
-// core2dmem_addr_o_r <= `RISC_CORE.core2dmem_addr_o;
-// core2dmem_cmd_o_r <= `RISC_CORE.core2dmem_cmd_o;
-// end
-//
-// if(`RISC_CORE.imem2core_resp_i !=0)
-// $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x Resonse: %x", core2imem_addr_o_r,`RISC_CORE.imem2core_rdata_i,`RISC_CORE.imem2core_resp_i);
-// if((`RISC_CORE.dmem2core_resp_i !=0) && core2dmem_cmd_o_r)
-// $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", core2dmem_addr_o_r,`RISC_CORE.core2dmem_wdata_o,`RISC_CORE.dmem2core_resp_i);
-// if((`RISC_CORE.dmem2core_resp_i !=0) && !core2dmem_cmd_o_r)
-// $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", core2dmem_addr_o_r,`RISC_CORE.dmem2core_rdata_i,`RISC_CORE.dmem2core_resp_i);
-//end
+`ifdef GL
+//-----------------------------------------------------------------------------
+// RISC IMEM amd DMEM Monitoring TASK
+//-----------------------------------------------------------------------------
+
+`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
+
+always@(posedge `RISC_CORE.wb_clk) begin
+ if(`RISC_CORE.wbd_imem_ack_i)
+ $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
+ if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
+ $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
+ if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
+ $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
+end
+
+`endif
endmodule
`default_nettype wire
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c
index 079d1ef..684f275 100644
--- a/verilog/dv/wb_port/wb_port.c
+++ b/verilog/dv/wb_port/wb_port.c
@@ -22,6 +22,7 @@
// User Project Slaves (0x3000_0000)
#define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
+#define reg_mprj_wbhost_reg0 (*(volatile uint32_t*)0x30800000)
#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x30000000)
#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x30000004)
#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x30000008)
@@ -102,6 +103,9 @@
// Flag start of the test
reg_mprj_datal = 0xAB600000;
+ // Remove Wishbone Reset
+ reg_mprj_wbhost_reg0 = 0x1;
+
if (reg_mprj_globl_reg1 != 0xA55AA55A) bFail = 1;
if (reg_mprj_globl_reg2 != 0xAABBCCDD) bFail = 1;
diff --git a/verilog/rtl/digital_core/src/digital_core.sv b/verilog/rtl/digital_core/src/digital_core.sv
index d80af75..7e76212 100644
--- a/verilog/rtl/digital_core/src/digital_core.sv
+++ b/verilog/rtl/digital_core/src/digital_core.sv
@@ -43,6 +43,22 @@
//// 0.3 - 20th June 2021, Dinesh A ////
//// 1. uart core is integrated ////
//// 2. 3rd Slave ported added to wishbone interconnect ////
+//// 0.4 - 25th June 2021, Dinesh A ////
+//// Moved the pad logic inside sdram,spi,uart block to ////
+//// avoid logic at digital core level ////
+//// 0.5 - 25th June 2021, Dinesh A ////
+//// Since carvel gives only 16MB address space for user ////
+//// space, we have implemented indirect address select ////
+//// with 8 bit bank select given inside wb_host ////
+//// core Address = {Bank_Sel[7:0], Wb_Address[23:0] ////
+//// caravel user address space is ////
+//// 0x3000_0000 to 0x30FF_FFFF ////
+//// 0.6 - 27th June 2021, Dinesh A ////
+//// Digital core level tie are moved inside IP to avoid ////
+//// power hook up at core level ////
+//// u_risc_top - test_mode & test_rst_n ////
+//// u_intercon - s*_wbd_err_i ////
+//// unused wb_cti_i is removed from u_sdram_ctrl ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
@@ -71,12 +87,7 @@
//// ////
//////////////////////////////////////////////////////////////////////
-`include "scr1_arch_description.svh"
-`ifdef SCR1_IPIC_EN
-`include "scr1_ipic.svh"
-`endif // SCR1_IPIC_EN
-`include "sdrc_define.v"
module digital_core
#(
parameter SDR_DW = 8, // SDR Data Width
@@ -87,33 +98,32 @@
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
- input logic wb_clk_i , // System clock
- input logic user_clock2 , // user Clock
- input logic wb_rst_i , // Regular Reset signal
+ input wire wb_clk_i , // System clock
+ input wire user_clock2 , // user Clock
+ input wire wb_rst_i , // Regular Reset signal
- input logic wbd_ext_cyc_i , // strobe/request
- input logic wbd_ext_stb_i , // strobe/request
- input logic [WB_WIDTH-1:0] wbd_ext_adr_i , // address
- input logic wbd_ext_we_i , // write
- input logic [WB_WIDTH-1:0] wbd_ext_dat_i , // data output
- input logic [3:0] wbd_ext_sel_i , // byte enable
- output logic [WB_WIDTH-1:0] wbd_ext_dat_o , // data input
- output logic wbd_ext_ack_o , // acknowlegement
- output logic wbd_ext_err_o , // error
+ input wire wbd_ext_cyc_i , // strobe/request
+ input wire wbd_ext_stb_i , // strobe/request
+ input wire [WB_WIDTH-1:0] wbd_ext_adr_i , // address
+ input wire wbd_ext_we_i , // write
+ input wire [WB_WIDTH-1:0] wbd_ext_dat_i , // data output
+ input wire [3:0] wbd_ext_sel_i , // byte enable
+ output wire [WB_WIDTH-1:0] wbd_ext_dat_o , // data input
+ output wire wbd_ext_ack_o , // acknowlegement
// Logic Analyzer Signals
- input logic [127:0] la_data_in ,
- output logic [127:0] la_data_out ,
- input logic [127:0] la_oenb ,
+ input wire [127:0] la_data_in ,
+ output wire [127:0] la_data_out ,
+ input wire [127:0] la_oenb ,
// IOs
- input logic [37:0] io_in ,
- output logic [37:0] io_out ,
- output logic [37:0] io_oeb ,
+ input wire [37:0] io_in ,
+ output wire [37:0] io_out ,
+ output wire [37:0] io_oeb ,
- output logic [2:0] user_irq
+ output wire [2:0] user_irq
);
@@ -125,208 +135,181 @@
//---------------------------------------------------------------------
// Wishbone Risc V Instruction Memory Interface
//---------------------------------------------------------------------
-logic wbd_riscv_imem_stb_i; // strobe/request
-logic [WB_WIDTH-1:0] wbd_riscv_imem_adr_i; // address
-logic wbd_riscv_imem_we_i; // write
-logic [WB_WIDTH-1:0] wbd_riscv_imem_dat_i; // data output
-logic [3:0] wbd_riscv_imem_sel_i; // byte enable
-logic [WB_WIDTH-1:0] wbd_riscv_imem_dat_o; // data input
-logic wbd_riscv_imem_ack_o; // acknowlegement
-logic wbd_riscv_imem_err_o; // error
+wire wbd_riscv_imem_stb_i; // strobe/request
+wire [WB_WIDTH-1:0] wbd_riscv_imem_adr_i; // address
+wire wbd_riscv_imem_we_i; // write
+wire [WB_WIDTH-1:0] wbd_riscv_imem_dat_i; // data output
+wire [3:0] wbd_riscv_imem_sel_i; // byte enable
+wire [WB_WIDTH-1:0] wbd_riscv_imem_dat_o; // data input
+wire wbd_riscv_imem_ack_o; // acknowlegement
+wire wbd_riscv_imem_err_o; // error
//---------------------------------------------------------------------
// RISC V Wishbone Data Memory Interface
//---------------------------------------------------------------------
-logic wbd_riscv_dmem_stb_i; // strobe/request
-logic [WB_WIDTH-1:0] wbd_riscv_dmem_adr_i; // address
-logic wbd_riscv_dmem_we_i; // write
-logic [WB_WIDTH-1:0] wbd_riscv_dmem_dat_i; // data output
-logic [3:0] wbd_riscv_dmem_sel_i; // byte enable
-logic [WB_WIDTH-1:0] wbd_riscv_dmem_dat_o; // data input
-logic wbd_riscv_dmem_ack_o; // acknowlegement
-logic wbd_riscv_dmem_err_o; // error
+wire wbd_riscv_dmem_stb_i; // strobe/request
+wire [WB_WIDTH-1:0] wbd_riscv_dmem_adr_i; // address
+wire wbd_riscv_dmem_we_i; // write
+wire [WB_WIDTH-1:0] wbd_riscv_dmem_dat_i; // data output
+wire [3:0] wbd_riscv_dmem_sel_i; // byte enable
+wire [WB_WIDTH-1:0] wbd_riscv_dmem_dat_o; // data input
+wire wbd_riscv_dmem_ack_o; // acknowlegement
+wire wbd_riscv_dmem_err_o; // error
+
+//---------------------------------------------------------------------
+// WB HOST Interface
+//---------------------------------------------------------------------
+wire wbd_int_cyc_i; // strobe/request
+wire wbd_int_stb_i; // strobe/request
+wire [WB_WIDTH-1:0] wbd_int_adr_i; // address
+wire wbd_int_we_i; // write
+wire [WB_WIDTH-1:0] wbd_int_dat_i; // data output
+wire [3:0] wbd_int_sel_i; // byte enable
+wire [WB_WIDTH-1:0] wbd_int_dat_o; // data input
+wire wbd_int_ack_o; // acknowlegement
+wire wbd_int_err_o; // error
+//---------------------------------------------------------------------
+// SPI Master Wishbone Interface
+//---------------------------------------------------------------------
+wire wbd_spim_stb_o; // strobe/request
+wire [WB_WIDTH-1:0] wbd_spim_adr_o; // address
+wire wbd_spim_we_o; // write
+wire [WB_WIDTH-1:0] wbd_spim_dat_o; // data output
+wire [3:0] wbd_spim_sel_o; // byte enable
+wire wbd_spim_cyc_o ;
+wire [WB_WIDTH-1:0] wbd_spim_dat_i; // data input
+wire wbd_spim_ack_i; // acknowlegement
+wire wbd_spim_err_i; // error
//---------------------------------------------------------------------
// SPI Master Wishbone Interface
//---------------------------------------------------------------------
-logic wbd_spim_stb_o; // strobe/request
-logic [WB_WIDTH-1:0] wbd_spim_adr_o; // address
-logic wbd_spim_we_o; // write
-logic [WB_WIDTH-1:0] wbd_spim_dat_o; // data output
-logic [3:0] wbd_spim_sel_o; // byte enable
-logic wbd_spim_cyc_o ;
-logic [WB_WIDTH-1:0] wbd_spim_dat_i; // data input
-logic wbd_spim_ack_i; // acknowlegement
-logic wbd_spim_err_i; // error
-
-//---------------------------------------------------------------------
-// SPI Master Wishbone Interface
-//---------------------------------------------------------------------
-logic wbd_sdram_stb_o ;
-logic [WB_WIDTH-1:0] wbd_sdram_adr_o ;
-logic wbd_sdram_we_o ; // 1 - Write, 0 - Read
-logic [WB_WIDTH-1:0] wbd_sdram_dat_o ;
-logic [WB_WIDTH/8-1:0] wbd_sdram_sel_o ; // Byte enable
-logic wbd_sdram_cyc_o ;
-logic [2:0] wbd_sdram_cti_o ;
-logic [WB_WIDTH-1:0] wbd_sdram_dat_i ;
-logic wbd_sdram_ack_i ;
+wire wbd_sdram_stb_o ;
+wire [WB_WIDTH-1:0] wbd_sdram_adr_o ;
+wire wbd_sdram_we_o ; // 1 - Write, 0 - Read
+wire [WB_WIDTH-1:0] wbd_sdram_dat_o ;
+wire [WB_WIDTH/8-1:0] wbd_sdram_sel_o ; // Byte enable
+wire wbd_sdram_cyc_o ;
+wire [2:0] wbd_sdram_cti_o ;
+wire [WB_WIDTH-1:0] wbd_sdram_dat_i ;
+wire wbd_sdram_ack_i ;
//---------------------------------------------------------------------
// Global Register Wishbone Interface
//---------------------------------------------------------------------
-logic wbd_glbl_stb_o; // strobe/request
-logic [7:0] wbd_glbl_adr_o; // address
-logic wbd_glbl_we_o; // write
-logic [WB_WIDTH-1:0] wbd_glbl_dat_o; // data output
-logic [3:0] wbd_glbl_sel_o; // byte enable
-logic wbd_glbl_cyc_o ;
-logic [WB_WIDTH-1:0] wbd_glbl_dat_i; // data input
-logic wbd_glbl_ack_i; // acknowlegement
-logic wbd_glbl_err_i; // error
+wire wbd_glbl_stb_o; // strobe/request
+wire [7:0] wbd_glbl_adr_o; // address
+wire wbd_glbl_we_o; // write
+wire [WB_WIDTH-1:0] wbd_glbl_dat_o; // data output
+wire [3:0] wbd_glbl_sel_o; // byte enable
+wire wbd_glbl_cyc_o ;
+wire [WB_WIDTH-1:0] wbd_glbl_dat_i; // data input
+wire wbd_glbl_ack_i; // acknowlegement
+wire wbd_glbl_err_i; // error
//---------------------------------------------------------------------
// Global Register Wishbone Interface
//---------------------------------------------------------------------
-logic wbd_uart_stb_o; // strobe/request
-logic [7:0] wbd_uart_adr_o; // address
-logic wbd_uart_we_o; // write
-logic [7:0] wbd_uart_dat_o; // data output
-logic wbd_uart_sel_o; // byte enable
-logic wbd_uart_cyc_o ;
-logic [7:0] wbd_uart_dat_i; // data input
-logic wbd_uart_ack_i; // acknowlegement
-logic wbd_uart_err_i; // error
+wire wbd_uart_stb_o; // strobe/request
+wire [7:0] wbd_uart_adr_o; // address
+wire wbd_uart_we_o; // write
+wire [7:0] wbd_uart_dat_o; // data output
+wire wbd_uart_sel_o; // byte enable
+wire wbd_uart_cyc_o ;
+wire [7:0] wbd_uart_dat_i; // data input
+wire wbd_uart_ack_i; // acknowlegement
+wire wbd_uart_err_i; // error
//----------------------------------------------------
// CPU Configuration
//----------------------------------------------------
-logic cpu_rst_n ;
-logic spi_rst_n ;
-logic sdram_rst_n ;
-logic cpu_clk ;
-logic rtc_clk ;
+wire cpu_rst_n ;
+wire spi_rst_n ;
+wire sdram_rst_n ;
+wire sdram_clk ;
+wire cpu_clk ;
+wire rtc_clk ;
+wire wbd_clk_int ;
+wire wbd_int_rst_n ;
-logic [31:0] fuse_mhartid ;
-logic [15:0] irq_lines ;
-logic soft_irq ;
+wire [31:0] fuse_mhartid ;
+wire [15:0] irq_lines ;
+wire soft_irq ;
+
+wire [7:0] cfg_glb_ctrl ;
+wire [31:0] cfg_clk_ctrl1 ;
+wire [31:0] cfg_clk_ctrl2 ;
//------------------------------------------------
// Configuration Parameter
//------------------------------------------------
-logic [1:0] cfg_sdr_width ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
-logic [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address,
-logic sdr_init_done ; // Indicate SDRAM Initialisation Done
-logic [3:0] cfg_sdr_tras_d ; // Active to precharge delay
-logic [3:0] cfg_sdr_trp_d ; // Precharge to active delay
-logic [3:0] cfg_sdr_trcd_d ; // Active to R/W delay
-logic cfg_sdr_en ; // Enable SDRAM controller
-logic [1:0] cfg_req_depth ; // Maximum Request accepted by SDRAM controller
-logic [12:0] cfg_sdr_mode_reg ;
-logic [2:0] cfg_sdr_cas ; // SDRAM CAS Latency
-logic [3:0] cfg_sdr_trcar_d ; // Auto-refresh period
-logic [3:0] cfg_sdr_twr_d ; // Write recovery delay
-logic [`SDR_RFSH_TIMER_W-1 : 0] cfg_sdr_rfsh ;
-logic [`SDR_RFSH_ROW_CNT_W -1 : 0] cfg_sdr_rfmax ;
-
-//----------------------------------------------------------------------
-// Interface to SDRAMs
-//--------------------------------------------------------------------------
-logic sdr_cke ; // SDRAM CKE
-logic sdr_cs_n ; // SDRAM Chip Select
-logic sdr_ras_n ; // SDRAM ras
-logic sdr_cas_n ; // SDRAM cas
-logic sdr_we_n ; // SDRAM write enable
-logic [SDR_BW-1:0] sdr_dqm ; // SDRAM Data Mask
-logic [1:0] sdr_ba ; // SDRAM Bank Enable
-logic [12:0] sdr_addr ; // SDRAM Address
-logic [SDR_DW-1:0] pad_sdr_din ; // SDRA Data Input
-logic [SDR_DW-1:0] sdr_dout ; // SDRA Data output
-logic [SDR_BW-1:0] sdr_den_n ; // SDRAM Data Output enable
-logic sdram_clk ; // Sdram clock loop back from pad
-logic pad_sdram_clk ; // Sdram clock loop back from pad
+wire [1:0] cfg_sdr_width ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
+wire [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address,
+wire sdr_init_done ; // Indicate SDRAM Initialisation Done
+wire [3:0] cfg_sdr_tras_d ; // Active to precharge delay
+wire [3:0] cfg_sdr_trp_d ; // Precharge to active delay
+wire [3:0] cfg_sdr_trcd_d ; // Active to R/W delay
+wire cfg_sdr_en ; // Enable SDRAM controller
+wire [1:0] cfg_req_depth ; // Maximum Request accepted by SDRAM controller
+wire [12:0] cfg_sdr_mode_reg ;
+wire [2:0] cfg_sdr_cas ; // SDRAM CAS Latency
+wire [3:0] cfg_sdr_trcar_d ; // Auto-refresh period
+wire [3:0] cfg_sdr_twr_d ; // Write recovery delay
+wire [11: 0] cfg_sdr_rfsh ;
+wire [2 : 0] cfg_sdr_rfmax ;
-assign pad_sdr_din[7:0] = io_in[7:0] ;
-assign io_out [7:0] = sdr_dout[7:0] ;
-assign io_out [20:8] = sdr_addr[12:0] ;
-assign io_out [22:21] = sdr_ba[1:0] ;
-assign io_out [23] = sdr_dqm[0] ;
-assign io_out [24] = sdr_we_n ;
-assign io_out [25] = sdr_cas_n ;
-assign io_out [26] = sdr_ras_n ;
-assign io_out [27] = sdr_cs_n ;
-assign io_out [28] = sdr_cke ;
-assign io_out [29] = sdram_clk ;
-assign pad_sdram_clk = io_in[29] ;
-
-assign io_oeb [7:0] = sdr_den_n ;
-assign io_oeb [20:8] = {(13) {1'b0}} ;
-assign io_oeb [22:21] = {(2) {1'b0}} ;
-assign io_oeb [23] = 1'b0 ;
-assign io_oeb [24] = 1'b0 ;
-assign io_oeb [25] = 1'b0 ;
-assign io_oeb [26] = 1'b0 ;
-assign io_oeb [27] = 1'b0 ;
-assign io_oeb [28] = 1'b0 ;
-assign io_oeb [29] = 1'b0 ;
-
-
-
-//-----------------------------------------------------------
-// SPI I/F
-// ////////////////////////////////////////////////////
-logic spim_sdo0 ; // SPI Master Data Out[0]
-logic spim_sdo1 ; // SPI Master Data Out[1]
-logic spim_sdo2 ; // SPI Master Data Out[2]
-logic spim_sdo3 ; // SPI Master Data Out[3]
-logic spim_sdi0 ; // SPI Master Data In[0]
-logic spim_sdi1 ; // SPI Master Data In[1]
-logic spim_sdi2 ; // SPI Master Data In[2]
-logic spim_sdi3 ; // SPI Master Data In[3]
-logic spim_clk ;
-logic spim_csn ;
-logic spi_en_tx ;
-
-assign spim_sdi0 = io_in[32];
-assign spim_sdi1 = io_in[33];
-assign spim_sdi2 = io_in[34];
-assign spim_sdi3 = io_in[35];
-
-assign io_out[30] = spim_clk;
-assign io_out[31] = spim_csn;
-assign io_out[32] = spim_sdo0;
-assign io_out[33] = spim_sdo1;
-assign io_out[34] = spim_sdo2;
-assign io_out[35] = spim_sdo3;
-
-assign io_oeb[30] = 1'b0; // spi_clk
-assign io_oeb[31] = 1'b0; // spi_csn
-assign io_oeb[32] = !spi_en_tx; // spi_dio0
-assign io_oeb[33] = !spi_en_tx; // spi_dio1
-assign io_oeb[34] = !spi_en_tx; // spi_dio2
-assign io_oeb[35] = !spi_en_tx; // spi_dio3
-
-/////////////////////////////////////////////////////////
-// uart interface
-///////////////////////////////////////////////////////
-
-logic uart_rx ;
-logic uart_tx ;
-
-// for uart
-assign io_oeb[36] = 1'b1; // Uart RX
-assign uart_rx = io_in[36];
-
-assign io_oeb[37] = 1'b0; // Uart TX
-assign io_out[37] = uart_tx;
/////////////////////////////////////////////////////////
// Generating acive low wishbone reset
// //////////////////////////////////////////////////////
-wire wb_rst_n = !wb_rst_i;
+assign wbd_int_rst_n = cfg_glb_ctrl[0];
+assign cpu_rst_n = cfg_glb_ctrl[1];
+assign spi_rst_n = cfg_glb_ctrl[2];
+assign sdram_rst_n = cfg_glb_ctrl[3];
+
+
+
+wb_host u_wb_host(
+
+ // Master Port
+ .wbm_rst_i (wb_rst_i ),
+ .wbm_clk_i (wb_clk_i ),
+ .wbm_cyc_i (wbd_ext_cyc_i ),
+ .wbm_stb_i (wbd_ext_stb_i ),
+ .wbm_adr_i (wbd_ext_adr_i ),
+ .wbm_we_i (wbd_ext_we_i ),
+ .wbm_dat_i (wbd_ext_dat_i ),
+ .wbm_sel_i (wbd_ext_sel_i ),
+ .wbm_dat_o (wbd_ext_dat_o ),
+ .wbm_ack_o (wbd_ext_ack_o ),
+ .wbm_err_o ( ),
+
+ // Slave Port
+ .wbs_clk_i (wbd_clk_int ),
+ .wbs_cyc_o (wbd_int_cyc_i ),
+ .wbs_stb_o (wbd_int_stb_i ),
+ .wbs_adr_o (wbd_int_adr_i ),
+ .wbs_we_o (wbd_int_we_i ),
+ .wbs_dat_o (wbd_int_dat_i ),
+ .wbs_sel_o (wbd_int_sel_i ),
+ .wbs_dat_i (wbd_int_dat_o ),
+ .wbs_ack_i (wbd_int_ack_o ),
+ .wbs_err_i (wbd_int_err_o ),
+
+ .cfg_glb_ctrl (cfg_glb_ctrl ),
+ .cfg_clk_ctrl1 (cfg_clk_ctrl1 ),
+ .cfg_clk_ctrl2 (cfg_clk_ctrl2 ),
+
+ // Logic Analyzer Signals
+ .la_data_in (la_data_in ),
+ .la_data_out (la_data_out ),
+ .la_oenb (la_oenb )
+ );
+
+
//------------------------------------------------------------------------------
@@ -334,13 +317,9 @@
//------------------------------------------------------------------------------
scr1_top_wb u_riscv_top (
// Reset
- .pwrup_rst_n (wb_rst_n ),
- .rst_n (wb_rst_n ),
+ .pwrup_rst_n (wbd_int_rst_n ),
+ .rst_n (wbd_int_rst_n ),
.cpu_rst_n (cpu_rst_n ),
-`ifdef SCR1_DBG_EN
- .sys_rst_n_o (sys_rst_n_o ),
- .sys_rdc_qlfy_o (sys_rdc_qlfy_o ),
-`endif // SCR1_DBG_EN
// Clock
.core_clk (cpu_clk ),
@@ -348,35 +327,18 @@
// Fuses
.fuse_mhartid (fuse_mhartid ),
-`ifdef SCR1_DBG_EN
- .fuse_idcode (`SCR1_TAP_IDCODE ),
-`endif // SCR1_DBG_EN
// IRQ
-`ifdef SCR1_IPIC_EN
.irq_lines (irq_lines ),
-`else // SCR1_IPIC_EN
- .ext_irq (ext_irq ), // TODO - Interrupts
-`endif // SCR1_IPIC_EN
.soft_irq (soft_irq ), // TODO - Interrupts
// DFT
- .test_mode (1'b0 ),
- .test_rst_n (1'b1 ),
-
-`ifdef SCR1_DBG_EN
- // JTAG
- .trst_n (trst_n ),
- .tck (tck ),
- .tms (tms ),
- .tdi (tdi ),
- .tdo (tdo ),
- .tdo_en (tdo_en ),
-`endif // SCR1_DBG_EN
+ // .test_mode (1'b0 ), // Moved inside IP
+ // .test_rst_n (1'b1 ), // Moved inside IP
- .wb_rst_n (wb_rst_n ),
- .wb_clk (wb_clk_i ),
+ .wb_rst_n (wbd_int_rst_n ),
+ .wb_clk (wbd_clk_int ),
// Instruction memory interface
.wbd_imem_stb_o (wbd_riscv_imem_stb_i ),
.wbd_imem_adr_o (wbd_riscv_imem_adr_i ),
@@ -412,7 +374,7 @@
`endif
) u_spi_master
(
- .mclk (wb_clk_i ),
+ .mclk (wbd_clk_int ),
.rst_n (spi_rst_n ),
.wbd_stb_i (wbd_spim_stb_o ),
@@ -426,21 +388,11 @@
.events_o ( ), // TODO - Need to connect to intr ?
- .spi_clk (spim_clk ),
- .spi_csn0 (spim_csn ),
- .spi_csn1 ( ),
- .spi_csn2 ( ),
- .spi_csn3 ( ),
- .spi_mode ( ),
- .spi_sdo0 (spim_sdo0 ),
- .spi_sdo1 (spim_sdo1 ),
- .spi_sdo2 (spim_sdo2 ),
- .spi_sdo3 (spim_sdo3 ),
- .spi_sdi0 (spim_sdi0 ),
- .spi_sdi1 (spim_sdi1 ),
- .spi_sdi2 (spim_sdi2 ),
- .spi_sdi3 (spim_sdi3 ),
- .spi_en_tx (spi_en_tx )
+ // Pad Interface
+ .io_in (io_in[35:30] ),
+ .io_out (io_out[35:30] ),
+ .io_oeb (io_oeb[35:30] )
+
);
@@ -457,8 +409,8 @@
.cfg_colbits (cfg_colbits ),
// WB bus
- .wb_rst_i (wb_rst_i ),
- .wb_clk_i (wb_clk_i ),
+ .wb_rst_n (wbd_int_rst_n ),
+ .wb_clk_i (wbd_clk_int ),
.wb_stb_i (wbd_sdram_stb_o ),
.wb_addr_i (wbd_sdram_adr_o ),
@@ -466,7 +418,6 @@
.wb_dat_i (wbd_sdram_dat_o ),
.wb_sel_i (wbd_sdram_sel_o ),
.wb_cyc_i (wbd_sdram_cyc_o ),
- .wb_cti_i (wbd_sdram_cti_o ),
.wb_ack_o (wbd_sdram_ack_i ),
.wb_dat_o (wbd_sdram_dat_i ),
@@ -474,18 +425,11 @@
/* Interface to SDRAMs */
.sdram_clk (sdram_clk ),
.sdram_resetn (sdram_rst_n ),
- .sdr_cs_n (sdr_cs_n ),
- .sdr_cke (sdr_cke ),
- .sdr_ras_n (sdr_ras_n ),
- .sdr_cas_n (sdr_cas_n ),
- .sdr_we_n (sdr_we_n ),
- .sdr_dqm (sdr_dqm ),
- .sdr_ba (sdr_ba ),
- .sdr_addr (sdr_addr ),
- .pad_sdr_din (pad_sdr_din ),
- .sdr_dout (sdr_dout ),
- .sdr_den_n (sdr_den_n ),
- .sdram_pad_clk (pad_sdram_clk ),
+
+ /** Pad Interface **/
+ .io_in (io_in[29:0] ),
+ .io_oeb (io_oeb[29:0] ),
+ .io_out (io_out[29:0] ),
/* Parameters */
.sdr_init_done (sdr_init_done ),
@@ -504,8 +448,8 @@
wb_interconnect u_intercon (
- .clk_i (wb_clk_i ),
- .rst_n (wb_rst_n ),
+ .clk_i (wbd_clk_int ),
+ .rst_n (wbd_int_rst_n ),
// Master 0 Interface
.m0_wbd_dat_i (wbd_riscv_imem_dat_i ),
@@ -530,19 +474,19 @@
.m1_wbd_err_o (wbd_riscv_dmem_err_o ),
// Master 2 Interface
- .m2_wbd_dat_i (wbd_ext_dat_i ),
- .m2_wbd_adr_i (wbd_ext_adr_i ),
- .m2_wbd_sel_i (wbd_ext_sel_i ),
- .m2_wbd_we_i (wbd_ext_we_i ),
- .m2_wbd_cyc_i (wbd_ext_cyc_i ),
- .m2_wbd_stb_i (wbd_ext_stb_i ),
- .m2_wbd_dat_o (wbd_ext_dat_o ),
- .m2_wbd_ack_o (wbd_ext_ack_o ),
- .m2_wbd_err_o (wbd_ext_err_o ),
+ .m2_wbd_dat_i (wbd_int_dat_i ),
+ .m2_wbd_adr_i (wbd_int_adr_i ),
+ .m2_wbd_sel_i (wbd_int_sel_i ),
+ .m2_wbd_we_i (wbd_int_we_i ),
+ .m2_wbd_cyc_i (wbd_int_cyc_i ),
+ .m2_wbd_stb_i (wbd_int_stb_i ),
+ .m2_wbd_dat_o (wbd_int_dat_o ),
+ .m2_wbd_ack_o (wbd_int_ack_o ),
+ .m2_wbd_err_o (wbd_int_err_o ),
// Slave 0 Interface
- .s0_wbd_err_i (1'b0 ),
+ // .s0_wbd_err_i (1'b0 ), - Moved inside IP
.s0_wbd_dat_i (wbd_spim_dat_i ),
.s0_wbd_ack_i (wbd_spim_ack_i ),
.s0_wbd_dat_o (wbd_spim_dat_o ),
@@ -553,7 +497,7 @@
.s0_wbd_stb_o (wbd_spim_stb_o ),
// Slave 1 Interface
- .s1_wbd_err_i (1'b0 ),
+ // .s1_wbd_err_i (1'b0 ), - Moved inside IP
.s1_wbd_dat_i (wbd_sdram_dat_i ),
.s1_wbd_ack_i (wbd_sdram_ack_i ),
.s1_wbd_dat_o (wbd_sdram_dat_o ),
@@ -564,7 +508,7 @@
.s1_wbd_stb_o (wbd_sdram_stb_o ),
// Slave 2 Interface
- .s2_wbd_err_i (1'b0 ),
+ // .s2_wbd_err_i (1'b0 ), - Moved inside IP
.s2_wbd_dat_i (wbd_glbl_dat_i ),
.s2_wbd_ack_i (wbd_glbl_ack_i ),
.s2_wbd_dat_o (wbd_glbl_dat_o ),
@@ -575,7 +519,7 @@
.s2_wbd_stb_o (wbd_glbl_stb_o ),
// Slave 3 Interface
- .s3_wbd_err_i (1'b0 ),
+ // .s3_wbd_err_i (1'b0 ), - Moved inside IP
.s3_wbd_dat_i (wbd_uart_dat_i ),
.s3_wbd_ack_i (wbd_uart_ack_i ),
.s3_wbd_dat_o (wbd_uart_dat_o ),
@@ -588,8 +532,8 @@
glbl_cfg u_glbl_cfg (
- .mclk (wb_clk_i ),
- .reset_n (wb_rst_n ),
+ .mclk (wbd_clk_int ),
+ .reset_n (wbd_int_rst_n ),
.user_clock2 (user_clock2 ),
.device_idcode ( ),
@@ -610,11 +554,6 @@
.cpu_clk (cpu_clk ),
.rtc_clk (rtc_clk ),
- // reset
- .cpu_rst_n (cpu_rst_n ),
- .spi_rst_n (spi_rst_n ),
- .sdram_rst_n (sdram_rst_n ),
-
// Risc configuration
.fuse_mhartid (fuse_mhartid ),
.irq_lines (irq_lines ),
@@ -643,8 +582,8 @@
);
uart_core u_uart_core (
- .arst_n (wb_rst_n ), // async reset
- .app_clk (wb_clk_i ),
+ .arst_n (wbd_int_rst_n ), // async reset
+ .app_clk (wbd_clk_int ),
// Reg Bus Interface Signal
.reg_cs (wbd_uart_stb_o ),
@@ -657,9 +596,10 @@
.reg_rdata (wbd_uart_dat_i[7:0] ),
.reg_ack (wbd_uart_ack_i ),
- // Line Interface
- .si ( uart_rx ),
- .so ( uart_tx )
+ // Pad interface
+ .io_in (io_in [37:36] ),
+ .io_oeb (io_oeb[37:36] ),
+ .io_out (io_out[37:36] )
);
diff --git a/verilog/rtl/digital_core/src/glbl_cfg.sv b/verilog/rtl/digital_core/src/glbl_cfg.sv
index 1754aec..9e1f371 100644
--- a/verilog/rtl/digital_core/src/glbl_cfg.sv
+++ b/verilog/rtl/digital_core/src/glbl_cfg.sv
@@ -69,10 +69,6 @@
output logic cpu_clk,
output logic rtc_clk,
- // reset
- output logic cpu_rst_n,
- output logic spi_rst_n,
- output logic sdram_rst_n,
// Risc configuration
output logic [31:0] fuse_mhartid,
@@ -254,9 +250,6 @@
// reg-0
// -----------------------------------------------------------------
-assign cpu_rst_n = reg_0[0];
-assign spi_rst_n = reg_0[1];
-assign sdram_rst_n = reg_0[2];
// SDRAM Clock source & div selection
wire cfg_sdram_clk_src_sel = reg_0[4];
diff --git a/verilog/rtl/sdram_ctrl/src/top/sdrc_top.v b/verilog/rtl/sdram_ctrl/src/top/sdrc_top.v
index 00d9606..ab99a8c 100755
--- a/verilog/rtl/sdram_ctrl/src/top/sdrc_top.v
+++ b/verilog/rtl/sdram_ctrl/src/top/sdrc_top.v
@@ -31,6 +31,11 @@
sdram_dq and sdram_pad_clk are internally generated
0.3 - 26th April 2013
Sdram Address witdh is increased from 12 to 13bits
+ 0.3 - 25th June 2021
+ Move the Pad logic inside the sdram to avoid combo logic
+ at digital core level
+ 0.4 - 27th June 2021
+ Unused port wb_cti_i removed
Copyright (C) 2000 Authors and OPENCORES.ORG
@@ -66,7 +71,7 @@
cfg_colbits ,
// WB bus
- wb_rst_i ,
+ wb_rst_n ,
wb_clk_i ,
wb_stb_i ,
@@ -77,25 +82,18 @@
wb_sel_i ,
wb_dat_o ,
wb_cyc_i ,
- wb_cti_i ,
/* Interface to SDRAMs */
sdram_clk ,
sdram_resetn ,
- sdr_cs_n ,
- sdr_cke ,
- sdr_ras_n ,
- sdr_cas_n ,
- sdr_we_n ,
- sdr_dqm ,
- sdr_ba ,
- sdr_addr ,
- pad_sdr_din ,
- sdr_dout ,
- sdr_den_n ,
- sdram_pad_clk ,
+
+ /** Pad Interface **/
+ io_in ,
+ io_oeb ,
+ io_out ,
+
/* Parameters */
sdr_init_done ,
cfg_req_depth , //how many req. buffer should hold
@@ -134,7 +132,7 @@
//--------------------------------------
// Wish Bone Interface
// -------------------------------------
-input wb_rst_i ;
+input wb_rst_n ;
input wb_clk_i ;
input wb_stb_i ;
@@ -145,23 +143,28 @@
input [APP_DW/8-1:0] wb_sel_i ; // Byte enable
output [APP_DW-1:0] wb_dat_o ;
input wb_cyc_i ;
-input [2:0] wb_cti_i ;
+//--------------------------------------
+// Pad Interface
+// -------------------------------------
+input [29:0] io_in ;
+output [29:0] io_oeb ;
+output [29:0] io_out ;
//------------------------------------------------
// Interface to SDRAMs
//------------------------------------------------
-output sdr_cke ; // SDRAM CKE
-output sdr_cs_n ; // SDRAM Chip Select
-output sdr_ras_n ; // SDRAM ras
-output sdr_cas_n ; // SDRAM cas
-output sdr_we_n ; // SDRAM write enable
-output [SDR_BW-1:0] sdr_dqm ; // SDRAM Data Mask
-output [1:0] sdr_ba ; // SDRAM Bank Enable
-output [12:0] sdr_addr ; // SDRAM Address
-input sdram_pad_clk ; // Sdram clock loop back from pad
-input [SDR_DW-1:0] pad_sdr_din ; // SDRA Data Input
-output [SDR_DW-1:0] sdr_dout ; // SDRAM Data Output
-output [SDR_BW-1:0] sdr_den_n ; // SDRAM Data Output enable
+wire sdram_pad_clk ; // Sdram clock loop back from pad
+wire sdr_cke ; // SDRAM CKE
+wire sdr_cs_n ; // SDRAM Chip Select
+wire sdr_ras_n ; // SDRAM ras
+wire sdr_cas_n ; // SDRAM cas
+wire sdr_we_n ; // SDRAM write enable
+wire [SDR_BW-1:0] sdr_dqm ; // SDRAM Data Mask
+wire [1:0] sdr_ba ; // SDRAM Bank Enable
+wire [12:0] sdr_addr ; // SDRAM Address
+wire [SDR_DW-1:0] pad_sdr_din ; // SDRA Data Input
+wire [SDR_DW-1:0] sdr_dout ; // SDRAM Data Output
+wire [SDR_BW-1:0] sdr_den_n ; // SDRAM Data Output enable
//------------------------------------------------
// Configuration Parameter
@@ -196,13 +199,33 @@
wire [APP_DW-1:0] app_wr_data ; // sdr write data
wire [APP_DW-1:0] app_rd_data ; // sdr read data
-/****************************************
-* These logic has to be implemented using Pads
-* **************************************/
-wire [SDR_DW-1:0] pad_sdr_din ; // SDRA Data Input
-wire [SDR_DW-1:0] sdr_dout ; // SDRAM Data Output
-wire [SDR_BW-1:0] sdr_den_n ; // SDRAM Data Output enable
+//-----------------------------------------------------------------
+// To avoid the logic at digital core, pad control are brought inside the
+// block to support efabless/carvel soc enviornmental support
+// -----------------------------------------------------------------
+assign pad_sdr_din[7:0] = io_in[7:0] ;
+assign io_out [7:0] = sdr_dout[7:0] ;
+assign io_out [20:8] = sdr_addr[12:0] ;
+assign io_out [22:21] = sdr_ba[1:0] ;
+assign io_out [23] = sdr_dqm[0] ;
+assign io_out [24] = sdr_we_n ;
+assign io_out [25] = sdr_cas_n ;
+assign io_out [26] = sdr_ras_n ;
+assign io_out [27] = sdr_cs_n ;
+assign io_out [28] = sdr_cke ;
+assign io_out [29] = sdram_clk ;
+assign sdram_pad_clk = io_in[29] ;
+assign io_oeb [7:0] = sdr_den_n ;
+assign io_oeb [20:8] = {(13) {1'b0}} ;
+assign io_oeb [22:21] = {(2) {1'b0}} ;
+assign io_oeb [23] = 1'b0 ;
+assign io_oeb [24] = 1'b0 ;
+assign io_oeb [25] = 1'b0 ;
+assign io_oeb [26] = 1'b0 ;
+assign io_oeb [27] = 1'b0 ;
+assign io_oeb [28] = 1'b0 ;
+assign io_oeb [29] = 1'b0 ;
//assign sdr_dq = (&sdr_den_n == 1'b0) ? sdr_dout : {SDR_DW{1'bz}};
//assign pad_sdr_din = sdr_dq;
@@ -214,7 +237,7 @@
/************** Ends Here **************************/
wb2sdrc #(.dw(APP_DW),.tw(tw),.bl(bl),.APP_AW(APP_AW)) u_wb2sdrc (
// WB bus
- .wb_rst_i (wb_rst_i ) ,
+ .wb_rst_n (wb_rst_n ) ,
.wb_clk_i (wb_clk_i ) ,
.wb_stb_i (wb_stb_i ) ,
@@ -225,7 +248,6 @@
.wb_sel_i (wb_sel_i ) ,
.wb_dat_o (wb_dat_o ) ,
.wb_cyc_i (wb_cyc_i ) ,
- .wb_cti_i (wb_cti_i ) ,
//SDRAM Controller Hand-Shake Signal
diff --git a/verilog/rtl/sdram_ctrl/src/wb2sdrc/wb2sdrc.v b/verilog/rtl/sdram_ctrl/src/wb2sdrc/wb2sdrc.v
index 4a0f74b..023a3ee 100755
--- a/verilog/rtl/sdram_ctrl/src/wb2sdrc/wb2sdrc.v
+++ b/verilog/rtl/sdram_ctrl/src/wb2sdrc/wb2sdrc.v
@@ -48,7 +48,7 @@
module wb2sdrc (
// WB bus
- wb_rst_i ,
+ wb_rst_n ,
wb_clk_i ,
wb_stb_i ,
@@ -59,7 +59,6 @@
wb_sel_i ,
wb_dat_o ,
wb_cyc_i ,
- wb_cti_i ,
//SDRAM Controller Hand-Shake Signal
@@ -87,7 +86,7 @@
//--------------------------------------
// Wish Bone Interface
// -------------------------------------
-input wb_rst_i ;
+input wb_rst_n ;
input wb_clk_i ;
input wb_stb_i ;
@@ -98,7 +97,6 @@
input [dw/8-1:0] wb_sel_i ; // Byte enable
output [dw-1:0] wb_dat_o ;
input wb_cyc_i ;
-input [2:0] wb_cti_i ;
/***************************************************
The Cycle Type Idenfier [CTI_IO()] Address Tag provides
additional information about the current cycle.
@@ -199,8 +197,8 @@
// set - with Read Request
// reset - with Read Request + Ack
// ----------------------------------------------------------------------------
-always @(posedge wb_rst_i or posedge wb_clk_i) begin
- if(wb_rst_i) begin
+always @(negedge wb_rst_n or posedge wb_clk_i) begin
+ if(!wb_rst_n) begin
pending_read <= 1'b0;
end else begin
//pending_read <= wb_stb_i & wb_cyc_i & !wb_we_i & !wb_ack_o;
@@ -217,7 +215,7 @@
async_fifo #(.W(APP_AW+bl+1),.DP(4),.WR_FAST(1'b0), .RD_FAST(1'b0)) u_cmdfifo (
// Write Path Sys CLock Domain
.wr_clk (wb_clk_i ),
- .wr_reset_n (!wb_rst_i ),
+ .wr_reset_n (wb_rst_n ),
.wr_en (cmdfifo_wr ),
.wr_data ({burst_length,
!wb_we_i,
@@ -275,7 +273,7 @@
async_fifo #(.W(dw+(dw/8)), .DP(8), .WR_FAST(1'b0), .RD_FAST(1'b1)) u_wrdatafifo (
// Write Path , System clock domain
.wr_clk (wb_clk_i ),
- .wr_reset_n (!wb_rst_i ),
+ .wr_reset_n (wb_rst_n ),
.wr_en (wrdatafifo_wr ),
.wr_data ({~wb_sel_i,
wb_dat_i} ),
@@ -345,7 +343,7 @@
// Read Path , SYS clock domain
.rd_clk (wb_clk_i ),
- .rd_reset_n (!wb_rst_i ),
+ .rd_reset_n (wb_rst_n ),
.empty (rddatafifo_empty ),
.aempty ( ),
.rd_en (rddatafifo_rd ),
diff --git a/verilog/rtl/spi_master/src/spim_top.sv b/verilog/rtl/spi_master/src/spim_top.sv
index 3c322fa..a405e9a 100644
--- a/verilog/rtl/spi_master/src/spim_top.sv
+++ b/verilog/rtl/spi_master/src/spim_top.sv
@@ -16,6 +16,9 @@
//// ////
//// Revision : ////
//// V.0 - June 8, 2021 ////
+//// V.1 - June 25, 2021 ////
+//// Pad logic is brought inside the block to avoid ////
+//// logic at digital core level for caravel project ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
@@ -62,23 +65,13 @@
output logic wbd_ack_o, // acknowlegement
output logic wbd_err_o, // error
- output logic [1:0] events_o,
+ output logic [1:0] events_o,
- output logic spi_clk,
- output logic spi_csn0,
- output logic spi_csn1,
- output logic spi_csn2,
- output logic spi_csn3,
- output logic [1:0] spi_mode,
- output logic spi_sdo0,
- output logic spi_sdo1,
- output logic spi_sdo2,
- output logic spi_sdo3,
- input logic spi_sdi0,
- input logic spi_sdi1,
- input logic spi_sdi2,
- input logic spi_sdi3,
- output logic spi_en_tx
+ // PAD I/f
+ input [5:0] io_in ,
+ output [5:0] io_out ,
+ output [5:0] io_oeb
+
);
@@ -121,6 +114,45 @@
logic s_eot;
+//-------------------------------------------------------
+// SPI Interface moved inside to support carvel IO pad
+// -------------------------------------------------------
+
+logic spi_clk;
+logic spi_csn0;
+logic spi_csn1;
+logic spi_csn2;
+logic spi_csn3;
+logic [1:0] spi_mode;
+logic spi_sdo0;
+logic spi_sdo1;
+logic spi_sdo2;
+logic spi_sdo3;
+logic spi_sdi0;
+logic spi_sdi1;
+logic spi_sdi2;
+logic spi_sdi3;
+logic spi_en_tx;
+
+
+assign spi_sdi0 = io_in[2];
+assign spi_sdi1 = io_in[3];
+assign spi_sdi2 = io_in[4];
+assign spi_sdi3 = io_in[5];
+
+assign io_out[0] = spi_clk;
+assign io_out[1] = spi_csn0;
+assign io_out[2] = spi_sdo0;
+assign io_out[3] = spi_sdo1;
+assign io_out[4] = spi_sdo2;
+assign io_out[5] = spi_sdo3;
+
+assign io_oeb[0] = 1'b0; // spi_clk
+assign io_oeb[1] = 1'b0; // spi_csn
+assign io_oeb[2] = !spi_en_tx; // spi_dio0
+assign io_oeb[3] = !spi_en_tx; // spi_dio1
+assign io_oeb[4] = !spi_en_tx; // spi_dio2
+assign io_oeb[5] = !spi_en_tx; // spi_dio3
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
index d72afd1..3ded0b8 100644
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
+++ b/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
@@ -70,8 +70,8 @@
input logic pwrup_rst_n, // Power-Up Reset
input logic rst_n, // Regular Reset signal
input logic cpu_rst_n, // CPU Reset (Core Reset)
- input logic test_mode, // Test mode
- input logic test_rst_n, // Test mode's reset
+ // input logic test_mode, // Test mode - unused
+ // input logic test_rst_n, // Test mode's reset - unused
input logic core_clk, // Core clock
input logic rtc_clk, // Real-time clock
`ifdef SCR1_DBG_EN
@@ -138,6 +138,8 @@
// Local signal declaration
//-------------------------------------------------------------------------------
// Reset logic
+logic test_mode; // Test mode - unused
+logic test_rst_n; // Test mode's reset - unused
logic pwrup_rst_n_sync;
logic rst_n_sync;
logic cpu_rst_n_sync;
@@ -216,6 +218,12 @@
logic [63:0] timer_val;
+//---------------------------------------------------------------------------------
+// To avoid core level power hook up, we have brought this signal inside, to
+// avoid any cell at digital core level
+// --------------------------------------------------------------------------------
+assign test_mode = 1'b0;
+assign test_rst_n = 1'b0;
//-------------------------------------------------------------------------------
// Reset logic
//-------------------------------------------------------------------------------
diff --git a/verilog/rtl/uart/src/uart_core.sv b/verilog/rtl/uart/src/uart_core.sv
index 258c134..09b3f6a 100644
--- a/verilog/rtl/uart/src/uart_core.sv
+++ b/verilog/rtl/uart/src/uart_core.sv
@@ -17,6 +17,9 @@
//// 0.1 - 20th June 2021, Dinesh A ////
//// 1. initial version picked from ////
//// http://www.opencores.org/cores/oms8051mini ////
+//// 0.2 - 25th June 2021, Dinesh A ////
+//// Pad logic moved inside core to avoid combo logic at ////
+//// soc digital core level ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
@@ -49,23 +52,24 @@
(
- arst_n , // async reset
- app_clk ,
+ input logic arst_n , // async reset
+ input logic app_clk ,
// Reg Bus Interface Signal
- reg_cs,
- reg_wr,
- reg_addr,
- reg_wdata,
- reg_be,
+ input logic reg_cs,
+ input logic reg_wr,
+ input logic [3:0] reg_addr,
+ input logic [7:0] reg_wdata,
+ input logic reg_be,
// Outputs
- reg_rdata,
- reg_ack,
+ output logic [7:0] reg_rdata,
+ output logic reg_ack,
- // Line Interface
- si,
- so
+ // Pad Control
+ input logic [1:0] io_in,
+ output logic [1:0] io_out,
+ output logic [1:0] io_oeb
);
@@ -85,26 +89,6 @@
-input arst_n ; // async reset
-input app_clk ; // application clock
-
-//---------------------------------
-// Reg Bus Interface Signal
-//---------------------------------
-input reg_cs ;
-input reg_wr ;
-input [3:0] reg_addr ;
-input [7:0] reg_wdata ;
-input reg_be ;
-
-// Outputs
-output [7:0] reg_rdata ;
-output reg_ack ;
-
-// Line Interface
-input si ; // uart si
-output so ; // uart so
-
// Wire Declaration
wire app_reset_n ;
wire line_reset_n ;
@@ -138,6 +122,22 @@
wire [AW:0] rx_fifo_dval ; // Total Rx fifo Data Available
wire si_ss ;
+
+/////////////////////////////////////////////////////////
+// uart interface
+///////////////////////////////////////////////////////
+
+wire si ;
+wire so ;
+
+// for uart
+assign io_oeb[0] = 1'b1; // Uart RX
+assign si = io_in[0];
+assign io_out[0] = 1'b0;
+
+assign io_oeb[1] = 1'b0; // Uart TX
+assign io_out[1] = so;
+
uart_cfg u_cfg (
. mclk (app_clk),
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index ba06633..e31d589 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -54,6 +54,9 @@
`include "digital_core/src/glbl_cfg.sv"
`include "digital_core/src/digital_core.sv"
+ `include "wb_host/src/wb_host.sv"
+ `include "lib/async_wb.sv"
+
`include "lib/wb_stagging.sv"
`include "wb_interconnect/src/wb_arb.sv"
`include "wb_interconnect/src/wb_interconnect.sv"
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 303a53d..bf72715 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -103,7 +103,6 @@
.wbd_ext_dat_i(wbs_dat_i),
.wbd_ext_ack_o(wbs_ack_o),
.wbd_ext_dat_o(wbs_dat_o),
- .wbd_ext_err_o(),
// Logic Analyzer
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
index 410dc9b..e6c9f40 100644
--- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
+++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -22,6 +22,12 @@
//// path ////
//// 0.3 - 21th June 2021, Dinesh A ////
//// slave port 3 added for uart ////
+//// 0.4 - 25th June 2021, Dinesh A ////
+//// External Memory Map changed and made same as ////
+//// internal memory map ////
+//// 0.4 - 27th June 2021, Dinesh A ////
+//// unused tie off at digital core level brought inside ////
+//// to avoid core level power hook up ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
@@ -93,7 +99,7 @@
// Slave 0 Interface
input logic [31:0] s0_wbd_dat_i,
input logic s0_wbd_ack_i,
- input logic s0_wbd_err_i,
+ //input logic s0_wbd_err_i, - unused
output logic [31:0] s0_wbd_dat_o,
output logic [31:0] s0_wbd_adr_o,
output logic [3:0] s0_wbd_sel_o,
@@ -104,7 +110,7 @@
// Slave 1 Interface
input logic [31:0] s1_wbd_dat_i,
input logic s1_wbd_ack_i,
- input logic s1_wbd_err_i,
+ // input logic s1_wbd_err_i, - unused
output logic [31:0] s1_wbd_dat_o,
output logic [31:0] s1_wbd_adr_o,
output logic [3:0] s1_wbd_sel_o,
@@ -115,7 +121,7 @@
// Slave 2 Interface
input logic [31:0] s2_wbd_dat_i,
input logic s2_wbd_ack_i,
- input logic s2_wbd_err_i,
+ // input logic s2_wbd_err_i, - unused
output logic [31:0] s2_wbd_dat_o,
output logic [7:0] s2_wbd_adr_o, // glbl reg need only 8 bits
output logic [3:0] s2_wbd_sel_o,
@@ -127,7 +133,7 @@
// Uart is 8bit interface
input logic [7:0] s3_wbd_dat_i,
input logic s3_wbd_ack_i,
- input logic s3_wbd_err_i,
+ // input logic s3_wbd_err_i,
output logic [7:0] s3_wbd_dat_o,
output logic [7:0] s3_wbd_adr_o,
output logic s3_wbd_sel_o,
@@ -213,15 +219,17 @@
//-------------------------------------------------------------------
// EXTERNAL MEMORY MAP
-// 0x3000_0000 to 0x3000_00FF - GLOBAL REGISTER
+// 0x0000_0000 to 0x0FFF_FFFF - SPI FLASH MEMORY
+// 0x1000_0000 to 0x1000_00FF - SPI REGISTER
+// 0x2000_0000 to 0x2FFF_FFFF - SDRAM
+// 0x3000_0000 to 0x3000_00FF - GLOBAL REGISTER
// 0x3000_0000 to 0x3001_00FF - UART Register
-// 0x4000_0000 to 0x4FFF_FFFF - SPI FLASH MEMORY
-// 0x5000_0000 to 0x5000_00FF - SPI REGISTER
-// 0x6000_0000 to 0x6FFF_FFFF - SDRAM
+// 0x3080_0000 to 0x3080_00FF - WB HOST (This decoding happens at wb_host block)
+// ---------------------------------------------------------------------------
//
-wire [3:0] m2_wbd_tid_i = (m2_wbd_adr_i[31:28] == 4'b0100 ) ? 4'b0000 :
- (m2_wbd_adr_i[31:28] == 4'b0101 ) ? 4'b0000 :
- (m2_wbd_adr_i[31:28] == 4'b0110 ) ? 4'b0001 :
+wire [3:0] m2_wbd_tid_i = (m2_wbd_adr_i[31:28] == 4'b0000 ) ? 4'b0000 :
+ (m2_wbd_adr_i[31:28] == 4'b0001 ) ? 4'b0000 :
+ (m2_wbd_adr_i[31:28] == 4'b0010 ) ? 4'b0001 :
(m2_wbd_adr_i[31:16] == 16'h3000 ) ? 4'b0010 :
(m2_wbd_adr_i[31:16] == 16'h3001 ) ? 4'b0011 : 4'b0000;
@@ -298,19 +306,19 @@
assign s0_wb_rd.wbd_dat = s0_wbd_dat_i ;
assign s0_wb_rd.wbd_ack = s0_wbd_ack_i ;
- assign s0_wb_rd.wbd_err = s0_wbd_err_i ;
+ assign s0_wb_rd.wbd_err = 1'b0; // s0_wbd_err_i ; - unused
assign s1_wb_rd.wbd_dat = s1_wbd_dat_i ;
assign s1_wb_rd.wbd_ack = s1_wbd_ack_i ;
- assign s1_wb_rd.wbd_err = s1_wbd_err_i ;
+ assign s1_wb_rd.wbd_err = 1'b0; // s1_wbd_err_i ; - unused
assign s2_wb_rd.wbd_dat = s2_wbd_dat_i ;
assign s2_wb_rd.wbd_ack = s2_wbd_ack_i ;
- assign s2_wb_rd.wbd_err = s2_wbd_err_i ;
+ assign s2_wb_rd.wbd_err = 1'b0; // s2_wbd_err_i ; - unused
assign s3_wb_rd.wbd_dat = {24'h0,s3_wbd_dat_i} ;
assign s3_wb_rd.wbd_ack = s3_wbd_ack_i ;
- assign s3_wb_rd.wbd_err = s3_wbd_err_i ;
+ assign s3_wb_rd.wbd_err = 1'b0; // s3_wbd_err_i ; - unused
//
// arbitor
