commit | 054bd1c08b8490f19243764fd035ee4f324db520 | [log] [tgz] |
---|---|---|
author | dineshannayya <dinesh.annayya@gmail.com> | Mon Aug 16 19:18:49 2021 +0530 |
committer | dineshannayya <dinesh.annayya@gmail.com> | Mon Aug 16 19:18:49 2021 +0530 |
tree | 6c90eff707f6681f3d164a4f8fc15aa5b78b6f1d | |
parent | 70876fa1aaeb0497e5586972b788b424fe155133 [diff] |
modelsim compile cleanup
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv index eabaf49..d42adf4 100644 --- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv +++ b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv
@@ -188,7 +188,7 @@ if (~rst_n) begin exu2ialu_main_op1_ff <= '0; exu2ialu_main_op2_ff <= '0; - exu2ialu_cmd_ff <= '0; + exu2ialu_cmd_ff <= SCR1_IALU_CMD_NONE; exu2ialu_rvm_cmd_vd_ff <= '0; end else begin exu2ialu_main_op1_ff <= exu2ialu_main_op1_i;