clean up
diff --git a/openlane/user_project_wrapper/gen_pdn.tcl b/openlane/user_project_wrapper/gen_pdn.tcl
deleted file mode 100644
index 94bd008..0000000
--- a/openlane/user_project_wrapper/gen_pdn.tcl
+++ /dev/null
@@ -1,50 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-
-read_lef $::env(MERGED_LEF_UNPADDED)
-read_def $::env(CURRENT_DEF)
-
-set ::env(_SPACING) 1.7
-set ::env(_WIDTH) 3
-
-set power_domains [list {vccd1 vssd1 1} {vccd2 vssd2 0} {vdda1 vssa1 0} {vdda2 vssa2 0}]
-
-set ::env(_VDD_NET_NAME) vccd1
-set ::env(_GND_NET_NAME) vssd1
-set ::env(_WITH_STRAPS) 1
-set ::env(_V_OFFSET) 14
-set ::env(_H_OFFSET) $::env(_V_OFFSET)
-set ::env(_V_PITCH) 80
-set ::env(_H_PITCH) 80
-set ::env(_V_PDN_OFFSET) 0
-set ::env(_H_PDN_OFFSET) 0
-
-foreach domain $power_domains {
- set ::env(_VDD_NET_NAME) [lindex $domain 0]
- set ::env(_GND_NET_NAME) [lindex $domain 1]
- set ::env(_WITH_STRAPS) [lindex $domain 2]
-
- pdngen $::env(PDN_CFG) -verbose
-
- set ::env(_V_OFFSET) \
- [expr $::env(_V_OFFSET) + 2*($::env(_WIDTH)+$::env(_SPACING))]
- set ::env(_H_OFFSET) \
- [expr $::env(_H_OFFSET) + 2*($::env(_WIDTH)+$::env(_SPACING))]
- set ::env(_V_PDN_OFFSET) [expr $::env(_V_PDN_OFFSET)+6*$::env(_WIDTH)]
- set ::env(_H_PDN_OFFSET) [expr $::env(_H_PDN_OFFSET)+6*$::env(_WIDTH)]
-}
-
-write_def $::env(SAVE_DEF)
diff --git a/openlane/user_project_wrapper/interactive.mpw4.tcl b/openlane/user_project_wrapper/interactive.mpw4.tcl
deleted file mode 100644
index 1c24305..0000000
--- a/openlane/user_project_wrapper/interactive.mpw4.tcl
+++ /dev/null
@@ -1,394 +0,0 @@
-#!/usr/bin/tclsh
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-# Copyright 2020 Efabless Corporation
-# Copyright 2020 Sylvain Munaut
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-package require openlane;
-
-
-proc run_placement_step {args} {
- if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
- set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
- }
-
- run_placement
-}
-
-proc run_placement {args} {
- puts_info "Running Placement..."
-# |----------------------------------------------------|
-# |---------------- 3. PLACEMENT ------------------|
-# |----------------------------------------------------|
- set ::env(CURRENT_STAGE) placement
-
- if { [info exists ::env(PL_TARGET_DENSITY_CELLS)] } {
- set old_pl_target_density $::env(PL_TARGET_DENSITY)
- set ::env(PL_TARGET_DENSITY) $::env(PL_TARGET_DENSITY_CELLS)
- }
-
- if { $::env(PL_RANDOM_GLB_PLACEMENT) } {
- # useful for very tiny designs
- random_global_placement
- } else {
- global_placement_or
- }
-
- if { [info exists ::env(PL_TARGET_DENSITY_CELLS)] } {
- set ::env(PL_TARGET_DENSITY) $old_pl_target_density
- }
-
- run_resizer_design
-
- if { [info exists ::env(DONT_BUFFER_PORTS) ]} {
- remove_buffers
- }
- detailed_placement_or
- scrot_klayout -layout $::env(CURRENT_DEF)
-}
-
-
-proc run_cts_step {args} {
- if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
- set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
- }
-
- run_cts
- run_resizer_timing
-}
-
-proc run_routing_step {args} {
- if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
- set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
- }
- run_routing
-}
-
-proc run_diode_insertion_2_5_step {args} {
- if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
- set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
- }
- if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
- run_antenna_check
- heal_antenna_violators; # modifies the routed DEF
- }
-
-}
-
-proc run_power_pins_insertion_step {args} {
- # set_def $::env(tritonRoute_result_file_tag).def
- if { ! [ info exists ::env(POWER_PINS_INSERTION_CURRENT_DEF) ] } {
- set ::env(POWER_PINS_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(POWER_PINS_INSERTION_CURRENT_DEF)
- }
- if { $::env(LVS_INSERT_POWER_PINS) } {
- write_powered_verilog
- set_netlist $::env(lvs_result_file_tag).powered.v
- }
-
-}
-
-
-proc run_lvs_step {{ lvs_enabled 1 }} {
- if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
- set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
- }
- if { $lvs_enabled } {
- run_magic_spice_export
- run_lvs; # requires run_magic_spice_export
- }
-
-}
-
-proc run_drc_step {{ drc_enabled 1 }} {
- if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
- set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
- }
- if { $drc_enabled } {
- run_magic_drc
- run_klayout_drc
- }
-}
-
-proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
- if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
- set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
- }
- if { $antenna_check_enabled } {
- run_antenna_check
- }
-}
-
-
-proc gen_pdn {args} {
- puts_info "Generating PDN..."
- TIMER::timer_start
-
- set ::env(SAVE_DEF) [index_file $::env(pdn_tmp_file_tag).def]
- set ::env(PGA_RPT_FILE) [index_file $::env(pdn_report_file_tag).pga.rpt]
-
- try_catch $::env(OPENROAD_BIN) -exit $::env(SCRIPTS_DIR)/openroad/pdn.tcl \
- |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(pdn_log_file_tag).log 0]
-
-
- TIMER::timer_stop
- exec echo "[TIMER::get_runtime]" >> [index_file $::env(pdn_log_file_tag)_runtime.txt 0]
-
- quit_on_unconnected_pdn_nodes
-
- set_def $::env(SAVE_DEF)
-}
-
-proc run_power_grid_generation {args} {
-
- if {[info exists ::env(FP_PDN_POWER_STRAPS)]} {
- set power_domains [split $::env(FP_PDN_POWER_STRAPS) ","]
- }
-
- # internal macros power connections
- if {[info exists ::env(FP_PDN_MACRO_HOOKS)]} {
- set macro_hooks [dict create]
- set pdn_hooks [split $::env(FP_PDN_MACRO_HOOKS) ","]
- foreach pdn_hook $pdn_hooks {
- set instance_name [lindex $pdn_hook 0]
- set power_net [lindex $pdn_hook 1]
- set ground_net [lindex $pdn_hook 2]
- dict append macro_hooks $instance_name [subst {$power_net $ground_net}]
- }
-
- set power_net_indx [lsearch $::env(VDD_NETS) $power_net]
- set ground_net_indx [lsearch $::env(GND_NETS) $ground_net]
-
- # make sure that the specified power domains exist.
- if { $power_net_indx == -1 || $ground_net_indx == -1 || $power_net_indx != $ground_net_indx } {
- puts_err "Can't find $power_net and $ground_net domain. \
- Make sure that both exist in $::env(VDD_NETS) and $::env(GND_NETS)."
- }
- }
-
- # generate multiple power grids per pair of (VDD,GND)
- # offseted by WIDTH + SPACING
- foreach domain $power_domains {
- set ::env(VDD_NET) [lindex $domain 0]
- set ::env(GND_NET) [lindex $domain 1]
- set ::env(_WITH_STRAPS) [lindex $domain 2]
-
- puts_info "Connecting Power: $::env(VDD_NET) & $::env(GND_NET) to All internal macros."
- # internal macros power connections
- set ::env(FP_PDN_MACROS) ""
- if { $::env(FP_PDN_ENABLE_MACROS_GRID) == 1 } {
- # if macros connections to power are explicitly set
- # default behavoir macro pins will be connected to the first power domain
- if { [info exists ::env(FP_PDN_MACRO_HOOKS)] } {
- set ::env(FP_PDN_ENABLE_MACROS_GRID) 0
- foreach {instance_name hooks} $macro_hooks {
- set power [lindex $hooks 0]
- set ground [lindex $hooks 1]
- if { $power == $::env(VDD_NET) && $ground == $::env(GND_NET) } {
- set ::env(FP_PDN_ENABLE_MACROS_GRID) 1
- set ::env(FP_PDN_IRDROP) "1"
- puts_info "Connecting $instance_name to $power and $ground nets."
- lappend ::env(FP_PDN_MACROS) $instance_name
- }
- }
- }
- } else {
- puts_warn "All internal macros will not be connected to power $::env(VDD_NET) & $::env(GND_NET)."
- }
-
- gen_pdn
-
- set ::env(FP_PDN_ENABLE_RAILS) 0
- set ::env(FP_PDN_ENABLE_MACROS_GRID) 0
- set ::env(FP_PDN_IRDROP) "0"
-
- # allow failure until open_pdks is up to date...
- catch {set ::env(FP_PDN_VOFFSET) [expr $::env(FP_PDN_VOFFSET)+$::env(FP_PDN_VWIDTH)+$::env(FP_PDN_VSPACING)]}
- catch {set ::env(FP_PDN_HOFFSET) [expr $::env(FP_PDN_HOFFSET)+$::env(FP_PDN_HWIDTH)+$::env(FP_PDN_HSPACING)]}
-
- catch {set ::env(FP_PDN_CORE_RING_VOFFSET) \
- [expr $::env(FP_PDN_CORE_RING_VOFFSET)\
- +2*($::env(FP_PDN_CORE_RING_VWIDTH)\
- +max($::env(FP_PDN_CORE_RING_VSPACING), $::env(FP_PDN_CORE_RING_HSPACING)))]}
- catch {set ::env(FP_PDN_CORE_RING_HOFFSET) [expr $::env(FP_PDN_CORE_RING_HOFFSET)\
- +2*($::env(FP_PDN_CORE_RING_HWIDTH)+\
- max($::env(FP_PDN_CORE_RING_VSPACING), $::env(FP_PDN_CORE_RING_HSPACING)))]}
- puts "FP_PDN_VOFFSET: $::env(FP_PDN_VOFFSET)"
- puts "FP_PDN_HOFFSET: $::env(FP_PDN_HOFFSET)"
- puts "FP_PDN_CORE_RING_VOFFSET: $::env(FP_PDN_CORE_RING_VOFFSET)"
- puts "FP_PDN_CORE_RING_HOFFSET: $::env(FP_PDN_CORE_RING_HOFFSET)"
-
- }
- set ::env(FP_PDN_ENABLE_RAILS) 1
-}
-
-
-proc run_floorplan {args} {
- puts_info "Running Floorplanning..."
- # |----------------------------------------------------|
- # |---------------- 2. FLOORPLAN ------------------|
- # |----------------------------------------------------|
- #
- # intial fp
- init_floorplan
-
-
- # place io
- if { [info exists ::env(FP_PIN_ORDER_CFG)] } {
- place_io_ol
- } else {
- if { [info exists ::env(FP_CONTEXT_DEF)] && [info exists ::env(FP_CONTEXT_LEF)] } {
- place_io
- global_placement_or
- place_contextualized_io \
- -lef $::env(FP_CONTEXT_LEF) \
- -def $::env(FP_CONTEXT_DEF)
- } else {
- place_io
- }
- }
-
- apply_def_template
-
- if { [info exist ::env(EXTRA_LEFS)] } {
- if { [info exist ::env(MACRO_PLACEMENT_CFG)] } {
- file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(TMP_DIR)/macro_placement.cfg
- manual_macro_placement f
- } else {
- global_placement_or
- basic_macro_placement
- }
- }
-
- # tapcell
- tap_decap_or
- scrot_klayout -layout $::env(CURRENT_DEF)
- # power grid generation
- run_power_grid_generation
-}
-
-
-proc run_flow {args} {
- set script_dir [file dirname [file normalize [info script]]]
-
- set options {
- {-design required}
- {-save_path optional}
- {-no_lvs optional}
- {-no_drc optional}
- {-no_antennacheck optional}
- }
- set flags {-save}
- parse_key_args "run_flow" args arg_values $options flags_map $flags -no_consume
-
- prep {*}$args
-
- set LVS_ENABLED 1
- set DRC_ENABLED 0
- set ANTENNACHECK_ENABLED 1
-
- set steps [dict create \
- "synthesis" {run_synthesis "" } \
- "floorplan" {run_floorplan ""} \
- "placement" {run_placement_step ""} \
- "cts" {run_cts_step ""} \
- "routing" {run_routing_step ""} \
- "diode_insertion" {run_diode_insertion_2_5_step ""} \
- "power_pins_insertion" {run_power_pins_insertion_step ""} \
- "gds_magic" {run_magic ""} \
- "gds_drc_klayout" {run_klayout ""} \
- "gds_xor_klayout" {run_klayout_gds_xor ""} \
- "lvs" "run_lvs_step $LVS_ENABLED" \
- "drc" "run_drc_step $DRC_ENABLED" \
- "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \
- "cvc" {run_lef_cvc}
- ]
-
- set_if_unset arg_values(-to) "cvc";
-
- if { [info exists ::env(CURRENT_STEP) ] } {
- puts "\[INFO\]:Picking up where last execution left off"
- puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)]
- } else {
- set ::env(CURRENT_STEP) "synthesis";
- }
- set_if_unset arg_values(-from) $::env(CURRENT_STEP);
- set exe 0;
- dict for {step_name step_exe} $steps {
- if { [ string equal $arg_values(-from) $step_name ] } {
- set exe 1;
- }
-
- if { $exe } {
- # For when it fails
- set ::env(CURRENT_STEP) $step_name
- [lindex $step_exe 0] [lindex $step_exe 1] ;
- }
-
- if { [ string equal $arg_values(-to) $step_name ] } {
- set exe 0:
- break;
- }
-
- }
-
- # for when it resumes
- set steps_as_list [dict keys $steps]
- set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
- set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
-
- if { [info exists flags_map(-save) ] } {
- if { ! [info exists arg_values(-save_path)] } {
- set arg_values(-save_path) ""
- }
- save_views -lef_path $::env(magic_result_file_tag).lef \
- -def_path $::env(CURRENT_DEF) \
- -gds_path $::env(magic_result_file_tag).gds \
- -mag_path $::env(magic_result_file_tag).mag \
- -maglef_path $::env(magic_result_file_tag).lef.mag \
- -spice_path $::env(magic_result_file_tag).spice \
- -spef_path $::env(CURRENT_SPEF) \
- -verilog_path $::env(CURRENT_NETLIST) \
- -save_path $arg_values(-save_path) \
- -tag $::env(RUN_TAG)
- }
-
-
- calc_total_runtime
- save_state
- generate_final_summary_report
-
- check_timing_violations
-
- puts_success "Flow Completed Without Fatal Errors."
-
-}
-
-run_flow {*}$argv
diff --git a/openlane/user_project_wrapper/mod.tcl b/openlane/user_project_wrapper/mod.tcl
deleted file mode 100644
index 6eeebbe..0000000
--- a/openlane/user_project_wrapper/mod.tcl
+++ /dev/null
@@ -1,73 +0,0 @@
-# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-
-set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
-set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
-set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
-set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
-set ::env(SYNTH_CAP_LOAD) "17.65"
-set ::env(WIRE_RC_LAYER) "met1"
-
-#To disable empty filler cell black box get created
-#set link_make_black_boxes 0
-
-
-set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
-define_corners wc bc
-read_liberty -corner bc $::env(LIB_FASTEST)
-read_liberty -corner wc $::env(LIB_SLOWEST)
-
-# Removing the decap and diode
-read_verilog ../../verilog/gl/clk_buf.v
-link_design clk_buf
-write_verilog -remove_cells [get_lib_cells {sky130_fd_sc_hd__decap* sky130_fd_sc_hd__fill* sky130_fd_sc_hd__diode_* sky130_ef_sc_hd__fakediode* sky130_fd_sc_hd__tapvpwrvgnd*}] netlist/clk_buf.v
-# Removing the decap and diode
-read_verilog ../../verilog/gl/clk_skew_adjust.v
-link_design clk_skew_adjust
-write_verilog -remove_cells [get_lib_cells {sky130_fd_sc_hd__decap* sky130_fd_sc_hd__fill* sky130_fd_sc_hd__diode_* sky130_ef_sc_hd__fakediode* sky130_fd_sc_hd__tapvpwrvgnd*}] netlist/clk_skew_adjust.v
-
-# Removing the decap and diode
-read_verilog ../../verilog/gl/glbl_cfg.v
-link_design glbl_cfg
-write_verilog -remove_cells [get_lib_cells {sky130_fd_sc_hd__decap* sky130_fd_sc_hd__fill* sky130_fd_sc_hd__diode_* sky130_ef_sc_hd__fakediode* sky130_fd_sc_hd__tapvpwrvgnd*}] netlist/glbl_cfg.v
-
-read_verilog ../../verilog/gl/sdram.v
-link_design sdrc_top
-write_verilog -remove_cells [get_lib_cells {sky130_fd_sc_hd__decap* sky130_fd_sc_hd__fill* sky130_fd_sc_hd__diode_* sky130_ef_sc_hd__fakediode* sky130_fd_sc_hd__tapvpwrvgnd*}] netlist/sdram.v
-
-read_verilog ../../verilog/gl/spi_master.v
-link_design spim_top
-write_verilog -remove_cells [get_lib_cells {sky130_fd_sc_hd__decap* sky130_fd_sc_hd__fill* sky130_fd_sc_hd__diode_* sky130_ef_sc_hd__fakediode* sky130_fd_sc_hd__tapvpwrvgnd*}] netlist/spi_master.v
-
-read_verilog ../../verilog/gl/syntacore.v
-link_design scr1_top_wb
-write_verilog -remove_cells [get_lib_cells {sky130_fd_sc_hd__decap* sky130_fd_sc_hd__fill* sky130_fd_sc_hd__diode_* sky130_ef_sc_hd__fakediode* sky130_fd_sc_hd__tapvpwrvgnd*}] netlist/syntacore.v
-
-read_verilog ../../verilog/gl/uart_i2cm_usb.v
-link_design uart_i2c_usb_top
-write_verilog -remove_cells [get_lib_cells {sky130_fd_sc_hd__decap* sky130_fd_sc_hd__fill* sky130_fd_sc_hd__diode_* sky130_ef_sc_hd__fakediode* sky130_fd_sc_hd__tapvpwrvgnd*}] netlist/uart_i2cm_usb.v
-
-read_verilog ../../verilog/gl/wb_host.v
-link_design wb_host
-write_verilog -remove_cells [get_lib_cells {sky130_fd_sc_hd__decap* sky130_fd_sc_hd__fill* sky130_fd_sc_hd__diode_* sky130_ef_sc_hd__fakediode* sky130_fd_sc_hd__tapvpwrvgnd*}] netlist/wb_host.v
-
-read_verilog ../../verilog/gl/wb_interconnect.v
-link_design wb_interconnect
-write_verilog -remove_cells [get_lib_cells {sky130_fd_sc_hd__decap* sky130_fd_sc_hd__fill* sky130_fd_sc_hd__diode_* sky130_ef_sc_hd__fakediode* sky130_fd_sc_hd__tapvpwrvgnd*}] netlist/wb_interconnect.v
-
-
-exit
diff --git a/openlane/user_project_wrapper/sta.tcl b/openlane/user_project_wrapper/sta.tcl
deleted file mode 100644
index 7d1086a..0000000
--- a/openlane/user_project_wrapper/sta.tcl
+++ /dev/null
@@ -1,131 +0,0 @@
-# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
-set ::env(LIB_TYPICAL) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib"
-set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
-set ::env(DESIGN_NAME) "user_project_wrapper"
-set ::env(BASE_SDC_FILE) "base.sdc"
-set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
-set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
-set ::env(SYNTH_CAP_LOAD) "17.65"
-set ::env(WIRE_RC_LAYER) "met1"
-
-#To disable empty filler cell black box get created
-#set link_make_black_boxes 0
-
-
-set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
-define_corners wc bc tt
-read_liberty -corner bc $::env(LIB_FASTEST)
-read_liberty -corner wc $::env(LIB_SLOWEST)
-read_liberty -corner tt $::env(LIB_TYPICAL)
-
-read_lib -corner tt ../../lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
-
-read_verilog netlist/qspim.v
-read_verilog netlist/syntacore.v
-read_verilog netlist/uart_i2cm_usb_spi.v
-read_verilog netlist/wb_host.v
-read_verilog netlist/wb_interconnect.v
-read_verilog netlist/pinmux.v
-read_verilog netlist/sar_adc.v
-read_verilog netlist/user_project_wrapper.v
-
-link_design $::env(DESIGN_NAME)
-
-
-read_spef -path u_riscv_top ../../spef/scr1_top_wb.spef
-read_spef -path u_pinmux ../../spef/pinmux.spef
-read_spef -path u_qspi_master ../../spef/qspim_top.spef
-read_spef -path u_uart_i2c_usb_spi ../../spef/uart_i2c_usb_spi_top.spef
-read_spef -path u_wb_host ../../spef/wb_host.spef
-read_spef -path u_intercon ../../spef/wb_interconnect.spef
-read_spef ../../spef/user_project_wrapper.spef
-
-
-read_sdc -echo $::env(BASE_SDC_FILE)
-
-# check for missing constraints
-check_setup -verbose > unconstraints.rpt
-
-set_operating_conditions -analysis_type single
-# Propgate the clock
-set_propagated_clock [all_clocks]
-
-report_tns
-report_wns
-#report_power
-#
-echo "################ CORNER : WC (MAX) TIMING Report ###################" > timing_ss_max.rpt
-report_checks -unique -slack_max -0.0 -path_delay max -group_count 100 -corner wc -format full_clock_expanded >> timing_ss_max.rpt
-report_checks -group_count 100 -path_delay max -path_group wbm_clk_i -corner wc -format full_clock_expanded >> timing_ss_max.rpt
-report_checks -group_count 100 -path_delay max -path_group wbs_clk_i -corner wc -format full_clock_expanded >> timing_ss_max.rpt
-report_checks -group_count 100 -path_delay max -path_group cpu_clk -corner wc -format full_clock_expanded >> timing_ss_max.rpt
-report_checks -group_count 100 -path_delay max -path_group rtc_clk -corner wc -format full_clock_expanded >> timing_ss_max.rpt
-report_checks -group_count 100 -path_delay max -path_group line_clk -corner wc -format full_clock_expanded >> timing_ss_max.rpt
-report_checks -path_delay max -corner wc >> timing_ss_max.rpt
-
-echo "################ CORNER : WC (MIN) TIMING Report ###################" > timing_ss_min.rpt
-report_checks -unique -slack_max -0.0 -path_delay min -group_count 100 -corner wc -format full_clock_expanded >> timing_ss_min.rpt
-report_checks -group_count 100 -path_delay min -path_group wbm_clk_i -corner wc -format full_clock_expanded >> timing_ss_min.rpt
-report_checks -group_count 100 -path_delay min -path_group wbs_clk_i -corner wc -format full_clock_expanded >> timing_ss_min.rpt
-report_checks -group_count 100 -path_delay min -path_group cpu_clk -corner wc -format full_clock_expanded >> timing_ss_min.rpt
-report_checks -group_count 100 -path_delay min -path_group rtc_clk -corner wc -format full_clock_expanded >> timing_ss_min.rpt
-report_checks -group_count 100 -path_delay min -path_group line_clk -corner wc -format full_clock_expanded >> timing_ss_min.rpt
-report_checks -path_delay min -corner wc >> timing_ss_min.rpt
-
-echo "################ CORNER : BC (MAX) TIMING Report ###################" > timing_ff_max.rpt
-report_checks -unique -slack_max -0.0 -path_delay max -group_count 100 -corner bc -format full_clock_expanded >> timing_ff_max.rpt
-report_checks -group_count 100 -path_delay max -path_group wbm_clk_i -corner bc -format full_clock_expanded >> timing_ff_max.rpt
-report_checks -group_count 100 -path_delay max -path_group wbs_clk_i -corner bc -format full_clock_expanded >> timing_ff_max.rpt
-report_checks -group_count 100 -path_delay max -path_group cpu_clk -corner bc -format full_clock_expanded >> timing_ff_max.rpt
-report_checks -group_count 100 -path_delay max -path_group rtc_clk -corner bc -format full_clock_expanded >> timing_ff_max.rpt
-report_checks -group_count 100 -path_delay max -path_group line_clk -corner bc -format full_clock_expanded >> timing_ff_max.rpt
-report_checks -path_delay max -corner bc >> timing_ff_max.rpt
-
-echo "################ CORNER : BC (MIN) TIMING Report ###################" > timing_ff_min.rpt
-report_checks -unique -slack_max -0.0 -path_delay min -group_count 100 -corner bc -format full_clock_expanded >> timing_ff_min.rpt
-report_checks -group_count 100 -path_delay min -path_group wbm_clk_i -corner bc -format full_clock_expanded >> timing_ff_min.rpt
-report_checks -group_count 100 -path_delay min -path_group wbs_clk_i -corner bc -format full_clock_expanded >> timing_ff_min.rpt
-report_checks -group_count 100 -path_delay min -path_group cpu_clk -corner bc -format full_clock_expanded >> timing_ff_min.rpt
-report_checks -group_count 100 -path_delay min -path_group rtc_clk -corner bc -format full_clock_expanded >> timing_ff_min.rpt
-report_checks -group_count 100 -path_delay min -path_group line_clk -corner bc -format full_clock_expanded >> timing_ff_min.rpt
-report_checks -path_delay min -corner bc >> timing_ff_min.rpt
-
-
-echo "################ CORNER : TT (MAX) TIMING Report ###################" > timing_tt_max.rpt
-report_checks -unique -slack_max -0.0 -path_delay max -group_count 100 -corner tt -format full_clock_expanded >> timing_tt_max.rpt
-report_checks -group_count 100 -path_delay max -path_group wbm_clk_i -corner tt -format full_clock_expanded >> timing_tt_max.rpt
-report_checks -group_count 100 -path_delay max -path_group wbs_clk_i -corner tt -format full_clock_expanded >> timing_tt_max.rpt
-report_checks -group_count 100 -path_delay max -path_group cpu_clk -corner tt -format full_clock_expanded >> timing_tt_max.rpt
-report_checks -group_count 100 -path_delay max -path_group rtc_clk -corner tt -format full_clock_expanded >> timing_tt_max.rpt
-report_checks -group_count 100 -path_delay max -path_group line_clk -corner tt -format full_clock_expanded >> timing_tt_max.rpt
-report_checks -path_delay max -corner tt >> timing_tt_max.rpt
-
-echo "################ CORNER : TT (MIN) TIMING Report ###################" > timing_tt_min.rpt
-report_checks -unique -slack_max -0.0 -path_delay min -group_count 100 -corner tt -format full_clock_expanded >> timing_tt_min.rpt
-report_checks -group_count 100 -path_delay min -path_group wbm_clk_i -corner tt -format full_clock_expanded >> timing_tt_min.rpt
-report_checks -group_count 100 -path_delay min -path_group wbs_clk_i -corner tt -format full_clock_expanded >> timing_tt_min.rpt
-report_checks -group_count 100 -path_delay min -path_group cpu_clk -corner tt -format full_clock_expanded >> timing_tt_min.rpt
-report_checks -group_count 100 -path_delay min -path_group rtc_clk -corner tt -format full_clock_expanded >> timing_tt_min.rpt
-report_checks -group_count 100 -path_delay min -path_group line_clk -corner tt -format full_clock_expanded >> timing_tt_min.rpt
-report_checks -path_delay min -corner tt >> timing_tt_min.rpt
-
-
-report_checks -path_delay min_max
-
-#exit
