mpw6 pd database
diff --git a/Makefile b/Makefile
index 4cd69b5..8769137 100644
--- a/Makefile
+++ b/Makefile
@@ -95,6 +95,7 @@
docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \
-v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
-e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \
+ -e PDK=${PDK} \
-e CARAVEL_ROOT=${CARAVEL_ROOT} \
-e TOOLS=/opt/riscv64i \
-e DESIGNS=$(TARGET_PATH) \
diff --git a/sta/scripts/caravel_timing.tcl b/sta/scripts/caravel_timing.tcl
index 464c419..5d73c61 100644
--- a/sta/scripts/caravel_timing.tcl
+++ b/sta/scripts/caravel_timing.tcl
@@ -1,9 +1,7 @@
- set ::env(USER_ROOT) "/home/dinesha/workarea/opencore/git/riscduino"
- #set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-4/caravel_openframe"
- #set ::env(CARAVEL_PDK_ROOT) "/opt/pdk_mpw4"
- set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-5/caravel"
- set ::env(CARAVEL_PDK_ROOT) "/opt/pdk_mpw4"
+ set ::env(USER_ROOT) ".."
+ set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-6/caravel"
+ set ::env(CARAVEL_PDK_ROOT) "/opt/pdk_mpw6"
read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
@@ -46,7 +44,9 @@
# User project netlist
read_verilog $::env(USER_ROOT)/verilog/gl/qspim_top.v
- read_verilog $::env(USER_ROOT)/verilog/gl/yifive.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/ycr_iconnect.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/ycr_intf.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/ycr_core_top.v
read_verilog $::env(USER_ROOT)/verilog/gl/uart_i2c_usb_spi_top.v
read_verilog $::env(USER_ROOT)/verilog/gl/wb_host.v
read_verilog $::env(USER_ROOT)/verilog/gl/wb_interconnect.v
@@ -105,11 +105,8 @@
read_spef -path \gpio_control_in_2[7] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
read_spef -path \gpio_control_in_2[8] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
read_spef -path \gpio_control_in_2[9] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path gpio_defaults_block_0 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_1803.spef
- read_spef -path gpio_defaults_block_1 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_1803.spef
- read_spef -path gpio_defaults_block_2 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef
- read_spef -path gpio_defaults_block_3 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef
- read_spef -path gpio_defaults_block_4 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef
+ read_spef -path gpio_defaults_block_0[0] $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_0[1] $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
read_spef -path gpio_defaults_block_5 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
read_spef -path gpio_defaults_block_6 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
read_spef -path gpio_defaults_block_7 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
@@ -135,6 +132,9 @@
read_spef -path gpio_defaults_block_27 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
read_spef -path gpio_defaults_block_28 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
read_spef -path gpio_defaults_block_29 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_2[0] $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_2[1] $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_2[2] $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
read_spef -path gpio_defaults_block_30 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
read_spef -path gpio_defaults_block_31 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
read_spef -path gpio_defaults_block_32 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
@@ -145,24 +145,21 @@
read_spef -path gpio_defaults_block_37 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
## User Project Spef
- read_spef -path mprj/u_riscv_top $::env(USER_ROOT)/spef/ycr1_top_wb.spef
- read_spef -path mprj/u_pinmux $::env(USER_ROOT)/spef/pinmux.spef
- read_spef -path mprj/u_qspi_master $::env(USER_ROOT)/spef/qspim_top.spef
- read_spef -path mprj/u_uart_i2c_usb_spi $::env(USER_ROOT)/spef/uart_i2c_usb_spi_top.spef
- read_spef -path mprj/u_wb_host $::env(USER_ROOT)/spef/wb_host.spef
- read_spef -path mprj/u_intercon $::env(USER_ROOT)/spef/wb_interconnect.spef
- read_spef -path mprj/u_tcm_1KB_mem0 $::env(CARAVEL_ROOT)/mgmt_core_wrapper/spef/DFFRAM.spef
- read_spef -path mprj/u_tcm_1KB_mem1 $::env(CARAVEL_ROOT)/mgmt_core_wrapper/spef/DFFRAM.spef
- read_spef -path mprj/u_icache_1KB_mem0 $::env(CARAVEL_ROOT)/mgmt_core_wrapper/spef/DFFRAM.spef
- read_spef -path mprj/u_icache_1KB_mem1 $::env(CARAVEL_ROOT)/mgmt_core_wrapper/spef/DFFRAM.spef
- read_spef -path mprj/u_dcache_1KB_mem0 $::env(CARAVEL_ROOT)/mgmt_core_wrapper/spef/DFFRAM.spef
- read_spef -path mprj/u_dcache_1KB_mem1 $::env(CARAVEL_ROOT)/mgmt_core_wrapper/spef/DFFRAM.spef
- read_spef -path mprj $::env(USER_ROOT)/spef/user_project_wrapper.spef
+
+ read_spef -path mprj/u_riscv_top.u_connect $::env(USER_ROOT)/spef/ycr_iconnect.spef
+ read_spef -path mprj/u_riscv_top.u_intf $::env(USER_ROOT)/spef/ycr_intf.spef
+ read_spef -path mprj/u_riscv_top.i_core_top_0 $::env(USER_ROOT)/spef/ycr_core_top.spef
+ read_spef -path mprj/u_pinmux $::env(USER_ROOT)/spef/pinmux.spef
+ read_spef -path mprj/u_qspi_master $::env(USER_ROOT)/spef/qspim_top.spef
+ read_spef -path mprj/u_uart_i2c_usb_spi $::env(USER_ROOT)/spef/uart_i2c_usb_spi_top.spef
+ read_spef -path mprj/u_wb_host $::env(USER_ROOT)/spef/wb_host.spef
+ read_spef -path mprj/u_intercon $::env(USER_ROOT)/spef/wb_interconnect.spef
+ read_spef -path mprj/u_pll $::env(USER_ROOT)/spef/digital_pll.spef
+ read_spef -path mprj $::env(USER_ROOT)/spef/user_project_wrapper.spef
read_sdc -echo ./sdc/caravel.sdc
set_propagated_clock [all_clocks]
-
check_setup -verbose > unconstraints.rpt
report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50
report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50
@@ -189,117 +186,4 @@
echo "Wishbone Interface Timing for [get_full_name $pin]" >> wb.min.rpt
report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin >> wb.min.rpt
}
-
- #Min Delay check around DFFRAM
- echo "DFFRAM Interface Min Timing.................." > mprj.dffram.min.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem0/WE[*] >> mprj.dffram.min.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem0/EN >> mprj.dffram.min.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem0/Di[*] >> mprj.dffram.min.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem0/A[*] >> mprj.dffram.min.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem0/Do[*] >> mprj.dffram.min.rpt
-
- report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem1/WE[*] >> mprj.dffram.min.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem1/EN >> mprj.dffram.min.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem1/Di[*] >> mprj.dffram.min.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem1/A[*] >> mprj.dffram.min.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem1/Do[*] >> mprj.dffram.min.rpt
-
- report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem0/WE[*] >> mprj.dffram.min.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem0/EN >> mprj.dffram.min.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem0/Di[*] >> mprj.dffram.min.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem0/A[*] >> mprj.dffram.min.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem0/Do[*] >> mprj.dffram.min.rpt
-
- report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem1/WE[*] >> mprj.dffram.min.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem1/EN >> mprj.dffram.min.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem1/Di[*] >> mprj.dffram.min.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem1/A[*] >> mprj.dffram.min.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem1/Do[*] >> mprj.dffram.min.rpt
-
- report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem0/WE[*] >> mprj.dffram.min.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem0/EN >> mprj.dffram.min.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem0/Di[*] >> mprj.dffram.min.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem0/A[*] >> mprj.dffram.min.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem0/A[*] >> mprj.dffram.min.rpt
-
- report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem1/WE[*] >> mprj.dffram.min.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem1/EN >> mprj.dffram.min.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem1/Di[*] >> mprj.dffram.min.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem1/A[*] >> mprj.dffram.min.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem1/Do[*] >> mprj.dffram.min.rpt
-
- #Max Delay check around DFFRAM
- echo "DFFRAM Interface Max Timing.................." > mprj.dffram.max.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem0/WE[*] >> mprj.dffram.max.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem0/EN >> mprj.dffram.max.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem0/Di[*] >> mprj.dffram.max.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem0/A[*] >> mprj.dffram.max.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem0/Do[*] >> mprj.dffram.max.rpt
-
- report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem1/WE[*] >> mprj.dffram.max.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem1/EN >> mprj.dffram.max.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem1/Di[*] >> mprj.dffram.max.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem1/A[*] >> mprj.dffram.max.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem1/Do[*] >> mprj.dffram.max.rpt
-
- report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem0/WE[*] >> mprj.dffram.max.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem0/EN >> mprj.dffram.max.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem0/Di[*] >> mprj.dffram.max.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem0/A[*] >> mprj.dffram.max.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem0/Do[*] >> mprj.dffram.max.rpt
-
- report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem1/WE[*] >> mprj.dffram.max.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem1/EN >> mprj.dffram.max.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem1/Di[*] >> mprj.dffram.max.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem1/A[*] >> mprj.dffram.max.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem1/Do[*] >> mprj.dffram.max.rpt
-
- report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem0/WE[*] >> mprj.dffram.max.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem0/EN >> mprj.dffram.max.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem0/Di[*] >> mprj.dffram.max.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem0/A[*] >> mprj.dffram.max.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem0/A[*] >> mprj.dffram.max.rpt
-
- report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem1/WE[*] >> mprj.dffram.max.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem1/EN >> mprj.dffram.max.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem1/Di[*] >> mprj.dffram.max.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem1/A[*] >> mprj.dffram.max.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem1/Do[*] >> mprj.dffram.max.rpt
-
-
- #Set False path from managment gpio enable towards SPI
- set_false_path -through gpio_control_in_2[10]/mgmt_ena
- set_false_path -through gpio_control_in_2[10]/gpio_outenb
-
- echo " ##### SPI Timing" > spi.rpt
- # SPI Inputs
- report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/u_qspi_master/spi_sdi[0] -from mprj_io[29] >> spi.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/u_qspi_master/spi_sdi[1] -from mprj_io[30] >> spi.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/u_qspi_master/spi_sdi[2] -from mprj_io[31] >> spi.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/u_qspi_master/spi_sdi[3] -from mprj_io[32] >> spi.rpt
-
- report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_in[29] -from mprj_io[29] >> spi.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_in[30] -from mprj_io[30] >> spi.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_in[31] -from mprj_io[31] >> spi.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_in[32] -from mprj_io[32] >> spi.rpt
-
- #SPI output
- report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_out[29] -to mprj_io[29] >> spi.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_out[30] -to mprj_io[30] >> spi.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_out[31] -to mprj_io[31] >> spi.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_out[32] -to mprj_io[32] >> spi.rpt
-
- report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_oeb[29] -to mprj_io[29] >> spi.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_oeb[30] -to mprj_io[30] >> spi.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_oeb[31] -to mprj_io[31] >> spi.rpt
- report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_oeb[32] -to mprj_io[32] >> spi.rpt
-
- report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_out[29] -to mprj_io[29] >> spi.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_out[30] -to mprj_io[30] >> spi.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_out[31] -to mprj_io[31] >> spi.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_out[32] -to mprj_io[32] >> spi.rpt
-
- report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_out[29] -to mprj_io[29] >> spi.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_out[30] -to mprj_io[30] >> spi.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_out[31] -to mprj_io[31] >> spi.rpt
- report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -through mprj/io_out[32] -to mprj_io[32] >> spi.rpt
+
diff --git a/sta/scripts/ycr_core_timing.tcl b/sta/scripts/ycr_core_timing.tcl
new file mode 100644
index 0000000..62484ae
--- /dev/null
+++ b/sta/scripts/ycr_core_timing.tcl
@@ -0,0 +1,83 @@
+
+ set ::env(USER_ROOT) ".."
+ set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-5/caravel"
+ set ::env(CARAVEL_PDK_ROOT) "/opt/pdk_mpw5"
+
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_gpiov2_tt_tt_025C_1v80_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_hvc_wpad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_025C_1v80_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_100C_1v80_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_power_lvc_wpad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib
+
+ # User project netlist
+ read_verilog $::env(USER_ROOT)/verilog/gl/ycr_core_top.v
+
+
+ link_design ycr_core_top
+
+
+ ## User Project Spef
+ read_spef $::env(USER_ROOT)/spef/ycr_core_top.spef
+
+
+ read_sdc -echo ./sdc/ycr_core_top.sdc
+ set_propagated_clock [all_clocks]
+
+ check_setup -verbose > unconstraints.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50
+ report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50
+ report_worst_slack -max
+ report_worst_slack -min
+ report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -slack_max 0.18 -group_count 10
+ report_check_types -max_slew -max_capacitance -max_fanout -violators > slew.cap.fanout.vio.rpt
+
+
+ #Delay check around imem
+ echo "imem Interface Min Timing.................." > imem.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through core2imem_cmd_o >> imem.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through core2imem_req_o >> imem.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through imem2core_req_ack_i >> imem.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through core2imem_addr_o[*] >> imem.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through core2imem_bl_o[*] >> imem.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through imem2core_rdata_i[*] >> imem.min.rpt
+
+ echo "imem Interface max Timing.................." > imem.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through core2imem_cmd_o >> imem.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through core2imem_req_o >> imem.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through imem2core_req_ack_i >> imem.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through core2imem_addr_o[*] >> imem.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through core2imem_bl_o[*] >> imem.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through imem2core_rdata_i[*] >> imem.max.rpt
+
+ #Delay check around imem
+ echo "dmem Interface Min Timing.................." > dmem.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through core2dmem_cmd_o >> dmem.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through core2dmem_req_o >> dmem.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through dmem2core_req_ack_i >> dmem.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through core2dmem_addr_o[*] >> dmem.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through core2dmem_wdata_o[*] >> dmem.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through core2dmem_width_o[*] >> dmem.min.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -through dmem2core_rdata_i[*] >> dmem.min.rpt
+
+ echo "imem Interface max Timing.................." > imem.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through core2dmem_cmd_o >> dmem.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through core2dmem_req_o >> dmem.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through dmem2core_req_ack_i >> dmem.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through core2dmem_addr_o[*] >> dmem.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through core2dmem_wdata_o[*] >> dmem.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through core2dmem_width_o[*] >> dmem.max.rpt
+ report_checks -path_delay max -fields {slew cap input nets fanout} -through dmem2core_rdata_i[*] >> dmem.max.rpt
+
diff --git a/sta/sdc/caravel.sdc b/sta/sdc/caravel.sdc
index f84307f..32f58b5 100644
--- a/sta/sdc/caravel.sdc
+++ b/sta/sdc/caravel.sdc
@@ -14,14 +14,24 @@
#create_clock [get_pins clocking/pll_clk90 ] -name "pll_clk90" -period 25
create_generated_clock -name wb_clk -add -source [get_ports {clock}] -master_clock [get_clocks clock] -divide_by 1 -comment {Wishbone User Clock} [get_pins mprj/wb_clk_i]
-create_clock -name wbs_clk_i -period 15.0000 [get_pins {mprj/u_wb_host/wbs_clk_out}]
-create_clock -name cpu_ref_clk -period 10.0000 [get_pins {mprj/u_wb_host/u_cpu_ref_sel.u_mux/X}]
-create_clock -name cpu_clk -period 20.0000 [get_pins {mprj/u_wb_host/cpu_clk}]
+create_clock -name int_pll_clock -period 5.0000 [get_pins {mprj/u_wb_host/u_clkbuf_pll.u_buf/X}]
+
+create_clock -name wbs_ref_clk -period 5.0000 [get_pins {mprj/u_wb_host/u_wbs_ref_clkbuf.u_buf/X}]
+create_clock -name wbs_clk_i -period 10.0000 [get_pins {mprj/u_wb_host/wbs_clk_out}]
+
+create_clock -name cpu_ref_clk -period 5.0000 [get_pins {mprj/u_wb_host/u_cpu_ref_clkbuf.u_buf/X}]
+create_clock -name cpu_clk -period 10.0000 [get_pins {mprj/u_wb_host/cpu_clk}]
+
create_clock -name rtc_clk -period 50.0000 [get_pins {mprj/u_wb_host/rtc_clk}]
+
+create_clock -name pll_ref_clk -period 20.0000 [get_pins {mprj/u_wb_host/pll_ref_clk}]
+create_clock -name pll_clk_0 -period 5.0000 [get_pins {mprj/u_pll/ringosc.ibufp01/Y}]
+
+create_clock -name usb_ref_clk -period 5.0000 [get_pins {mprj/u_wb_host/u_usb_ref_clkbuf.u_buf/X}]
create_clock -name usb_clk -period 20.0000 [get_pins {mprj/u_wb_host/usb_clk}]
-create_clock -name uarts0_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart0_core.u_lineclk_buf.u_mux/X}]
-create_clock -name uarts1_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart0_core.u_lineclk_buf.u_mux/X}]
-create_clock -name uartm_clk -period 100.0000 [get_pins {mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.u_mux/X}]
+create_clock -name uarts0_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart0_core.u_lineclk_buf.genblk1.u_mux/X}]
+create_clock -name uarts1_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart1_core.u_lineclk_buf.genblk1.u_mux/X}]
+create_clock -name uartm_clk -period 100.0000 [get_pins {mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X}]
## Case analysis
@@ -41,19 +51,19 @@
set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[2]}]
set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[3]}]
-set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[0]}]
+set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[0]}]
set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[1]}]
set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[2]}]
set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[3]}]
-set_case_analysis 0 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[0]}]
-set_case_analysis 0 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[1]}]
-set_case_analysis 1 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[2]}]
-set_case_analysis 1 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[3]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[0]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[2]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[3]}]
set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[0]}]
set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[1]}]
-set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[2]}]
+set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[2]}]
set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[3]}]
set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[0]}]
@@ -62,19 +72,30 @@
set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[3]}]
+#Keept the SRAM clock driving edge at pos edge
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_sram_lphase[0]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_sram_lphase[1]}]
+
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_sram_lphase[0]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_sram_lphase[1]}]
#disable clock gating check at static clock select pins
-set_false_path -through [get_pins mprj/u_wb_host/u_wbs_clk_sel.u_mux/S]
+set_false_path -through [get_pins mprj/u_wb_host/u_wbs_clk_sel.genblk1.u_mux/S]
set_propagated_clock [all_clocks]
set_clock_groups -name async_clock -asynchronous \
- -group [get_clocks {clock wb_clk}]\
+ -group [get_clocks {clock wb_clk }]\
-group [get_clocks {user_clk2}]\
- -group [get_clocks {wbs_clk_i spi_clk}]\
+ -group [get_clocks {int_pll_clock}]\
+ -group [get_clocks {wbs_clk_i}]\
+ -group [get_clocks {wbs_ref_clk}]\
-group [get_clocks {cpu_clk}]\
-group [get_clocks {cpu_ref_clk}]\
-group [get_clocks {rtc_clk}]\
+ -group [get_clocks {usb_ref_clk}]\
+ -group [get_clocks {pll_ref_clk}]\
+ -group [get_clocks {pll_clk_0}]\
-group [get_clocks {usb_clk}]\
-group [get_clocks {uarts0_clk}]\
-group [get_clocks {uarts1_clk}]\
@@ -143,9 +164,8 @@
set_false_path -from [get_ports mprj_io[*]]
set_false_path -from [get_ports gpio]
-## User Project static signals
-set_false_path -through [get_pins mprj/u_pinmux/bist_en]
+# TODO set this as parameter
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
set_load $cap_load [all_outputs]
@@ -160,6 +180,89 @@
set_clock_uncertainty -hold $::env(SYNTH_CLOCK_HOLD_UNCERTAINITY) [all_clocks]
+#set_output_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_adr_i[*]}]
+#set_output_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_cyc_i}]
+#set_output_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_i[*]}]
+#set_output_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_sel_i[*]}]
+#set_output_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_stb_i}]
+#set_output_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_we_i}]
+#
+#set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_adr_i[*]}]
+#set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_cyc_i}]
+#set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_i[*]}]
+#set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_sel_i[*]}]
+#set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_stb_i}]
+#set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_we_i}]
+#
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_ack_o}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[0]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[10]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[11]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[12]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[13]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[14]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[15]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[16]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[17]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[18]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[19]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[1]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[20]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[21]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[22]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[23]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[24]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[25]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[26]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[27]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[28]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[29]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[2]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[30]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[31]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[3]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[4]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[5]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[6]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[7]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[8]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[9]}]
+#
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_ack_o}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[0]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[10]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[11]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[12]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[13]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[14]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[15]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[16]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[17]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[18]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[19]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[1]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[20]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[21]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[22]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[23]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[24]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[25]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[26]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[27]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[28]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[29]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[2]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[30]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[31]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[3]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[4]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[5]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[6]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[7]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[8]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[9]}]
+
+
puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {clock}]
diff --git a/sta/sdc/ycr_core_top.sdc b/sta/sdc/ycr_core_top.sdc
new file mode 100644
index 0000000..0a05d50
--- /dev/null
+++ b/sta/sdc/ycr_core_top.sdc
@@ -0,0 +1,65 @@
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name core_clk -period 10.0000 [get_ports {clk}]
+
+set_clock_transition 0.1500 [all_clocks]
+set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -hold 0.2500 [all_clocks]
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
+#IMEM Constraints
+set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_cmd_o}]
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_req_o}]
+set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_addr_o[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_bl_o[*]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_cmd_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_req_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_addr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_bl_o[*]}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_req_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_rdata_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_resp_i[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_req_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_rdata_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_resp_i[*]}]
+
+#DMEM Constraints
+set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}]
+set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_req_o}]
+set_output_delay -max 2.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_addr_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_wdata_o[*]}]
+set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_width_o[*]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_req_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_addr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_wdata_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_width_o[*]}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_req_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_rdata_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_resp_i[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_req_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_rdata_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_resp_i[*]}]
+
+###############################################################################
+# Environment
+###############################################################################
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} [all_inputs]
+set cap_load 0.0334
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load $cap_load [all_outputs]
+
+###############################################################################
+# Design Rules
+###############################################################################
