Google Git
Sign in
foss-eda-tools / third_party / shuttle / sky130 / mpw-006 / slot-005 / 288d6944726a934f0181c2e1f6bc14c1afa92c7e
commit288d6944726a934f0181c2e1f6bc14c1afa92c7e[log] [tgz]
authordineshannayya <dinesh.annayya@gmail.com>Fri Jul 22 16:30:34 2022 +0530
committerdineshannayya <dinesh.annayya@gmail.com>Fri Jul 22 16:30:34 2022 +0530
tree165b18fe5e379082dc0d45fcd949c9e11cbc4adf
parent86801a99d06b508a30c011c62b410d613f84e382 [diff]
spi isp mode added + mpw7 tool version
30 files changed
tree: 165b18fe5e379082dc0d45fcd949c9e11cbc4adf
  1. checks/
  2. docs/
  3. gds/
  4. hacks/
  5. lef/
  6. lib/
  7. openlane/
  8. signoff/
  9. spef/
  10. spi/
  11. sta/
  12. verilog/
  13. .gitmodules
  14. info.yaml
  15. LICENSE
  16. Makefile
  17. README.md
  18. run_regress
README.md
  Riscduino Quad Risc Core SOC


Permission to use, copy, modify, and/or distribute this soc for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.

THE SOC IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOC INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOC.

Table of contents

Overview

Riscduino is a Quad 32 bit RISC V based SOC design pin compatible to arduino platform and this soc targetted for efabless Shuttle program. This project uses only open source tool set for simulation,synthesis and backend tools. The SOC flow follow the openlane methodology and SOC environment is compatible with efabless/carvel methodology.

Key features

    * Open sourced under Apache-2.0 License (see LICENSE file) - unrestricted commercial use allowed.
    * Quad Core  32 Bit RISC-V core
    * 2KB SRAM for instruction cache 
    * 2KB SRAM for data cache
    * 2KB SRAM for Tightly coupled memory - For Data Memory
    * Quad SPI Master with 4 Chip select, supports both SPI flash and SRAM interface
    * 2 x UART with 16Byte FIFO
    * USB 1.1 Host
    * I2C Master
    * UART Master
    * Simple SPI Master with 4 Chip select
    * 6 Channel ADC (in Progress)
    * 6 x PWM
    * 3 x Timer (16 Bit), 1us/1ms/1second resolution
    * Pin Compatbible to arduino uno
    * Wishbone compatible design
    * Written in System Verilog
    * Open-source tool set
       * simulation - iverilog
       * synthesis  - yosys
       * backend/sta - openlane tool set
    * Verification suite provided.

Riscduino derivatives

MPW Shuttle on Riscduino

SOC Pin Mapping

Carvel SOC provides 38 GPIO pins for user functionality. Riscduino SOC GPIO Pin Mapping as follows vs ATMEGA328 and Arudino

RISC V Core

Riscduino SOC Integrated Quad 32 Bits RISC V core. Initial version of Single core RISC-V core is picked from Syntacore SCR1 (https://github.com/syntacore/scr1)

RISC V core customization for Riscduino SOC

Following Design changes are done on the basic version of syntacore RISC core

   * Some of the sv syntex are changed to standard verilog format to make compatibile with opensource tool iverilog & yosys
   * local Instruction Memory is increased from 4 to 8 location
   * Instruction Request are changed from Single word to 4 Word Burst
   * Multiplication and Divsion are changed to improve timing
   * Additional pipe line stages added to improve the RISC timing closure near to 50Mhz
   * 2KB instruction cache 
   * 2KB data cache
   * Additional router are added towards instruction cache
   * Additional router are added towards data cache
   * Quad core related changes
   * Modified AXI/AHB interface to wishbone interface for instruction and data memory interface

Block Diagram

RISC V Core Key feature

   * RV32I or RV32E ISA base + optional RVM and RVC standard extensions
   * Machine privilege mode only
   * 2 to 5 stage pipeline
   * 2KB icache
   * 2KB dcache
   * Optional Integrated Programmable Interrupt Controller with 16 IRQ lines
   * Optional RISC-V Debug subsystem with JTAG interface
   * Optional on-chip Tightly-Coupled Memory

6 Channel SAR ADC

In Process - Looking for community help ...

SOC Memory Map

SOC Size

BlockTotal CellSeqCombo
RISC20982316417818
PINMUX569310224671
SPI712012815839
UART_I2C_USB_SPI1119624488748
WB_HOST27965882208
WB_INTC18781081770
SAR_ADC11818100
MBIST31255432582
TOTAL52908917243736

SOC Register Map

Register Map: Wishbone HOST
OffsetNameDescription
0x00GLBL_CTRL[RW] Global Wishbone Access Control Register
0x04BANK_CTRL[RW] Bank Selection, MSB 8 bit Address
0x08CLK_SKEW_CTRL1[RW] Clock Skew Control2
0x0cCLK_SKEW_CTRL2[RW] Clock Skew Control2
Register: GLBL_CTRL
BitsNameDescription
31:24ReseveredUnsused
23:20RTC_CLK_CTRLRTC Clock Div Selection
19:16CPU_CLK_CTRLCPU Clock Div Selection
15:12SDARM_CLK_CTRLSDRAM Clock Div Selection
10:8WB_CLK_CTRLCore Wishbone Clock Div Selection
7UART_I2C_SEL0 - UART , 1 - I2C Master IO Selection
5I2C_RSTI2C Reset Control
4UART_RSTUART Reset Control
3SDRAM_RSTSDRAM Reset Control
2SPI_RSTSPI Reset Control
1CPU_RSTCPU Reset Control
0WB_RSTWishbone Core Reset Control
Register: BANK_CTRL
BitsNameDescription
31:24ReseveredUnsused
7:0BANK_SELHolds the upper 8 bit address core Wishbone Address
Register: CLK_SKEW_CTRL1
BitsNameDescription
31:28ReseveredUnsused
27:24CLK_SKEW_WBWishBone Core Clk Skew Control
23:20CLK_SKEW_GLBLGlbal Register Clk Skew Control
19:16CLK_SKEW_SDRAMSDRAM Clk Skew Control
15:12CLK_SKEW_SPISPI Clk Skew Control
11:8CLK_SKEW_UARTUART/I2C Clk Skew Control
7:4CLK_SKEW_RISCRISC Clk Skew Control
3:0CLK_SKEW_WIWishbone Clk Skew Control
Register Map: SPI MASTER
OffsetNameDescription
0x00GLBL_CTRL[RW] Global SPI Access Control Register
0x04DMEM_CTRL1[RW] Direct SPI Memory Access Control Register1
0x08DMEM_CTRL2[RW] Direct SPI Memory Access Control Register2
0x0cIMEM_CTRL1[RW] Indirect SPI Memory Access Control Register1
0x10IMEM_CTRL2[RW] Indirect SPI Memory Access Control Register2
0x14IMEM_ADDR[RW] Indirect SPI Memory Address
0x18IMEM_WDATA[W] Indirect SPI Memory Write Data
0x1cIMEM_RDATA[R] Indirect SPI Memory Read Data
0x20SPI_STATUS[R] SPI Debug Status
Register: GLBL_CTRL
BitsNameDescription
31:16ReseveredUnsused
15:8SPI_CLK_DIVSPI Clock Div Rato Selection
7:4ReservedUnused
3:2CS_LATECS DE_ASSERTION CONTROL
1:0CS_EARLYCS ASSERTION CONTROL
Register: DMEM_CTRL1
BitsNameDescription
31:9ReseveredUnsused
8FSM_RSTDirect Mem State Machine Reset
7:6SPI_SWITCHPhase at which SPI Mode need to switch
5:4SPI_MODESPI Mode, 0 - Single, 1 - Dual, 2 - Quad, 3 - QDDR
3:0CS_SELECTCHIP SELECT
Register: DMEM_CTRL2
BitsNameDescription
31:24DATA_CNTTotal Data Byte Count
23:22DUMMY_CNTTotal Dummy Byte Count
21:20ADDR_CNTTotal Address Byte Count
19:16SPI_SEQSPI Access Sequence
15:8MODE_REGMode Register Value
7:0CMD_REGCommand Register Value
Register: IMEM_CTRL1
BitsNameDescription
31:9ReseveredUnsused
8FSM_RSTInDirect Mem State Machine Reset
7:6SPI_SWITCHPhase at which SPI Mode need to switch
5:4SPI_MODESPI Mode, 0 - Single, 1 - Dual, 2 - Quad, 3 - QDDR
3:0CS_SELECTCHIP SELECT
Register: IMEM_CTRL2
BitsNameDescription
31:24DATA_CNTTotal Data Byte Count
23:22DUMMY_CNTTotal Dummy Byte Count
21:20ADDR_CNTTotal Address Byte Count
19:16SPI_SEQSPI Access Sequence
15:8MODE_REGMode Register Value
7:0CMD_REGCommand Register Value
Register: IMEM_ADDR
BitsNameDescription
31:0ADDRIndirect Memory Address
Register: IMEM_WDATA
BitsNameDescription
31:0WDATAIndirect Memory Write Data
Register: IMEM_RDATA
BitsNameDescription
31:0RDATAIndirect Memory Read Data
Register: SPI_STATUS
BitsNameDescription
31:0DEBUGSPI Debug Status
Register Map: Global Register
OffsetNameDescription
0x00SOFT_REG0[RW] Software Register0
0x04RISC_FUSE[RW] Risc Fuse Value
0x08SOFT_REG2[RW] Software Register2
0x0cINTR_CTRL[RW] Interrupt Control
0x10SDRAM_CTRL1[RW] Indirect SPI Memory Access Control Register2
0x14SDRAM_CTRL2[RW] Indirect SPI Memory Address
0x18SOFT_REG6[RW] Software Register6
0x1CSOFT_REG7[RW] Software Register7
0x20SOFT_REG8[RW] Software Register8
0x24SOFT_REG9[RW] Software Register9
0x28SOFT_REG10[RW] Software Register10
0x2CSOFT_REG11[RW] Software Register11
0x30SOFT_REG12[RW] Software Register12
0x34SOFT_REG13[RW] Software Register13
0x38SOFT_REG14[RW] Software Register14
0x3CSOFT_REG15[RW] Software Register15
Register: RISC_FUSE
BitsNameDescription
31:0RISC_FUSERISC Core Fuse Value
Register: INTR_CTRL
BitsNameDescription
31:20ReservedUnused
19:17USER_IRQUser Interrupt generation toward riscv
16SOFT_IRQSoftware Interrupt generation toward riscv
15:0EXT_IRQExternal Interrupt generation toward riscv

Repository contents

|verilog
|   ├─  rtl
|   |     |-  syntacore
|   |     |     |─  scr1
|   |     |     |    ├─ **docs**                           | **SCR1 documentation**
|   |     |     |    |      ├─ scr1_eas.pdf                | SCR1 External Architecture Specification
|   |     |     |    |      └─ scr1_um.pdf                 | SCR1 User Manual
|   |     |     |    |─  **src**                           | **SCR1 RTL source and testbench files**
|   |     |     |    |   ├─ includes                       | Header files
|   |     |     |    |   ├─ core                           | Core top source files
|   |     |     |    |   ├─ top                            | Cluster source files
|   |     |     |    |─  **synth**                         | **SCR1 RTL Synthesis files **
|   |     |- Qspi_master
|   |     |     |- src                                     | Qard SPI Master Source files
|   |     |-wb_interconnect
|   |     |     |- src                                     | 3x4 Wishbone Interconnect
|   |     |- digital_core
|   |     |     |- src                                     | Digital core Source files
|   |     |- lib                                           | common library source files
|   |- dv
|   |   |- la_test1                                        | carevel LA test
|   |   |- risc_boot                                       | user core risc boot test
|   |   |- wb_port                                         | user wishbone test
|   |   |- user_risc_boot                                  | user standalone test without carevel soc
|   |- gl                                                  | ** GLS Source files **
|
|- openlane
    |- spi_master                                          | spi_master openlane scripts   
    |- syntacore                                           | Risc Core openlane scripts   
    |- user_project_wrapper                                | carvel user project wrapper

Prerequisites

  • Docker (ensure docker daemon is running) -- tested with version 19.03.12, but any recent version should suffice.

Step-1: Docker in ubuntu 20.04 version

   sudo apt update
   sudo apt-get install apt-transport-https curl rtificates -agent software-properties-common
   curl -fsSL https://download.docker.com/linux/ubuntu/gpg | sudo apt-key add -
   sudo add-apt-repository "deb [arch=amd64] https://download.docker.com/linux/ubuntu focal stable"
   sudo apt update
   apt-cache policy docker-ce
   sudo apt install docker-ce

   #Add User Name to docker
   sudo usermod -aG docker <your user name>
   # Reboot the system to enable the docker setup

Step-2: Clone , update the Submodule, unzip the content

   git clone https://github.com/dineshannayya/riscduino.git
   cd riscduino
   git submodule init
   git submodule update
   make unzip

Note-1: RTL to GDS Docker

- Required openlane and pdk are moved inside the riscduino docker to avoid the external dependency. 
- flow automatically pull the required docker based on MPW version.
- RTL to gds docker is hardcoded inside File: openlane/Makefile

     OPENLANE_TAG = mpw6
     OPENLANE_IMAGE_NAME = riscduino/openlane:$(OPENLANE_TAG)

Note-1.1: View the RTL to GDS Docker content

- for MPW-6 caravel pdk and openlane avaible inside riscduino/openlane:mpw6 docker 
- caravel, openlane and pdk envionment are automatically pointed to internal docker pointer
- To view the docker contents

    docker run -ti --rm riscduino/openlane:mpw6  bash
    cd /opt/pdk_mpw6     -  pdk folder
    cd /opt/caravel      -  caravel folder 
    cd /openlane         -  openlane folder
    env   - Show the internally defined env's
        CARAVEL_ROOT=/opt/caravel
        PDK_ROOT=/opt/pdk_mpw6

Note-2: RTL Simulation Docker

- Required caravel and pdk are moved inside the riscduino docker to avoid the external dependency. 
- flow automatically pull the required docker based on MPW version.
- To view the docker contents
- RTL simulation docker hardcoded inside File: Makefile
    simenv:
    docker pull riscduino/dv_setup:mpw6

Note-2.1: View the RTL Simulation Docker content

- for MPW-6 caravel and pdk avaible inside riscduino/dv_setup:mpw6 docker this is used for RTL to gds flows
- caravel and pdk envionment are automatically pointed to internal docker pointer
- To view the docker contents

    docker run -ti --rm riscduino/dv_setup:mpw6  bash
    cd /opt/pdk_mpw6     -  pdk folder
    cd /opt/caravel      -  caravel folder 
    env   - Show the internally defined env's
        CARAVEL_ROOT=/opt/caravel
        PDK_ROOT=/opt/pdk_mpw6

Tests preparation

The simulation package includes the following tests:

  • risc_boot - Complete caravel User Risc core boot
  • wb_port - Complete caravel User Wishbone validation
  • uart_master - complete caravel user uart master test
  • user_risc_boot - Standalone User Risc core boot
  • user_sspi - Standalone SSPI test
  • user_qspi - Standalone Quad SPI test
  • user_spi - Standalone SPI test
  • user_i2c - Standalone I2C test
  • user_usb - Standalone USB Host test
  • user_risc_boot - Standalone Risc Boot test
  • user_uart - Standalone Risc with UART-0 Test
  • user_uart1 - Standalone Risc with UART-1 Test
  • user_gpio - Standalone GPIO Test
  • user_pwm - Standalone pwm Test
  • user_timer - Standalone timer Test
  • user_uart_master - Standalone uart master test
  • riscv_regress - Standalone riscv compliance and regression test suite

Running Simulation

Examples:

    make verify-wb_port                        - User Wishbone Test from caravel
    make verify-risc_boot                      - User Risc core test from caravel
    make verify-uart_master                    - User uart master test from caravel
    make verify-user_basic                     - Standalone Basic signal and clock divider test
    make verify-user_uart                      - Standalone user uart-0 test using user risc core
    make verify-user_uart1                     - Standalone user uart-0 test using user risc core
    make verify-user_i2cm                      - Standalone user i2c test
    make verify-user_risc_boot                 - standalone user risc core-0 boot test
    make verify-user_pwm                       - standalone user pwm test
    make verify-user_timer                     - standalone user timer test
    make verify-user_sspi                      - standalone user spi test
    make verify-user_qspi                      - standalone user quad spi test
    make verify-user_usb                       - standalone user usb host test
    make verify-user_gpio                      - standalone user gpio test
    make verify-user_aes                       - standalone aes test with risc core-0
    make verify-user_cache_bypass              - standalone icache and dcache bypass test with risc core-0
    make verify-user_uart_master               - standalone user uart master test
    make verify-user_sram_exec                 - standalone riscv core-0 test with executing code from data memory
    make verify-riscv_regress                  - standalone riscv compliance test suite
    make verify-arduino_risc_boot              - standalone riscv core-0 boot using arduino tool set
    make verify-arduino_hello_world            - standalone riscv core-0 hello world test using arduino tool set
    make verify-user_mcore                     - standalone riscv multi-core test
    make verify-user_sram_exec RISC_CORE=1     - standalone riscv core-1 test with executing code from data memory
    make verify-user_sram_exec RISC_CORE=2     - standalone riscv core-2 test with executing code from data memory
    make verify-user_sram_exec RISC_CORE=3     - standalone riscv core-3 test with executing code from data memory
    make verify-user_risc_boot RISC_CORE=1     - standalone user risc core-1 boot test
    make verify-user_risc_boot RISC_CORE=2     - standalone user risc core-2 boot test
    make verify-user_risc_boot RISC_CORE=3     - standalone user risc core-3 boot test
    make verify-user_uart RISC_CORE=1          - Standalone user uart test using user risc core-1
    make verify-user_uart RISC_CORE=2          - Standalone user uart test using user risc core-2
    make verify-user_uart RISC_CORE=3          - Standalone user uart test using user risc core-3
    make verify-user_uart1 RISC_CORE=1         - Standalone user uart test using user risc core-1
    make verify-user_uart1 RISC_CORE=2         - Standalone user uart test using user risc core-2
    make verify-user_uart1 RISC_CORE=3         - Standalone user uart test using user risc core-3
    make verify-user_aes  RISC_CORE=1          - standalone aes test with risc core-1
    make verify-user_aes  RISC_CORE=2          - standalone aes test with risc core-1
    make verify-user_aes  RISC_CORE=3          - standalone aes test with risc core-1
    make verify-user_cache_bypass RISC_CORE=1  - standalone icache and dcache bypass test with risc core-1
    make verify-user_cache_bypass RISC_CORE=2  - standalone icache and dcache bypass test with risc core-2
    make verify-user_cache_bypass RISC_CORE=3  - standalone icache and dcache bypass test with risc core-3
    make verify-arduino_risc_boot RISC_CORE=1  - standalone riscv core-1 boot using arduino tool set
    make verify-arduino_risc_boot RISC_CORE=2  - standalone riscv core-1 boot using arduino tool set
    make verify-arduino_risc_boot RISC_CORE=3  - standalone riscv core-1 boot using arduino tool set
    
    make verify-user_uart SIM=RTL DUMP=OFF     - Standalone user uart-0 test using user risc core with waveform dump off
    make verify-user_uart SIM=RTL DUMP=ON      - Standalone user uart-0 test using user risc core with waveform dump on
    make verify-user_uart SIM=GL DUMP=OFF      - Standalone user uart-0 test using user risc core with gatelevel netlist
    make verify-user_uart SIM=GL DUMP=ON       - Standalone user uart-0 test using user risc core with gatelevel netlist and waveform on

Running RTL to GDS flows

  • First run the individual macro file
  • Last run the user_project_wrapper
   cd openlane
   make pinmux
   make qspim_top
   make uart_i2cm_usb_spi_top
   make wb_host
   make wb_interconnect
   make ycr_intf
   make ycr_core_top
   make ycr_iconnect
   make user_project_wrapper

Tool Sets

Riscduino Soc flow uses Openlane tool sets.

  1. Synthesis
    1. yosys - Performs RTL synthesis
    2. abc - Performs technology mapping
    3. OpenSTA - Pefroms static timing analysis on the resulting netlist to generate timing reports
  2. Floorplan and PDN
    1. init_fp - Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing)
    2. ioplacer - Places the macro input and output ports
    3. pdn - Generates the power distribution network
    4. tapcell - Inserts welltap and decap cells in the floorplan
  3. Placement
    1. RePLace - Performs global placement
    2. Resizer - Performs optional optimizations on the design
    3. OpenPhySyn - Performs timing optimizations on the design
    4. OpenDP - Perfroms detailed placement to legalize the globally placed components
  4. CTS
    1. TritonCTS - Synthesizes the clock distribution network (the clock tree)
  5. Routing
    1. FastRoute - Performs global routing to generate a guide file for the detailed router
    2. CU-GR - Another option for performing global routing.
    3. TritonRoute - Performs detailed routing
    4. SPEF-Extractor - Performs SPEF extraction
  6. GDSII Generation
    1. Magic - Streams out the final GDSII layout file from the routed def
    2. Klayout - Streams out the final GDSII layout file from the routed def as a back-up
  7. Checks
    1. Magic - Performs DRC Checks & Antenna Checks
    2. Klayout - Performs DRC Checks
    3. Netgen - Performs LVS Checks
    4. CVC - Performs Circuit Validity Checks

Riscduino documentation

Riscduino documentation available at <https://riscduino.readthedocs.io/en/latest/>

Arduino ide integration

We are in initial phase of Riscduino board integration into arduino and integration details are available at <https://github.com/dineshannayya/riscduino_board/>

News

How To Contribute

We are looking for community help in following activity, interested user can ping me in efabless slack platform

  • Analog Design - ADC, DAC, PLL,
  • Digital Design - New IP Integration, Encription,DSP, Floating point functions
  • Verification - Improving the Verification flow
  • Linux Porting - Build Root integration
  • Arudino Software Update - Tool Customisation for Riscduino, Adding additional plug-in and Riscv compilation support
  • Riscv Simulator - integration to Riscduino
  • Any other ideas

Contacts

Report an issue: https://github.com/dineshannayya/riscduino_qcore/issues

Documentation

News on Riscduino