commit eaa0c9009a5e04598b46627d2d449b6d86d77b78
author dineshannayya <dinesh.annayya@gmail.com> Thu May 26 22:13:48 2022 +0530
committer dineshannayya <dinesh.annayya@gmail.com> Thu May 26 22:13:48 2022 +0530
tree bed8158be1f441adb8d9bc0af33085d4b1ef01c5
parent 4cc944c1a571a4ebdf34ed0ffa68a437b45385a5

ctech bug fix

verilog/rtl/lib/ctech_cells.sv

diff --git a/verilog/rtl/lib/ctech_cells.sv b/verilog/rtl/lib/ctech_cells.sv
index f28fced..ebbd617 100644
--- a/verilog/rtl/lib/ctech_cells.sv
+++ b/verilog/rtl/lib/ctech_cells.sv
@@ -8,7 +8,17 @@
 `ifndef SYNTHESIS
 assign X = (S) ? A1 : A0;
 `else 
-sky130_fd_sc_hd__mux2_8 u_mux (.A0 (A0), .A1 (A1), .S  (S), .X (X));
+    generate
+       if (WB > 1)
+       begin : bus_
+         genvar tcnt;
+         for (tcnt = 0; $unsigned(tcnt) < WB; tcnt=tcnt+1) begin : bit_
+             sky130_fd_sc_hd__mux2_8 u_mux (.A0 (A0[tcnt]), .A1 (A1[tcnt]), .S  (S), .X (X[tcnt]));
+         end
+       end else begin : bit_
+          sky130_fd_sc_hd__mux2_8 u_mux (.A0 (A0), .A1 (A1), .S  (S), .X (X));
+       end
+    endgenerate
 `endif
 
 endmodule
@@ -22,7 +32,17 @@
 `ifndef SYNTHESIS
 assign X = (S) ? A1 : A0;
 `else 
-sky130_fd_sc_hd__mux2_2 u_mux (.A0 (A0), .A1 (A1), .S  (S), .X (X));
+    generate
+       if (WB > 1)
+       begin : bus_
+         genvar tcnt;
+         for (tcnt = 0; $unsigned(tcnt) < WB; tcnt=tcnt+1) begin : bit_
+             sky130_fd_sc_hd__mux2_2 u_mux (.A0 (A0[tcnt]), .A1 (A1[tcnt]), .S  (S), .X (X[tcnt]));
+         end
+       end else begin : bit_
+          sky130_fd_sc_hd__mux2_2 u_mux (.A0 (A0), .A1 (A1), .S  (S), .X (X));
+       end
+    endgenerate
 `endif
 
 endmodule
@@ -36,7 +56,17 @@
 `ifndef SYNTHESIS
 assign X = (S) ? A1 : A0;
 `else 
-sky130_fd_sc_hd__mux2_4 u_mux (.A0 (A0), .A1 (A1), .S  (S), .X (X));
+    generate
+       if (WB > 1)
+       begin : bus_
+         genvar tcnt;
+         for (tcnt = 0; $unsigned(tcnt) < WB; tcnt=tcnt+1) begin : bit_
+             sky130_fd_sc_hd__mux2_4 u_mux (.A0 (A0[tcnt]), .A1 (A1[tcnt]), .S  (S), .X (X[tcnt]));
+         end
+       end else begin : bit_
+          sky130_fd_sc_hd__mux2_4 u_mux (.A0 (A0), .A1 (A1), .S  (S), .X (X));
+       end
+    endgenerate
 `endif
 
 endmodule

verilog/rtl/yifive/ycr4c

diff --git a/verilog/rtl/yifive/ycr4c b/verilog/rtl/yifive/ycr4c
index e153157..724e944 160000
--- a/verilog/rtl/yifive/ycr4c
+++ b/verilog/rtl/yifive/ycr4c
@@ -1 +1 @@
-Subproject commit e153157fa5b26f62d23fe6cb3e7922b113efe5d4
+Subproject commit 724e944688a135294783a4e41f82d13e66a401c1