Doc update

README.md

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     <td  align="center"> 18-June-2021  </td>
     <td  align="center"> YiFive</td>
     <td  align="center"> Single 32bit RISCV core without cache + SDRAM Controller + WB Interconnect</td>
-    <td  align="center"> <a href="https://github.com/dineshannayya/yifive">Github</td>
-    <td  align="center"> <a href="https://platform.efabless.com/projects/152">Efabless</td>
+    <td  align="center"> <a href="https://github.com/dineshannayya/yifive">Github</a></td>
+    <td  align="center"> <a href="https://platform.efabless.com/projects/152">Efabless</a></td>
   </tr>
   <tr>
     <td  align="center"> MPW-3 </td>