sspi bug fix and wb interconnect update for cross bar

diff --git a/openlane/Makefile b/openlane/Makefile
index d5f37cb..efd2b9b 100644
--- a/openlane/Makefile
+++ b/openlane/Makefile

@@ -19,8 +19,8 @@
 CONFIG = $(foreach block,$(BLOCKS), ./$(block)/config.tcl)
 CLEAN = $(foreach block,$(BLOCKS), clean-$(block))
 
-OPENLANE_TAG ?= mpw4
-OPENLANE_IMAGE_NAME ?= riscduino/openlane:$(OPENLANE_TAG)
+OPENLANE_TAG = mpw5
+OPENLANE_IMAGE_NAME = riscduino/openlane:$(OPENLANE_TAG)
 OPENLANE_BASIC_COMMAND = "cd /project/openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
 OPENLANE_INTERACTIVE_COMMAND = "cd /project/openlane && flow.tcl -it -file ./$*/interactive.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
 
@@ -31,33 +31,17 @@
 	@exit 1
 
 $(BLOCKS) : % : ./%/config.tcl FORCE
-ifeq ($(OPENLANE_ROOT),)
-	@echo "Please export OPENLANE_ROOT"
-	@exit 1
-endif
-ifeq ($(PDK_ROOT),)
-	@echo "Please export PDK_ROOT"
-	@exit 1
-endif
 	@echo "###############################################"
 	@sleep 1
 
 	@if [ -f ./$*/interactive.tcl ]; then\
 		docker run -it -v $(OPENLANE_ROOT):/openLANE_flow \
-		-v $(PDK_ROOT):$(PDK_ROOT) \
 		-v $(PWD)/..:/project \
-		-v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
-		-e PDK_ROOT=$(PDK_ROOT) \
-		-e CARAVEL_ROOT=$(CARAVEL_ROOT) \
 		-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
 		$(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_INTERACTIVE_COMMAND);\
 	else\
 		docker run -it -v $(OPENLANE_ROOT):/openLANE_flow \
-		-v $(PDK_ROOT):$(PDK_ROOT) \
 		-v $(PWD)/..:/project \
-		-v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
-		-e PDK_ROOT=$(PDK_ROOT) \
-		-e CARAVEL_ROOT=$(CARAVEL_ROOT) \
 		-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
 		$(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_BASIC_COMMAND);\
 	fi
@@ -66,17 +50,6 @@
 	cp $*/runs/$*/PDK_SOURCES ../signoff/$*/
 	cp $*/runs/$*/reports/final_summary_report.csv ../signoff/$*/
 
-.PHONY: openlane
-openlane:
-ifeq ($(OPENLANE_ROOT),)
-	@echo "Please export OPENLANE_ROOT"
-	@exit 1
-endif
-	git clone https://github.com/efabless/OpenLane --branch=$(OPENLANE_TAG) --depth=1 $(OPENLANE_ROOT) && \
-		cd $(OPENLANE_ROOT) && \
-		export IMAGE_NAME=efabless/openlane:$(OPENLANE_TAG) && \
-		make openlane
-
 FORCE:
 
 clean:

diff --git a/openlane/Read.me b/openlane/Read.me
new file mode 100644
index 0000000..c0c9895
--- /dev/null
+++ b/openlane/Read.me

@@ -0,0 +1,3 @@
+ycr2_mintf harden with riscduino/openlane:mpw4  (mpw5 version not able to root due to conjuestion)
+Rest of the cores & top-level are  harden with riscduino/openlane:mpw5 docker
+

diff --git a/openlane/pinmux/base.sdc b/openlane/pinmux/base.sdc
index bea31b6..91f9b40 100644
--- a/openlane/pinmux/base.sdc
+++ b/openlane/pinmux/base.sdc

@@ -44,11 +44,16 @@
 set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wr}]
 
 
-set_output_delay -max 4.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_ack}]
-set_output_delay -max 4.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_ack}]
+set_output_delay -max 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[*]}]
 
-set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_ack}]
-set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[*]}]
+set_output_delay -min -3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_ack}]
+set_output_delay -min -3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[*]}]
+
+
+set_output_delay -max 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {qspim_rst_n}]
+set_output_delay -min -3.000 -clock [get_clocks {mclk}] -add_delay [get_ports {qspim_rst_n}]
+
 ###############################################################################
 # Environment
 ###############################################################################

diff --git a/openlane/pinmux/config.tcl b/openlane/pinmux/config.tcl
index 25a4a16..f082733 100755
--- a/openlane/pinmux/config.tcl
+++ b/openlane/pinmux/config.tcl

@@ -96,6 +96,7 @@
 set ::env(FP_PDN_VWIDTH) 5
 set ::env(FP_PDN_HWIDTH) 5
 
+set ::env(GLB_RT_MAXLAYER) 5
 set ::env(RT_MAX_LAYER) {met4}
 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 

diff --git a/openlane/qspim/base.sdc b/openlane/qspim_top/base.sdc
similarity index 76%
rename from openlane/qspim/base.sdc
rename to openlane/qspim_top/base.sdc
index 4c12420..327d1f4 100644
--- a/openlane/qspim/base.sdc
+++ b/openlane/qspim_top/base.sdc

@@ -269,75 +269,13 @@
 set_max_delay  10.0000 -to [get_ports {spi_debug[8]}]
 set_max_delay  10.0000 -to [get_ports {spi_debug[9]}]
 
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_ack_o}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[0]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[10]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[11]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[12]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[13]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[14]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[15]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[16]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[17]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[18]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[19]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[1]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[20]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[21]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[22]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[23]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[24]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[25]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[26]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[27]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[28]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[29]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[2]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[30]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[31]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[3]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[4]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[5]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[6]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[7]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[8]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[9]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_err_o}]
+set_output_delay -max 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_ack_o}]
+set_output_delay -max 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_err_o}]
 
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_ack_o}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[0]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[10]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[11]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[12]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[13]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[14]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[15]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[16]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[17]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[18]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[19]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[1]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[20]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[21]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[22]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[23]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[24]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[25]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[26]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[27]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[28]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[29]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[2]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[30]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[31]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[3]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[4]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[5]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[6]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[7]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[8]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[9]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_err_o}]
+set_output_delay -min -2.7500 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_ack_o}]
+set_output_delay -min -2.7500 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[*]}]
+set_output_delay -min -2.7500 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_err_o}]
 ###############################################################################
 # Environment
 ###############################################################################

diff --git a/openlane/qspim/config.tcl b/openlane/qspim_top/config.tcl
similarity index 98%
rename from openlane/qspim/config.tcl
rename to openlane/qspim_top/config.tcl
index 129e657..e2a3b24 100755
--- a/openlane/qspim/config.tcl
+++ b/openlane/qspim_top/config.tcl

@@ -93,6 +93,7 @@
 set ::env(FP_PDN_VWIDTH) 5
 set ::env(FP_PDN_HWIDTH) 5
 
+set ::env(GLB_RT_MAXLAYER) 5
 set ::env(RT_MAX_LAYER) {met4}
 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 set ::env(DIODE_INSERTION_STRATEGY) 4

diff --git a/openlane/qspim/pdn.tcl b/openlane/qspim_top/pdn.tcl
similarity index 100%
rename from openlane/qspim/pdn.tcl
rename to openlane/qspim_top/pdn.tcl


diff --git a/openlane/qspim/pin_order.cfg b/openlane/qspim_top/pin_order.cfg
similarity index 100%
rename from openlane/qspim/pin_order.cfg
rename to openlane/qspim_top/pin_order.cfg


diff --git a/openlane/qspim/sta.tcl b/openlane/qspim_top/sta.tcl
similarity index 100%
rename from openlane/qspim/sta.tcl
rename to openlane/qspim_top/sta.tcl


diff --git a/openlane/uart_i2cm_usb_spi/base.sdc b/openlane/uart_i2cm_usb_spi_top/base.sdc
similarity index 83%
rename from openlane/uart_i2cm_usb_spi/base.sdc
rename to openlane/uart_i2cm_usb_spi_top/base.sdc
index bee06d8..36725cd 100644
--- a/openlane/uart_i2cm_usb_spi/base.sdc
+++ b/openlane/uart_i2cm_usb_spi_top/base.sdc

@@ -52,11 +52,17 @@
 set_input_delay  -min 2.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_wr}]
 
 
-set_output_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_ack}]
-set_output_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_rdata[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_ack}]
+set_output_delay -max 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_rdata[*]}]
 
-set_output_delay -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_ack}]
-set_output_delay -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_rdata[*]}]
+set_output_delay -min -2.7500 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_ack}]
+set_output_delay -min -2.7500 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_rdata[*]}]
+
+set_multicycle_path -setup  -from [get_ports {reg_addr[*]}] -to [get_ports {reg_ack}] 2
+set_multicycle_path -setup  -from [get_ports {reg_addr[*]}] -to [get_ports {reg_rdata[*]}] 2
+
+set_multicycle_path -hold  -from [get_ports {reg_addr[*]}] -to [get_ports {reg_ack}] 1
+set_multicycle_path -hold  -from [get_ports {reg_addr[*]}] -to [get_ports {reg_rdata[*]}] 1
 
 ###############################################################################
 # Environment

diff --git a/openlane/uart_i2cm_usb_spi/config.tcl b/openlane/uart_i2cm_usb_spi_top/config.tcl
similarity index 97%
rename from openlane/uart_i2cm_usb_spi/config.tcl
rename to openlane/uart_i2cm_usb_spi_top/config.tcl
index 026ba3c..48ac117 100644
--- a/openlane/uart_i2cm_usb_spi/config.tcl
+++ b/openlane/uart_i2cm_usb_spi_top/config.tcl

@@ -114,10 +114,14 @@
 set ::env(FP_PDN_VWIDTH) 5
 set ::env(FP_PDN_HWIDTH) 5
 
+set ::env(GLB_RT_MAXLAYER) 5
 set ::env(RT_MAX_LAYER) {met4}
 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 set ::env(DIODE_INSERTION_STRATEGY) 4
 
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {1}
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {1}
+
 set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
 set ::env(QUIT_ON_MAGIC_DRC) "1"
 set ::env(QUIT_ON_LVS_ERROR) "0"

diff --git a/openlane/uart_i2cm_usb_spi/pdn.tcl b/openlane/uart_i2cm_usb_spi_top/pdn.tcl
similarity index 100%
rename from openlane/uart_i2cm_usb_spi/pdn.tcl
rename to openlane/uart_i2cm_usb_spi_top/pdn.tcl


diff --git a/openlane/uart_i2cm_usb_spi/pin_order.cfg b/openlane/uart_i2cm_usb_spi_top/pin_order.cfg
similarity index 100%
rename from openlane/uart_i2cm_usb_spi/pin_order.cfg
rename to openlane/uart_i2cm_usb_spi_top/pin_order.cfg


diff --git a/openlane/uart_i2cm_usb_spi/sta.tcl b/openlane/uart_i2cm_usb_spi_top/sta.tcl
similarity index 100%
rename from openlane/uart_i2cm_usb_spi/sta.tcl
rename to openlane/uart_i2cm_usb_spi_top/sta.tcl


diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 4ca67f1..6cb3902 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl

@@ -20,11 +20,11 @@
 set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
 
 # YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS 
-source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl
+source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/fixed_wrapper_cfgs.tcl
 
 
 # YOU CAN CHANGE ANY VARIABLES DEFINED IN THE DEFAULT WRAPPER CFGS BY OVERRIDING THEM IN THIS CONFIG.TCL
-source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper_empty/default_wrapper_cfgs.tcl
+source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/default_wrapper_cfgs.tcl
 
 
 set script_dir [file dirname [file normalize [info script]]]
@@ -71,7 +71,7 @@
         $proj_dir/../../verilog/gl/qspim_top.v \
         $proj_dir/../../verilog/gl/wb_interconnect.v \
         $proj_dir/../../verilog/gl/pinmux.v     \
-        $proj_dir/../../verilog/gl/uart_i2cm_usb_spi.v     \
+        $proj_dir/../../verilog/gl/uart_i2c_usb_spi_top.v     \
 	$proj_dir/../../verilog/gl/wb_host.v \
 	$proj_dir/../../verilog/gl/ycr2_mintf.v \
 	$proj_dir/../../verilog/gl/ycr_core_top.v \
@@ -82,7 +82,7 @@
 	$lef_root/qspim_top.lef \
 	$lef_root/pinmux.lef \
 	$lef_root/wb_interconnect.lef \
-	$lef_root/uart_i2cm_usb_spi.lef \
+	$lef_root/uart_i2c_usb_spi_top.lef \
 	$lef_root/wb_host.lef \
 	$lef_root/ycr2_mintf.lef \
 	$lef_root/ycr_core_top.lef \
@@ -93,7 +93,7 @@
 	$gds_root/qspim_top.gds \
 	$gds_root/pinmux.gds \
 	$gds_root/wb_interconnect.gds \
-	$gds_root/uart_i2cm_usb_spi.gds \
+	$gds_root/uart_i2c_usb_spi_top.gds \
 	$gds_root/wb_host.gds \
 	$gds_root/ycr2_mintf.gds \
 	$gds_root/ycr_core_top.gds \
@@ -104,6 +104,7 @@
 
 set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr2c/src/includes ]
 
+set ::env(GLB_RT_MAXLAYER) 6
 set ::env(RT_MAX_LAYER) {met5}
 
 set ::env(FP_PDN_CHECK_NODES) 0
@@ -176,9 +177,8 @@
 set ::env(QUIT_ON_NEGATIVE_WNS) "0"
 set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
 set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
-set ::env(QUIT_ON_TR_DRC) "0"
 
-set ::env(FP_PDN_IRDROP) "1"
+set ::env(FP_PDN_IRDROP) "0"
 set ::env(FP_PDN_HORIZONTAL_HALO) "10"
 set ::env(FP_PDN_VERTICAL_HALO) "10"
 

diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl
index 45668cd..92de09f 100644
--- a/openlane/user_project_wrapper/interactive.tcl
+++ b/openlane/user_project_wrapper/interactive.tcl

@@ -223,7 +223,7 @@
 					set ground [lindex $hooks 1]			 
 					if { $power == $::env(VDD_NET) && $ground == $::env(GND_NET) } {
 						set ::env(FP_PDN_ENABLE_MACROS_GRID) 1
-                                                set ::env(FP_PDN_IRDROP) "1"
+                                                set ::env(FP_PDN_IRDROP) "0"
 						puts_info "Connecting $instance_name to $power and $ground nets."
 						lappend ::env(FP_PDN_MACROS) $instance_name
 					}

diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index ea9cf65..b9d6ef1 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg

@@ -1,6 +1,6 @@
-u_qspi_master                2225             700           N
-u_uart_i2c_usb_spi           2225            1400           N
-u_pinmux                     2225            2300           N
+u_qspi_master                2250             700           N
+u_uart_i2c_usb_spi           2250            1400           N
+u_pinmux                     2250            2300           N
 
 u_riscv_top.i_core_top_0    150	            1500	   N
 u_riscv_top.i_core_top_1    950	            1500	   N

diff --git a/openlane/wb_host/base.sdc b/openlane/wb_host/base.sdc
index ee8410c..9d9cc79 100644
--- a/openlane/wb_host/base.sdc
+++ b/openlane/wb_host/base.sdc

@@ -71,19 +71,19 @@
 set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_ack_i}]
 set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[*]}]
 
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[*]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_cyc_o}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[*]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[*]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_stb_o}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_we_o}]
+set_output_delay -max 3.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[*]}]
+set_output_delay -max 3.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_cyc_o}]
+set_output_delay -max 3.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[*]}]
+set_output_delay -max 3.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[*]}]
+set_output_delay -max 3.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_stb_o}]
+set_output_delay -max 3.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_we_o}]
 
-set_output_delay -min -1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[*]}]
-set_output_delay -min -1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_cyc_o}]
-set_output_delay -min -1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[*]}]
-set_output_delay -min -1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[*]}]
-set_output_delay -min -1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_stb_o}]
-set_output_delay -min -1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_we_o}]
+set_output_delay -min -1.7500 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[*]}]
+set_output_delay -min -1.7500 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_cyc_o}]
+set_output_delay -min -1.7500 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[*]}]
+set_output_delay -min -1.7500 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[*]}]
+set_output_delay -min -1.7500 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_stb_o}]
+set_output_delay -min -1.7500 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_we_o}]
 
 ###############################################################################
 # Environment

diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
index 7c2708c..1dabc40 100755
--- a/openlane/wb_host/config.tcl
+++ b/openlane/wb_host/config.tcl

@@ -97,6 +97,7 @@
 set ::env(FP_PDN_VWIDTH) 5
 set ::env(FP_PDN_HWIDTH) 5
 
+set ::env(GLB_RT_MAXLAYER) 5
 set ::env(RT_MAX_LAYER) {met4}
 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 

diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index c5f0155..d0ccab1 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl

@@ -44,6 +44,7 @@
         $script_dir/../../verilog/rtl/lib/sync_wbb.sv                \
         $script_dir/../../verilog/rtl/lib/sync_fifo2.sv                \
         $script_dir/../../verilog/rtl/wb_interconnect/src/wb_arb.sv     \
+        $script_dir/../../verilog/rtl/wb_interconnect/src/wb_slave_port.sv  \
         $script_dir/../../verilog/rtl/wb_interconnect/src/wb_interconnect.sv  \
 	"
 
@@ -69,7 +70,7 @@
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 200 2300"
+set ::env(DIE_AREA) "0 0 320 1800"
 
 
 # If you're going to use multiple power domains, then keep this disabled.
@@ -77,17 +78,11 @@
 
 #set ::env(PDN_CFG) $script_dir/pdn.tcl
 
-## PDN
-set ::env(FP_PDN_CORE_RING) 0
-set ::env(FP_PDN_VPITCH) 120
-set ::env(FP_PDN_HPITCH) 120
-
-set ::env(FP_PDN_VWIDTH) 1.6
-set ::env(FP_PDN_CORE_RING_VWIDTH) 1.6
 
 
 set ::env(PL_TIME_DRIVEN) 1
-set ::env(PL_TARGET_DENSITY) "0.30"
+set ::env(PL_TARGET_DENSITY) "0.20"
+set ::env(CELL_PAD) "10"
 
 # helps in anteena fix
 set ::env(USE_ARC_ANTENNA_CHECK) "0"
@@ -118,6 +113,7 @@
 set ::env(GLB_RT_ALLOW_CONGESTION) 0
 set ::env(GLB_RT_OVERFLOW_ITERS) 200
 
+set ::env(GLB_RT_MAXLAYER) 5
 set ::env(RT_MAX_LAYER) {met4}
 
 

diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg
index d9fb1bd..e722a83 100644
--- a/openlane/wb_interconnect/pin_order.cfg
+++ b/openlane/wb_interconnect/pin_order.cfg

@@ -147,14 +147,64 @@
 
 
 #W
-ch_data_out\[3\]     0000 0 2
+ch_data_out\[68\]   0750 0 2
+ch_data_out\[67\] 
+ch_data_out\[66\] 
+ch_data_out\[65\] 
+ch_data_out\[64\] 
+ch_data_out\[63\] 
+ch_data_out\[62\] 
+ch_data_out\[61\] 
+ch_data_out\[60\] 
+ch_data_out\[59\] 
+ch_data_out\[58\] 
+ch_data_out\[57\] 
+ch_data_out\[56\] 
+ch_data_out\[55\] 
+ch_data_out\[54\] 
+ch_data_out\[53\] 
+ch_data_out\[52\] 
+ch_data_out\[51\] 
+ch_data_out\[50\] 
+ch_data_out\[49\] 
+ch_data_out\[48\] 
+ch_data_out\[47\] 
+ch_data_out\[46\] 
+ch_data_out\[45\] 
+ch_data_out\[44\] 
+ch_data_out\[43\] 
+ch_data_out\[42\] 
+ch_data_out\[41\] 
+ch_data_out\[40\] 
+ch_data_out\[39\] 
+ch_data_out\[38\] 
+ch_data_out\[37\] 
+ch_data_out\[36\] 
+ch_data_out\[35\] 
+ch_data_out\[34\] 
+ch_data_out\[33\] 
+ch_data_out\[32\] 
+ch_data_out\[31\] 
+ch_data_out\[30\] 
+ch_data_out\[29\] 
+ch_data_out\[28\] 
+ch_data_out\[27\] 
+ch_data_out\[26\] 
+ch_data_out\[25\] 
+ch_data_out\[24\] 
+ch_data_out\[23\] 
+ch_data_out\[22\] 
+ch_data_out\[21\] 
+ch_data_out\[20\] 
+
+ch_data_out\[3\]   
 ch_data_out\[2\]
 ch_data_out\[1\]
 ch_data_out\[0\]
 
 ch_clk_out\[0\]
 
-m1_wbd_stb_i         0100 0 2 
+m1_wbd_stb_i         0950 0 2 
 m1_wbd_we_i         
 m1_wbd_adr_i\[31\]  
 m1_wbd_adr_i\[30\]  
@@ -261,7 +311,7 @@
 m1_wbd_err_o        
 m1_wbd_cyc_i        
 
-m2_wbd_stb_i        250 0 2
+m2_wbd_stb_i        1150 0 2
 m2_wbd_we_i         
 m2_wbd_adr_i\[31\]  
 m2_wbd_adr_i\[30\]  
@@ -379,7 +429,7 @@
 m2_wbd_err_o        
 m2_wbd_cyc_i       
 
-m3_wbd_stb_i        450 0 2
+m3_wbd_stb_i        1350 0 2
 m3_wbd_we_i         
 m3_wbd_adr_i\[31\]  
 m3_wbd_adr_i\[30\]  
@@ -465,55 +515,6 @@
 m3_wbd_err_o        
 m3_wbd_cyc_i       
 
-ch_data_out\[68\]   0750 0 2
-ch_data_out\[67\] 
-ch_data_out\[66\] 
-ch_data_out\[65\] 
-ch_data_out\[64\] 
-ch_data_out\[63\] 
-ch_data_out\[62\] 
-ch_data_out\[61\] 
-ch_data_out\[60\] 
-ch_data_out\[59\] 
-ch_data_out\[58\] 
-ch_data_out\[57\] 
-ch_data_out\[56\] 
-ch_data_out\[55\] 
-ch_data_out\[54\] 
-ch_data_out\[53\] 
-ch_data_out\[52\] 
-ch_data_out\[51\] 
-ch_data_out\[50\] 
-ch_data_out\[49\] 
-ch_data_out\[48\] 
-ch_data_out\[47\] 
-ch_data_out\[46\] 
-ch_data_out\[45\] 
-ch_data_out\[44\] 
-ch_data_out\[43\] 
-ch_data_out\[42\] 
-ch_data_out\[41\] 
-ch_data_out\[40\] 
-ch_data_out\[39\] 
-ch_data_out\[38\] 
-ch_data_out\[37\] 
-ch_data_out\[36\] 
-ch_data_out\[35\] 
-ch_data_out\[34\] 
-ch_data_out\[33\] 
-ch_data_out\[32\] 
-ch_data_out\[31\] 
-ch_data_out\[30\] 
-ch_data_out\[29\] 
-ch_data_out\[28\] 
-ch_data_out\[27\] 
-ch_data_out\[26\] 
-ch_data_out\[25\] 
-ch_data_out\[24\] 
-ch_data_out\[23\] 
-ch_data_out\[22\] 
-ch_data_out\[21\] 
-ch_data_out\[20\] 
 
 #E
 ch_data_out\[19\]   0000 0  2  
@@ -731,7 +732,7 @@
 s1_wbd_ack_i        
 s1_wbd_cyc_o  
 
-ch_data_in\[68\]  1600 0 2  
+ch_data_in\[68\]  1400 0 2  
 ch_data_in\[67\]
 ch_data_in\[66\]
 ch_data_in\[65\]
@@ -787,7 +788,7 @@
 ch_data_out\[12\]
 ch_clk_out\[3\]
 
-s2_wbd_stb_o         1800 0 2
+s2_wbd_stb_o         1500 0 2
 s2_wbd_we_o         
 s2_wbd_adr_o\[7\]   
 s2_wbd_adr_o\[6\]   

diff --git a/signoff/pinmux/final_summary_report.csv b/signoff/pinmux/final_summary_report.csv
index 422cccf..e2baeec 100644
--- a/signoff/pinmux/final_summary_report.csv
+++ b/signoff/pinmux/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/pinmux,pinmux,pinmux,flow completed,0h7m46s0ms,0h5m1s0ms,43806.06060606061,0.2475,21903.030303030304,26.1,891.37,5421,0,0,0,0,0,0,0,-1,0,-1,-1,427475,54258,0.0,-0.31,-1,0.0,0.0,0.0,-0.96,-1,0.0,0.0,341607677.0,0.0,56.96,41.66,30.97,18.6,-1,3480,8519,562,5601,0,0,0,4063,123,107,40,77,933,109,14,285,1086,1034,11,314,3259,0,3573,100.0,10.0,10,AREA 0,4,50,1,100,100,0.3,0.3,sky130_fd_sc_hd,4,4
+0,/project/openlane/pinmux,pinmux,pinmux,flow completed,0h11m25s0ms,0h7m6s0ms,43806.06060606061,0.2475,21903.030303030304,26.1,892.25,5421,0,0,0,0,0,0,0,-1,0,-1,-1,436360,55335,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,340333025.0,0.0,57.99,42.16,31.77,19.51,-1,3480,8519,562,5601,0,0,0,4063,123,107,40,77,933,109,14,285,1086,1034,11,314,3259,0,3573,100.0,10.0,10,AREA 0,4,50,1,100,100,0.3,0.3,sky130_fd_sc_hd,4,4

diff --git a/signoff/qspim_top/OPENLANE_VERSION b/signoff/qspim_top/OPENLANE_VERSION
new file mode 100644
index 0000000..80c7664
--- /dev/null
+++ b/signoff/qspim_top/OPENLANE_VERSION

@@ -0,0 +1 @@
+openlane N/A

diff --git a/signoff/qspim_top/PDK_SOURCES b/signoff/qspim_top/PDK_SOURCES
new file mode 100644
index 0000000..22e7dc1
--- /dev/null
+++ b/signoff/qspim_top/PDK_SOURCES

@@ -0,0 +1,3 @@
+openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f
+skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46

diff --git a/signoff/qspim_top/final_summary_report.csv b/signoff/qspim_top/final_summary_report.csv
new file mode 100644
index 0000000..1bf2607
--- /dev/null
+++ b/signoff/qspim_top/final_summary_report.csv

@@ -0,0 +1,2 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/qspim_top,qspim_top,qspim_top,flow completed,0h15m15s0ms,0h11m13s0ms,65696.9696969697,0.2475,32848.48484848485,37.92,1082.31,8130,0,0,0,0,0,0,0,-1,0,-1,-1,419590,71747,-0.55,-5.04,-1,0.0,0.0,-21.45,-1943.78,-1,0.0,0.0,256460720.0,0.0,50.47,49.05,23.05,22.36,-1,7374,11038,803,4466,0,0,0,8348,263,96,195,114,1420,214,34,1460,1553,1517,17,388,3234,0,3622,100.0,10.0,10,AREA 0,4,50,1,100,100,0.42,0.3,sky130_fd_sc_hd,4,4

diff --git a/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION b/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION
new file mode 100644
index 0000000..80c7664
--- /dev/null
+++ b/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION

@@ -0,0 +1 @@
+openlane N/A

diff --git a/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES b/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES
new file mode 100644
index 0000000..22e7dc1
--- /dev/null
+++ b/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES

@@ -0,0 +1,3 @@
+openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f
+skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46

diff --git a/signoff/uart_i2cm_usb_spi_top/final_summary_report.csv b/signoff/uart_i2cm_usb_spi_top/final_summary_report.csv
new file mode 100644
index 0000000..1ae8e4f
--- /dev/null
+++ b/signoff/uart_i2cm_usb_spi_top/final_summary_report.csv

@@ -0,0 +1,2 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/uart_i2cm_usb_spi_top,uart_i2c_usb_spi_top,uart_i2cm_usb_spi_top,flow completed,0h19m27s0ms,0h14m25s0ms,69400.0,0.35,34700.0,39.27,1540.1,12145,0,0,0,0,0,0,0,-1,0,-1,-1,630996,105793,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,373528655.0,0.0,53.48,52.78,23.7,25.92,-1,8698,13063,1552,5853,0,0,0,9820,378,189,259,276,2194,356,86,807,2409,2348,19,498,4643,0,5141,100.0,10.0,10,AREA 0,4,50,1,100,100,0.45,0.3,sky130_fd_sc_hd,4,4

diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 6910b9d..5386c94 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,0h43m48s0ms,0h4m4s0ms,-2.0,-1,-1,-1,589.75,11,0,0,0,0,0,0,-1,0,0,-1,-1,1906026,14065,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,7.76,7.73,2.42,0.84,0.0,318,3364,318,3364,0,0,0,11,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,100,0.55,0.3,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,0h47m50s0ms,0h5m25s0ms,-2.0,-1,-1,-1,607.65,11,0,0,0,0,0,0,-1,0,0,-1,-1,2484327,19911,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,8.49,12.26,3.27,2.9,0.0,318,3364,318,3364,0,0,0,11,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,100,0.55,0.3,sky130_fd_sc_hd,4,0

diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv
index 6a37170..5698503 100644
--- a/signoff/wb_host/final_summary_report.csv
+++ b/signoff/wb_host/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_host,wb_host,wb_host,flow completed,0h5m54s0ms,0h4m3s0ms,60517.64705882353,0.14875,30258.823529411766,36.67,777.48,4501,0,0,0,0,0,0,0,4,0,0,-1,207083,36502,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,156702042.0,0.0,46.57,48.25,3.69,11.24,-1,3461,6134,1009,3538,0,0,0,3773,372,52,74,184,652,130,23,458,1014,989,11,296,1950,0,2246,100.0,10.0,10,AREA 0,4,50,1,100,100,0.38,0.3,sky130_fd_sc_hd,4,4
+0,/project/openlane/wb_host,wb_host,wb_host,flow completed,0h5m37s0ms,0h3m37s0ms,60517.64705882353,0.14875,30258.823529411766,36.67,759.41,4501,0,0,0,0,0,0,0,9,0,0,-1,206351,36529,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,156181924.0,0.0,45.83,48.0,4.16,12.69,-1,3461,6134,1009,3538,0,0,0,3773,372,52,74,184,652,130,23,458,1014,989,11,296,1950,0,2246,100.0,10.0,10,AREA 0,4,50,1,100,100,0.38,0.3,sky130_fd_sc_hd,4,4

diff --git a/signoff/wb_interconnect/final_summary_report.csv b/signoff/wb_interconnect/final_summary_report.csv
index 481675a..c0d17f6 100644
--- a/signoff/wb_interconnect/final_summary_report.csv
+++ b/signoff/wb_interconnect/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow completed,0h35m55s0ms,0h32m6s0ms,22860.869565217392,0.46,11430.434782608696,9.82,1061.57,5258,0,0,0,0,0,0,0,-1,0,-1,-1,900638,55837,0.0,-2.26,-1,-1.76,-2.22,0.0,-101.82,-1,-197.22,-286.21,832828329.0,0.0,24.44,49.29,2.25,39.09,-1,1460,4695,237,3471,0,0,0,2321,146,4,12,55,280,29,6,550,919,860,20,1674,5873,0,7547,81.8330605564648,12.22,10,AREA 0,2,50,1,120,120,0.3,0,sky130_fd_sc_hd,4,4
+0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow completed,0h46m54s0ms,0h40m26s0ms,37937.5,0.5760000000000001,18968.75,16.98,1608.16,10926,0,0,0,0,0,0,0,-1,0,-1,-1,1075525,94792,-1.53,-3.34,-1,-2.98,-3.4,-106.67,-233.97,-1,-293.74,-303.87,834639052.0,0.0,25.33,47.4,4.97,27.65,-1,3846,12928,637,9716,0,0,0,5341,269,12,304,131,626,98,13,1402,1753,1688,16,1306,7532,0,8838,74.6268656716418,13.4,10,AREA 0,2,50,1,153.6,153.18,0.2,0,sky130_fd_sc_hd,10,4

diff --git a/signoff/ycr2_mintf/OPENLANE_VERSION b/signoff/ycr2_mintf/OPENLANE_VERSION
new file mode 100644
index 0000000..80c7664
--- /dev/null
+++ b/signoff/ycr2_mintf/OPENLANE_VERSION

@@ -0,0 +1 @@
+openlane N/A

diff --git a/signoff/ycr2_mintf/PDK_SOURCES b/signoff/ycr2_mintf/PDK_SOURCES
new file mode 100644
index 0000000..ca3684a
--- /dev/null
+++ b/signoff/ycr2_mintf/PDK_SOURCES

@@ -0,0 +1,6 @@
+-ne openlane 
+8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b
+-ne skywater-pdk 
+c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+-ne open_pdks 
+14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad

diff --git a/signoff/ycr2_mintf/final_summary_report.csv b/signoff/ycr2_mintf/final_summary_report.csv
new file mode 100644
index 0000000..098dfda
--- /dev/null
+++ b/signoff/ycr2_mintf/final_summary_report.csv

@@ -0,0 +1,2 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/ycr2_mintf,ycr2_mintf,ycr2_mintf,flow_completed,0h55m36s,-1,59950.0,0.56,29975.0,34.63,1318.32,16786,0,-1,-1,-1,-1,0,0,-1,0,0,-1,1417781,196456,-10.62,-28.82,-1,0.0,-1,-17949.18,-46631.03,-1,0.0,-1,1008802804.0,17.72,59.07,49.55,18.1,3.02,-1,12554,26414,1451,14949,0,0,0,15249,0,0,0,0,0,0,0,4,4400,4298,34,498,7655,0,8153,90.9090909090909,11,10,AREA 0,4,50,1,153.6,153.18,0.36,0.0,sky130_fd_sc_hd,4,4

diff --git a/signoff/ycr_core/OPENLANE_VERSION b/signoff/ycr_core/OPENLANE_VERSION
new file mode 100644
index 0000000..80c7664
--- /dev/null
+++ b/signoff/ycr_core/OPENLANE_VERSION

@@ -0,0 +1 @@
+openlane N/A

diff --git a/signoff/ycr_core/PDK_SOURCES b/signoff/ycr_core/PDK_SOURCES
new file mode 100644
index 0000000..22e7dc1
--- /dev/null
+++ b/signoff/ycr_core/PDK_SOURCES

@@ -0,0 +1,3 @@
+openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f
+skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46

diff --git a/signoff/ycr_core/final_summary_report.csv b/signoff/ycr_core/final_summary_report.csv
new file mode 100644
index 0000000..e9b99da
--- /dev/null
+++ b/signoff/ycr_core/final_summary_report.csv

@@ -0,0 +1,2 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/ycr_core,ycr_core_top,ycr_core,flow completed,0h21m21s0ms,0h12m57s0ms,68215.12605042018,0.595,34107.56302521009,34.04,2244.03,20294,0,0,0,0,0,0,0,56,0,0,-1,1315671,191055,-23.39,-45.73,-1,0.0,0.0,-25027.54,-49475.34,-1,0.0,0.0,971204312.0,0.0,59.17,62.72,31.36,43.72,-1,16419,22655,510,6646,0,0,0,19197,693,255,524,595,2870,895,265,4812,2529,2405,42,608,8109,0,8717,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.36,0.3,sky130_fd_sc_hd,4,4

diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index c721d0f..836d0cd 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile

@@ -19,7 +19,7 @@
 .SUFFIXES:
 .SILENT: clean all
 
-PATTERNS = wb_port risc_boot user_risc_boot user_uart user_spi user_i2cm riscv_regress user_basic user_uart_master uart_master
+PATTERNS = wb_port risc_boot user_risc_boot user_uart user_qspi user_i2cm riscv_regress user_basic user_uart_master uart_master
 
 all:  ${PATTERNS}
 	for i in ${PATTERNS}; do \

diff --git a/verilog/dv/risc_boot/risc_boot.c b/verilog/dv/risc_boot/risc_boot.c
index 126b3c1..3e42aaa 100644
--- a/verilog/dv/risc_boot/risc_boot.c
+++ b/verilog/dv/risc_boot/risc_boot.c

@@ -178,7 +178,7 @@
 
 
     // Remove All Reset
-    reg_mprj_globl_reg2 = 0x21F;
+    reg_mprj_globl_reg2 = 0x11F;
 
     // Enable UART Multi Functional Ports
 

diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v
index bc4db63..766e403 100644
--- a/verilog/dv/risc_boot/risc_boot_tb.v
+++ b/verilog/dv/risc_boot/risc_boot_tb.v

@@ -71,6 +71,8 @@
 
 `timescale 1 ns / 1 ps
 
+`define FULL_CHIP_SIM
+
 `include "s25fl256s.sv"
 `include "uprj_netlists.v"
 `include "caravel_netlists.v"
@@ -312,7 +314,7 @@
 //-----------------------------------------
 
    wire user_flash_clk = mprj_io[24];
-   wire user_flash_csb = mprj_io[28];
+   wire user_flash_csb = mprj_io[25];
    //tri  user_flash_io0 = mprj_io[26];
    //tri  user_flash_io1 = mprj_io[27];
    //tri  user_flash_io2 = mprj_io[28];

diff --git a/verilog/dv/riscv_regress/user_risc_regress_tb.v b/verilog/dv/riscv_regress/user_risc_regress_tb.v
index c23fe35..eac26f5 100644
--- a/verilog/dv/riscv_regress/user_risc_regress_tb.v
+++ b/verilog/dv/riscv_regress/user_risc_regress_tb.v

@@ -392,7 +392,7 @@
 //  ----------------------------------------------------
 
    wire flash_clk = io_out[24];
-   wire flash_csb = io_out[28];
+   wire flash_csb = io_out[25];
    // Creating Pad Delay
    wire #1 io_oeb_29 = io_oeb[29];
    wire #1 io_oeb_30 = io_oeb[30];
@@ -427,7 +427,7 @@
        );
 
 
-   wire spiram_csb = io_out[26];
+   wire spiram_csb = io_out[27];
 
    is62wvs1288 #(.mem_file_name("none"))
 	u_sram (

diff --git a/verilog/dv/uart_master/uart_master_tb.v b/verilog/dv/uart_master/uart_master_tb.v
index 8a7f66e..4636dce 100644
--- a/verilog/dv/uart_master/uart_master_tb.v
+++ b/verilog/dv/uart_master/uart_master_tb.v

@@ -17,6 +17,8 @@
 
 `timescale 1 ns / 1 ps
 
+`define FULL_CHIP_SIM
+
 `include "uprj_netlists.v"
 `include "caravel_netlists.v"
 `include "spiflash.v"

diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index 18fbad1..99e0acb 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v

@@ -242,8 +242,8 @@
          wb_user_core_write('h3080_0000,'h1);
 
 	 wb_user_core_read_check(32'h30020058,read_data,32'h8273_8343);
-	 wb_user_core_read_check(32'h3002005C,read_data,32'h1402_2022);
-	 wb_user_core_read_check(32'h30020060,read_data,32'h0003_4000);
+	 wb_user_core_read_check(32'h3002005C,read_data,32'h0203_2022);
+	 wb_user_core_read_check(32'h30020060,read_data,32'h0003_7000);
 
       end
    

diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v
index b56a263..f0bed30 100644
--- a/verilog/dv/user_i2cm/user_i2cm_tb.v
+++ b/verilog/dv/user_i2cm/user_i2cm_tb.v

@@ -358,7 +358,7 @@
 //  ----------------------------------------------------
 
    wire flash_clk = io_out[24];
-   wire flash_csb = io_out[28];
+   wire flash_csb = io_out[25];
    // Creating Pad Delay
    wire #1 io_oeb_29 = io_oeb[29];
    wire #1 io_oeb_30 = io_oeb[30];

diff --git a/verilog/dv/user_spi/Makefile b/verilog/dv/user_qspi/Makefile
similarity index 99%
rename from verilog/dv/user_spi/Makefile
rename to verilog/dv/user_qspi/Makefile
index bedef96..250d502 100644
--- a/verilog/dv/user_spi/Makefile
+++ b/verilog/dv/user_qspi/Makefile

@@ -50,7 +50,7 @@
 
 .SUFFIXES:
 
-PATTERN = user_spi
+PATTERN = user_qspi
 
 all:  ${PATTERN:=.vcd}
 

diff --git a/verilog/dv/user_spi/flash0.hex b/verilog/dv/user_qspi/flash0.hex
similarity index 100%
rename from verilog/dv/user_spi/flash0.hex
rename to verilog/dv/user_qspi/flash0.hex


diff --git a/verilog/dv/user_spi/flash1.hex b/verilog/dv/user_qspi/flash1.hex
similarity index 100%
copy from verilog/dv/user_spi/flash1.hex
copy to verilog/dv/user_qspi/flash1.hex


diff --git a/verilog/dv/user_spi/run_iverilog b/verilog/dv/user_qspi/run_iverilog
similarity index 100%
rename from verilog/dv/user_spi/run_iverilog
rename to verilog/dv/user_qspi/run_iverilog


diff --git a/verilog/dv/user_spi/user_spi_tb.v b/verilog/dv/user_qspi/user_qspi_tb.v
similarity index 99%
rename from verilog/dv/user_spi/user_spi_tb.v
rename to verilog/dv/user_qspi/user_qspi_tb.v
index 97b7c9f..4a35096 100644
--- a/verilog/dv/user_spi/user_spi_tb.v
+++ b/verilog/dv/user_qspi/user_qspi_tb.v

@@ -103,7 +103,7 @@
 
  `define ADDR_SPACE_PINMUX  32'h3002_0000
 
-module user_spi_tb;
+module user_qspi_tb;
 	reg clock;
 	reg wb_rst_i;
 	reg power1, power2;
@@ -207,7 +207,7 @@
 	`ifdef WFDUMP
 	   initial begin
 	   	$dumpfile("simx.vcd");
-	   	$dumpvars(5, user_spi_tb);
+	   	$dumpvars(5, user_qspi_tb);
 	   end
        `endif
 
@@ -1229,7 +1229,7 @@
 //  ----------------------------------------------------
 
    wire flash_clk = io_out[24];
-   wire flash_csb = io_out[28];
+   wire flash_csb = io_out[25];
    // Creating Pad Delay
    wire #1 io_oeb_29 = io_oeb[29];
    wire #1 io_oeb_30 = io_oeb[30];
@@ -1263,7 +1263,7 @@
 
        );
 
-   wire spiram_csb = io_out[26];
+   wire spiram_csb = io_out[27];
 
    is62wvs1288 #(.mem_file_name("flash1.hex"))
 	u_sfram (
@@ -1358,7 +1358,7 @@
   wbd_ext_sel_i ='h0;  // byte enable
   if(data !== cmp_data) begin
      $display("ERROR : WB USER ACCESS READ  Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
-     user_spi_tb.test_fail = 1;
+     user_qspi_tb.test_fail = 1;
   end else begin
      $display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,data);
   end

diff --git a/verilog/dv/user_spi/user_risc_boot.c b/verilog/dv/user_qspi/user_risc_boot.c
similarity index 100%
rename from verilog/dv/user_spi/user_risc_boot.c
rename to verilog/dv/user_qspi/user_risc_boot.c


diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
index 11360d2..4d4e731 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v

@@ -267,7 +267,7 @@
 //  ----------------------------------------------------
 
    wire flash_clk = io_out[24];
-   wire flash_csb = io_out[28];
+   wire flash_csb = io_out[25];
    // Creating Pad Delay
    wire #1 io_oeb_29 = io_oeb[29];
    wire #1 io_oeb_30 = io_oeb[30];

diff --git a/verilog/dv/user_sspi/.flash1.hex.swp b/verilog/dv/user_sspi/.flash1.hex.swp
new file mode 100644
index 0000000..efe36dc
--- /dev/null
+++ b/verilog/dv/user_sspi/.flash1.hex.swp
Binary files differ

diff --git a/verilog/dv/user_sspi/.sspi_task.v.swp b/verilog/dv/user_sspi/.sspi_task.v.swp
new file mode 100644
index 0000000..ecd1440
--- /dev/null
+++ b/verilog/dv/user_sspi/.sspi_task.v.swp
Binary files differ

diff --git a/verilog/dv/user_sspi/.user_sspi_tb.v.swp b/verilog/dv/user_sspi/.user_sspi_tb.v.swp
new file mode 100644
index 0000000..7af26eb
--- /dev/null
+++ b/verilog/dv/user_sspi/.user_sspi_tb.v.swp
Binary files differ

diff --git a/verilog/dv/user_spi/Makefile b/verilog/dv/user_sspi/Makefile
similarity index 98%
copy from verilog/dv/user_spi/Makefile
copy to verilog/dv/user_sspi/Makefile
index bedef96..0f8d1a7 100644
--- a/verilog/dv/user_spi/Makefile
+++ b/verilog/dv/user_sspi/Makefile

@@ -42,7 +42,7 @@
 ## RISCV GCC 
 GCC_PATH?=/ef/apps/bin
 GCC_PREFIX?=riscv32-unknown-elf
-PDK_PATH?=/ef/tech/SW/sky130A
+PDK_PATH?=/opt/pdk/sky130A
 
 ## Simulation mode: RTL/GL
 SIM?=RTL
@@ -50,7 +50,7 @@
 
 .SUFFIXES:
 
-PATTERN = user_spi
+PATTERN = user_sspi
 
 all:  ${PATTERN:=.vcd}
 

diff --git a/verilog/dv/user_spi/flash1.hex b/verilog/dv/user_sspi/flash1.hex
similarity index 100%
rename from verilog/dv/user_spi/flash1.hex
rename to verilog/dv/user_sspi/flash1.hex


diff --git a/verilog/dv/user_sspi/sspi_task.v b/verilog/dv/user_sspi/sspi_task.v
new file mode 100755
index 0000000..1ce38eb
--- /dev/null
+++ b/verilog/dv/user_sspi/sspi_task.v

@@ -0,0 +1,350 @@
+
+// #################################################################
+// Module: spi tasks
+//
+// Description : All ST and ATMEL commands are made into tasks
+// Note: CMD+ADDRESS Sent is Big Endian
+//       Write Data/Read Data Send as Little endian to match RISCV
+//       Data accesss
+// #################################################################
+
+parameter LITTLE_ENDIAN  = 1'b0;
+parameter BIG_ENDIAN     = 1'b1;
+
+event      sspi_error_detected;
+reg  [1:0] sspi_chip_no;
+
+integer sspi_err_cnt;
+
+task sspi_init;
+begin
+   sspi_err_cnt = 0;
+   sspi_chip_no = 0;
+end 
+endtask 
+
+
+always @sspi_error_detected
+begin
+    `TB_GLBL.test_err;
+     sspi_err_cnt = sspi_err_cnt + 1;
+end
+//***** Read Double Word Data from Specific Address ******//
+task sspi_dw_read;
+    input    [7:0]  cmd;
+    input    [23:0] address;
+    output   [31:0] read_data;
+    reg      [31:0] read_data;
+begin
+      sspi_write_dword({cmd,address[23:0]},BIG_ENDIAN,8'h0);
+      sspi_write_byte(32'h00,BIG_ENDIAN,8'h0);  // 8 Bit Dummy Cycle
+      sspi_read_dword(LITTLE_ENDIAN,read_data,8'h1);
+
+end
+endtask
+
+task sspi_dw_write;
+    input    [7:0]  cmd;
+    input    [23:0] address;
+    input   [31:0] write_data;
+begin
+      sspi_write_dword({cmd,address[23:0]},BIG_ENDIAN,8'h0);
+      sspi_write_dword(write_data,LITTLE_ENDIAN,8'h1);
+
+end
+endtask
+
+task sspi_dw_read_check;
+    input    [7:0]  cmd;
+    input    [23:0] address;
+    input    [31:0] exp_data;
+    reg      [31:0] read_data;
+begin
+      sspi_write_dword({cmd,address[23:0]},BIG_ENDIAN,8'h0);
+      sspi_write_byte(32'h00,BIG_ENDIAN,8'h0);  // 8 Bit Dummy Cycle
+      sspi_read_dword(LITTLE_ENDIAN,read_data,8'h1);
+      if(read_data != exp_data) begin
+         -> sspi_error_detected;
+         $display("%m : ERROR :  Address: %x Exp : %x Rxd : %x",address,exp_data,read_data);
+      end else begin
+         $display("%m : STATUS : Address: %x Matched : %x ",address,read_data);
+      end
+
+end
+endtask
+
+// Write One Byte
+task sspi_write_byte;
+    input [7:0] datain;
+    input       endian;
+    input [7:0] cs_byte;
+    reg  [31:0] read_data;
+    begin
+
+      @(posedge `TB_GLBL.clock) 
+      `TB_GLBL.wb_user_core_write(`ADDR_SPACE_SSPI+'h4,{datain,24'h0});
+      `TB_GLBL.wb_user_core_write(`ADDR_SPACE_SSPI+'h0,{1'b1,5'h0,
+	                        endian,
+                                spi_chip_no[1:0],
+                                2'b0,    // Write Operatopm
+                                2'b0,    // Single Transfer
+                                6'h10,    // sck clock period
+                                5'h2,    // cs setup/hold period
+                                cs_byte }); // cs bit 0x40 for 1 byte transaction
+      
+     `TB_GLBL.wb_user_core_read(`ADDR_SPACE_SSPI+'h0,read_data);
+     while(read_data[31]) begin
+        @(posedge `TB_GLBL.clock) ;
+        `TB_GLBL.wb_user_core_read(`ADDR_SPACE_SSPI+'h0,read_data);
+      end 
+    end
+endtask
+
+//***** ST : Write Enable task ******//
+task sspi_write_dword;
+    input [31:0] cmd;
+    input        endian; // 0 - Little,1 - Big
+    input [7:0]  cs_byte;
+    reg   [31:0] read_data;
+    begin
+      @(posedge `TB_GLBL.clock) 
+      `TB_GLBL.wb_user_core_write(`ADDR_SPACE_SSPI+'h4,{cmd});
+      `TB_GLBL.wb_user_core_write(`ADDR_SPACE_SSPI+'h0,{1'b1,5'h0,
+	                        endian,
+                                spi_chip_no[1:0],
+                                2'b0,    // Write Operatopm
+                                2'h3,    // 4 Transfer
+                                6'h10,    // sck clock period
+                                5'h2,    // cs setup/hold period
+                                cs_byte[7:0] }); // cs bit information
+      
+     `TB_GLBL.wb_user_core_read(`ADDR_SPACE_SSPI+'h0,read_data);
+     while(read_data[31]) begin
+        @(posedge `TB_GLBL.clock) ;
+        `TB_GLBL.wb_user_core_read(`ADDR_SPACE_SSPI+'h0,read_data);
+      end 
+    end
+endtask
+
+
+//***** ST : Write Enable task ******//
+task sspi_read_dword;
+    input         endian;
+    output [31:0] dataout;
+    input  [7:0]  cs_byte;
+    reg    [31:0] read_data;
+    begin
+
+      @(posedge `TB_GLBL.clock) 
+      `TB_GLBL.wb_user_core_write(`ADDR_SPACE_SSPI+'h0,{1'b1,5'h0,
+	                        endian,
+                                spi_chip_no[1:0],
+                                2'b1,    // Read Operatopm
+                                2'h3,    // 4 Transfer
+                                6'h10,    // sck clock period
+                                5'h2,    // cs setup/hold period
+                                cs_byte[7:0] }); // cs bit information
+      
+     `TB_GLBL.wb_user_core_read(`ADDR_SPACE_SSPI+'h0,read_data);
+
+     while(read_data[31]) begin
+        @(posedge `TB_GLBL.clock) ;
+        `TB_GLBL.wb_user_core_read(`ADDR_SPACE_SSPI+'h0,read_data);
+     end 
+
+     `TB_GLBL.wb_user_core_read(`ADDR_SPACE_SSPI+'h8,dataout);
+
+    end
+endtask
+
+
+
+task sspi_sector_errase;
+    input [23:0] address;
+    reg   [31:0] read_data;
+    begin
+
+      @(posedge `TB_GLBL.clock) ;
+      `TB_GLBL.wb_user_core_write(`ADDR_SPACE_SSPI+'h4,{8'hD8,address[23:0]});
+      `TB_GLBL.wb_user_core_write(`ADDR_SPACE_SSPI+'h0,{1'b1,5'h0,
+	                        BIG_ENDIAN,
+                                spi_chip_no[1:0],
+                                2'b0,    // Write Operatopm
+                                2'h3,    // 4 Transfer
+                                6'h10,    // sck clock period
+                                5'h2,    // cs setup/hold period
+                                8'h1 }); // cs bit information
+      
+     `TB_GLBL.wb_user_core_read(`ADDR_SPACE_SSPI+'h0,read_data);
+
+      $display("%t : %m : Sending Sector Errase for Address : %x",$time,address);
+      
+
+     `TB_GLBL.wb_user_core_read(`ADDR_SPACE_SSPI+'h0,read_data);
+     while(read_data[31]) begin
+        @(posedge `TB_GLBL.clock) ;
+        `TB_GLBL.wb_user_core_read(`ADDR_SPACE_SSPI+'h0,read_data);
+     end 
+   end
+endtask
+
+
+task sspi_page_write;
+    input [23:0] address;
+    reg [7:0] i;
+    reg [31:0] write_data;
+    begin
+
+      sspi_write_dword({8'h02,address[23:0]},BIG_ENDIAN,8'h0);
+
+      for(i = 0; i < 252 ; i = i + 4) begin
+         write_data [31:24]  = i;
+         write_data [23:16]  = i+1;
+         write_data [15:8]   = i+2;
+         write_data [7:0]    = i+3;
+         sspi_write_dword(write_data,LITTLE_ENDIAN,8'h0);
+         $display("%m : Writing Data-%d : %x",i,write_data);
+      end
+     
+      // Writting last 4 byte with de-selecting the chip select 
+         write_data [31:24]  = i;
+         write_data [23:16]  = i+1;
+         write_data [15:8]   = i+2;
+         write_data [7:0]    = i+3;
+      sspi_write_dword(write_data,LITTLE_ENDIAN,8'h1);
+      $display("%m : Writing Data-%d : %x",i,write_data);
+
+    end
+endtask
+
+
+task sspi_page_read_verify;
+    input [23:0] address;
+    reg   [31:0] read_data;
+    reg [7:0] i;
+    reg [31:0] exp_data;
+    begin
+
+      sspi_write_dword({8'h03,address[23:0]},BIG_ENDIAN,8'h0);
+
+      for(i = 0; i < 252 ; i = i + 4) begin
+         exp_data [31:24]  = i;
+         exp_data [23:16]  = i+1;
+         exp_data [15:8]   = i+2;
+         exp_data [7:0]    = i+3;
+         sspi_read_dword(LITTLE_ENDIAN,read_data,8'h0);
+         if(read_data != exp_data) begin
+            -> sspi_error_detected;
+            $display("%m : ERROR : Data:%d-> Exp : %x Rxd : %x",i,exp_data,read_data);
+         end else begin
+            $display("%m : STATUS :  Data:%d Matched : %x ",i,read_data);
+         end
+
+      end
+     
+      // Reading last 4 byte with de-selecting the chip select 
+         exp_data [31:24]  = i;
+         exp_data [23:16]  = i+1;
+         exp_data [15:8]   = i+2;
+         exp_data [7:0]    = i+3;
+
+         sspi_read_dword(LITTLE_ENDIAN,read_data,8'h1);
+         if(read_data != exp_data) begin
+            -> sspi_error_detected;
+            $display("%m : ERROR : Data:%d-> Exp : %x Rxd : %x",i,exp_data,read_data);
+         end else begin
+            $display("%m : STATUS :  Data:%d Matched : %x ",i,read_data);
+         end
+
+    end
+endtask
+
+
+
+
+task sspi_op_over;
+    reg [31:0] read_data;
+    begin
+     `TB_GLBL.wb_user_core_read('h0,read_data);
+      while(read_data[31]) begin
+        @(posedge `TB_GLBL.clock) ;
+        `TB_GLBL.wb_user_core_read('h0,read_data);
+      end 
+      #100;
+    end
+endtask
+
+task sspi_wait_busy;
+    reg [31:0] read_data;
+    reg        exit_flag;
+    integer    pretime;
+    begin
+
+    read_data = 1;
+    pretime = $time;
+
+     
+  exit_flag = 1;
+   while(exit_flag == 1) begin 
+
+    `TB_GLBL.wb_user_core_write(`ADDR_SPACE_SSPI+'h4,{8'h05,24'h0});
+    `TB_GLBL.wb_user_core_write(`ADDR_SPACE_SSPI+'h0,{1'b1,5'h0,
+	                        BIG_ENDIAN,
+                                spi_chip_no[1:0],
+                                2'b0,    // Write Operation
+                                2'b0,    // 1 Transfer
+                                6'h10,    // sck clock period
+                                5'h2,    // cs setup/hold period
+                                8'h0 }); // cs bit information
+
+
+        `TB_GLBL.wb_user_core_read(`ADDR_SPACE_SSPI+'h0,read_data);
+        while(read_data[31]) begin
+          @(posedge `TB_GLBL.clock) ;
+          `TB_GLBL.wb_user_core_read(`ADDR_SPACE_SSPI+'h0,read_data);
+        end 
+
+     // Send Status Request Cmd
+
+
+      `TB_GLBL.wb_user_core_write('h0,{1'b1,5'h0,
+	                        BIG_ENDIAN,
+                                spi_chip_no[1:0],
+                                2'b1,    // Read Operation
+                                2'b0,    // 1 Transfer
+                                6'h10,    // sck clock period
+                                5'h2,    // cs setup/hold period
+                                8'h40 }); // cs bit information
+
+        
+        `TB_GLBL.wb_user_core_read(`ADDR_SPACE_SSPI+'h0,read_data);
+        while(read_data[31]) begin
+          @(posedge `TB_GLBL.clock) ;
+          `TB_GLBL.wb_user_core_read(`ADDR_SPACE_SSPI+'h0,read_data);
+        end 
+      
+        `TB_GLBL.wb_user_core_read(`ADDR_SPACE_SSPI+'h8,read_data);
+        exit_flag = read_data[24];
+        $display("Total time Elapsed: %0t(us): %m : Checking the SPI RDStatus : %x",($time - pretime)/1000000 ,read_data);
+      repeat (1000) @ (posedge `TB_GLBL.clock) ;
+     end
+  end
+endtask
+
+
+
+task sspi_tb_status;
+begin
+
+   $display("#############################");
+   $display("   Test Statistic            ");
+   if(sspi_err_cnt >0) begin 
+      $display("TEST STATUS : FAILED ");
+      $display("TOTAL ERROR COUNT : %d ",sspi_err_cnt);
+   end else begin
+      $display("TEST STATUS : PASSED ");
+   end
+   $display("#############################");
+end
+endtask
+

diff --git a/verilog/dv/user_sspi/user_sspi_tb.v b/verilog/dv/user_sspi/user_sspi_tb.v
new file mode 100644
index 0000000..8330de7
--- /dev/null
+++ b/verilog/dv/user_sspi/user_sspi_tb.v

@@ -0,0 +1,460 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  Standalone User validation Test bench                       ////
+////                                                              ////
+////  This file is part of the YIFive cores project               ////
+////  https://github.com/dineshannayya/yifive_r0.git              ////
+////  http://www.opencores.org/cores/yifive/                      ////
+////                                                              ////
+////  Description                                                 ////
+////   This is a standalone test bench to validate the            ////
+////   sspi interfaface through External WB i/F.                  ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.1 - 01 Oct 2021, Dinesh A                               ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ns
+
+// Note in caravel, 0x30XX_XXXX only come to user interface
+// So, using wb_host bank select we have changing MSB address [31:24] = 0x10
+`define ADDR_SPACE_UART    32'h3001_0000
+`define ADDR_SPACE_SSPI    32'h3001_00C0
+`define ADDR_SPACE_PINMUX  32'h3002_0000
+
+`define TB_GLBL    user_sspi_tb
+
+`include "uprj_netlists.v"
+`include "is62wvs1288.v"
+
+
+module user_sspi_tb;
+	reg clock;
+	reg wb_rst_i;
+	reg power1, power2;
+	reg power3, power4;
+
+        reg        wbd_ext_cyc_i;  // strobe/request
+        reg        wbd_ext_stb_i;  // strobe/request
+        reg [31:0] wbd_ext_adr_i;  // address
+        reg        wbd_ext_we_i;  // write
+        reg [31:0] wbd_ext_dat_i;  // data output
+        reg [3:0]  wbd_ext_sel_i;  // byte enable
+
+        wire [31:0] wbd_ext_dat_o;  // data input
+        wire        wbd_ext_ack_o;  // acknowlegement
+        wire        wbd_ext_err_o;  // error
+
+	// User I/O
+	wire [37:0] io_oeb;
+	wire [37:0] io_out;
+	wire [37:0] io_in;
+
+
+	reg [1:0] spi_chip_no;
+
+	wire gpio;
+	wire [37:0] mprj_io;
+	wire [7:0] mprj_io_0;
+	reg        test_fail;
+	reg [31:0] read_data;
+
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+                wbd_ext_cyc_i ='h0;  // strobe/request
+                wbd_ext_stb_i ='h0;  // strobe/request
+                wbd_ext_adr_i ='h0;  // address
+                wbd_ext_we_i  ='h0;  // write
+                wbd_ext_dat_i ='h0;  // data output
+                wbd_ext_sel_i ='h0;  // byte enable
+	end
+
+	`ifdef WFDUMP
+	   initial begin
+	   	$dumpfile("simx.vcd");
+	   	$dumpvars(5, user_sspi_tb);
+	   end
+       `endif
+
+	initial begin
+		$dumpon;
+
+		#200; // Wait for reset removal
+	        repeat (10) @(posedge clock);
+		$display("Monitor: Standalone User Risc Boot Test Started");
+
+		// Remove Wb Reset
+		wb_user_core_write('h3080_0000,'h1);
+
+                // Enable SPI Multi Functional Ports
+                wb_user_core_write(`ADDR_SPACE_PINMUX+'h0038,'h400);
+
+	        repeat (2) @(posedge clock);
+		#1;
+
+                // Remove the reset
+		// Remove WB and SPI/UART Reset, Keep CORE under Reset
+                wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h01F);
+
+
+		test_fail = 0;
+		sspi_init();
+	        repeat (200) @(posedge clock);
+                wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
+                $display("############################################");
+                $display("   Testing IS62/65WVS1288GALL SSRAM Read/Write Access       ");
+                $display("############################################");
+		// SSPI Indirect RAM READ ACCESS-
+		// Byte Read Option
+		// <Instr:0x3> <Addr:24Bit Address> <Read Data Out>
+                spi_chip_no = 2'b00; // Select the Chip Select to zero
+		sspi_dw_read_check(8'h03,24'h0000,32'h03020100);
+		sspi_dw_read_check(8'h03,24'h0004,32'h07060504);
+		sspi_dw_read_check(8'h03,24'h0008,32'h0b0a0908);
+		sspi_dw_read_check(8'h03,24'h000C,32'h0f0e0d0c);
+		sspi_dw_read_check(8'h03,24'h0010,32'h13121110);
+		sspi_dw_read_check(8'h03,24'h0014,32'h17161514);
+		sspi_dw_read_check(8'h03,24'h0018,32'h1B1A1918);
+		sspi_dw_read_check(8'h03,24'h001C,32'h1F1E1D1C);
+
+		sspi_dw_read_check(8'h03,24'h0040,32'h43424140);
+		sspi_dw_read_check(8'h03,24'h0044,32'h47464544);
+		sspi_dw_read_check(8'h03,24'h0048,32'h4B4A4948);
+		sspi_dw_read_check(8'h03,24'h004C,32'h4F4E4D4C);
+
+		sspi_dw_read_check(8'h03,24'h00a0,32'ha3a2a1a0);
+		sspi_dw_read_check(8'h03,24'h00a4,32'ha7a6a5a4);
+		sspi_dw_read_check(8'h03,24'h00a8,32'habaaa9a8);
+		sspi_dw_read_check(8'h03,24'h00aC,32'hafaeadac);
+
+		sspi_dw_read_check(8'h03,24'h0200,32'h11111111);
+		sspi_dw_read_check(8'h03,24'h0204,32'h22222222);
+		sspi_dw_read_check(8'h03,24'h0208,32'h33333333);
+		sspi_dw_read_check(8'h03,24'h020C,32'h44444444);
+
+		// SPI Write
+		sspi_dw_write(8'h02,24'h0000,32'h00112233);
+		sspi_dw_write(8'h02,24'h0004,32'h44556677);
+		sspi_dw_write(8'h02,24'h0008,32'h8899AABB);
+		sspi_dw_write(8'h02,24'h000C,32'hCCDDEEFF);
+
+		sspi_dw_write(8'h02,24'h0200,32'h11223344);
+		sspi_dw_write(8'h02,24'h0204,32'h55667788);
+		sspi_dw_write(8'h02,24'h0208,32'h99AABBCC);
+		sspi_dw_write(8'h02,24'h020C,32'hDDEEFF00);
+
+		// SPI Read Check
+		sspi_dw_read_check(8'h03,24'h0000,32'h00112233);
+		sspi_dw_read_check(8'h03,24'h0004,32'h44556677);
+		sspi_dw_read_check(8'h03,24'h0008,32'h8899AABB);
+		sspi_dw_read_check(8'h03,24'h000C,32'hCCDDEEFF);
+
+		sspi_dw_read_check(8'h03,24'h0200,32'h11223344);
+		sspi_dw_read_check(8'h03,24'h0204,32'h55667788);
+		sspi_dw_read_check(8'h03,24'h0208,32'h99AABBCC);
+		sspi_dw_read_check(8'h03,24'h020C,32'hDDEEFF00);
+
+
+		repeat (100) @(posedge clock);
+			// $display("+1000 cycles");
+
+          	if(test_fail == 0) begin
+		   `ifdef GL
+	    	       $display("Monitor: SPI Master Mode (GL) Passed");
+		   `else
+		       $display("Monitor: SPI Master Mode (RTL) Passed");
+		   `endif
+	        end else begin
+		    `ifdef GL
+	    	        $display("Monitor: SPI Master Mode (GL) Failed");
+		    `else
+		        $display("Monitor: SPI Master Mode (RTL) Failed");
+		    `endif
+		 end
+	    	$display("###################################################");
+	        $finish;
+	end
+
+	initial begin
+		wb_rst_i <= 1'b1;
+		#100;
+		wb_rst_i <= 1'b0;	    	// Release reset
+	end
+wire USER_VDD1V8 = 1'b1;
+wire VSS = 1'b0;
+
+user_project_wrapper u_top(
+`ifdef USE_POWER_PINS
+    .vccd1(USER_VDD1V8),	// User area 1 1.8V supply
+    .vssd1(VSS),	// User area 1 digital ground
+`endif
+    .wb_clk_i        (clock),  // System clock
+    .user_clock2     (1'b1),  // Real-time clock
+    .wb_rst_i        (wb_rst_i),  // Regular Reset signal
+
+    .wbs_cyc_i   (wbd_ext_cyc_i),  // strobe/request
+    .wbs_stb_i   (wbd_ext_stb_i),  // strobe/request
+    .wbs_adr_i   (wbd_ext_adr_i),  // address
+    .wbs_we_i    (wbd_ext_we_i),  // write
+    .wbs_dat_i   (wbd_ext_dat_i),  // data output
+    .wbs_sel_i   (wbd_ext_sel_i),  // byte enable
+
+    .wbs_dat_o   (wbd_ext_dat_o),  // data input
+    .wbs_ack_o   (wbd_ext_ack_o),  // acknowlegement
+
+ 
+    // Logic Analyzer Signals
+    .la_data_in      ('1) ,
+    .la_data_out     (),
+    .la_oenb         ('0),
+ 
+
+    // IOs
+    .io_in          (io_in)  ,
+    .io_out         (io_out) ,
+    .io_oeb         (io_oeb) ,
+
+    .user_irq       () 
+
+);
+
+`ifndef GL // Drive Power for Hold Fix Buf
+    // All standard cell need power hook-up for functionality work
+    initial begin
+
+    end
+`endif    
+
+//------------------------------------------------------
+//  Integrate the Serial flash with qurd support to
+//  user core using the gpio pads
+//  ----------------------------------------------------
+   wire flash_io1;
+   wire flash_clk = io_out[16];
+   wire spiram_csb = io_out[13];
+   tri  #1 flash_io0 = io_out[15];
+   assign io_in[14] = flash_io1;
+
+   tri  #1 flash_io2 = 1'b1;
+   tri  #1 flash_io3 = 1'b1;
+
+
+   is62wvs1288 #(.mem_file_name("flash1.hex"))
+	u_sfram (
+         // Data Inputs/Outputs
+           .io0     (flash_io0),
+           .io1     (flash_io1),
+           // Controls
+           .clk    (flash_clk),
+           .csb    (spiram_csb),
+           .io2    (flash_io2),
+           .io3    (flash_io3)
+    );
+
+
+//----------------------------------------------------
+//  Task
+// --------------------------------------------------
+task test_err;
+begin
+     test_fail = 1;
+end
+endtask
+
+task wb_user_core_write;
+input [31:0] address;
+input [31:0] data;
+begin
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_adr_i =address;  // address
+  wbd_ext_we_i  ='h1;  // write
+  wbd_ext_dat_i =data;  // data output
+  wbd_ext_sel_i ='hF;  // byte enable
+  wbd_ext_cyc_i ='h1;  // strobe/request
+  wbd_ext_stb_i ='h1;  // strobe/request
+  wait(wbd_ext_ack_o == 1);
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_cyc_i ='h0;  // strobe/request
+  wbd_ext_stb_i ='h0;  // strobe/request
+  wbd_ext_adr_i ='h0;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='h0;  // data output
+  wbd_ext_sel_i ='h0;  // byte enable
+  $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data);
+  repeat (2) @(posedge clock);
+end
+endtask
+
+task  wb_user_core_read;
+input [31:0] address;
+output [31:0] data;
+reg    [31:0] data;
+begin
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_adr_i =address;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='0;  // data output
+  wbd_ext_sel_i ='hF;  // byte enable
+  wbd_ext_cyc_i ='h1;  // strobe/request
+  wbd_ext_stb_i ='h1;  // strobe/request
+  wait(wbd_ext_ack_o == 1);
+  data  = wbd_ext_dat_o;  
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_cyc_i ='h0;  // strobe/request
+  wbd_ext_stb_i ='h0;  // strobe/request
+  wbd_ext_adr_i ='h0;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='h0;  // data output
+  wbd_ext_sel_i ='h0;  // byte enable
+  //$display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,data);
+  repeat (2) @(posedge clock);
+end
+endtask
+
+task  wb_user_core_read_check;
+input [31:0] address;
+output [31:0] data;
+input [31:0] cmp_data;
+reg    [31:0] data;
+begin
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_adr_i =address;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='0;  // data output
+  wbd_ext_sel_i ='hF;  // byte enable
+  wbd_ext_cyc_i ='h1;  // strobe/request
+  wbd_ext_stb_i ='h1;  // strobe/request
+  wait(wbd_ext_ack_o == 1);
+  data  = wbd_ext_dat_o;  
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_cyc_i ='h0;  // strobe/request
+  wbd_ext_stb_i ='h0;  // strobe/request
+  wbd_ext_adr_i ='h0;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='h0;  // data output
+  wbd_ext_sel_i ='h0;  // byte enable
+  if(data !== cmp_data) begin
+     $display("ERROR : WB USER ACCESS READ  Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
+     user_sspi_tb.test_fail = 1;
+  end else begin
+     $display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,data);
+  end
+  repeat (2) @(posedge clock);
+end
+endtask
+
+
+`ifdef GL
+
+wire        wbd_spi_stb_i   = u_top.u_spi_master.wbd_stb_i;
+wire        wbd_spi_ack_o   = u_top.u_spi_master.wbd_ack_o;
+wire        wbd_spi_we_i    = u_top.u_spi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i   = u_top.u_spi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i   = u_top.u_spi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o   = u_top.u_spi_master.wbd_dat_o;
+wire [3:0]  wbd_spi_sel_i   = u_top.u_spi_master.wbd_sel_i;
+
+wire        wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i;
+wire        wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o;
+wire        wbd_sdram_we_i  = u_top.u_sdram_ctrl.wb_we_i;
+wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i;
+wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i;
+wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
+wire [3:0]  wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;
+
+wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb.reg_cs;
+wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb.reg_ack;
+wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb.reg_wr;
+wire [7:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb.reg_addr;
+wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb.reg_wdata;
+wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb.reg_rdata;
+wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb.reg_be;
+
+`endif
+
+/**
+`ifdef GL
+//-----------------------------------------------------------------------------
+// RISC IMEM amd DMEM Monitoring TASK
+//-----------------------------------------------------------------------------
+
+`define RISC_CORE  user_uart_tb.u_top.u_core.u_riscv_top
+
+always@(posedge `RISC_CORE.wb_clk) begin
+    if(`RISC_CORE.wbd_imem_ack_i)
+          $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
+    if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
+          $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
+    if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
+          $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
+end
+
+`endif
+**/
+`include "sspi_task.v"
+
+endmodule
+`default_nettype wire

diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index 9e150f4..32abd1a 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v

@@ -313,7 +313,7 @@
 //  ----------------------------------------------------
 
    wire flash_clk = io_out[24];
-   wire flash_csb = io_out[28];
+   wire flash_csb = io_out[25];
    // Creating Pad Delay
    wire #1 io_oeb_29 = io_oeb[29];
    wire #1 io_oeb_30 = io_oeb[30];

diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile
index 8844da3..7b5585e 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/wb_port/Makefile

@@ -82,7 +82,7 @@
 %.vcd: %.vvp
 	vvp $<
 
-%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env
+%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s 
 	${GCC64_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
 
 %.hex: %.elf

diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c
index 2649c67..fdddf4f 100644
--- a/verilog/dv/wb_port/wb_port.c
+++ b/verilog/dv/wb_port/wb_port.c

@@ -120,7 +120,10 @@
     // Remove Wishbone Reset
     reg_mprj_wbhost_reg0 = 0x1;
 
-    if (reg_mprj_globl_reg0 != 0x89490201) bFail = 1;
+    // Remove Reset
+    reg_mprj_globl_reg2 = 0x01F;
+
+    if (reg_mprj_globl_reg0 != 0x82682301) bFail = 1;
     if (reg_mprj_globl_reg1 != 0xA55AA55A) bFail = 1;
 
     // Write software Write & Read Register

diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v
index 88e8bee..2f7099e 100644
--- a/verilog/dv/wb_port/wb_port_tb.v
+++ b/verilog/dv/wb_port/wb_port_tb.v

@@ -17,6 +17,8 @@
 
 `timescale 1 ns / 1 ps
 
+`define FULL_CHIP_SIM
+
 `include "uprj_netlists.v"
 `include "caravel_netlists.v"
 `include "spiflash.v"
@@ -49,7 +51,7 @@
 
 	`ifdef WFDUMP
 	initial begin
-		$dumpfile("wb_port.vcd");
+		$dumpfile("simx.vcd");
 		$dumpvars(1, wb_port_tb);
 		$dumpvars(2, wb_port_tb.uut);
 		//$dumpvars(1, wb_port_tb.uut.mprj);

diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv
index bb53fb1..4446c89 100755
--- a/verilog/rtl/pinmux/src/pinmux.sv
+++ b/verilog/rtl/pinmux/src/pinmux.sv

@@ -451,10 +451,10 @@
 *
 *  Additional Pad used for Externam ROM/RAM
 *                sflash_sck          digital_io[24]
-*                sflash_ss[3]        digital_io[25]
-*                sflash_ss[2]        digital_io[26]
-*                sflash_ss[1]        digital_io[27]
-*                sflash_ss[0]        digital_io[28]
+*                sflash_ss[0]        digital_io[25]
+*                sflash_ss[1]        digital_io[26]
+*                sflash_ss[2]        digital_io[27]
+*                sflash_ss[3]        digital_io[28]
 *                sflash_io0          digital_io[29]
 *                sflash_io1          digital_io[30]
 *                sflash_io2          digital_io[31]
@@ -669,10 +669,10 @@
 
      // Serial Flash
      digital_io_out[24] = sflash_sck   ;
-     digital_io_out[25] = sflash_ss[3] ;
-     digital_io_out[26] = sflash_ss[2] ;
-     digital_io_out[27] = sflash_ss[1] ;
-     digital_io_out[28] = sflash_ss[0] ;
+     digital_io_out[25] = sflash_ss[0] ;
+     digital_io_out[26] = sflash_ss[1] ;
+     digital_io_out[27] = sflash_ss[2] ;
+     digital_io_out[28] = sflash_ss[3] ;
      digital_io_out[29] = sflash_do[0] ;
      digital_io_out[30] = sflash_do[1] ;
      digital_io_out[31] = sflash_do[2] ;

diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv
index 5794be8..e9f7125 100644
--- a/verilog/rtl/pinmux/src/pinmux_reg.sv
+++ b/verilog/rtl/pinmux/src/pinmux_reg.sv

@@ -279,6 +279,12 @@
 //-----------------------------------------------------------------------
 
 // Chip ID
+// chip-id[3:0] mapping
+//    0 -  YIFIVE (MPW-2)
+//    1 -  Riscdunio (MPW-3)
+//    2 -  Riscdunio (MPW-4)
+//    3 -  Riscdunio (MPW-5)
+
 wire [15:0] manu_id      =  16'h8268; // Asci value of RD
 wire [3:0]  total_core   =  4'h02;
 wire [3:0]  chip_id      =  4'h03;
@@ -763,7 +769,7 @@
 //-----------------------------------------
 // Software Reg-2, Release date: <DAY><MONTH><YEAR>
 // ----------------------------------------
-gen_32b_reg  #(32'h2202_2022) u_reg_23	(
+gen_32b_reg  #(32'h0203_2022) u_reg_23	(
 	      //List of Inputs
 	      .reset_n    (h_reset_n     ),
 	      .clk        (mclk          ),
@@ -776,9 +782,9 @@
 	      );
 
 //-----------------------------------------
-// Software Reg-3: Poject Revison 3.3 = 0003400
+// Software Reg-3: Poject Revison 3.7 = 0003700
 // ----------------------------------------
-gen_32b_reg  #(32'h0003_5000) u_reg_24	(
+gen_32b_reg  #(32'h0003_7000) u_reg_24	(
 	      //List of Inputs
 	      .reset_n    (h_reset_n     ),
 	      .clk        (mclk          ),

diff --git a/verilog/rtl/qspim b/verilog/rtl/qspim
index f83d4c0..efa1519 160000
--- a/verilog/rtl/qspim
+++ b/verilog/rtl/qspim

@@ -1 +1 @@
-Subproject commit f83d4c0182dfd50f867f7cb49ec1bebc833e0a58
+Subproject commit efa151915f9d00cb329388845356c5b734601571

diff --git a/verilog/rtl/sspim/src/sspim_cfg.sv b/verilog/rtl/sspim/src/sspim_cfg.sv
index cd39e1f..e849f81 100755
--- a/verilog/rtl/sspim/src/sspim_cfg.sv
+++ b/verilog/rtl/sspim/src/sspim_cfg.sv

@@ -56,6 +56,7 @@
               output logic [1:0]    cfg_tgt_sel        ,
               
               output logic          cfg_op_req         , // SPI operation request
+	      output logic          cfg_endian         , // Endian selection
               output logic [1:0]    cfg_op_type        , // SPI operation type
               output logic [1:0]    cfg_transfer_size  , // SPI transfer size
               output logic [5:0]    cfg_sck_period     , // sck clock period
@@ -89,7 +90,6 @@
 logic           sw_rd_en               ;
 logic           sw_wr_en;
 logic   [1:0]   sw_addr; // addressing 16 registers
-logic   [31:0]  sw_reg_wdata;
 logic   [3:0]   wr_be  ;
 logic           reg_cs_l;
 logic           reg_cs_2l;
@@ -104,29 +104,12 @@
 //-----------------------------------------------------------------------
 
 //-----------------------------------------------------------------------
-// To avoid interface timing, all the content are registered
+// Internal Logic Starts here
 //-----------------------------------------------------------------------
-always @ (posedge mclk or negedge reset_n)
-begin 
-   if (reset_n == 1'b0)
-   begin
-    sw_addr       <= '0;
-    sw_rd_en      <= '0;
-    sw_wr_en      <= '0;
-    sw_reg_wdata  <= '0;
-    wr_be         <= '0;
-    reg_cs_l      <= '0;
-    reg_cs_2l     <= '0;
-  end else begin
-    sw_addr       <= reg_addr [3:2];
-    sw_rd_en      <= reg_cs & !reg_wr;
-    sw_wr_en      <= reg_cs & reg_wr;
-    sw_reg_wdata  <= reg_wdata;
-    wr_be         <= reg_be;
-    reg_cs_l      <= reg_cs;
-    reg_cs_2l     <= reg_cs_l;
-  end
-end
+    assign sw_addr       = reg_addr [3:2];
+    assign sw_rd_en      = reg_cs & !reg_wr;
+    assign sw_wr_en      = reg_cs & reg_wr;
+    assign wr_be         = reg_be;
 
 //-----------------------------------------------------------------------
 // Read path mux
@@ -134,18 +117,24 @@
 
 always @ (posedge mclk or negedge reset_n)
 begin : preg_out_Seq
-   if (reset_n == 1'b0) begin
-      reg_rdata [31:0]  <= 32'h0000_0000;
-      reg_ack           <= 1'b0;
-   end else if (sw_rd_en && !reg_ack && !reg_cs_2l) begin
-      reg_rdata [31:0]  <= reg_out [31:0];
-      reg_ack           <= 1'b1;
-   end else if (sw_wr_en && !reg_ack && !reg_cs_2l) begin 
-      reg_ack           <= 1'b1;
-   end else begin
-      reg_ack        <= 1'b0;
+   if (reset_n == 1'b0)
+   begin
+      reg_rdata  <= 'h0;
+      reg_ack    <= 1'b0;
+   end
+   else if (sw_rd_en && !reg_ack) 
+   begin
+      reg_rdata  <= reg_out;
+      reg_ack    <= 1'b1;
+   end
+   else if (sw_wr_en && !reg_ack) 
+      reg_ack    <= 1'b1;
+   else
+   begin
+      reg_ack    <= 1'b0;
    end
 end
+
 //-----------------------------------------------------------------------
 // register read enable and write enable decoding logic
 //-----------------------------------------------------------------------
@@ -164,10 +153,10 @@
 
   reg_out [31:0] = 32'd0;
 
-  case (sw_addr [3:0])
-    4'b0000 : reg_out [31:0] = reg_0 [31:0];     
-    4'b0001 : reg_out [31:0] = reg_1 [31:0];    
-    4'b0010 : reg_out [31:0] = reg_2 [31:0];     
+  case (sw_addr [1:0])
+    2'b00 : reg_out [31:0] = reg_0 [31:0];     
+    2'b01 : reg_out [31:0] = reg_1 [31:0];    
+    2'b10 : reg_out [31:0] = reg_2 [31:0];     
     default : reg_out [31:0] = 32'h0;
   endcase
 end
@@ -180,6 +169,7 @@
 // Logic for Register 0 : SPI Control Register
 //-----------------------------------------------------------------------
 assign    cfg_op_req         = reg_0[31];    // cpu request
+assign    cfg_endian         = reg_0[25];    // Endian, 0 - little, 1 - Big
 assign    cfg_tgt_sel        = reg_0[24:23]; // target chip select
 assign    cfg_op_type        = reg_0[22:21]; // SPI operation type
 assign    cfg_transfer_size  = reg_0[20:19]; // SPI transfer size
@@ -190,7 +180,7 @@
 generic_register #(8,0  ) u_spi_ctrl_be0 (
 	      .we            ({8{sw_wr_en_0 & 
                                  wr_be[0]   }}  ),		 
-	      .data_in       (sw_reg_wdata[7:0]    ),
+	      .data_in       (reg_wdata[7:0]    ),
 	      .reset_n       (reset_n           ),
 	      .clk           (mclk              ),
 	      
@@ -201,7 +191,7 @@
 generic_register #(8,0  ) u_spi_ctrl_be1 (
 	      .we            ({8{sw_wr_en_0 & 
                                 wr_be[1]   }}  ),		 
-	      .data_in       (sw_reg_wdata[15:8]  ),
+	      .data_in       (reg_wdata[15:8]  ),
 	      .reset_n       (reset_n           ),
 	      .clk           (mclk              ),
 	      
@@ -212,7 +202,7 @@
 generic_register #(8,0  ) u_spi_ctrl_be2 (
 	      .we            ({8{sw_wr_en_0 & 
                                 wr_be[2]   }}  ),		 
-	      .data_in       (sw_reg_wdata[23:16] ),
+	      .data_in       (reg_wdata[23:16] ),
 	      .reset_n       (reset_n           ),
 	      .clk           (mclk              ),
 	      
@@ -220,12 +210,23 @@
 	      .data_out      (reg_0[23:16]       )
           );
 
-assign reg_0[30:24] = 7'h0;
+generic_register #(2,0  ) u_spi_ctrl_be3 (
+	      .we            ({2{sw_wr_en_0 & 
+                                wr_be[3]   }}  ),		 
+	      .data_in       (reg_wdata[25:24] ),
+	      .reset_n       (reset_n           ),
+	      .clk           (mclk              ),
+	      
+	      //List of Outs
+	      .data_out      (reg_0[25:24]       )
+          );
+
+assign reg_0[30:26] = 5'h0;
 
 req_register #(0  ) u_spi_ctrl_req (
 	      .cpu_we       ({sw_wr_en_0 & 
                              wr_be[3]   }       ),		 
-	      .cpu_req      (sw_reg_wdata[31]      ),
+	      .cpu_req      (reg_wdata[31]      ),
 	      .hware_ack    (hware_op_done      ),
 	      .reset_n       (reset_n           ),
 	      .clk           (mclk              ),
@@ -245,7 +246,7 @@
 generic_register #(8,0  ) u_spi_din_be0 (
 	      .we            ({8{sw_wr_en_1 & 
                                 wr_be[0]   }}  ),		 
-	      .data_in       (sw_reg_wdata[7:0]    ),
+	      .data_in       (reg_wdata[7:0]    ),
 	      .reset_n       (reset_n           ),
 	      .clk           (mclk              ),
 	      
@@ -256,7 +257,7 @@
 generic_register #(8,0  ) u_spi_din_be1 (
 	      .we            ({8{sw_wr_en_1 & 
                                 wr_be[1]   }}  ),		 
-	      .data_in       (sw_reg_wdata[15:8]   ),
+	      .data_in       (reg_wdata[15:8]   ),
 	      .reset_n       (reset_n           ),
 	      .clk           (mclk              ),
 	      
@@ -267,7 +268,7 @@
 generic_register #(8,0  ) u_spi_din_be2 (
 	      .we            ({8{sw_wr_en_1 & 
                                 wr_be[2]   }}  ),		 
-	      .data_in       (sw_reg_wdata[23:16]  ),
+	      .data_in       (reg_wdata[23:16]  ),
 	      .reset_n       (reset_n           ),
 	      .clk           (mclk              ),
 	      
@@ -279,7 +280,7 @@
 generic_register #(8,0  ) u_spi_din_be3 (
 	      .we            ({8{sw_wr_en_1 & 
                                 wr_be[3]   }}  ),		 
-	      .data_in       (sw_reg_wdata[31:24]  ),
+	      .data_in       (reg_wdata[31:24]  ),
 	      .reset_n       (reset_n           ),
 	      .clk           (mclk              ),
 	      

diff --git a/verilog/rtl/sspim/src/sspim_ctl.sv b/verilog/rtl/sspim/src/sspim_ctl.sv
index f65c0c2..ea6aa1f 100755
--- a/verilog/rtl/sspim/src/sspim_ctl.sv
+++ b/verilog/rtl/sspim/src/sspim_ctl.sv

@@ -53,6 +53,7 @@
   input  logic          clk,

   input  logic          reset_n,

   input  logic          cfg_op_req,

+  input  logic          cfg_endian,

   input  logic [1:0]    cfg_op_type,

   input  logic [1:0]    cfg_transfer_size,

     

@@ -77,6 +78,8 @@
 

  //*************************************************************************

 

+ parameter LITTLE_ENDIAN  = 1'b0;

+ parameter BIG_ENDIAN     = 1'b1;

 

   logic [5:0]       clk_cnt;

   logic [5:0]       sck_cnt;

@@ -150,9 +153,14 @@
                       (byte_cnt == 2'b01) ? cfg_cs_byte[5:4]  :

                       (byte_cnt == 2'b10) ? cfg_cs_byte[3:2]  : cfg_cs_byte[1:0] ;

 

-assign byte_out = (byte_cnt == 2'b00) ? cfg_datain[31:24] :

-                      (byte_cnt == 2'b01) ? cfg_datain[23:16] :

-                      (byte_cnt == 2'b10) ? cfg_datain[15:8]  : cfg_datain[7:0] ;

+assign byte_out =     (cfg_endian == LITTLE_ENDIAN) ? 

+	                   ((byte_cnt == 2'b00) ? cfg_datain[7:0] :

+                            (byte_cnt == 2'b01) ? cfg_datain[15:8] :

+                            (byte_cnt == 2'b10) ? cfg_datain[23:16]  : cfg_datain[31:24]) :

+	                   ((byte_cnt == 2'b00) ? cfg_datain[31:24] :

+                            (byte_cnt == 2'b01) ? cfg_datain[23:16] :

+                            (byte_cnt == 2'b10) ? cfg_datain[15:8]  : cfg_datain[7:0]) ;

+         

          

 assign shift_out =  shift_enb && sck_ne;

 

@@ -252,13 +260,15 @@
              cs_int_n <= cs_data[0];

             if(sck_cnt == cfg_sck_cs_period) begin

                if(cfg_op_type == 1) begin // Read Mode

-                  cfg_dataout <= (byte_cnt[1:0] == 2'b00) ? { byte_in, cfg_dataout[23:0] } :

-                                 (byte_cnt[1:0] == 2'b01) ? { cfg_dataout[31:24] ,

-                                                              byte_in, cfg_dataout[15:0] } :

-                                 (byte_cnt[1:0] == 2'b10) ? { cfg_dataout[31:16] ,

-                                                              byte_in, cfg_dataout[7:0]  } :

-                                                            { cfg_dataout[31:8]  ,

-                                                              byte_in  } ;

+                  cfg_dataout <= (cfg_endian == LITTLE_ENDIAN) ?

+			         ((byte_cnt[1:0] == 2'b00) ? { cfg_dataout[31:8],byte_in } :

+                                  (byte_cnt[1:0] == 2'b01) ? { cfg_dataout[31:16], byte_in, cfg_dataout[7:0] } :

+                                  (byte_cnt[1:0] == 2'b10) ? { cfg_dataout[31:24], byte_in, cfg_dataout[15:0]  } :

+                                                             { byte_in,cfg_dataout[23:0]}) :

+			         ((byte_cnt[1:0] == 2'b00) ? { byte_in,cfg_dataout[23:0] } :

+                                  (byte_cnt[1:0] == 2'b01) ? { cfg_dataout[31:24], byte_in, cfg_dataout[15:0] } :

+                                  (byte_cnt[1:0] == 2'b10) ? { cfg_dataout[31:16], byte_in, cfg_dataout[7:0]  } :

+                                                             { cfg_dataout[31:8],byte_in}) ;

                end

                clr_sck_cnt <= 1'b1;

                if(byte_cnt == cfg_transfer_size) begin


diff --git a/verilog/rtl/sspim/src/sspim_top.sv b/verilog/rtl/sspim/src/sspim_top.sv
index 0c740d6..8a632a0 100755
--- a/verilog/rtl/sspim/src/sspim_top.sv
+++ b/verilog/rtl/sspim/src/sspim_top.sv

@@ -38,6 +38,12 @@
 ////    0.1 - 03 Oct 2021, Dinesh A                               ////
 ////          Initial SpI Module picked from                      ////
 ////           http://www.opencores.org/cores/turbo8051/          ////
+////    0.2 - Mar 2, 2022, Dinesh A                               ////
+////         1. Reg Bus changes to match with wishbone format     ////
+////         2. SPI tx and rx change to little endian format      ////
+////            i.e byte transfer [7:0],[15:8] ...[31:24]         ////
+////            Note: As per SPI transfer still first bit sent    ////
+////            out is big endian, i.e bit[7],[6] ..[0]           ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
@@ -108,6 +114,7 @@
 logic  [1:0]         cfg_tgt_sel                   ;
 
 logic                cfg_op_req                    ; // SPI operation request
+logic                cfg_endian                    ; // Endian selection
 logic  [1:0]         cfg_op_type                   ; // SPI operation type
 logic  [1:0]         cfg_transfer_size             ; // SPI transfer size
 logic  [5:0]         cfg_sck_period                ; // sck clock period
@@ -150,6 +157,7 @@
           . reset_n                     (reset_n                      ),
 
           . cfg_op_req                  (cfg_op_req                   ),
+          . cfg_endian                  (cfg_endian                   ),
           . cfg_op_type                 (cfg_op_type                  ),
           . cfg_transfer_size           (cfg_transfer_size            ),
           . cfg_sck_period              (cfg_sck_period               ),
@@ -194,6 +202,7 @@
            // configuration signal
           . cfg_tgt_sel                 (cfg_tgt_sel                  ),
           . cfg_op_req                  (cfg_op_req                   ), // SPI operation request
+          . cfg_endian                  (cfg_endian                   ),
           . cfg_op_type                 (cfg_op_type                  ), // SPI operation type
           . cfg_transfer_size           (cfg_transfer_size            ), // SPI transfer size
           . cfg_sck_period              (cfg_sck_period               ), // sck clock period

diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 938ce8d..b54f218 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v

@@ -102,6 +102,7 @@
      `include "lib/sync_wbb.sv"
      `include "lib/sync_fifo2.sv"
      `include "wb_interconnect/src/wb_arb.sv"
+     `include "wb_interconnect/src/wb_slave_port.sv"
      `include "wb_interconnect/src/wb_interconnect.sv"
 
      `include "yifive/ycr2c/src/core/pipeline/ycr_pipe_hdu.sv"

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index c8e4874..c5c4ca2 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v

@@ -172,7 +172,21 @@
 ////      C. Individual block reset are moved to pinmux to        ////
 ////         support peripheral reset from Risc and WishBone      ////
 ////         Host.                                                ////
-////                                                              ////
+////    3.6  Feb 19, Dinesh A                                     ////
+////       A.  Changed Module: wb_host                            ////
+////       wishbone slave clock generation config increase from   ////
+////       3 to 4 bit support clock source selection              ////
+////       B.  Changed Module: qspim                              ////
+//////      1. Bug fix in spi rise and fall pulse relation w.r.t  ////
+////           spi_clk. Note: Previous version work only with     ////
+////           spi clock config = 0x2                             ////
+////        2. spi_oen generation fix for different spi mode      ////
+////        3. spi_csn de-assertion fix for different spi clk div ////
+////    3.7  Mar 2 2022, Dinesh A                                 ////
+////       1. qspi cs# port mapping changed from io 28:25 to 25:28////
+////       2. sspi, bug fix in reg access and endian support added////
+////       3. Wishbone interconnect now support cross-connect     ////
+////          feature
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
 //// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
@@ -866,7 +880,7 @@
 * *******************************************************/
 
 qspim_top
-#                             (
+#(
 `ifndef SYNTHESIS
     .WB_WIDTH  (WB_WIDTH                                    )
 `endif

diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
index 7e062f0..fd68e08 100644
--- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
+++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv

@@ -240,18 +240,28 @@
   logic  	wbd_err;
 } type_wb_rd_intf;
 
-
-// Master Write Interface
-type_wb_wr_intf  m0_wb_wr;
-type_wb_wr_intf  m1_wb_wr;
-type_wb_wr_intf  m2_wb_wr;
-type_wb_wr_intf  m3_wb_wr;
-
 // Master Read Interface
-type_wb_rd_intf  m0_wb_rd;
-type_wb_rd_intf  m1_wb_rd;
-type_wb_rd_intf  m2_wb_rd;
-type_wb_rd_intf  m3_wb_rd;
+type_wb_rd_intf  m0_bus_rd;
+type_wb_rd_intf  m1_bus_rd;
+type_wb_rd_intf  m2_bus_rd;
+type_wb_rd_intf  m3_bus_rd;
+
+
+type_wb_rd_intf  m0_s0_wb_rd;
+type_wb_rd_intf  m1_s0_wb_rd;
+type_wb_rd_intf  m2_s0_wb_rd;
+type_wb_rd_intf  m3_s0_wb_rd;
+
+type_wb_rd_intf  m0_s1_wb_rd;
+type_wb_rd_intf  m1_s1_wb_rd;
+type_wb_rd_intf  m2_s1_wb_rd;
+type_wb_rd_intf  m3_s1_wb_rd;
+
+type_wb_rd_intf  m0_s2_wb_rd;
+type_wb_rd_intf  m1_s2_wb_rd;
+type_wb_rd_intf  m2_s2_wb_rd;
+type_wb_rd_intf  m3_s2_wb_rd;
+
 
 // Slave Write Interface
 type_wb_wr_intf  s0_wb_wr;
@@ -264,12 +274,6 @@
 type_wb_rd_intf  s2_wb_rd;
 
 
-type_wb_wr_intf  m_bus_wr;  // Multiplexed Master I/F
-type_wb_rd_intf  m_bus_rd;  // Multiplexed Slave I/F
-
-type_wb_wr_intf  s_bus_wr;  // Multiplexed Master I/F
-type_wb_rd_intf  s_bus_rd;  // Multiplexed Slave I/F
-
 // channel repeater
 assign ch_clk_out  = ch_clk_in;
 assign ch_data_out = ch_data_in;
@@ -331,73 +335,321 @@
                               (m3_wbd_adr_i[31:16] == 16'h1001 ) ? TARGET_UART : 
                               (m3_wbd_adr_i[31:16] == 16'h1002 ) ? TARGET_PINMUX : 
 			      4'b0000; 
-//----------------------------------------
-// Master Mapping
-// -------------------------------------
-assign m0_wb_wr.wbd_dat = m0_wbd_dat_i;
-assign m0_wb_wr.wbd_adr = {m0_wbd_adr_i[31:2],2'b00};
-assign m0_wb_wr.wbd_sel = m0_wbd_sel_i;
-assign m0_wb_wr.wbd_bl  = 'h1;
-assign m0_wb_wr.wbd_bry = 'b1;
-assign m0_wb_wr.wbd_we  = m0_wbd_we_i;
-assign m0_wb_wr.wbd_cyc = m0_wbd_cyc_i;
-assign m0_wb_wr.wbd_stb = m0_wbd_stb_i;
-assign m0_wb_wr.wbd_tid = m0_wbd_tid_i;
 
-assign m1_wb_wr.wbd_dat = m1_wbd_dat_i;
-assign m1_wb_wr.wbd_adr = {m1_wbd_adr_i[31:2],2'b00};
-assign m1_wb_wr.wbd_sel = m1_wbd_sel_i;
-assign m1_wb_wr.wbd_bl  = 'h1;
-assign m1_wb_wr.wbd_bry = 'b1;
-assign m1_wb_wr.wbd_we  = m1_wbd_we_i;
-assign m1_wb_wr.wbd_cyc = m1_wbd_cyc_i;
-assign m1_wb_wr.wbd_stb = m1_wbd_stb_i;
-assign m1_wb_wr.wbd_tid = m1_wbd_tid_i;
 
-assign m2_wb_wr.wbd_dat = m2_wbd_dat_i;
-assign m2_wb_wr.wbd_adr = {m2_wbd_adr_i[31:2],2'b00};
-assign m2_wb_wr.wbd_sel = m2_wbd_sel_i;
-assign m2_wb_wr.wbd_bl  = m2_wbd_bl_i;
-assign m2_wb_wr.wbd_bry = m2_wbd_bry_i;
-assign m2_wb_wr.wbd_we  = m2_wbd_we_i;
-assign m2_wb_wr.wbd_cyc = m2_wbd_cyc_i;
-assign m2_wb_wr.wbd_stb = m2_wbd_stb_i;
-assign m2_wb_wr.wbd_tid = m2_wbd_tid_i;
+// Target Port -0
+wb_slave_port  u_s0 (
 
-assign m3_wb_wr.wbd_dat = 'h0;
-assign m3_wb_wr.wbd_adr = {m3_wbd_adr_i[31:2],2'b00};
-assign m3_wb_wr.wbd_sel = m3_wbd_sel_i;
-assign m3_wb_wr.wbd_bl  = m3_wbd_bl_i;
-assign m3_wb_wr.wbd_bry = m3_wbd_bry_i;
-assign m3_wb_wr.wbd_we  = m3_wbd_we_i;
-assign m3_wb_wr.wbd_cyc = m3_wbd_cyc_i;
-assign m3_wb_wr.wbd_stb = m3_wbd_stb_i;
-assign m3_wb_wr.wbd_tid = m3_wbd_tid_i;
+          .clk_i                   (clk_i                  ), 
+          .rst_n                   (rst_n                  ),
+	  .cfg_slave_id            (TARGET_SPI_MEM         ),
 
-assign m0_wbd_dat_o  =  m0_wb_rd.wbd_dat;
-assign m0_wbd_ack_o  =  m0_wb_rd.wbd_ack;
-assign m0_wbd_lack_o =  m0_wb_rd.wbd_lack;
-assign m0_wbd_err_o  =  m0_wb_rd.wbd_err;
+         // Master 0 Interface
+          .m0_wbd_dat_i            (m0_wbd_dat_i           ),
+          .m0_wbd_adr_i            (m0_wbd_adr_i           ),
+          .m0_wbd_sel_i            (m0_wbd_sel_i           ),
+          .m0_wbd_we_i             (m0_wbd_we_i            ),
+          .m0_wbd_cyc_i            (m0_wbd_cyc_i           ),
+          .m0_wbd_stb_i            (m0_wbd_stb_i           ),
+	  .m0_wbd_tid_i            (m0_wbd_tid_i           ),
+          .m0_wbd_dat_o            (m0_s0_wb_rd.wbd_dat    ),
+          .m0_wbd_ack_o            (m0_s0_wb_rd.wbd_ack    ),
+          .m0_wbd_lack_o           (m0_s0_wb_rd.wbd_lack   ),
+          .m0_wbd_err_o            (m0_s0_wb_rd.wbd_err    ),
+         
+         // Master 1 Interface
+          .m1_wbd_dat_i            (m1_wbd_dat_i           ),
+          .m1_wbd_adr_i            (m1_wbd_adr_i           ),
+          .m1_wbd_sel_i            (m1_wbd_sel_i           ),
+          .m1_wbd_we_i             (m1_wbd_we_i            ),
+          .m1_wbd_cyc_i            (m1_wbd_cyc_i           ),
+          .m1_wbd_stb_i            (m1_wbd_stb_i           ),
+	  .m1_wbd_tid_i            (m1_wbd_tid_i           ),
+          .m1_wbd_dat_o            (m1_s0_wb_rd.wbd_dat    ),
+          .m1_wbd_ack_o            (m1_s0_wb_rd.wbd_ack    ),
+          .m1_wbd_lack_o           (m1_s0_wb_rd.wbd_lack   ),
+          .m1_wbd_err_o            (m1_s0_wb_rd.wbd_err    ),
+         
+         // Master 2 Interface
+          .m2_wbd_dat_i            (m2_wbd_dat_i           ),
+          .m2_wbd_adr_i            (m2_wbd_adr_i           ),
+          .m2_wbd_sel_i            (m2_wbd_sel_i           ),
+          .m2_wbd_bl_i             (m2_wbd_bl_i            ),
+          .m2_wbd_bry_i            (m2_wbd_bry_i           ),
+          .m2_wbd_we_i             (m2_wbd_we_i            ),
+          .m2_wbd_cyc_i            (m2_wbd_cyc_i           ),
+          .m2_wbd_stb_i            (m2_wbd_stb_i           ),
+	  .m2_wbd_tid_i            (m2_wbd_tid_i           ),
+          .m2_wbd_dat_o            (m2_s0_wb_rd.wbd_dat    ),
+          .m2_wbd_ack_o            (m2_s0_wb_rd.wbd_ack    ),
+          .m2_wbd_lack_o           (m2_s0_wb_rd.wbd_lack   ),
+          .m2_wbd_err_o            (m2_s0_wb_rd.wbd_err    ),
 
-assign m1_wbd_dat_o  =  m1_wb_rd.wbd_dat;
-assign m1_wbd_ack_o  =  m1_wb_rd.wbd_ack;
-assign m1_wbd_lack_o =  m1_wb_rd.wbd_lack;
-assign m1_wbd_err_o  =  m1_wb_rd.wbd_err;
+         // Master 3 Interface
+          .m3_wbd_adr_i            (m3_wbd_adr_i           ),
+          .m3_wbd_sel_i            (m3_wbd_sel_i           ),
+          .m3_wbd_bl_i             (m3_wbd_bl_i            ),
+          .m3_wbd_bry_i            (m3_wbd_bry_i           ),
+          .m3_wbd_we_i             (m3_wbd_we_i            ),
+          .m3_wbd_cyc_i            (m3_wbd_cyc_i           ),
+          .m3_wbd_stb_i            (m3_wbd_stb_i           ),
+	  .m3_wbd_tid_i            (m3_wbd_tid_i           ),
+          .m3_wbd_dat_o            (m3_s0_wb_rd.wbd_dat    ),
+          .m3_wbd_ack_o            (m3_s0_wb_rd.wbd_ack    ),
+          .m3_wbd_lack_o           (m3_s0_wb_rd.wbd_lack   ),
+          .m3_wbd_err_o            (m3_s0_wb_rd.wbd_err    ),
+         
+         
+         // Slave  Interface
+          .s_wbd_dat_i            (s0_wb_rd.wbd_dat        ),
+          .s_wbd_ack_i            (s0_wb_rd.wbd_ack        ),
+          .s_wbd_lack_i           (s0_wb_rd.wbd_lack       ),
+          .s_wbd_dat_o            (s0_wb_wr.wbd_dat        ),
+          .s_wbd_adr_o            (s0_wb_wr.wbd_adr        ),
+          .s_wbd_bry_o            (s0_wb_wr.wbd_bry        ),
+          .s_wbd_bl_o             (s0_wb_wr.wbd_bl         ),
+          .s_wbd_sel_o            (s0_wb_wr.wbd_sel        ),
+          .s_wbd_we_o             (s0_wb_wr.wbd_we         ),  
+          .s_wbd_cyc_o            (s0_wb_wr.wbd_cyc        ),
+          .s_wbd_stb_o            (s0_wb_wr.wbd_stb        )
+         
+	);
 
-assign m2_wbd_dat_o  =  m2_wb_rd.wbd_dat;
-assign m2_wbd_ack_o  =  m2_wb_rd.wbd_ack;
-assign m2_wbd_lack_o =  m2_wb_rd.wbd_lack;
-assign m2_wbd_err_o  =  m2_wb_rd.wbd_err;
+// Target Port -1
+wb_slave_port  u_s1 (
 
-assign m3_wbd_dat_o  =  m3_wb_rd.wbd_dat;
-assign m3_wbd_ack_o  =  m3_wb_rd.wbd_ack;
-assign m3_wbd_lack_o =  m3_wb_rd.wbd_lack;
-assign m3_wbd_err_o  =  m3_wb_rd.wbd_err;
+          .clk_i                   (clk_i                  ), 
+          .rst_n                   (rst_n                  ),
+	  .cfg_slave_id            (TARGET_UART            ),
+
+         // Master 0 Interface
+          .m0_wbd_dat_i            (m0_wbd_dat_i           ),
+          .m0_wbd_adr_i            (m0_wbd_adr_i           ),
+          .m0_wbd_sel_i            (m0_wbd_sel_i           ),
+          .m0_wbd_we_i             (m0_wbd_we_i            ),
+          .m0_wbd_cyc_i            (m0_wbd_cyc_i           ),
+          .m0_wbd_stb_i            (m0_wbd_stb_i           ),
+	  .m0_wbd_tid_i            (m0_wbd_tid_i           ),
+          .m0_wbd_dat_o            (m0_s1_wb_rd.wbd_dat    ),
+          .m0_wbd_ack_o            (m0_s1_wb_rd.wbd_ack    ),
+          .m0_wbd_lack_o           (m0_s1_wb_rd.wbd_lack   ),
+          .m0_wbd_err_o            (m0_s1_wb_rd.wbd_err    ),
+         
+         // Master 1 Interface
+          .m1_wbd_dat_i            (m1_wbd_dat_i           ),
+          .m1_wbd_adr_i            (m1_wbd_adr_i           ),
+          .m1_wbd_sel_i            (m1_wbd_sel_i           ),
+          .m1_wbd_we_i             (m1_wbd_we_i            ),
+          .m1_wbd_cyc_i            (m1_wbd_cyc_i           ),
+          .m1_wbd_stb_i            (m1_wbd_stb_i           ),
+	  .m1_wbd_tid_i            (m1_wbd_tid_i           ),
+          .m1_wbd_dat_o            (m1_s1_wb_rd.wbd_dat    ),
+          .m1_wbd_ack_o            (m1_s1_wb_rd.wbd_ack    ),
+          .m1_wbd_lack_o           (m1_s1_wb_rd.wbd_lack   ),
+          .m1_wbd_err_o            (m1_s1_wb_rd.wbd_err    ),
+         
+         // Master 2 Interface
+          .m2_wbd_dat_i            (m2_wbd_dat_i           ),
+          .m2_wbd_adr_i            (m2_wbd_adr_i           ),
+          .m2_wbd_sel_i            (m2_wbd_sel_i           ),
+          .m2_wbd_bl_i             (m2_wbd_bl_i            ),
+          .m2_wbd_bry_i            (m2_wbd_bry_i           ),
+          .m2_wbd_we_i             (m2_wbd_we_i            ),
+          .m2_wbd_cyc_i            (m2_wbd_cyc_i           ),
+          .m2_wbd_stb_i            (m2_wbd_stb_i           ),
+	  .m2_wbd_tid_i            (m2_wbd_tid_i           ),
+          .m2_wbd_dat_o            (m2_s1_wb_rd.wbd_dat    ),
+          .m2_wbd_ack_o            (m2_s1_wb_rd.wbd_ack    ),
+          .m2_wbd_lack_o           (m2_s1_wb_rd.wbd_lack   ),
+          .m2_wbd_err_o            (m2_s1_wb_rd.wbd_err    ),
+
+         // Master 3 Interface
+          .m3_wbd_adr_i            (m3_wbd_adr_i           ),
+          .m3_wbd_sel_i            (m3_wbd_sel_i           ),
+          .m3_wbd_bl_i             (m3_wbd_bl_i            ),
+          .m3_wbd_bry_i            (m3_wbd_bry_i           ),
+          .m3_wbd_we_i             (m3_wbd_we_i            ),
+          .m3_wbd_cyc_i            (m3_wbd_cyc_i           ),
+          .m3_wbd_stb_i            (m3_wbd_stb_i           ),
+	  .m3_wbd_tid_i            (m3_wbd_tid_i           ),
+          .m3_wbd_dat_o            (m3_s1_wb_rd.wbd_dat    ),
+          .m3_wbd_ack_o            (m3_s1_wb_rd.wbd_ack    ),
+          .m3_wbd_lack_o           (m3_s1_wb_rd.wbd_lack   ),
+          .m3_wbd_err_o            (m3_s1_wb_rd.wbd_err    ),
+         
+         
+         // Slave  Interface
+          .s_wbd_dat_i            (s1_wb_rd.wbd_dat        ),
+          .s_wbd_ack_i            (s1_wb_rd.wbd_ack        ),
+          .s_wbd_lack_i           (s1_wb_rd.wbd_lack       ),
+          .s_wbd_dat_o            (s1_wb_wr.wbd_dat        ),
+          .s_wbd_adr_o            (s1_wb_wr.wbd_adr        ),
+          .s_wbd_bry_o            (s1_wb_wr.wbd_bry        ),
+          .s_wbd_bl_o             (s1_wb_wr.wbd_bl         ),
+          .s_wbd_sel_o            (s1_wb_wr.wbd_sel        ),
+          .s_wbd_we_o             (s1_wb_wr.wbd_we         ),  
+          .s_wbd_cyc_o            (s1_wb_wr.wbd_cyc        ),
+          .s_wbd_stb_o            (s1_wb_wr.wbd_stb        )
+         
+	);
+
+// Target Port -2
+wb_slave_port  u_s2 (
+
+          .clk_i                   (clk_i                  ), 
+          .rst_n                   (rst_n                  ),
+	  .cfg_slave_id            (TARGET_PINMUX          ),
+
+         // Master 0 Interface
+          .m0_wbd_dat_i            (m0_wbd_dat_i           ),
+          .m0_wbd_adr_i            (m0_wbd_adr_i           ),
+          .m0_wbd_sel_i            (m0_wbd_sel_i           ),
+          .m0_wbd_we_i             (m0_wbd_we_i            ),
+          .m0_wbd_cyc_i            (m0_wbd_cyc_i           ),
+          .m0_wbd_stb_i            (m0_wbd_stb_i           ),
+	  .m0_wbd_tid_i            (m0_wbd_tid_i           ),
+          .m0_wbd_dat_o            (m0_s2_wb_rd.wbd_dat    ),
+          .m0_wbd_ack_o            (m0_s2_wb_rd.wbd_ack    ),
+          .m0_wbd_lack_o           (m0_s2_wb_rd.wbd_lack   ),
+          .m0_wbd_err_o            (m0_s2_wb_rd.wbd_err    ),
+         
+         // Master 1 Interface
+          .m1_wbd_dat_i            (m1_wbd_dat_i           ),
+          .m1_wbd_adr_i            (m1_wbd_adr_i           ),
+          .m1_wbd_sel_i            (m1_wbd_sel_i           ),
+          .m1_wbd_we_i             (m1_wbd_we_i            ),
+          .m1_wbd_cyc_i            (m1_wbd_cyc_i           ),
+          .m1_wbd_stb_i            (m1_wbd_stb_i           ),
+	  .m1_wbd_tid_i            (m1_wbd_tid_i           ),
+          .m1_wbd_dat_o            (m1_s2_wb_rd.wbd_dat    ),
+          .m1_wbd_ack_o            (m1_s2_wb_rd.wbd_ack    ),
+          .m1_wbd_lack_o           (m1_s2_wb_rd.wbd_lack   ),
+          .m1_wbd_err_o            (m1_s2_wb_rd.wbd_err    ),
+         
+         // Master 2 Interface
+          .m2_wbd_dat_i            (m2_wbd_dat_i           ),
+          .m2_wbd_adr_i            (m2_wbd_adr_i           ),
+          .m2_wbd_sel_i            (m2_wbd_sel_i           ),
+          .m2_wbd_bl_i             (m2_wbd_bl_i            ),
+          .m2_wbd_bry_i            (m2_wbd_bry_i           ),
+          .m2_wbd_we_i             (m2_wbd_we_i            ),
+          .m2_wbd_cyc_i            (m2_wbd_cyc_i           ),
+          .m2_wbd_stb_i            (m2_wbd_stb_i           ),
+	  .m2_wbd_tid_i            (m2_wbd_tid_i           ),
+          .m2_wbd_dat_o            (m2_s2_wb_rd.wbd_dat    ),
+          .m2_wbd_ack_o            (m2_s2_wb_rd.wbd_ack    ),
+          .m2_wbd_lack_o           (m2_s2_wb_rd.wbd_lack   ),
+          .m2_wbd_err_o            (m2_s2_wb_rd.wbd_err    ),
+
+         // Master 3 Interface
+          .m3_wbd_adr_i            (m3_wbd_adr_i           ),
+          .m3_wbd_sel_i            (m3_wbd_sel_i           ),
+          .m3_wbd_bl_i             (m3_wbd_bl_i            ),
+          .m3_wbd_bry_i            (m3_wbd_bry_i           ),
+          .m3_wbd_we_i             (m3_wbd_we_i            ),
+          .m3_wbd_cyc_i            (m3_wbd_cyc_i           ),
+          .m3_wbd_stb_i            (m3_wbd_stb_i           ),
+	  .m3_wbd_tid_i            (m3_wbd_tid_i           ),
+          .m3_wbd_dat_o            (m3_s2_wb_rd.wbd_dat    ),
+          .m3_wbd_ack_o            (m3_s2_wb_rd.wbd_ack    ),
+          .m3_wbd_lack_o           (m3_s2_wb_rd.wbd_lack   ),
+          .m3_wbd_err_o            (m3_s2_wb_rd.wbd_err    ),
+         
+         
+         // Slave  Interface
+          .s_wbd_dat_i            (s2_wb_rd.wbd_dat        ),
+          .s_wbd_ack_i            (s2_wb_rd.wbd_ack        ),
+          .s_wbd_lack_i           (s2_wb_rd.wbd_lack       ),
+          .s_wbd_dat_o            (s2_wb_wr.wbd_dat        ),
+          .s_wbd_adr_o            (s2_wb_wr.wbd_adr        ),
+          .s_wbd_bry_o            (s2_wb_wr.wbd_bry        ),
+          .s_wbd_bl_o             (s2_wb_wr.wbd_bl         ),
+          .s_wbd_sel_o            (s2_wb_wr.wbd_sel        ),
+          .s_wbd_we_o             (s2_wb_wr.wbd_we         ),  
+          .s_wbd_cyc_o            (s2_wb_wr.wbd_cyc        ),
+          .s_wbd_stb_o            (s2_wb_wr.wbd_stb        )
+         
+	);
+
+/////////////////////////////////////////////////
+// Master-0 Mapping
+// ---------------------------------------------
+
+assign m0_wbd_dat_o  = m0_bus_rd.wbd_dat;
+assign m0_wbd_ack_o  = m0_bus_rd.wbd_ack;
+assign m0_wbd_lack_o = m0_bus_rd.wbd_lack;
+assign m0_wbd_err_o  = m0_bus_rd.wbd_err;
+
+always_comb begin
+     case(m0_wbd_tid_i)
+        TARGET_SPI_MEM:	   m0_bus_rd = m0_s0_wb_rd;
+        TARGET_SPI_REG:	   m0_bus_rd = m0_s0_wb_rd;
+        TARGET_UART:	   m0_bus_rd = m0_s1_wb_rd;
+        TARGET_PINMUX:	   m0_bus_rd = m0_s2_wb_rd;
+        default:           m0_bus_rd = m0_s0_wb_rd;
+     endcase			
+end
+
+/////////////////////////////////////////////////
+// Master-1 Mapping
+// ---------------------------------------------
+
+assign m1_wbd_dat_o  = m1_bus_rd.wbd_dat;
+assign m1_wbd_ack_o  = m1_bus_rd.wbd_ack;
+assign m1_wbd_lack_o = m1_bus_rd.wbd_lack;
+assign m1_wbd_err_o  = m1_bus_rd.wbd_err;
+
+always_comb begin
+     case(m1_wbd_tid_i)
+        TARGET_SPI_MEM:	   m1_bus_rd = m1_s0_wb_rd;
+        TARGET_SPI_REG:	   m1_bus_rd = m1_s0_wb_rd;
+        TARGET_UART:	   m1_bus_rd = m1_s1_wb_rd;
+        TARGET_PINMUX:	   m1_bus_rd = m1_s2_wb_rd;
+        default:           m1_bus_rd = m1_s0_wb_rd;
+     endcase			
+end
+
+/////////////////////////////////////////////////
+// Master-2 Mapping
+// ---------------------------------------------
+
+assign m2_wbd_dat_o  = m2_bus_rd.wbd_dat;
+assign m2_wbd_ack_o  = m2_bus_rd.wbd_ack;
+assign m2_wbd_lack_o = m2_bus_rd.wbd_lack;
+assign m2_wbd_err_o  = m2_bus_rd.wbd_err;
+
+always_comb begin
+     case(m2_wbd_tid_i)
+        TARGET_SPI_MEM:	   m2_bus_rd = m2_s0_wb_rd;
+        TARGET_SPI_REG:	   m2_bus_rd = m2_s0_wb_rd;
+        TARGET_UART:	   m2_bus_rd = m2_s1_wb_rd;
+        TARGET_PINMUX:	   m2_bus_rd = m2_s2_wb_rd;
+        default:           m2_bus_rd = m2_s0_wb_rd;
+     endcase			
+end
+
+/////////////////////////////////////////////////
+// Master-3 Mapping
+// ---------------------------------------------
+
+assign m3_wbd_dat_o  = m3_bus_rd.wbd_dat;
+assign m3_wbd_ack_o  = m3_bus_rd.wbd_ack;
+assign m3_wbd_lack_o = m3_bus_rd.wbd_lack;
+assign m3_wbd_err_o  = m3_bus_rd.wbd_err;
+
+always_comb begin
+     case(m3_wbd_tid_i)
+        TARGET_SPI_MEM:	   m3_bus_rd = m3_s0_wb_rd;
+        TARGET_SPI_REG:	   m3_bus_rd = m3_s0_wb_rd;
+        TARGET_UART:	   m3_bus_rd = m3_s1_wb_rd;
+        TARGET_PINMUX:	   m3_bus_rd = m3_s2_wb_rd;
+        default:           m3_bus_rd = m3_s0_wb_rd;
+     endcase			
+end
 
 //----------------------------------------
 // Slave Mapping
 // -------------------------------------
-// Masked Now and added stagging FF now
  assign  s0_wbd_dat_o =  s0_wb_wr.wbd_dat ;
  assign  s0_wbd_adr_o =  s0_wb_wr.wbd_adr ;
  assign  s0_wbd_sel_o =  s0_wb_wr.wbd_sel ;
@@ -439,93 +691,8 @@
  assign s2_wb_rd.wbd_err  = 1'b0; // s2_wbd_err_i ; - unused
 
 
-//
-// arbitor 
-//
-logic [1:0]  gnt;
-
-wb_arb	u_wb_arb(
-	.clk(clk_i), 
-	.rstn(rst_n),
-	.req({	m3_wbd_stb_i & !m3_wbd_lack_o,
-	        m2_wbd_stb_i & !m2_wbd_lack_o,
-		m1_wbd_stb_i & !m1_wbd_lack_o,
-		m0_wbd_stb_i & !m0_wbd_lack_o}),
-	.gnt(gnt)
-);
 
 
-// Generate Multiplexed Master Interface based on grant
-always_comb begin
-     case(gnt)
-        3'h0:	   m_bus_wr = m0_wb_wr;
-        3'h1:	   m_bus_wr = m1_wb_wr;
-        3'h2:	   m_bus_wr = m2_wb_wr;
-        3'h3:	   m_bus_wr = m3_wb_wr;
-        default:   m_bus_wr = m0_wb_wr;
-     endcase			
-end
-
-
-// Generate Multiplexed Slave Interface based on target Id
-wire [3:0] s_wbd_tid =  s_bus_wr.wbd_tid; // to fix iverilog warning
-always_comb begin
-     case(s_wbd_tid)
-        4'h0:	   s_bus_rd = s0_wb_rd;
-        4'h1:	   s_bus_rd = s1_wb_rd;
-        4'h2:	   s_bus_rd = s2_wb_rd;
-        default:   s_bus_rd = s0_wb_rd;
-     endcase			
-end
-
-
-// Connect Master => Slave
-assign  s0_wb_wr = (s_wbd_tid == 3'b000) ? s_bus_wr : 'h0;
-assign  s1_wb_wr = (s_wbd_tid == 3'b001) ? s_bus_wr : 'h0;
-assign  s2_wb_wr = (s_wbd_tid == 3'b010) ? s_bus_wr : 'h0;
-
-// Connect Slave to Master
-assign  m0_wb_rd = (gnt == 2'b00) ? m_bus_rd : 'h0;
-assign  m1_wb_rd = (gnt == 2'b01) ? m_bus_rd : 'h0;
-assign  m2_wb_rd = (gnt == 2'b10) ? m_bus_rd : 'h0;
-assign  m3_wb_rd = (gnt == 2'b11) ? m_bus_rd : 'h0;
-
-
-// Stagging FF to break write and read timing path
-sync_wbb u_sync_wbb(
-         .clk_i            (clk_i               ), 
-         .rst_n            (rst_n               ),
-         // WishBone Input master I/P
-         .wbm_dat_i      (m_bus_wr.wbd_dat    ),
-         .wbm_adr_i      (m_bus_wr.wbd_adr    ),
-         .wbm_sel_i      (m_bus_wr.wbd_sel    ),
-         .wbm_bl_i       (m_bus_wr.wbd_bl     ),
-         .wbm_bry_i      (m_bus_wr.wbd_bry    ),
-         .wbm_we_i       (m_bus_wr.wbd_we     ),
-         .wbm_cyc_i      (m_bus_wr.wbd_cyc    ),
-         .wbm_stb_i      (m_bus_wr.wbd_stb    ),
-         .wbm_tid_i      (m_bus_wr.wbd_tid    ),
-         .wbm_dat_o      (m_bus_rd.wbd_dat    ),
-         .wbm_ack_o      (m_bus_rd.wbd_ack    ),
-         .wbm_lack_o     (m_bus_rd.wbd_lack   ),
-         .wbm_err_o      (m_bus_rd.wbd_err    ),
-
-         // Slave Interface
-         .wbs_dat_i      (s_bus_rd.wbd_dat    ),
-         .wbs_ack_i      (s_bus_rd.wbd_ack    ),
-         .wbs_lack_i     (s_bus_rd.wbd_lack   ),
-         .wbs_err_i      (s_bus_rd.wbd_err    ),
-         .wbs_dat_o      (s_bus_wr.wbd_dat    ),
-         .wbs_adr_o      (s_bus_wr.wbd_adr    ),
-         .wbs_sel_o      (s_bus_wr.wbd_sel    ),
-         .wbs_bl_o       (s_bus_wr.wbd_bl     ),
-         .wbs_bry_o      (s_bus_wr.wbd_bry    ),
-         .wbs_we_o       (s_bus_wr.wbd_we     ),
-         .wbs_cyc_o      (s_bus_wr.wbd_cyc    ),
-         .wbs_stb_o      (s_bus_wr.wbd_stb    ),
-         .wbs_tid_o      (s_bus_wr.wbd_tid    )
-
-);
 
 
 endmodule

diff --git a/verilog/rtl/wb_interconnect/src/wb_slave_port.sv b/verilog/rtl/wb_interconnect/src/wb_slave_port.sv
new file mode 100644
index 0000000..87f0d4a
--- /dev/null
+++ b/verilog/rtl/wb_interconnect/src/wb_slave_port.sv

@@ -0,0 +1,289 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  Wishbone interconnect for slave port                        ////
+////                                                              ////
+////  This file is part of the YIFive cores project               ////
+////  https://github.com/dineshannayya/riscduino.git              ////
+////                                                              ////
+////  Description                                                 ////
+////	1. This block implement simple round robine request       ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.1 - Mar 2, 2022, Dinesh A                               ////
+//////////////////////////////////////////////////////////////////////
+
+
+
+module wb_slave_port  (
+         input logic		clk_i, 
+         input logic            rst_n,
+
+         input logic [3:0]      cfg_slave_id,
+
+         
+         // Master 0 Interface
+         input   logic	[31:0]	m0_wbd_dat_i,
+         input   logic  [31:0]	m0_wbd_adr_i,
+         input   logic  [3:0]	m0_wbd_sel_i,
+         input   logic  	m0_wbd_we_i,
+         input   logic  	m0_wbd_cyc_i,
+         input   logic  	m0_wbd_stb_i,
+         input   logic  [3:0]   m0_wbd_tid_i,
+         output  logic	[31:0]	m0_wbd_dat_o,
+         output  logic		m0_wbd_ack_o,
+         output  logic		m0_wbd_lack_o,
+         output  logic		m0_wbd_err_o,
+         
+         // Master 1 Interface
+         input	logic [31:0]	m1_wbd_dat_i,
+         input	logic [31:0]	m1_wbd_adr_i,
+         input	logic [3:0]	m1_wbd_sel_i,
+         input	logic 	        m1_wbd_we_i,
+         input	logic 	        m1_wbd_cyc_i,
+         input	logic 	        m1_wbd_stb_i,
+         input  logic [3:0]     m1_wbd_tid_i,
+         output	logic [31:0]	m1_wbd_dat_o,
+         output	logic 	        m1_wbd_ack_o,
+         output	logic 	        m1_wbd_lack_o,
+         output	logic 	        m1_wbd_err_o,
+         
+         // Master 2 Interface
+         input	logic [31:0]	m2_wbd_dat_i,
+         input	logic [31:0]	m2_wbd_adr_i,
+         input	logic [3:0]	m2_wbd_sel_i,
+         input	logic [9:0]	m2_wbd_bl_i,
+         input	logic    	m2_wbd_bry_i,
+         input	logic 	        m2_wbd_we_i,
+         input	logic 	        m2_wbd_cyc_i,
+         input	logic 	        m2_wbd_stb_i,
+         input  logic [3:0]     m2_wbd_tid_i,
+         output	logic [31:0]	m2_wbd_dat_o,
+         output	logic 	        m2_wbd_ack_o,
+         output	logic 	        m2_wbd_lack_o,
+         output	logic 	        m2_wbd_err_o,
+         
+         // Master 3 Interface
+         input	logic [31:0]	m3_wbd_adr_i,
+         input	logic [3:0]	m3_wbd_sel_i,
+         input	logic [9:0]	m3_wbd_bl_i,
+         input	logic    	m3_wbd_bry_i,
+         input	logic 	        m3_wbd_we_i,
+         input	logic 	        m3_wbd_cyc_i,
+         input	logic 	        m3_wbd_stb_i,
+         input  logic [3:0]     m3_wbd_tid_i,
+         output	logic [31:0]	m3_wbd_dat_o,
+         output	logic 	        m3_wbd_ack_o,
+         output	logic 	        m3_wbd_lack_o,
+         output	logic 	        m3_wbd_err_o,
+         
+         // Slave 0 Interface
+         input	logic [31:0]	s_wbd_dat_i,
+         input	logic 	        s_wbd_ack_i,
+         input	logic 	        s_wbd_lack_i,
+         output	logic [31:0]	s_wbd_dat_o,
+         output	logic [31:0]	s_wbd_adr_o,
+         output	logic [3:0]	s_wbd_sel_o,
+         output	logic [9:0]	s_wbd_bl_o,
+         output	logic 	        s_wbd_bry_o,
+         output	logic 	        s_wbd_we_o,
+         output	logic 	        s_wbd_cyc_o,
+         output	logic 	        s_wbd_stb_o
+
+	);
+
+// WishBone Wr Interface
+typedef struct packed { 
+  logic	[31:0]	wbd_dat;
+  logic  [31:0]	wbd_adr;
+  logic  [3:0]	wbd_sel;
+  logic  [9:0]	wbd_bl;
+  logic  	wbd_bry;
+  logic  	wbd_we;
+  logic  	wbd_cyc;
+  logic  	wbd_stb;
+  logic [3:0] 	wbd_tid; // target id
+} type_wb_wr_intf;
+
+// WishBone Rd Interface
+typedef struct packed { 
+  logic	[31:0]	wbd_dat;
+  logic  	wbd_ack;
+  logic  	wbd_lack;
+  logic  	wbd_err;
+} type_wb_rd_intf;
+
+
+// Master Write Interface
+type_wb_wr_intf  m0_wb_wr;
+type_wb_wr_intf  m1_wb_wr;
+type_wb_wr_intf  m2_wb_wr;
+type_wb_wr_intf  m3_wb_wr;
+
+// Master Read Interface
+type_wb_rd_intf  m0_wb_rd;
+type_wb_rd_intf  m1_wb_rd;
+type_wb_rd_intf  m2_wb_rd;
+type_wb_rd_intf  m3_wb_rd;
+
+wire m0_stb_i = (m0_wbd_stb_i & (m0_wbd_tid_i== cfg_slave_id));
+wire m1_stb_i = (m1_wbd_stb_i & (m1_wbd_tid_i== cfg_slave_id));
+wire m2_stb_i = (m2_wbd_stb_i & (m2_wbd_tid_i== cfg_slave_id));
+wire m3_stb_i = (m3_wbd_stb_i & (m3_wbd_tid_i== cfg_slave_id));
+
+type_wb_wr_intf  m_bus_wr;  // Multiplexed Master I/F
+type_wb_rd_intf  m_bus_rd;  // Multiplexed Slave I/F
+
+//----------------------------------------
+// Master Mapping
+// -------------------------------------
+assign m0_wb_wr.wbd_dat = m0_wbd_dat_i;
+assign m0_wb_wr.wbd_adr = {m0_wbd_adr_i[31:2],2'b00};
+assign m0_wb_wr.wbd_sel = m0_wbd_sel_i;
+assign m0_wb_wr.wbd_bl  = 'h1;
+assign m0_wb_wr.wbd_bry = 'b1;
+assign m0_wb_wr.wbd_we  = m0_wbd_we_i;
+assign m0_wb_wr.wbd_cyc = m0_wbd_cyc_i;
+assign m0_wb_wr.wbd_stb = m0_stb_i;
+assign m0_wb_wr.wbd_tid = m0_wbd_tid_i;
+
+assign m1_wb_wr.wbd_dat = m1_wbd_dat_i;
+assign m1_wb_wr.wbd_adr = {m1_wbd_adr_i[31:2],2'b00};
+assign m1_wb_wr.wbd_sel = m1_wbd_sel_i;
+assign m1_wb_wr.wbd_bl  = 'h1;
+assign m1_wb_wr.wbd_bry = 'b1;
+assign m1_wb_wr.wbd_we  = m1_wbd_we_i;
+assign m1_wb_wr.wbd_cyc = m1_wbd_cyc_i;
+assign m1_wb_wr.wbd_stb = m1_stb_i;
+assign m1_wb_wr.wbd_tid = m1_wbd_tid_i;
+
+assign m2_wb_wr.wbd_dat = m2_wbd_dat_i;
+assign m2_wb_wr.wbd_adr = {m2_wbd_adr_i[31:2],2'b00};
+assign m2_wb_wr.wbd_sel = m2_wbd_sel_i;
+assign m2_wb_wr.wbd_bl  = m2_wbd_bl_i;
+assign m2_wb_wr.wbd_bry = m2_wbd_bry_i;
+assign m2_wb_wr.wbd_we  = m2_wbd_we_i;
+assign m2_wb_wr.wbd_cyc = m2_wbd_cyc_i;
+assign m2_wb_wr.wbd_stb = m2_stb_i;
+assign m2_wb_wr.wbd_tid = m2_wbd_tid_i;
+
+assign m3_wb_wr.wbd_dat = 'h0;
+assign m3_wb_wr.wbd_adr = {m3_wbd_adr_i[31:2],2'b00};
+assign m3_wb_wr.wbd_sel = m3_wbd_sel_i;
+assign m3_wb_wr.wbd_bl  = m3_wbd_bl_i;
+assign m3_wb_wr.wbd_bry = m3_wbd_bry_i;
+assign m3_wb_wr.wbd_we  = m3_wbd_we_i;
+assign m3_wb_wr.wbd_cyc = m3_wbd_cyc_i;
+assign m3_wb_wr.wbd_stb = m3_stb_i;
+assign m3_wb_wr.wbd_tid = m3_wbd_tid_i;
+
+assign m0_wbd_dat_o  =  m0_wb_rd.wbd_dat;
+assign m0_wbd_ack_o  =  m0_wb_rd.wbd_ack;
+assign m0_wbd_lack_o =  m0_wb_rd.wbd_lack;
+assign m0_wbd_err_o  =  m0_wb_rd.wbd_err;
+
+assign m1_wbd_dat_o  =  m1_wb_rd.wbd_dat;
+assign m1_wbd_ack_o  =  m1_wb_rd.wbd_ack;
+assign m1_wbd_lack_o =  m1_wb_rd.wbd_lack;
+assign m1_wbd_err_o  =  m1_wb_rd.wbd_err;
+
+assign m2_wbd_dat_o  =  m2_wb_rd.wbd_dat;
+assign m2_wbd_ack_o  =  m2_wb_rd.wbd_ack;
+assign m2_wbd_lack_o =  m2_wb_rd.wbd_lack;
+assign m2_wbd_err_o  =  m2_wb_rd.wbd_err;
+
+assign m3_wbd_dat_o  =  m3_wb_rd.wbd_dat;
+assign m3_wbd_ack_o  =  m3_wb_rd.wbd_ack;
+assign m3_wbd_lack_o =  m3_wb_rd.wbd_lack;
+assign m3_wbd_err_o  =  m3_wb_rd.wbd_err;
+
+//
+// arbitor 
+//
+logic [1:0]  gnt;
+wb_arb	u_wb_arb(
+	.clk(clk_i), 
+	.rstn(rst_n),
+	.req({	m3_stb_i & !m3_wbd_lack_o,
+	        m2_stb_i & !m2_wbd_lack_o,
+		m1_stb_i & !m1_wbd_lack_o,
+		m0_stb_i & !m0_wbd_lack_o}),
+	.gnt(gnt)
+);
+
+// Generate Multiplexed Master Interface based on grant
+always_comb begin
+     case(gnt)
+        3'h0:	   m_bus_wr = m0_wb_wr;
+        3'h1:	   m_bus_wr = m1_wb_wr;
+        3'h2:	   m_bus_wr = m2_wb_wr;
+        3'h3:	   m_bus_wr = m3_wb_wr;
+        default:   m_bus_wr = m0_wb_wr;
+     endcase			
+end
+
+// Stagging FF to break write and read timing path
+sync_wbb u_sync_wbb(
+         .clk_i            (clk_i               ), 
+         .rst_n            (rst_n               ),
+         // WishBone Input master I/P
+         .wbm_dat_i      (m_bus_wr.wbd_dat    ),
+         .wbm_adr_i      (m_bus_wr.wbd_adr    ),
+         .wbm_sel_i      (m_bus_wr.wbd_sel    ),
+         .wbm_bl_i       (m_bus_wr.wbd_bl     ),
+         .wbm_bry_i      (m_bus_wr.wbd_bry    ),
+         .wbm_we_i       (m_bus_wr.wbd_we     ),
+         .wbm_cyc_i      (m_bus_wr.wbd_cyc    ),
+         .wbm_stb_i      (m_bus_wr.wbd_stb    ),
+         .wbm_tid_i      (m_bus_wr.wbd_tid    ),
+         .wbm_dat_o      (m_bus_rd.wbd_dat    ),
+         .wbm_ack_o      (m_bus_rd.wbd_ack    ),
+         .wbm_lack_o     (m_bus_rd.wbd_lack   ),
+         .wbm_err_o      (m_bus_rd.wbd_err    ),
+
+         // Slave Interface
+         .wbs_dat_i      (s_wbd_dat_i    ),
+         .wbs_ack_i      (s_wbd_ack_i    ),
+         .wbs_lack_i     (s_wbd_lack_i   ),
+         .wbs_err_i      (1'b0           ),
+         .wbs_dat_o      (s_wbd_dat_o    ),
+         .wbs_adr_o      (s_wbd_adr_o    ),
+         .wbs_sel_o      (s_wbd_sel_o    ),
+         .wbs_bl_o       (s_wbd_bl_o     ),
+         .wbs_bry_o      (s_wbd_bry_o    ),
+         .wbs_we_o       (s_wbd_we_o     ),
+         .wbs_cyc_o      (s_wbd_cyc_o    ),
+         .wbs_stb_o      (s_wbd_stb_o    ),
+         .wbs_tid_o      (               )
+
+);
+
+// Connect Slave to Master
+assign  m0_wb_rd = (gnt == 2'b00) ? m_bus_rd : 'h0;
+assign  m1_wb_rd = (gnt == 2'b01) ? m_bus_rd : 'h0;
+assign  m2_wb_rd = (gnt == 2'b10) ? m_bus_rd : 'h0;
+assign  m3_wb_rd = (gnt == 2'b11) ? m_bus_rd : 'h0;
+
+endmodule