spi cs# increased to 1 to 4 and addition uart i/f added
diff --git a/openlane/pinmux/pin_order.cfg b/openlane/pinmux/pin_order.cfg index cc3fbf6..46dd963 100644 --- a/openlane/pinmux/pin_order.cfg +++ b/openlane/pinmux/pin_order.cfg
@@ -10,7 +10,8 @@ cpu_intf_rst_n qspim_rst_n sspim_rst_n -uart_rst_n +uart_rst_n\[1\] +uart_rst_n\[0\] i2cm_rst_n usb_rst_n cfg_riscv_ctrl\[15\] @@ -37,8 +38,10 @@ usb_oen usb_dp_i usb_dn_i -uart_txd -uart_rxd +uart_txd\[1\] +uart_rxd\[1\] +uart_txd\[0\] +uart_rxd\[0\] i2cm_clk_o i2cm_clk_i i2cm_clk_oen @@ -46,7 +49,10 @@ i2cm_data_o i2cm_data_i spim_sck -spim_ss +spim_ssn\[3\] +spim_ssn\[2\] +spim_ssn\[1\] +spim_ssn\[0\] spim_miso spim_mosi pulse1m_mclk
diff --git a/openlane/uart_i2cm_usb_spi_top/base.sdc b/openlane/uart_i2cm_usb_spi_top/base.sdc index 36725cd..735b5fb 100644 --- a/openlane/uart_i2cm_usb_spi_top/base.sdc +++ b/openlane/uart_i2cm_usb_spi_top/base.sdc
@@ -7,7 +7,8 @@ # Timing Constraints ############################################################################### create_clock -name app_clk -period 10.0000 [get_ports {app_clk}] -create_clock -name line_clk -period 100.0000 [get_pins {u_uart_core.u_lineclk_buf.u_mux/X}] +create_clock -name uart0_baud_clk -period 100.0000 [get_pins {u_uart0_core.u_lineclk_buf.u_mux/X}] +create_clock -name uart1_baud_clk -period 100.0000 [get_pins {u_uart1_core.u_lineclk_buf.u_mux/X}] create_clock -name usb_clk -period 100.0000 [get_ports {usb_clk}] set_clock_transition 0.1500 [all_clocks] @@ -19,7 +20,8 @@ set_clock_groups -name async_clock -asynchronous \ -group [get_clocks {app_clk}]\ -group [get_clocks {usb_clk}]\ - -group [get_clocks {line_clk}] -comment {Async Clock group} + -group [get_clocks {uart0_baud_clk}]\ + -group [get_clocks {uart1_baud_clk}] -comment {Async Clock group} ### ClkSkew Adjust set_case_analysis 0 [get_ports {cfg_cska_uart[0]}]
diff --git a/openlane/uart_i2cm_usb_spi_top/config.tcl b/openlane/uart_i2cm_usb_spi_top/config.tcl index 48ac117..2627452 100644 --- a/openlane/uart_i2cm_usb_spi_top/config.tcl +++ b/openlane/uart_i2cm_usb_spi_top/config.tcl
@@ -90,7 +90,7 @@ set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg set ::env(FP_SIZING) "absolute" -set ::env(DIE_AREA) [list 0.0 0.0 500.0 700.0] +set ::env(DIE_AREA) [list 0.0 0.0 510.0 725.0]
diff --git a/openlane/uart_i2cm_usb_spi_top/pin_order.cfg b/openlane/uart_i2cm_usb_spi_top/pin_order.cfg index 3fc5625..aba1684 100644 --- a/openlane/uart_i2cm_usb_spi_top/pin_order.cfg +++ b/openlane/uart_i2cm_usb_spi_top/pin_order.cfg
@@ -12,6 +12,7 @@ reg_cs 0100 0 2 reg_wr +reg_addr\[8\] reg_addr\[7\] reg_addr\[6\] reg_addr\[5\] @@ -94,7 +95,8 @@ #S usb_clk -uart_rstn +uart_rstn\[1] +uart_rstn\[0] i2c_rstn usb_rstn @@ -106,8 +108,10 @@ sda_pad_i sda_pad_o sda_padoen_o -uart_rxd -uart_txd +uart_rxd\[0\] +uart_txd\[0\] +uart_rxd\[1\] +uart_txd\[1\] usb_in_dp usb_in_dn usb_out_dp @@ -121,7 +125,10 @@ sspim_sck sspim_si sspim_so -sspim_ssn +sspim_ssn\[3\] +sspim_ssn\[2\] +sspim_ssn\[1\] +sspim_ssn\[0\]
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl index 882273d..2b03cd9 100755 --- a/openlane/wb_interconnect/config.tcl +++ b/openlane/wb_interconnect/config.tcl
@@ -70,7 +70,7 @@ set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 300 1800" +set ::env(DIE_AREA) "0 0 300 1725" # If you're going to use multiple power domains, then keep this disabled.
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg index 565b205..1534993 100644 --- a/openlane/wb_interconnect/pin_order.cfg +++ b/openlane/wb_interconnect/pin_order.cfg
@@ -621,6 +621,7 @@ s1_wbd_stb_o 0800 0 2 s1_wbd_we_o +s1_wbd_adr_o\[8\] s1_wbd_adr_o\[7\] s1_wbd_adr_o\[6\] s1_wbd_adr_o\[5\]
diff --git a/signoff/pinmux/final_summary_report.csv b/signoff/pinmux/final_summary_report.csv index 8e1159a..ebb323b 100644 --- a/signoff/pinmux/final_summary_report.csv +++ b/signoff/pinmux/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/pinmux,pinmux,pinmux,flow completed,0h9m20s0ms,0h6m7s0ms,49519.191919191915,0.2475,24759.595959595958,29.48,936.63,6128,0,0,0,0,0,0,0,-1,0,-1,-1,468563,60884,-9.8,-16.77,-1,0.0,0.0,-11351.48,-19355.22,-1,0.0,0.0,372119261.0,0.0,61.76,46.64,32.3,20.74,-1,4047,9543,812,6308,0,0,0,4592,151,83,49,96,1013,154,18,283,1206,1171,11,314,3259,0,3573,100.0,10.0,10,AREA 0,4,50,1,100,100,0.3,0.3,sky130_fd_sc_hd,4,4 +0,/project/openlane/pinmux,pinmux,pinmux,flow completed,0h9m26s0ms,0h6m3s0ms,49511.11111111112,0.2475,24755.55555555556,29.5,953.26,6127,0,0,0,0,0,0,0,-1,0,-1,-1,477211,61100,-9.79,-17.05,-1,0.0,0.0,-11345.75,-19529.63,-1,0.0,0.0,377081144.0,0.0,62.96,48.49,30.58,23.07,-1,4058,9565,814,6321,0,0,0,4603,152,83,49,97,1014,154,18,287,1210,1172,11,314,3259,0,3573,100.0,10.0,10,AREA 0,4,50,1,100,100,0.3,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/uart_i2cm_usb_spi_top/final_summary_report.csv b/signoff/uart_i2cm_usb_spi_top/final_summary_report.csv index 0ddfd92..3548532 100644 --- a/signoff/uart_i2cm_usb_spi_top/final_summary_report.csv +++ b/signoff/uart_i2cm_usb_spi_top/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/uart_i2cm_usb_spi_top,uart_i2c_usb_spi_top,uart_i2cm_usb_spi_top,flow completed,0h30m53s0ms,0h23m11s0ms,69285.71428571429,0.35,34642.857142857145,39.21,1367.28,12125,0,0,0,0,0,0,0,-1,0,-1,-1,594439,103896,0.0,0.0,0.0,0.0,-0.02,0.0,0.0,0.0,0.0,-0.02,369917177.0,0.0,51.11,51.47,19.26,22.98,-1,8702,13067,1552,5853,0,0,0,9824,392,189,256,272,2200,354,88,807,2409,2348,18,498,4643,0,5141,99.8003992015968,10.02,10,AREA 0,4,50,1,100,100,0.45,0.3,sky130_fd_sc_hd,4,4 +0,/project/openlane/uart_i2cm_usb_spi_top,uart_i2c_usb_spi_top,uart_i2cm_usb_spi_top,flow completed,0h17m15s0ms,0h11m50s0ms,78025.69303583504,0.36975,39012.84651791752,44.35,1438.48,14425,0,0,0,0,0,0,0,-1,0,-1,-1,702950,122604,0.0,-0.0,0.0,0.0,0.0,0.0,-0.0,0.0,0.0,0.0,442593619.0,0.0,56.86,57.94,21.95,25.41,-1,10340,15543,1940,7056,0,0,0,11580,425,250,279,358,2406,481,113,1133,2832,2749,18,516,4940,0,5456,100.0,10.0,10,AREA 0,4,50,1,100,100,0.45,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv index 2298a46..50ba5e6 100644 --- a/signoff/user_project_wrapper/final_summary_report.csv +++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,1h12m43s0ms,0h5m57s0ms,-2.0,-1,-1,-1,602.52,14,0,0,0,0,0,0,-1,0,0,-1,-1,1553303,14251,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,7.87,9.14,1.45,2.43,0.0,391,4300,391,4300,0,0,0,14,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,90,0.55,0.3,sky130_fd_sc_hd,4,0 +0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,1h8m41s0ms,0h4m26s0ms,-2.0,-1,-1,-1,590.45,14,0,0,0,0,0,0,-1,0,0,-1,-1,1558516,14240,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,7.83,9.11,1.58,2.6,0.0,391,4307,391,4307,0,0,0,14,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,90,0.55,0.3,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_interconnect/final_summary_report.csv b/signoff/wb_interconnect/final_summary_report.csv index 4087ef0..0f03517 100644 --- a/signoff/wb_interconnect/final_summary_report.csv +++ b/signoff/wb_interconnect/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow completed,0h31m53s0ms,0h24m20s0ms,40348.14814814815,0.54,20174.074074074077,18.13,1386.93,10894,0,0,0,0,0,0,0,-1,0,-1,-1,949047,90644,-1.53,-2.29,-1,-2.25,-2.33,-106.67,-188.2,-1,-259.9,-259.66,793691221.0,0.0,20.02,51.61,1.99,21.92,-1,3846,12864,637,9652,0,0,0,5341,269,12,304,131,626,98,13,1402,1753,1688,16,1306,7205,0,8511,81.10300081103001,12.33,10,AREA 0,2,50,1,153.6,153.18,0.2,0,sky130_fd_sc_hd,8,4 +0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow completed,0h41m2s0ms,0h36m0s0ms,42171.98067632851,0.5175,21085.990338164254,18.97,1315.86,10912,0,0,0,0,0,0,0,-1,0,-1,-1,944198,91561,-1.37,-2.18,-1,-2.16,-2.45,-101.7,-183.14,-1,-234.87,-227.37,766024314.0,0.0,22.5,51.36,3.09,22.47,-1,3853,12872,637,9653,0,0,0,5356,272,12,304,131,628,98,13,1407,1758,1694,17,1252,6908,0,8160,80.32128514056225,12.45,10,AREA 0,2,50,1,153.6,153.18,0.2,0,sky130_fd_sc_hd,8,4
diff --git a/sta/sdc/caravel.sdc b/sta/sdc/caravel.sdc index 85ec73f..494f7e6 100644 --- a/sta/sdc/caravel.sdc +++ b/sta/sdc/caravel.sdc
@@ -19,7 +19,8 @@ create_clock -name cpu_clk -period 20.0000 [get_pins {mprj/u_wb_host/cpu_clk}] create_clock -name rtc_clk -period 50.0000 [get_pins {mprj/u_wb_host/rtc_clk}] create_clock -name usb_clk -period 20.0000 [get_pins {mprj/u_wb_host/usb_clk}] -create_clock -name uarts_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart_core.u_lineclk_buf.u_mux/X}] +create_clock -name uarts0_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart0_core.u_lineclk_buf.u_mux/X}] +create_clock -name uarts1_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart0_core.u_lineclk_buf.u_mux/X}] create_clock -name uartm_clk -period 100.0000 [get_pins {mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.u_mux/X}] @@ -75,7 +76,8 @@ -group [get_clocks {cpu_ref_clk}]\ -group [get_clocks {rtc_clk}]\ -group [get_clocks {usb_clk}]\ - -group [get_clocks {uarts_clk}]\ + -group [get_clocks {uarts0_clk}]\ + -group [get_clocks {uarts1_clk}]\ -group [get_clocks {uartm_clk}]\ -comment {Async Clock group}
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile index 384be25..ca64f10 100644 --- a/verilog/dv/Makefile +++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@ .SUFFIXES: .SILENT: clean all -PATTERNS = wb_port risc_boot user_risc_boot user_uart user_qspi user_i2cm riscv_regress user_basic user_usb user_pwm user_timer user_uart_master uart_master +PATTERNS = wb_port risc_boot user_risc_boot user_uart user_uart1 user_qspi user_i2cm riscv_regress user_basic user_usb user_pwm user_timer user_uart_master uart_master all: ${PATTERNS} for i in ${PATTERNS}; do \
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v index e7612c8..94209cd 100644 --- a/verilog/dv/user_basic/user_basic_tb.v +++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -240,8 +240,8 @@ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h8273_8343); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h0104_2022); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0004_1000); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h0604_2022); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0004_2000); end
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v index 6be9759..aedd191 100644 --- a/verilog/dv/user_i2cm/user_i2cm_tb.v +++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -146,7 +146,7 @@ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h01); // Enable I2C Multi Functional Ports - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h200); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h4000); // Remove i2m reset wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h010);
diff --git a/verilog/dv/user_sspi/.flash1.hex.swp b/verilog/dv/user_sspi/.flash1.hex.swp deleted file mode 100644 index efe36dc..0000000 --- a/verilog/dv/user_sspi/.flash1.hex.swp +++ /dev/null Binary files differ
diff --git a/verilog/dv/user_sspi/.sspi_task.v.swp b/verilog/dv/user_sspi/.sspi_task.v.swp deleted file mode 100644 index ecd1440..0000000 --- a/verilog/dv/user_sspi/.sspi_task.v.swp +++ /dev/null Binary files differ
diff --git a/verilog/dv/user_sspi/flash0.hex b/verilog/dv/user_sspi/flash0.hex new file mode 100755 index 0000000..5f4ad8c --- /dev/null +++ b/verilog/dv/user_sspi/flash0.hex
@@ -0,0 +1,26 @@ +@00000000 +00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f +10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f +20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f +30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f +40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f +50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f +60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f +70 71 72 73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f +80 81 82 83 84 85 86 87 88 89 8a 8b 8c 8d 8e 8f +90 91 92 93 94 95 96 97 98 99 9a 9b 9c 9d 9e 9f +a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 aa ab ac ad ae af +b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 ba bb bc bd be bf +c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 ca cb cc cd ce cf +d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de df +e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 ea eb ec ed ee ef +f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff + +@00000100 +00 11 22 33 44 55 66 77 88 99 AA BB CC DD EE FF + +@00000200 +11 11 11 11 22 22 22 22 33 33 33 33 44 44 44 44 +55 55 55 55 66 66 66 66 77 77 77 77 88 88 88 88 +99 99 99 99 AA AA AA AA BB BB BB BB CC CC CC CC +DD DD DD DD EE EE EE EE FF FF FF FF 00 00 00 00
diff --git a/verilog/dv/user_sspi/flash1.hex b/verilog/dv/user_sspi/flash1.hex index e3c4b1b..476541e 100755 --- a/verilog/dv/user_sspi/flash1.hex +++ b/verilog/dv/user_sspi/flash1.hex
@@ -1,5 +1,4 @@ @00000000 -00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f @@ -17,10 +16,10 @@ f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff @00000100 -00 11 22 33 44 55 66 77 88 99 AA BB CC DD EE FF +11 22 33 44 55 66 77 88 99 AA BB CC DD EE FF 00 @00000200 -11 11 11 11 22 22 22 22 33 33 33 33 44 44 44 44 -55 55 55 55 66 66 66 66 77 77 77 77 88 88 88 88 -99 99 99 99 AA AA AA AA AA BB BB BB BB CC CC CC -DD DD DD DD EE EE EE EE FF FF FF FF 00 00 00 00 +22 22 22 22 33 33 33 33 44 44 44 44 55 55 55 55 +66 66 66 66 77 77 77 77 88 88 88 88 99 99 99 99 +AA AA AA AA BB BB BB BB CC CC CC CC DD DD DD DD +EE EE EE EE FF FF FF FF 00 00 00 00 11 11 11 11
diff --git a/verilog/dv/user_sspi/flash2.hex b/verilog/dv/user_sspi/flash2.hex new file mode 100755 index 0000000..477d682 --- /dev/null +++ b/verilog/dv/user_sspi/flash2.hex
@@ -0,0 +1,24 @@ +@00000000 +20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f +30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f +40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f +50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f +60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f +70 71 72 73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f +80 81 82 83 84 85 86 87 88 89 8a 8b 8c 8d 8e 8f +90 91 92 93 94 95 96 97 98 99 9a 9b 9c 9d 9e 9f +a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 aa ab ac ad ae af +b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 ba bb bc bd be bf +c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 ca cb cc cd ce cf +d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de df +e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 ea eb ec ed ee ef +f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff + +@00000100 +22 33 44 55 66 77 88 99 AA BB CC DD EE FF 00 11 + +@00000200 +33 33 33 33 44 44 44 44 55 55 55 55 66 66 66 66 +77 77 77 77 88 88 88 88 99 99 99 99 AA AA AA AA +BB BB BB BB CC CC CC CC DD DD DD DD EE EE EE EE +FF FF FF FF 00 00 00 00 11 11 11 11 22 22 22 22
diff --git a/verilog/dv/user_sspi/flash3.hex b/verilog/dv/user_sspi/flash3.hex new file mode 100755 index 0000000..200525e --- /dev/null +++ b/verilog/dv/user_sspi/flash3.hex
@@ -0,0 +1,23 @@ +@00000000 +30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f +40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f +50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f +60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f +70 71 72 73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f +80 81 82 83 84 85 86 87 88 89 8a 8b 8c 8d 8e 8f +90 91 92 93 94 95 96 97 98 99 9a 9b 9c 9d 9e 9f +a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 aa ab ac ad ae af +b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 ba bb bc bd be bf +c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 ca cb cc cd ce cf +d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de df +e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 ea eb ec ed ee ef +f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff + +@00000100 +33 44 55 66 77 88 99 AA BB CC DD EE FF 00 11 22 + +@00000200 +44 44 44 44 55 55 55 55 66 66 66 66 77 77 77 77 +88 88 88 88 99 99 99 99 AA AA AA AA BB BB BB BB +CC CC CC CC DD DD DD DD EE EE EE EE FF FF FF FF +00 00 00 00 11 11 11 11 22 22 22 22 11 11 11 11
diff --git a/verilog/dv/user_sspi/sspi_task.v b/verilog/dv/user_sspi/sspi_task.v index 1ce38eb..b084a0c 100755 --- a/verilog/dv/user_sspi/sspi_task.v +++ b/verilog/dv/user_sspi/sspi_task.v
@@ -63,7 +63,7 @@ sspi_write_dword({cmd,address[23:0]},BIG_ENDIAN,8'h0); sspi_write_byte(32'h00,BIG_ENDIAN,8'h0); // 8 Bit Dummy Cycle sspi_read_dword(LITTLE_ENDIAN,read_data,8'h1); - if(read_data != exp_data) begin + if(read_data !== exp_data) begin -> sspi_error_detected; $display("%m : ERROR : Address: %x Exp : %x Rxd : %x",address,exp_data,read_data); end else begin
diff --git a/verilog/dv/user_sspi/user_sspi_tb.v b/verilog/dv/user_sspi/user_sspi_tb.v index 6b6cbb4..e3cd34e 100644 --- a/verilog/dv/user_sspi/user_sspi_tb.v +++ b/verilog/dv/user_sspi/user_sspi_tb.v
@@ -140,7 +140,7 @@ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); // Enable SPI Multi Functional Ports - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h400); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h3C00); repeat (2) @(posedge clock); #1; @@ -155,7 +155,7 @@ repeat (200) @(posedge clock); wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 $display("############################################"); - $display(" Testing IS62/65WVS1288GALL SSRAM Read/Write Access "); + $display(" Testing IS62/65WVS1288GALL SSRAM[0] Read/Write Access "); $display("############################################"); // SSPI Indirect RAM READ ACCESS- // Byte Read Option @@ -207,7 +207,182 @@ sspi_dw_read_check(8'h03,24'h0208,32'h99AABBCC); sspi_dw_read_check(8'h03,24'h020C,32'hDDEEFF00); + $display("############################################"); + $display(" Testing IS62/65WVS1288GALL SSRAM[1] Read/Write Access "); + $display("############################################"); + // SSPI Indirect RAM READ ACCESS- + // Byte Read Option + // <Instr:0x3> <Addr:24Bit Address> <Read Data Out> + spi_chip_no = 2'b01; // Select the Chip Select to zero + sspi_dw_read_check(8'h03,24'h0000,32'h13121110); + sspi_dw_read_check(8'h03,24'h0004,32'h17161514); + sspi_dw_read_check(8'h03,24'h0008,32'h1B1A1918); + sspi_dw_read_check(8'h03,24'h000C,32'h1F1E1D1C); + + sspi_dw_read_check(8'h03,24'h0010,32'h23222120); + sspi_dw_read_check(8'h03,24'h0014,32'h27262524); + sspi_dw_read_check(8'h03,24'h0018,32'h2B2A2928); + sspi_dw_read_check(8'h03,24'h001C,32'h2F2E2D2C); + + sspi_dw_read_check(8'h03,24'h0020,32'h33323130); + sspi_dw_read_check(8'h03,24'h0024,32'h37363534); + sspi_dw_read_check(8'h03,24'h0028,32'h3B3A3938); + sspi_dw_read_check(8'h03,24'h002C,32'h3F3E3D3C); + sspi_dw_read_check(8'h03,24'h0030,32'h43424140); + sspi_dw_read_check(8'h03,24'h0034,32'h47464544); + sspi_dw_read_check(8'h03,24'h0038,32'h4B4A4948); + sspi_dw_read_check(8'h03,24'h003C,32'h4F4E4D4C); + + sspi_dw_read_check(8'h03,24'h00a0,32'hb3b2b1b0); + sspi_dw_read_check(8'h03,24'h00a4,32'hb7b6b5b4); + sspi_dw_read_check(8'h03,24'h00a8,32'hbbbab9b8); + sspi_dw_read_check(8'h03,24'h00aC,32'hbfbebdbc); + + sspi_dw_read_check(8'h03,24'h0200,32'h22222222); + sspi_dw_read_check(8'h03,24'h0204,32'h33333333); + sspi_dw_read_check(8'h03,24'h0208,32'h44444444); + sspi_dw_read_check(8'h03,24'h020C,32'h55555555); + + // SPI Write + sspi_dw_write(8'h02,24'h0000,32'h00112233); + sspi_dw_write(8'h02,24'h0004,32'h44556677); + sspi_dw_write(8'h02,24'h0008,32'h8899AABB); + sspi_dw_write(8'h02,24'h000C,32'hCCDDEEFF); + + sspi_dw_write(8'h02,24'h0200,32'h11223344); + sspi_dw_write(8'h02,24'h0204,32'h55667788); + sspi_dw_write(8'h02,24'h0208,32'h99AABBCC); + sspi_dw_write(8'h02,24'h020C,32'hDDEEFF00); + + // SPI Read Check + sspi_dw_read_check(8'h03,24'h0000,32'h00112233); + sspi_dw_read_check(8'h03,24'h0004,32'h44556677); + sspi_dw_read_check(8'h03,24'h0008,32'h8899AABB); + sspi_dw_read_check(8'h03,24'h000C,32'hCCDDEEFF); + + sspi_dw_read_check(8'h03,24'h0200,32'h11223344); + sspi_dw_read_check(8'h03,24'h0204,32'h55667788); + sspi_dw_read_check(8'h03,24'h0208,32'h99AABBCC); + sspi_dw_read_check(8'h03,24'h020C,32'hDDEEFF00); + + $display("############################################"); + $display(" Testing IS62/65WVS1288GALL SSRAM[2] Read/Write Access "); + $display("############################################"); + // SSPI Indirect RAM READ ACCESS- + // Byte Read Option + // <Instr:0x3> <Addr:24Bit Address> <Read Data Out> + spi_chip_no = 2'b10; // Select the Chip Select to zero + sspi_dw_read_check(8'h03,24'h0000,32'h23222120); + sspi_dw_read_check(8'h03,24'h0004,32'h27262524); + sspi_dw_read_check(8'h03,24'h0008,32'h2b2a2928); + sspi_dw_read_check(8'h03,24'h000C,32'h2f2e2d2c); + + sspi_dw_read_check(8'h03,24'h0010,32'h33323130); + sspi_dw_read_check(8'h03,24'h0014,32'h37363534); + sspi_dw_read_check(8'h03,24'h0018,32'h3B3A3938); + sspi_dw_read_check(8'h03,24'h001C,32'h3F3E3D3C); + + sspi_dw_read_check(8'h03,24'h0020,32'h43424140); + sspi_dw_read_check(8'h03,24'h0024,32'h47464544); + sspi_dw_read_check(8'h03,24'h0028,32'h4B4A4948); + sspi_dw_read_check(8'h03,24'h002C,32'h4F4E4D4C); + + sspi_dw_read_check(8'h03,24'h0030,32'h53525150); + sspi_dw_read_check(8'h03,24'h0034,32'h57565554); + sspi_dw_read_check(8'h03,24'h0038,32'h5B5A5958); + sspi_dw_read_check(8'h03,24'h003C,32'h5F5E5D5C); + + sspi_dw_read_check(8'h03,24'h0040,32'h63626160); + sspi_dw_read_check(8'h03,24'h0044,32'h67666564); + sspi_dw_read_check(8'h03,24'h0048,32'h6B6A6968); + sspi_dw_read_check(8'h03,24'h004C,32'h6F6E6D6C); + + sspi_dw_read_check(8'h03,24'h00a0,32'hc3c2c1c0); + sspi_dw_read_check(8'h03,24'h00a4,32'hc7c6c5c4); + sspi_dw_read_check(8'h03,24'h00a8,32'hcbcac9c8); + sspi_dw_read_check(8'h03,24'h00aC,32'hcfcecdcc); + + sspi_dw_read_check(8'h03,24'h0200,32'h33333333); + sspi_dw_read_check(8'h03,24'h0204,32'h44444444); + sspi_dw_read_check(8'h03,24'h0208,32'h55555555); + sspi_dw_read_check(8'h03,24'h020C,32'h66666666); + + // SPI Write + sspi_dw_write(8'h02,24'h0000,32'h00112233); + sspi_dw_write(8'h02,24'h0004,32'h44556677); + sspi_dw_write(8'h02,24'h0008,32'h8899AABB); + sspi_dw_write(8'h02,24'h000C,32'hCCDDEEFF); + + sspi_dw_write(8'h02,24'h0200,32'h11223344); + sspi_dw_write(8'h02,24'h0204,32'h55667788); + sspi_dw_write(8'h02,24'h0208,32'h99AABBCC); + sspi_dw_write(8'h02,24'h020C,32'hDDEEFF00); + + // SPI Read Check + sspi_dw_read_check(8'h03,24'h0000,32'h00112233); + sspi_dw_read_check(8'h03,24'h0004,32'h44556677); + sspi_dw_read_check(8'h03,24'h0008,32'h8899AABB); + sspi_dw_read_check(8'h03,24'h000C,32'hCCDDEEFF); + + sspi_dw_read_check(8'h03,24'h0200,32'h11223344); + sspi_dw_read_check(8'h03,24'h0204,32'h55667788); + sspi_dw_read_check(8'h03,24'h0208,32'h99AABBCC); + sspi_dw_read_check(8'h03,24'h020C,32'hDDEEFF00); + + $display("############################################"); + $display(" Testing IS62/65WVS1288GALL SSRAM[3] Read/Write Access "); + $display("############################################"); + // SSPI Indirect RAM READ ACCESS- + // Byte Read Option + // <Instr:0x3> <Addr:24Bit Address> <Read Data Out> + spi_chip_no = 2'b11; // Select the Chip Select to zero + sspi_dw_read_check(8'h03,24'h0000,32'h33323130); + sspi_dw_read_check(8'h03,24'h0004,32'h37363534); + sspi_dw_read_check(8'h03,24'h0008,32'h3b3a3938); + sspi_dw_read_check(8'h03,24'h000C,32'h3f3e3d3c); + + sspi_dw_read_check(8'h03,24'h0010,32'h43424140); + sspi_dw_read_check(8'h03,24'h0014,32'h47464544); + sspi_dw_read_check(8'h03,24'h0018,32'h4B4A4948); + sspi_dw_read_check(8'h03,24'h001C,32'h4F4E4D4C); + + sspi_dw_read_check(8'h03,24'h0020,32'h53525150); + sspi_dw_read_check(8'h03,24'h0024,32'h57565554); + sspi_dw_read_check(8'h03,24'h0028,32'h5B5A5958); + sspi_dw_read_check(8'h03,24'h002C,32'h5F5E5D5C); + + sspi_dw_read_check(8'h03,24'h00a0,32'hd3d2d1d0); + sspi_dw_read_check(8'h03,24'h00a4,32'hd7d6d5d4); + sspi_dw_read_check(8'h03,24'h00a8,32'hdbdad9d8); + sspi_dw_read_check(8'h03,24'h00aC,32'hdfdedddc); + + sspi_dw_read_check(8'h03,24'h0200,32'h44444444); + sspi_dw_read_check(8'h03,24'h0204,32'h55555555); + sspi_dw_read_check(8'h03,24'h0208,32'h66666666); + sspi_dw_read_check(8'h03,24'h020C,32'h77777777); + + // SPI Write + sspi_dw_write(8'h02,24'h0000,32'h00112233); + sspi_dw_write(8'h02,24'h0004,32'h44556677); + sspi_dw_write(8'h02,24'h0008,32'h8899AABB); + sspi_dw_write(8'h02,24'h000C,32'hCCDDEEFF); + + sspi_dw_write(8'h02,24'h0200,32'h11223344); + sspi_dw_write(8'h02,24'h0204,32'h55667788); + sspi_dw_write(8'h02,24'h0208,32'h99AABBCC); + sspi_dw_write(8'h02,24'h020C,32'hDDEEFF00); + + // SPI Read Check + sspi_dw_read_check(8'h03,24'h0000,32'h00112233); + sspi_dw_read_check(8'h03,24'h0004,32'h44556677); + sspi_dw_read_check(8'h03,24'h0008,32'h8899AABB); + sspi_dw_read_check(8'h03,24'h000C,32'hCCDDEEFF); + + sspi_dw_read_check(8'h03,24'h0200,32'h11223344); + sspi_dw_read_check(8'h03,24'h0204,32'h55667788); + sspi_dw_read_check(8'h03,24'h0208,32'h99AABBCC); + sspi_dw_read_check(8'h03,24'h020C,32'hDDEEFF00); repeat (100) @(posedge clock); // $display("+1000 cycles"); @@ -284,7 +459,6 @@ // ---------------------------------------------------- wire flash_io1; wire flash_clk = io_out[16]; - wire spiram_csb = io_out[13]; tri #1 flash_io0 = io_out[15]; assign io_in[14] = flash_io1; @@ -292,18 +466,57 @@ tri #1 flash_io3 = 1'b1; - is62wvs1288 #(.mem_file_name("flash1.hex")) - u_sfram ( + wire spiram_csb0 = io_out[13]; + is62wvs1288 #(.mem_file_name("flash0.hex")) + u_sfram_0 ( // Data Inputs/Outputs .io0 (flash_io0), .io1 (flash_io1), // Controls .clk (flash_clk), - .csb (spiram_csb), + .csb (spiram_csb0), .io2 (flash_io2), .io3 (flash_io3) ); + wire spiram_csb1 = io_out[12]; + is62wvs1288 #(.mem_file_name("flash1.hex")) + u_sfram_1 ( + // Data Inputs/Outputs + .io0 (flash_io0), + .io1 (flash_io1), + // Controls + .clk (flash_clk), + .csb (spiram_csb1), + .io2 (flash_io2), + .io3 (flash_io3) + ); + + wire spiram_csb2 = io_out[9]; +is62wvs1288 #(.mem_file_name("flash2.hex")) + u_sfram_2 ( + // Data Inputs/Outputs + .io0 (flash_io0), + .io1 (flash_io1), + // Controls + .clk (flash_clk), + .csb (spiram_csb2), + .io2 (flash_io2), + .io3 (flash_io3) + ); + + wire spiram_csb3 = io_out[8]; +is62wvs1288 #(.mem_file_name("flash3.hex")) + u_sfram_3 ( + // Data Inputs/Outputs + .io0 (flash_io0), + .io1 (flash_io1), + // Controls + .clk (flash_clk), + .csb (spiram_csb3), + .io2 (flash_io2), + .io3 (flash_io3) + ); //---------------------------------------------------- // Task
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v index 6fe9413..6f4e2ef 100644 --- a/verilog/dv/user_uart/user_uart_tb.v +++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -198,7 +198,7 @@ repeat (100) @(posedge clock); // wait for Processor Get Ready tb_uart.uart_init; - wb_user_core_write(`ADDR_SPACE_UART+8'h0,{3'h0,2'b00,1'b1,1'b1,1'b1}); + wb_user_core_write(`ADDR_SPACE_UART0+8'h0,{3'h0,2'b00,1'b1,1'b1,1'b1}); tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor);
diff --git a/verilog/dv/user_uart1/.user_uart.c.un~ b/verilog/dv/user_uart1/.user_uart.c.un~ new file mode 100644 index 0000000..5835313 --- /dev/null +++ b/verilog/dv/user_uart1/.user_uart.c.un~ Binary files differ
diff --git a/verilog/dv/user_uart1/Makefile b/verilog/dv/user_uart1/Makefile new file mode 100644 index 0000000..046c8df --- /dev/null +++ b/verilog/dv/user_uart1/Makefile
@@ -0,0 +1,84 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 + + +# ---- Include Partitioned Makefiles ---- + +CONFIG = caravel_user_project + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### + +DESIGNS?=../../.. + +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog +## YIFIVE FIRMWARE +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware +GCC64_PREFIX?=riscv64-unknown-elf + + +## Simulation mode: RTL/GL +SIM?=RTL +DUMP?=OFF +RISC_CORE?=0 + +### To Enable IVERILOG FST DUMP +export IVERILOG_DUMPER = fst + + +.SUFFIXES: + +PATTERN = user_uart1 + +all: ${PATTERN:=.vcd} + + +vvp: ${PATTERN:=.vvp} + +%.vvp: %_tb.v + ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_uart.c -o user_uart.o + ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o + ${GCC64_PREFIX}-gcc -o user_uart.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld user_uart.o crt.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N + ${GCC64_PREFIX}-objcopy -O verilog user_uart.elf user_uart.hex + ${GCC64_PREFIX}-objdump -D user_uart.elf > user_uart.dump + rm crt.o user_uart.o +ifeq ($(SIM),RTL) + ifeq ($(DUMP),OFF) + iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + $< -o $@ + else + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + $< -o $@ + endif +else + iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + $< -o $@ +endif + +%.vcd: %.vvp + vvp $< +risc_core_id=$(RISC_CORE) + + +# ---- Clean ---- + +clean: + rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump + +.PHONY: clean hex all
diff --git a/verilog/dv/user_uart1/run_iverilog b/verilog/dv/user_uart1/run_iverilog new file mode 100755 index 0000000..e461fd1 --- /dev/null +++ b/verilog/dv/user_uart1/run_iverilog
@@ -0,0 +1,42 @@ +# ////////////////////////////////////////////////////////////////////////////// +# // SPDX-FileCopyrightText: 2021, Dinesh Annayya +# // +# // Licensed under the Apache License, Version 2.0 (the "License"); +# // you may not use this file except in compliance with the License. +# // You may obtain a copy of the License at +# // +# // http://www.apache.org/licenses/LICENSE-2.0 +# // +# // Unless required by applicable law or agreed to in writing, software +# // distributed under the License is distributed on an "AS IS" BASIS, +# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# // See the License for the specific language governing permissions and +# // limitations under the License. +# // SPDX-License-Identifier: Apache-2.0 +# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> +# // ////////////////////////////////////////////////////////////////////////// +riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common user_uart.c -o user_uart.o + +riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common/ ../../rtl/syntacore/scr1/sim/tests/common/crt_tcm.S -o crt_tcm.o + +riscv64-unknown-elf-gcc -o user_uart.elf -T ../../rtl/syntacore/scr1/sim/tests/common/link_tcm.ld user_uart.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 + +riscv64-unknown-elf-objcopy -O verilog user_uart.elf user_uart.hex + +riscv64-unknown-elf-objdump -D user_uart.elf > user_uart.dump + +rm crt_tcm.o user_uart.o + +#iverilog with waveform dump +iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $PDK_PATH -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/rtl -I ../ -I ../../../verilog -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I ../../../verilog/rtl/i2cm/src/includes -I ../../../verilog/rtl/usb1_host/src/includes -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_uart_tb.vvp + + +#iverilog -g2005-sv -I $PDK_PATH -DFUNCTIONAL -DSIM -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/rtl -I ../../../verilog -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_uart_tb.vvp + +# GLS +#iverilog -g2005-sv -D GL -D FUNCTIONAL -I $PDK_PATH -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/gl -I ../../../verilog -I /home/dinesha/workarea/pdk/sky130A -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_uart_tb.vvp +# + +vvp user_uart_tb.vvp | tee test.log + +\rm -rf user_uart_tb.vvp
diff --git a/verilog/dv/user_uart1/user_uart.c b/verilog/dv/user_uart1/user_uart.c new file mode 100644 index 0000000..ac8c50f --- /dev/null +++ b/verilog/dv/user_uart1/user_uart.c
@@ -0,0 +1,43 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021, Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////////// +#define SC_SIM_OUTPORT (0xf0000000) +#define uint32_t long + + +#define reg_mprj_uart_reg0 (*(volatile uint32_t*)0x10010100) +#define reg_mprj_uart_reg1 (*(volatile uint32_t*)0x10010104) +#define reg_mprj_uart_reg2 (*(volatile uint32_t*)0x10010108) +#define reg_mprj_uart_reg3 (*(volatile uint32_t*)0x1001010C) +#define reg_mprj_uart_reg4 (*(volatile uint32_t*)0x10010110) +#define reg_mprj_uart_reg5 (*(volatile uint32_t*)0x10010114) +#define reg_mprj_uart_reg6 (*(volatile uint32_t*)0x10010118) +#define reg_mprj_uart_reg7 (*(volatile uint32_t*)0x1001011C) +#define reg_mprj_uart_reg8 (*(volatile uint32_t*)0x10010120) + +int main() +{ + + while(1) { + // Check UART RX fifo has data, if available loop back the data + if(reg_mprj_uart_reg8 != 0) { + reg_mprj_uart_reg5 = reg_mprj_uart_reg6; + } + } + + return 0; +}
diff --git a/verilog/dv/user_uart1/user_uart1_tb.v b/verilog/dv/user_uart1/user_uart1_tb.v new file mode 100644 index 0000000..4946c9f --- /dev/null +++ b/verilog/dv/user_uart1/user_uart1_tb.v
@@ -0,0 +1,469 @@ +//////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> +////////////////////////////////////////////////////////////////////// +//// //// +//// Standalone User validation Test bench //// +//// //// +//// This file is part of the YIFive cores project //// +//// https://github.com/dineshannayya/yifive_r0.git //// +//// http://www.opencores.org/cores/yifive/ //// +//// //// +//// Description //// +//// This is a standalone test bench to validate the //// +//// Digital core. //// +//// 1. User Risc core is booted using compiled code of //// +//// user_risc_boot.c //// +//// 2. User Risc core uses Serial Flash and SDRAM to boot //// +//// 3. After successful boot, Risc core will check the UART //// +//// RX Data, If it's available then it loop back the same //// +//// data in uart tx //// +//// 4. Test bench send random 40 character towards User uart //// +//// and expect same data to return back //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +//// Revision : //// +//// 0.1 - 16th Feb 2021, Dinesh A //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`default_nettype wire + +`timescale 1 ns/1 ps + +`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" +`include "uart_agent.v" + + +module user_uart1_tb; + +reg clock ; +reg wb_rst_i ; +reg power1, power2; +reg power3, power4; + +reg wbd_ext_cyc_i; // strobe/request +reg wbd_ext_stb_i; // strobe/request +reg [31:0] wbd_ext_adr_i; // address +reg wbd_ext_we_i; // write +reg [31:0] wbd_ext_dat_i; // data output +reg [3:0] wbd_ext_sel_i; // byte enable + +wire [31:0] wbd_ext_dat_o; // data input +wire wbd_ext_ack_o; // acknowlegement +wire wbd_ext_err_o; // error + +// User I/O +wire [37:0] io_oeb ; +wire [37:0] io_out ; +wire [37:0] io_in ; + +wire [37:0] mprj_io ; +wire [7:0] mprj_io_0 ; +reg test_fail ; +reg [31:0] read_data ; +//---------------------------------- +// Uart Configuration +// --------------------------------- +reg [1:0] uart_data_bit ; +reg uart_stop_bits ; // 0: 1 stop bit; 1: 2 stop bit; +reg uart_stick_parity ; // 1: force even parity +reg uart_parity_en ; // parity enable +reg uart_even_odd_parity ; // 0: odd parity; 1: even parity + +reg [7:0] uart_data ; +reg [15:0] uart_divisor ; // divided by n * 16 +reg [15:0] uart_timeout ;// wait time limit + +reg [15:0] uart_rx_nu ; +reg [15:0] uart_tx_nu ; +reg [7:0] uart_write_data [0:39]; +reg uart_fifo_enable ; // fifo mode disable + + integer d_risc_id; + +integer i,j; + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #12.5 clock <= (clock === 1'b0); + + initial begin + clock = 0; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + end + + `ifdef WFDUMP + initial begin + $dumpfile("simx.vcd"); + $dumpvars(0, user_uart1_tb); + end + `endif + + initial begin + wb_rst_i <= 1'b1; + #100; + wb_rst_i <= 1'b0; // Release reset + end +initial +begin + uart_data_bit = 2'b11; + uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit; + uart_stick_parity = 0; // 1: force even parity + uart_parity_en = 0; // parity enable + uart_even_odd_parity = 1; // 0: odd parity; 1: even parity + uart_divisor = 15;// divided by n * 16 + uart_timeout = 500;// wait time limit + uart_fifo_enable = 0; // fifo mode disable + + $value$plusargs("risc_core_id=%d", d_risc_id); + + #200; // Wait for reset removal + repeat (10) @(posedge clock); + $display("Monitor: Standalone User Uart Test Started"); + + // Remove Wb Reset + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + + // Enable UART Multi Functional Ports + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h200); + + repeat (2) @(posedge clock); + #1; + // Remove all the reset + if(d_risc_id == 0) begin + $display("STATUS: Working with Risc core 0"); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h143); + end else if(d_risc_id == 1) begin + $display("STATUS: Working with Risc core 1"); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h243); + end else if(d_risc_id == 2) begin + $display("STATUS: Working with Risc core 2"); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h443); + end else if(d_risc_id == 3) begin + $display("STATUS: Working with Risc core 2"); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h84F); + end + + repeat (100) @(posedge clock); // wait for Processor Get Ready + + tb_uart.uart_init; + wb_user_core_write(`ADDR_SPACE_UART1+8'h0,{3'h0,2'b00,1'b1,1'b1,1'b1}); + tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, + uart_stick_parity, uart_timeout, uart_divisor); + + repeat (30000) @(posedge clock); // wait for Processor Get Ready + + + for (i=0; i<40; i=i+1) + uart_write_data[i] = $random; + + + + fork + begin + for (i=0; i<40; i=i+1) + begin + $display ("\n... UART Agent Writing char %x ...", uart_write_data[i]); + tb_uart.write_char (uart_write_data[i]); + end + end + + begin + for (j=0; j<40; j=j+1) + begin + tb_uart.read_char_chk(uart_write_data[j]); + end + end + join + + #100 + tb_uart.report_status(uart_rx_nu, uart_tx_nu); + + test_fail = 0; + + // Check + // if all the 40 byte transmitted + // if all the 40 byte received + // if no error + if(uart_tx_nu != 40) test_fail = 1; + if(uart_rx_nu != 40) test_fail = 1; + if(tb_uart.err_cnt != 0) test_fail = 1; + + $display("###################################################"); + if(test_fail == 0) begin + `ifdef GL + $display("Monitor: Standalone User UART Test (GL) Passed"); + `else + $display("Monitor: Standalone User UART Test (RTL) Passed"); + `endif + end else begin + `ifdef GL + $display("Monitor: Standalone User UART Test (GL) Failed"); + `else + $display("Monitor: Standalone User UART Test (RTL) Failed"); + `endif + end + $display("###################################################"); + #100 + $finish; +end + + +wire USER_VDD1V8 = 1'b1; +wire VSS = 1'b0; + + +user_project_wrapper u_top( +`ifdef USE_POWER_PINS + .vccd1(USER_VDD1V8), // User area 1 1.8V supply + .vssd1(VSS), // User area 1 digital ground +`endif + .wb_clk_i (clock), // System clock + .user_clock2 (1'b1), // Real-time clock + .wb_rst_i (wb_rst_i), // Regular Reset signal + + .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request + .wbs_stb_i (wbd_ext_stb_i), // strobe/request + .wbs_adr_i (wbd_ext_adr_i), // address + .wbs_we_i (wbd_ext_we_i), // write + .wbs_dat_i (wbd_ext_dat_i), // data output + .wbs_sel_i (wbd_ext_sel_i), // byte enable + + .wbs_dat_o (wbd_ext_dat_o), // data input + .wbs_ack_o (wbd_ext_ack_o), // acknowlegement + + + // Logic Analyzer Signals + .la_data_in ('1) , + .la_data_out (), + .la_oenb ('0), + + + // IOs + .io_in (io_in) , + .io_out (io_out) , + .io_oeb (io_oeb) , + + .user_irq () + +); + +`ifndef GL // Drive Power for Hold Fix Buf + // All standard cell need power hook-up for functionality work + initial begin + end +`endif + + +//------------------------------------------------------ +// Integrate the Serial flash with qurd support to +// user core using the gpio pads +// ---------------------------------------------------- + + wire flash_clk = io_out[24]; + wire flash_csb = io_out[25]; + // Creating Pad Delay + wire #1 io_oeb_29 = io_oeb[29]; + wire #1 io_oeb_30 = io_oeb[30]; + wire #1 io_oeb_31 = io_oeb[31]; + wire #1 io_oeb_32 = io_oeb[32]; + tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; + tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz; + tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz; + tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz; + + assign io_in[29] = flash_io0; + assign io_in[30] = flash_io1; + assign io_in[31] = flash_io2; + assign io_in[32] = flash_io3; + + + // Quard flash + s25fl256s #(.mem_file_name("user_uart.hex"), + .otp_file_name("none"), + .TimingModel("S25FL512SAGMFI010_F_30pF")) + u_spi_flash_256mb + ( + // Data Inputs/Outputs + .SI (flash_io0), + .SO (flash_io1), + // Controls + .SCK (flash_clk), + .CSNeg (flash_csb), + .WPNeg (flash_io2), + .HOLDNeg (flash_io3), + .RSTNeg (!wb_rst_i) + + ); + + +//--------------------------- +// UART Agent integration +// -------------------------- +wire uart_txd,uart_rxd; + +assign uart_txd = io_out[5]; +assign io_in[3] = uart_rxd ; + +uart_agent tb_uart( + .mclk (clock ), + .txd (uart_rxd ), + .rxd (uart_txd ) + ); + + +task wb_user_core_write; +input [31:0] address; +input [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h1; // write + wbd_ext_dat_i =data; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data); + repeat (2) @(posedge clock); +end +endtask + +task wb_user_core_read; +input [31:0] address; +output [31:0] data; +reg [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='0; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + data = wbd_ext_dat_o; + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data); + repeat (2) @(posedge clock); +end +endtask + +`ifdef GL + +wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i; +wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o; +wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i; +wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i; +wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i; +wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o; +wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i; + +wire wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i; +wire wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o; +wire wbd_sdram_we_i = u_top.u_sdram_ctrl.wb_we_i; +wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i; +wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i; +wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o; +wire [3:0] wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i; + +wire wbd_uart_stb_i = u_top.u_uart_i2c_usb.reg_cs; +wire wbd_uart_ack_o = u_top.u_uart_i2c_usb.reg_ack; +wire wbd_uart_we_i = u_top.u_uart_i2c_usb.reg_wr; +wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb.reg_addr; +wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb.reg_wdata; +wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb.reg_rdata; +wire wbd_uart_sel_i = u_top.u_uart_i2c_usb.reg_be; + +`endif + +/** +`ifdef GL +//----------------------------------------------------------------------------- +// RISC IMEM amd DMEM Monitoring TASK +//----------------------------------------------------------------------------- + +`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top + +always@(posedge `RISC_CORE.wb_clk) begin + if(`RISC_CORE.wbd_imem_ack_i) + $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i); + if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o) + $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o); + if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o) + $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i); +end + +`endif +**/ +endmodule +`include "s25fl256s.sv" +`default_nettype wire
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv index b206f1d..6d9e5cd 100755 --- a/verilog/rtl/pinmux/src/pinmux.sv +++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -34,6 +34,9 @@ //// Revision : //// //// 0.1 - 16th Feb 2021, Dinesh A //// //// initial version //// +//// 0.2 - 6 April 2021, Dinesh A //// +//// 1. SSPI CS# increased from 1 to 4 //// +// 2. UART I/F increase from 1 to 2 //// ////////////////////////////////////////////////////////////////////// module pinmux ( @@ -55,7 +58,7 @@ output logic cpu_intf_rst_n , output logic qspim_rst_n , output logic sspim_rst_n , - output logic uart_rst_n , + output logic [1:0] uart_rst_n , output logic i2cm_rst_n , output logic usb_rst_n , @@ -106,8 +109,8 @@ output logic usb_dn_i, // UART I/F - input logic uart_txd, - output logic uart_rxd, + input logic [1:0] uart_txd, + output logic [1:0] uart_rxd, // I2CM I/F input logic i2cm_clk_o, @@ -119,7 +122,7 @@ // SPI MASTER input logic spim_sck, - input logic spim_ss, + input logic [3:0] spim_ssn, input logic spim_miso, output logic spim_mosi, @@ -542,9 +545,9 @@ assign cfg_pwm_enb = cfg_multi_func_sel[5:0]; wire [1:0] cfg_int_enb = cfg_multi_func_sel[7:6]; -wire cfg_uart_enb = cfg_multi_func_sel[8]; -wire cfg_i2cm_enb = cfg_multi_func_sel[9]; -wire cfg_spim_enb = cfg_multi_func_sel[10]; +wire [1:0] cfg_uart_enb = cfg_multi_func_sel[9:8]; +wire [3:0] cfg_spim_enb = cfg_multi_func_sel[13:10]; +wire cfg_i2cm_enb = cfg_multi_func_sel[14]; wire [7:0] cfg_port_a_dir_sel = cfg_gpio_dir_sel[7:0]; wire [7:0] cfg_port_b_dir_sel = cfg_gpio_dir_sel[15:8]; @@ -567,23 +570,24 @@ //Pin-1 PC6/RESET* digital_io[0] port_c_in[6] = digital_io_in[0]; - //Pin-2 PD0/RXD digital_io[1] + //Pin-2 PD0/RXD[0] digital_io[1] port_d_in[0] = digital_io_in[1]; - if(cfg_uart_enb) uart_rxd = digital_io_in[1]; + if(cfg_uart_enb[0]) uart_rxd[0] = digital_io_in[1]; - //Pin-3 PD1/TXD digital_io[2] + //Pin-3 PD1/TXD[0] digital_io[2] port_d_in[1] = digital_io_in[2]; - //Pin-4 PD2/INT0 digital_io[3] + //Pin-4 PD2/RXD[1]/INT0 digital_io[3] port_d_in[2] = digital_io_in[3]; - if(cfg_int_enb[0]) ext_intr_in[0] = digital_io_in[3]; + if(cfg_uart_enb[1]) uart_rxd[1] = digital_io_in[3]; + else if(cfg_int_enb[0]) ext_intr_in[0] = digital_io_in[3]; //Pin-5 PD3/INT1/OC2B(PWM0) digital_io[4] port_d_in[3] = digital_io_in[4]; if(cfg_int_enb[1]) ext_intr_in[1] = digital_io_in[4]; - //Pin-6 PD4 digital_io[5] + //Pin-6 PD4/TXD[1] digital_io[5] port_d_in[4] = digital_io_in[5]; //Pin-9 PB6/XTAL1/TOSC1 digital_io[6] @@ -612,7 +616,7 @@ //Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[14] port_b_in[3] = digital_io_in[14]; - if(cfg_spim_enb) spim_mosi = digital_io_in[14]; + if(cfg_spim_enb[0]) spim_mosi = digital_io_in[14]; //Pin-18 PB4/MISO digital_io[15] port_b_in[4] = digital_io_in[15]; @@ -658,23 +662,24 @@ //Pin-1 PC6/RESET* digital_io[0] if(cfg_port_c_dir_sel[6]) digital_io_out[0] = port_c_out[6]; - //Pin-2 PD0/RXD digital_io[1] + //Pin-2 PD0/RXD[0] digital_io[1] if(cfg_port_d_dir_sel[0]) digital_io_out[1] = port_d_out[0]; - //Pin-3 PD1/TXD digital_io[2] - if (cfg_uart_enb) digital_io_out[2] = uart_txd; + //Pin-3 PD1/TXD[0] digital_io[2] + if (cfg_uart_enb[0]) digital_io_out[2] = uart_txd[0]; else if(cfg_port_d_dir_sel[1]) digital_io_out[2] = port_d_out[1]; - //Pin-4 PD2/INT0 digital_io[3] + //Pin-4 PD2/RXD[1]/INT0 digital_io[3] if(cfg_port_d_dir_sel[2]) digital_io_out[3] = port_d_out[2]; //Pin-5 PD3/INT1/OC2B(PWM0) digital_io[4] if(cfg_pwm_enb[0]) digital_io_out[4] = pwm_wfm[0]; else if(cfg_port_d_dir_sel[3]) digital_io_out[4] = port_d_out[3]; - //Pin-6 PD4 digital_io[5] - if(cfg_port_d_dir_sel[4]) digital_io_out[5] = port_d_out[4]; + //Pin-6 PD4/TXD[1] digital_io[5] + if (cfg_uart_enb[1]) digital_io_out[5] = uart_txd[1]; + else if(cfg_port_d_dir_sel[4]) digital_io_out[5] = port_d_out[4]; //Pin-9 PB6/XTAL1/TOSC1 digital_io[6] if(cfg_port_b_dir_sel[6]) digital_io_out[6] = port_b_out[6]; @@ -683,12 +688,14 @@ // Pin-10 PB7/XTAL2/TOSC2 digital_io[7] if(cfg_port_b_dir_sel[7]) digital_io_out[7] = port_b_out[7]; - //Pin-11 PD5/OC0B(PWM1)/T1 digital_io[8] + //Pin-11 PD5/SS[3]/OC0B(PWM1)/T1 digital_io[8] if(cfg_pwm_enb[1]) digital_io_out[8] = pwm_wfm[1]; + else if(cfg_spim_enb[3]) digital_io_out[8] = spim_ssn[3]; else if(cfg_port_d_dir_sel[5]) digital_io_out[8] = port_d_out[5]; - //Pin-12 PD6/OC0A(PWM2)/AIN0 digital_io[9] /analog_io[2] + //Pin-12 PD6/SS[2]/OC0A(PWM2)/AIN0 digital_io[9] /analog_io[2] if(cfg_pwm_enb[2]) digital_io_out[9] = pwm_wfm[2]; + else if(cfg_spim_enb[2]) digital_io_out[9] = spim_ssn[2]; else if(cfg_port_d_dir_sel[6]) digital_io_out[9] = port_d_out[6]; @@ -698,13 +705,14 @@ //Pin-14 PB0/CLKO/ICP1 digital_io[11] if(cfg_port_b_dir_sel[0]) digital_io_out[11] = port_b_out[0]; - //Pin-15 PB1/OC1A(PWM3) digital_io[12] + //Pin-15 PB1/SS[1]/OC1A(PWM3) digital_io[12] if(cfg_pwm_enb[3]) digital_io_out[12] = pwm_wfm[3]; + else if(cfg_spim_enb[1]) digital_io_out[12] = spim_ssn[1]; else if(cfg_port_b_dir_sel[1]) digital_io_out[12] = port_b_out[1]; - //Pin-16 PB2/SS/OC1B(PWM4) digital_io[13] + //Pin-16 PB2/SS[0]/OC1B(PWM4) digital_io[13] if(cfg_pwm_enb[4]) digital_io_out[13] = pwm_wfm[4]; - else if(cfg_spim_enb) digital_io_out[13] = spim_ss; + else if(cfg_spim_enb[0]) digital_io_out[13] = spim_ssn[0]; else if(cfg_port_b_dir_sel[2]) digital_io_out[13] = port_b_out[2]; //Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[14] @@ -712,11 +720,11 @@ else if(cfg_port_b_dir_sel[3]) digital_io_out[14] = port_b_out[3]; //Pin-18 PB4/MISO digital_io[15] - if(cfg_spim_enb) digital_io_out[15] = spim_miso; + if(cfg_spim_enb[0]) digital_io_out[15] = spim_miso; else if(cfg_port_b_dir_sel[4]) digital_io_out[15] = port_b_out[4]; //Pin-19 PB5/SCK digital_io[16] - if(cfg_spim_enb) digital_io_out[16] = spim_sck; + if(cfg_spim_enb[0]) digital_io_out[16] = spim_sck; else if(cfg_port_b_dir_sel[5]) digital_io_out[16] = port_b_out[5]; //Pin-23 PC0/ADC0 digital_io[18]/analog_io[11] @@ -768,16 +776,17 @@ //Pin-1 PC6/RESET* digital_io[0] if(cfg_port_c_dir_sel[6]) digital_io_oen[0] = 1'b0; - //Pin-2 PD0/RXD digital_io[1] - if (cfg_uart_enb) digital_io_oen[1] = 1'b1; + //Pin-2 PD0/RXD[0] digital_io[1] + if (cfg_uart_enb[0]) digital_io_oen[1] = 1'b1; else if(cfg_port_d_dir_sel[0]) digital_io_oen[1] = 1'b0; - //Pin-3 PD1/TXD digital_io[2] - if (cfg_uart_enb) digital_io_oen[2] = 1'b0; + //Pin-3 PD1/TXD[0] digital_io[2] + if (cfg_uart_enb[0]) digital_io_oen[2] = 1'b0; else if(cfg_port_d_dir_sel[1]) digital_io_oen[2] = 1'b0; - //Pin-4 PD2/INT0 digital_io[3] - if(cfg_int_enb[0]) digital_io_oen[3] = 1'b1; + //Pin-4 PD2/RXD[1]/INT0 digital_io[3] + if (cfg_uart_enb[1]) digital_io_oen[3] = 1'b1; + else if(cfg_int_enb[0]) digital_io_oen[3] = 1'b1; else if(cfg_port_d_dir_sel[2]) digital_io_oen[3] = 1'b0; //Pin-5 PD3/INT1/OC2B(PWM0) digital_io[4] @@ -785,8 +794,9 @@ else if(cfg_int_enb[1]) digital_io_oen[4] = 1'b1; else if(cfg_port_d_dir_sel[3]) digital_io_oen[4] = 1'b0; - //Pin-6 PD4 digital_io[5] - if(cfg_port_d_dir_sel[4]) digital_io_oen[5] = 1'b0; + //Pin-6 PD4/TXD[1] digital_io[5] + if (cfg_uart_enb[1]) digital_io_oen[5] = 1'b0; + else if(cfg_port_d_dir_sel[4]) digital_io_oen[5] = 1'b0; //Pin-9 PB6/XTAL1/TOSC1 digital_io[6] if(cfg_port_b_dir_sel[6]) digital_io_oen[6] = 1'b0; @@ -794,12 +804,14 @@ // Pin-10 PB7/XTAL2/TOSC2 digital_io[7] if(cfg_port_b_dir_sel[7]) digital_io_oen[7] = 1'b0; - //Pin-11 PD5/OC0B(PWM1)/T1 digital_io[8] + //Pin-11 PD5/SS[3]/OC0B(PWM1)/T1 digital_io[8] if(cfg_pwm_enb[1]) digital_io_oen[8] = 1'b0; + else if(cfg_spim_enb[3]) digital_io_oen[8] = 1'b0; else if(cfg_port_d_dir_sel[5]) digital_io_oen[8] = 1'b0; - //Pin-12 PD6/OC0A(PWM2)/AIN0 digital_io[9] /analog_io[2] + //Pin-12 PD6/SS[2]/OC0A(PWM2)/AIN0 digital_io[9] /analog_io[2] if(cfg_pwm_enb[2]) digital_io_oen[9] = 1'b0; + else if(cfg_spim_enb[2]) digital_io_oen[9] = 1'b0; else if(cfg_port_d_dir_sel[6]) digital_io_oen[9] = 1'b0; //Pin-13 PD7/A1N1 digital_io[10]/analog_io[3] @@ -808,26 +820,27 @@ //Pin-14 PB0/CLKO/ICP1 digital_io[11] if(cfg_port_b_dir_sel[0]) digital_io_oen[11] = 1'b0; - //Pin-15 PB1/OC1A(PWM3) digital_io[12] + //Pin-15 PB1/SS[1]/OC1A(PWM3) digital_io[12] if(cfg_pwm_enb[3]) digital_io_oen[12] = 1'b0; + else if(cfg_spim_enb[1]) digital_io_oen[12] = 1'b0; else if(cfg_port_b_dir_sel[1]) digital_io_oen[12] = 1'b0; - //Pin-16 PB2/SS/OC1B(PWM4) digital_io[13] + //Pin-16 PB2/SS[0]/OC1B(PWM4) digital_io[13] if(cfg_pwm_enb[4]) digital_io_oen[13] = 1'b0; - else if(cfg_spim_enb) digital_io_oen[13] = 1'b0; + else if(cfg_spim_enb[0]) digital_io_oen[13] = 1'b0; else if(cfg_port_b_dir_sel[2]) digital_io_oen[13] = 1'b0; //Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[14] - if(cfg_spim_enb) digital_io_oen[14] = 1'b1; + if(cfg_spim_enb[0]) digital_io_oen[14] = 1'b1; else if(cfg_pwm_enb[5]) digital_io_oen[14] = 1'b0; else if(cfg_port_b_dir_sel[3]) digital_io_oen[14] = 1'b0; - //Pin-18 PB4/MISO digital_io[15] - if(cfg_spim_enb) digital_io_oen[15] = 1'b0; + //Pin-18 PB4/MISO digital_io[15] + if(cfg_spim_enb[0]) digital_io_oen[15] = 1'b0; else if(cfg_port_b_dir_sel[4]) digital_io_oen[15] = 1'b0; //Pin-19 PB5/SCK digital_io[16] - if(cfg_spim_enb) digital_io_oen[16] = 1'b0; + if(cfg_spim_enb[0]) digital_io_oen[16] = 1'b0; else if(cfg_port_b_dir_sel[5]) digital_io_oen[16] = 1'b0; //Pin-23 PC0/ADC0 digital_io[18]/analog_io[11]
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv index bb318d4..46642c7 100644 --- a/verilog/rtl/pinmux/src/pinmux_reg.sv +++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -47,7 +47,7 @@ output logic cpu_intf_rst_n , output logic qspim_rst_n , output logic sspim_rst_n , - output logic uart_rst_n , + output logic [1:0] uart_rst_n , output logic i2cm_rst_n , output logic usb_rst_n , @@ -281,9 +281,10 @@ ctech_buf u_buf_cpu_intf_rst (.A(cfg_glb_ctrl[0]),.X(cpu_intf_rst_n)); ctech_buf u_buf_qspim_rst (.A(cfg_glb_ctrl[1]),.X(qspim_rst_n)); ctech_buf u_buf_sspim_rst (.A(cfg_glb_ctrl[2]),.X(sspim_rst_n)); -ctech_buf u_buf_uart_rst (.A(cfg_glb_ctrl[3]),.X(uart_rst_n)); +ctech_buf u_buf_uart0_rst (.A(cfg_glb_ctrl[3]),.X(uart_rst_n[0])); ctech_buf u_buf_i2cm_rst (.A(cfg_glb_ctrl[4]),.X(i2cm_rst_n)); ctech_buf u_buf_usb_rst (.A(cfg_glb_ctrl[5]),.X(usb_rst_n)); +ctech_buf u_buf_uart1_rst (.A(cfg_glb_ctrl[6]),.X(uart_rst_n[1])); ctech_buf u_buf_cpu0_rst (.A(cfg_glb_ctrl[8]),.X(cpu_core_rst_n[0])); ctech_buf u_buf_cpu1_rst (.A(cfg_glb_ctrl[9]),.X(cpu_core_rst_n[1])); @@ -717,7 +718,7 @@ //----------------------------------------- // Software Reg-2, Release date: <DAY><MONTH><YEAR> // ---------------------------------------- -gen_32b_reg #(32'h0104_2022) u_reg_23 ( +gen_32b_reg #(32'h0604_2022) u_reg_23 ( //List of Inputs .reset_n (h_reset_n ), .clk (mclk ), @@ -730,9 +731,9 @@ ); //----------------------------------------- -// Software Reg-3: Poject Revison 4.1 = 0004100 +// Software Reg-3: Poject Revison 4.1 = 0004200 // ---------------------------------------- -gen_32b_reg #(32'h0004_1000) u_reg_24 ( +gen_32b_reg #(32'h0004_2000) u_reg_24 ( //List of Inputs .reset_n (h_reset_n ), .clk (mclk ),
diff --git a/verilog/rtl/sspim/src/sspim_top.sv b/verilog/rtl/sspim/src/sspim_top.sv index 8a632a0..2a28d2e 100755 --- a/verilog/rtl/sspim/src/sspim_top.sv +++ b/verilog/rtl/sspim/src/sspim_top.sv
@@ -44,6 +44,8 @@ //// i.e byte transfer [7:0],[15:8] ...[31:24] //// //// Note: As per SPI transfer still first bit sent //// //// out is big endian, i.e bit[7],[6] ..[0] //// +//// 0.3 - April 6, 2022, Dinesh A //// +//// Four chip select are driven out //// //// //// ////////////////////////////////////////////////////////////////////// //// //// @@ -98,7 +100,7 @@ output logic sck , // clock out output logic so , // serial data out input logic si , // serial data in - output logic ssn // cs_n + output logic [3:0] ssn // Chip Select ); @@ -123,9 +125,7 @@ logic [31:0] cfg_datain ; // data for transfer logic [31:0] cfg_dataout ; // data for received logic hware_op_done ; // operation done -logic [3:0] cs_n ; // cs_n -assign ssn = cs_n[0]; // Only 1 chip select supported in riscdunio sspim_if u_spi_if ( @@ -147,7 +147,7 @@ . sck (sck ), . so (so ), . si (si ), - . cs_n (cs_n ) + . cs_n (ssn ) );
diff --git a/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv b/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv index 028f1d7..d94013b 100644 --- a/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv +++ b/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv
@@ -35,7 +35,8 @@ //// - Dinesh Annayya, dinesha@opencores.org //// //// //// //// Revision : //// -//// //// +//// 0.2 - 7 April 2022, Dinesh-A //// +//// 2nd Uart Integrated //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// @@ -75,17 +76,17 @@ input logic wbd_clk_int, output logic wbd_clk_uart, - input logic uart_rstn , // async reset - input logic i2c_rstn , // async reset - input logic usb_rstn , // async reset - input logic spi_rstn , // async reset - input logic app_clk , - input logic usb_clk , // 48Mhz usb clock + input logic [1:0] uart_rstn , // async reset + input logic i2c_rstn , // async reset + input logic usb_rstn , // async reset + input logic spi_rstn , // async reset + input logic app_clk , + input logic usb_clk , // 48Mhz usb clock // Reg Bus Interface Signal input logic reg_cs, input logic reg_wr, - input logic [7:0] reg_addr, + input logic [8:0] reg_addr, input logic [31:0] reg_wdata, input logic [3:0] reg_be, @@ -106,8 +107,8 @@ output logic i2cm_intr_o , // UART I/F - input logic uart_rxd , - output logic uart_txd , + input logic [1:0] uart_rxd , + output logic [1:0] uart_txd , // USB 1.1 HOST I/F input logic usb_in_dp , @@ -123,7 +124,7 @@ output logic sspim_sck, // clock out output logic sspim_so, // serial data out input logic sspim_si, // serial data in - output logic sspim_ssn // cs_n + output logic [3:0] sspim_ssn // cs_n ); @@ -139,57 +140,84 @@ .clk_out (wbd_clk_uart ) ); -`define SEL_UART 2'b00 -`define SEL_I2C 2'b01 -`define SEL_USB 2'b10 -`define SEL_SPI 2'b11 +`define SEL_UART0 3'b000 +`define SEL_I2C 3'b001 +`define SEL_USB 3'b010 +`define SEL_SPI 3'b011 +`define SEL_UART1 3'b100 //---------------------------------------- // Register Response Path Mux // -------------------------------------- -logic [7:0] reg_uart_rdata; +logic [7:0] reg_uart0_rdata; +logic [7:0] reg_uart1_rdata; logic [7:0] reg_i2c_rdata; logic [31:0] reg_usb_rdata; logic [31:0] reg_spim_rdata; -logic reg_uart_ack; +logic reg_uart0_ack; +logic reg_uart1_ack; logic reg_i2c_ack; logic reg_usb_ack; logic reg_spim_ack; -assign reg_rdata = (reg_addr[7:6] == `SEL_UART) ? {24'h0,reg_uart_rdata} : - (reg_addr[7:6] == `SEL_I2C) ? {24'h0,reg_i2c_rdata} : - (reg_addr[7:6] == `SEL_USB) ? reg_usb_rdata : reg_spim_rdata; -assign reg_ack = (reg_addr[7:6] == `SEL_UART) ? reg_uart_ack : - (reg_addr[7:6] == `SEL_I2C) ? reg_i2c_ack : - (reg_addr[7:6] == `SEL_USB) ? reg_usb_ack : reg_spim_ack; +assign reg_rdata = (reg_addr[8:6] == `SEL_UART0) ? {24'h0,reg_uart0_rdata} : + (reg_addr[8:6] == `SEL_UART1) ? {24'h0,reg_uart1_rdata} : + (reg_addr[8:6] == `SEL_I2C) ? {24'h0,reg_i2c_rdata} : + (reg_addr[8:6] == `SEL_USB) ? reg_usb_rdata : reg_spim_rdata; +assign reg_ack = (reg_addr[8:6] == `SEL_UART0) ? reg_uart0_ack : + (reg_addr[8:6] == `SEL_UART1) ? reg_uart1_ack : + (reg_addr[8:6] == `SEL_I2C) ? reg_i2c_ack : + (reg_addr[8:6] == `SEL_USB) ? reg_usb_ack : reg_spim_ack; -wire reg_uart_cs = (reg_addr[7:6] == `SEL_UART) ? reg_cs : 1'b0; -wire reg_i2cm_cs = (reg_addr[7:6] == `SEL_I2C) ? reg_cs : 1'b0; -wire reg_usb_cs = (reg_addr[7:6] == `SEL_USB) ? reg_cs : 1'b0; -wire reg_spim_cs = (reg_addr[7:6] == `SEL_SPI) ? reg_cs : 1'b0; +wire reg_uart0_cs = (reg_addr[8:6] == `SEL_UART0) ? reg_cs : 1'b0; +wire reg_uart1_cs = (reg_addr[8:6] == `SEL_UART1) ? reg_cs : 1'b0; +wire reg_i2cm_cs = (reg_addr[8:6] == `SEL_I2C) ? reg_cs : 1'b0; +wire reg_usb_cs = (reg_addr[8:6] == `SEL_USB) ? reg_cs : 1'b0; +wire reg_spim_cs = (reg_addr[8:6] == `SEL_SPI) ? reg_cs : 1'b0; -uart_core u_uart_core ( +uart_core u_uart0_core ( - .arst_n (uart_rstn ), // async reset + .arst_n (uart_rstn[0] ), // async reset .app_clk (app_clk ), // Reg Bus Interface Signal - .reg_cs (reg_uart_cs ), + .reg_cs (reg_uart0_cs ), .reg_wr (reg_wr ), .reg_addr (reg_addr[5:2] ), .reg_wdata (reg_wdata[7:0] ), .reg_be (reg_be[0] ), // Outputs - .reg_rdata (reg_uart_rdata[7:0]), - .reg_ack (reg_uart_ack ), + .reg_rdata (reg_uart0_rdata[7:0]), + .reg_ack (reg_uart0_ack ), // Pad Control - .rxd (uart_rxd ), - .txd (uart_txd ) + .rxd (uart_rxd[0] ), + .txd (uart_txd[0] ) + ); + +uart_core u_uart1_core ( + + .arst_n (uart_rstn[1] ), // async reset + .app_clk (app_clk ), + + // Reg Bus Interface Signal + .reg_cs (reg_uart1_cs ), + .reg_wr (reg_wr ), + .reg_addr (reg_addr[5:2] ), + .reg_wdata (reg_wdata[7:0] ), + .reg_be (reg_be[0] ), + + // Outputs + .reg_rdata (reg_uart1_rdata[7:0]), + .reg_ack (reg_uart1_ack ), + + // Pad Control + .rxd (uart_rxd[1] ), + .txd (uart_txd[1] ) ); i2cm_top u_i2cm (
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 5c02cd7..d9366d0 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -200,6 +200,9 @@ //// 1. Four core risc v integration //// //// 4.1 April 1 2022, Dinesh A //// //// 1. sram lanuch phase control added inside risc core //// +//// 4.2 April 6 2022, Dinesh A //// +//// 1. SSPI CS# increased from 1 to 4 //// +//// 2. uart port increase to two //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// @@ -412,7 +415,7 @@ // Global Register Wishbone Interface //--------------------------------------------------------------------- wire wbd_uart_stb_o ; // strobe/request -wire [7:0] wbd_uart_adr_o ; // address +wire [8:0] wbd_uart_adr_o ; // address wire wbd_uart_we_o ; // write wire [31:0] wbd_uart_dat_o ; // data output wire [3:0] wbd_uart_sel_o ; // byte enable @@ -429,7 +432,7 @@ wire [3:0] cpu_core_rst_n ; wire qspim_rst_n ; wire sspim_rst_n ; -wire uart_rst_n ; // uart reset +wire [1:0] uart_rst_n ; // uart reset wire i2c_rst_n ; // i2c reset wire usb_rst_n ; // i2c reset wire bist_rst_n ; // i2c reset @@ -511,8 +514,8 @@ wire usb_dn_i ; // UART I/F -wire uart_txd ; -wire uart_rxd ; +wire [1:0] uart_txd ; +wire [1:0] uart_rxd ; // I2CM I/F wire i2cm_clk_o ; @@ -570,7 +573,7 @@ wire sspim_sck ; // clock out wire sspim_so ; // serial data out wire sspim_si ; // serial data in -wire sspim_ssn ; // cs_n +wire [3:0] sspim_ssn ; // cs_n wire usb_intr_o ; @@ -1101,7 +1104,7 @@ // Reg Bus Interface Signal .reg_cs (wbd_uart_stb_o ), .reg_wr (wbd_uart_we_o ), - .reg_addr (wbd_uart_adr_o[7:0] ), + .reg_addr (wbd_uart_adr_o[8:0] ), .reg_wdata (wbd_uart_dat_o ), .reg_be (wbd_uart_sel_o ), @@ -1219,7 +1222,7 @@ // SPI MASTER .spim_sck (sspim_sck ), - .spim_ss (sspim_ssn ), + .spim_ssn (sspim_ssn ), .spim_miso (sspim_so ), .spim_mosi (sspim_si ),
diff --git a/verilog/rtl/user_reg_map.v b/verilog/rtl/user_reg_map.v index 1926c76..dfe3a99 100644 --- a/verilog/rtl/user_reg_map.v +++ b/verilog/rtl/user_reg_map.v
@@ -3,10 +3,11 @@ // So, using wb_host bank select we have changing MSB address [31:16] = 0x1000 // `define ADDR_SPACE_QSPI 32'h3000_0000 -`define ADDR_SPACE_UART 32'h3001_0000 +`define ADDR_SPACE_UART0 32'h3001_0000 `define ADDR_SPACE_I2CM 32'h3001_0040 `define ADDR_SPACE_USB 32'h3001_0080 `define ADDR_SPACE_SSPI 32'h3001_00C0 +`define ADDR_SPACE_UART1 32'h3001_0100 `define ADDR_SPACE_PINMUX 32'h3002_0000 `define ADDR_SPACE_WBHOST 32'h3008_0000
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv index fd68e08..8ab9487 100644 --- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv +++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -190,7 +190,7 @@ input logic s1_wbd_ack_i, // input logic s1_wbd_err_i, - unused output logic [31:0] s1_wbd_dat_o, - output logic [7:0] s1_wbd_adr_o, + output logic [8:0] s1_wbd_adr_o, // Uart output logic [3:0] s1_wbd_sel_o, output logic s1_wbd_we_o, output logic s1_wbd_cyc_o, @@ -299,6 +299,7 @@ // 0x1001_0080 to 0x1001_00BF - USB // 0x1001_00C0 to 0x1001_00FF - SSPIM // 0x1002_0000 to 0x1002_00FF - PINMUX +// 0x1001_0100 to 0x1001_013F - UART1 // 0x3080_0000 to 0x3080_00FF - WB HOST (This decoding happens at wb_host block) // --------------------------------------------------------------------------- // @@ -312,10 +313,11 @@ // RISC Data Memory Map // 0x0000_0000 to 0x0FFF_FFFF - QSPIM MEMORY // 0x1000_0000 to 0x1000_00FF - QSPIM REG -// 0x1001_0000 to 0x1001_003F - UART +// 0x1001_0000 to 0x1001_003F - UART0 // 0x1001_0040 to 0x1001_007F - I2 // 0x1001_0080 to 0x1001_00BF - USB // 0x1001_00C0 to 0x1001_00FF - SSPIM +// 0x1001_0100 to 0x1001_013F - UART1 // 0x1002_0000 to 0x1002_00FF - PINMUX //----------------------------- // @@ -660,7 +662,7 @@ assign s0_wbd_stb_o = s0_wb_wr.wbd_stb ; assign s1_wbd_dat_o = s1_wb_wr.wbd_dat ; - assign s1_wbd_adr_o = s1_wb_wr.wbd_adr[7:0] ; + assign s1_wbd_adr_o = s1_wb_wr.wbd_adr[8:0] ; assign s1_wbd_sel_o = s1_wb_wr.wbd_sel ; assign s1_wbd_we_o = s1_wb_wr.wbd_we ; assign s1_wbd_cyc_o = s1_wb_wr.wbd_cyc ;