test bench sync with riscduino
diff --git a/.gitmodules b/.gitmodules
index 57ae809..916c6dd 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -4,3 +4,6 @@
[submodule "verilog/rtl/qspim"]
path = verilog/rtl/qspim
url = https://github.com/dineshannayya/qspim.git
+[submodule "verilog/dv/common/riscduino_board"]
+ path = verilog/dv/common/riscduino_board
+ url = https://github.com/dineshannayya/riscduino_board.git
diff --git a/README.md b/README.md
index e8233a8..34bdf01 100644
--- a/README.md
+++ b/README.md
@@ -580,81 +580,135 @@
sudo usermod -aG docker <your user name>
# Reboot the system to enable the docker setup
```
-## Step-2: Update the Submodule, To to project area
+## Step-2: Clone , update the Submodule, unzip the content
```bash
+ git clone https://github.com/dineshannayya/riscduino.git
+ cd riscduino
git submodule init
git submodule update
-```
-## Step-3: clone Openlane scripts under workarea
-```bash
- git clone https://github.com/The-OpenROAD-Project/OpenLane.git
+ make unzip
```
-## Step-4: add Environment setting
+## Note-1: RTL to GDS Docker
+ - Required openlane and pdk are moved inside the riscduino docker to avoid the external dependency.
+ - flow automatically pull the required docker based on MPW version.
+ - RTL to gds docker is hardcoded inside File: openlane/Makefile
```bash
- export CARAVEL_ROOT=<Carvel Installed Path>
- export OPENLANE_ROOT=<OpenLane Installed Path>
- export OPENLANE_IMAGE_NAME=efabless/openlane:latest
- export PDK_ROOT=<PDK Installed PATH>
- export PDK_PATH=<PDK Install Path>/sky130A
+ OPENLANE_TAG = mpw6
+ OPENLANE_IMAGE_NAME = riscduino/openlane:$(OPENLANE_TAG)
```
-## Step-5: To install the PDK
+## Note-1.1: View the RTL to GDS Docker content
+ - for MPW-6 caravel pdk and openlane avaible inside riscduino/openlane:mpw6 docker
+ - caravel, openlane and pdk envionment are automatically pointed to internal docker pointer
+ - To view the docker contents
```bash
- source ~/.bashrc
- cd OpenLane
- make pdk
+ docker run -ti --rm riscduino/openlane:mpw6 bash
+ cd /opt/pdk_mpw6 - pdk folder
+ cd /opt/caravel - caravel folder
+ cd /openlane - openlane folder
+ env - Show the internally defined env's
+ CARAVEL_ROOT=/opt/caravel
+ PDK_ROOT=/opt/pdk_mpw6
+```
+
+## Note-2: RTL Simulation Docker
+ - Required caravel and pdk are moved inside the riscduino docker to avoid the external dependency.
+ - flow automatically pull the required docker based on MPW version.
+ - To view the docker contents
+ - RTL simulation docker hardcoded inside File: Makefile
+ simenv:
+ docker pull riscduino/dv_setup:mpw6
+
+## Note-2.1: View the RTL Simulation Docker content
+ - for MPW-6 caravel and pdk avaible inside riscduino/dv_setup:mpw6 docker this is used for RTL to gds flows
+ - caravel and pdk envionment are automatically pointed to internal docker pointer
+ - To view the docker contents
+```bash
+ docker run -ti --rm riscduino/dv_setup:mpw6 bash
+ cd /opt/pdk_mpw6 - pdk folder
+ cd /opt/caravel - caravel folder
+ env - Show the internally defined env's
+ CARAVEL_ROOT=/opt/caravel
+ PDK_ROOT=/opt/pdk_mpw6
```
# Tests preparation
The simulation package includes the following tests:
-* **risc_boot** - Simple User Risc core boot
-* **wb_port** - User Wishbone validation
+* **risc_boot** - Complete caravel User Risc core boot
+* **wb_port** - Complete caravel User Wishbone validation
+* **uart_master** - complete caravel user uart master test
* **user_risc_boot** - Standalone User Risc core boot
-* **user_mbist_test1** - Standalone MBIST test
+* **user_sspi** - Standalone SSPI test
+* **user_qspi** - Standalone Quad SPI test
* **user_spi** - Standalone SPI test
* **user_i2c** - Standalone I2C test
-* **user_risc_soft_boot** - Standalone Risc with SRAM as Boot
+* **user_usb** - Standalone USB Host test
+* **user_risc_boot** - Standalone Risc Boot test
+* **user_uart** - Standalone Risc with UART-0 Test
+* **user_uart1** - Standalone Risc with UART-1 Test
+* **user_gpio** - Standalone GPIO Test
+* **user_pwm** - Standalone pwm Test
+* **user_timer** - Standalone timer Test
+* **user_uart_master** - Standalone uart master test
+* **riscv_regress** - Standalone riscv compliance and regression test suite
+
# Running Simulation
Examples:
``` sh
- make verify-wb_port
- make verify-risc_boot
- make verify-uart_master
- make verify-user_basic
- make verify-user_uart
- make verify-user_uart1
- make verify-user_sspi
- make verify-user_i2cm
- make verify-user_risc_boot
- make verify-user_pwm
- make verify-user_timer
- make verify-user_sspi
- make verify-user_qspi
- make verify-user_usb
- make verify-user_uart_master
- make verify-wb_port SIM=RTL DUMP=OFF
- make verify-wb_port SIM=RTL DUMP=ON
- make verify-riscv_regress
- make verify-wb_port SIM=GL
- make verify-risc_boot SIM=GL
- make verify-uart_master SIM=GL
- make verify-user_basic SIM=GL
- make verify-user_uart SIM=GL
- make verify-user_uart1 SIM=GL
- make verify-user_sspi SIM=GL
- make verify-user_i2cm SIM=GL
- make verify-user_risc_boot SIM=GL
- make verify-user_pwm SIM=GL
- make verify-user_timer SIM=GL
- make verify-user_sspi SIM=GL
- make verify-user_qspi SIM=GL
- make verify-user_usb SIM=GL
- make verify-user_uart_master
+ make verify-wb_port - User Wishbone Test from caravel
+ make verify-risc_boot - User Risc core test from caravel
+ make verify-uart_master - User uart master test from caravel
+ make verify-user_basic - Standalone Basic signal and clock divider test
+ make verify-user_uart - Standalone user uart-0 test using user risc core
+ make verify-user_uart1 - Standalone user uart-0 test using user risc core
+ make verify-user_i2cm - Standalone user i2c test
+ make verify-user_risc_boot - standalone user risc core-0 boot test
+ make verify-user_pwm - standalone user pwm test
+ make verify-user_timer - standalone user timer test
+ make verify-user_sspi - standalone user spi test
+ make verify-user_qspi - standalone user quad spi test
+ make verify-user_usb - standalone user usb host test
+ make verify-user_gpio - standalone user gpio test
+ make verify-user_aes - standalone aes test with risc core-0
+ make verify-user_cache_bypass - standalone icache and dcache bypass test with risc core-0
+ make verify-user_uart_master - standalone user uart master test
+ make verify-user_sram_exec - standalone riscv core-0 test with executing code from data memory
+ make verify-riscv_regress - standalone riscv compliance test suite
+ make verify-arudino_risc_boot - standalone riscv core-0 boot using arduino tool set
+ make verify-user_mcore - standalone riscv multi-core test
+ make verify-user_sram_exec RISC_CORE=1 - standalone riscv core-1 test with executing code from data memory
+ make verify-user_risc_boot RISC_CORE=1 - standalone user risc core-1 boot test
+ make verify-user_uart RISC_CORE=1 - Standalone user uart test using user risc core-1
+ make verify-user_uart1 RISC_CORE=1 - Standalone user uart test using user risc core-1
+ make verify-user_aes RISC_CORE=1 - standalone aes test with risc core-1
+ make verify-user_cache_bypass RISC_CORE=1 - standalone icache and dcache bypass test with risc core-1
+ make verify-arudino_risc_boot RISC_CORE=1 - standalone riscv core-1 boot using arduino tool set
+
+ make verify-user_uart SIM=RTL DUMP=OFF - Standalone user uart-0 test using user risc core with waveform dump off
+ make verify-user_uart SIM=RTL DUMP=ON - Standalone user uart-0 test using user risc core with waveform dump on
+ make verify-user_uart SIM=GL DUMP=OFF - Standalone user uart-0 test using user risc core with gatelevel netlist
+ make verify-user_uart SIM=GL DUMP=ON - Standalone user uart-0 test using user risc core with gatelevel netlist and waveform on
+
+```
+# Running RTL to GDS flows
+ - First run the individual macro file
+ - Last run the user_project_wrapper
+``` sh
+ cd openlane
+ make pinmux
+ make qspim_top
+ make uart_i2cm_usb_spi_top
+ make wb_host
+ make wb_interconnect
+ make ycr_intf
+ make ycr_core_top
+ make ycr_iconnect
+ make user_project_wrapper
```
# Tool Sets
@@ -691,6 +745,11 @@
3. `Netgen` - Performs LVS Checks
4. `CVC` - Performs Circuit Validity Checks
+# Riscduino documentation
+ Riscduino documentation available at <https://riscduino.readthedocs.io/en/latest/>
+
+# Arduino ide integration
+ We are in initial phase of Riscduino board integration into arduino and integration details are available at <https://github.com/dineshannayya/riscduino_board/>
# News
* **Riscduino Aim** - https://www.youtube.com/watch?v=lFVnicPhTI0
diff --git a/verilog/dv/arudino_risc_boot/Makefile b/verilog/dv/arudino_risc_boot/Makefile
new file mode 100644
index 0000000..6e6738d
--- /dev/null
+++ b/verilog/dv/arudino_risc_boot/Makefile
@@ -0,0 +1,141 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+DESIGNS?=../../..
+TOOLS?=/opt/riscv64i/
+
+export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
+export RISCDUINO_BOARD ?= $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+GCC64_PREFIX?=riscv64-unknown-elf
+GCC32_PREFIX?=riscv32-unknown-elf
+
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+RISC_CORE?=0
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
+.SUFFIXES:
+
+PATTERN = arudino_risc_boot
+
+all: ${PATTERN:=.vcd}
+
+
+vvp: ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+ ${GCC32_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=65000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${PATTERN}.ino.cpp -o ${PATTERN}.ino.cpp.o
+ ${GCC32_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=65000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/Print.cpp -o Print.cpp.o
+ ${GCC32_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=65000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WMath.cpp -o WMath.cpp.o
+ ${GCC32_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=65000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WString.cpp -o WString.cpp.o
+ ${GCC32_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=65000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WInterrupts.c -o WInterrupts.c.o
+ ${GCC32_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=65000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/fe300prci/fe300prci_driver.c -o fe300prci_driver.c.o
+ ${GCC32_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=65000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/abi.cpp -o abi.cpp.o
+ ${GCC32_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=65000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/plic/plic_driver.c -o plic_driver.c.o
+ ${GCC32_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=65000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/UARTClass.cpp -o UARTClass.cpp.o
+ ${GCC32_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=65000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/entry.S -o entry.S.o
+ ${GCC32_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=65000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/hooks.c -o hooks.c.o
+ ${GCC32_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=65000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/init.S -o init.S.o
+ ${GCC32_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=65000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/itoa.c -o itoa.c.o
+ ${GCC32_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=65000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/main.cpp -o main.cpp.o
+ ${GCC32_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=65000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/malloc.c -o malloc.c.o
+ ${GCC32_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=65000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/new.cpp -o new.cpp.o
+ ${GCC32_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=65000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/sbrk.c -o sbrk.c.o
+ ${GCC32_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=65000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/start.S -o start.S.o
+ ${GCC32_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=65000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring.c -o wiring.c.o
+ ${GCC32_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=65000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_analog.c -o wiring_analog.c.o
+ ${GCC32_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=65000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_digital.c -o wiring_digital.c.o
+ ${GCC32_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=65000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_pulse.cpp -o wiring_pulse.cpp.o
+ ${GCC32_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=65000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_shift.c -o wiring_shift.c.o
+ ${GCC32_PREFIX}-ar rcs core.a Print.cpp.o
+ ${GCC32_PREFIX}-ar rcs core.a UARTClass.cpp.o
+ ${GCC32_PREFIX}-ar rcs core.a WInterrupts.c.o
+ ${GCC32_PREFIX}-ar rcs core.a WMath.cpp.o
+ ${GCC32_PREFIX}-ar rcs core.a WString.cpp.o
+ ${GCC32_PREFIX}-ar rcs core.a abi.cpp.o
+ ${GCC32_PREFIX}-ar rcs core.a fe300prci_driver.c.o
+ ${GCC32_PREFIX}-ar rcs core.a plic_driver.c.o
+ ${GCC32_PREFIX}-ar rcs core.a entry.S.o
+ ${GCC32_PREFIX}-ar rcs core.a hooks.c.o
+ ${GCC32_PREFIX}-ar rcs core.a init.S.o
+ ${GCC32_PREFIX}-ar rcs core.a itoa.c.o
+ ${GCC32_PREFIX}-ar rcs core.a main.cpp.o
+ ${GCC32_PREFIX}-ar rcs core.a malloc.c.o
+ ${GCC32_PREFIX}-ar rcs core.a new.cpp.o
+ ${GCC32_PREFIX}-ar rcs core.a sbrk.c.o
+ ${GCC32_PREFIX}-ar rcs core.a start.S.o
+ ${GCC32_PREFIX}-ar rcs core.a wiring.c.o
+ ${GCC32_PREFIX}-ar rcs core.a wiring_analog.c.o
+ ${GCC32_PREFIX}-ar rcs core.a wiring_digital.c.o
+ ${GCC32_PREFIX}-ar rcs core.a wiring_pulse.cpp.o
+ ${GCC32_PREFIX}-ar rcs core.a wiring_shift.c.o
+ ${GCC32_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf
+ ${GCC32_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin
+ ${GCC32_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex
+ ${GCC32_PREFIX}-objdump -D ${PATTERN}.ino.elf > ${PATTERN}.ino.dump
+ rm *.o *.a
+ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ endif
+else
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ endif
+endif
+
+%.vcd: %.vvp
+ vvp $< +risc_core_id=$(RISC_CORE)
+
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump *.a *.o
+
+.PHONY: clean hex all
diff --git a/verilog/dv/arudino_risc_boot/arudino_risc_boot.ino b/verilog/dv/arudino_risc_boot/arudino_risc_boot.ino
new file mode 100644
index 0000000..524e74d
--- /dev/null
+++ b/verilog/dv/arudino_risc_boot/arudino_risc_boot.ino
@@ -0,0 +1,48 @@
+#define uint32_t long
+
+#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000)
+#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004)
+#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008)
+#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C)
+#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010)
+#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014)
+#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x10020018)
+#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x1002001C)
+#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x10020020)
+#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x10020024)
+#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x10020028)
+#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x1002002C)
+#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x10020030)
+#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x10020034)
+#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x10020038)
+#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x1002003C)
+#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x10020040)
+#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x10020044)
+#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x10020048)
+#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x1002004C)
+#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x10020050)
+#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x10020054)
+#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x10020058)
+#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x1002005C)
+#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x10020060)
+#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x10020064)
+#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x10020068)
+#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x1002006C)
+
+
+
+void setup() {
+ // put your setup code here, to run once:
+ reg_mprj_globl_reg22 = 0x11223344;
+ reg_mprj_globl_reg23 = 0x22334455;
+ reg_mprj_globl_reg24 = 0x33445566;
+ reg_mprj_globl_reg25 = 0x44556677;
+ reg_mprj_globl_reg26 = 0x55667788;
+ reg_mprj_globl_reg27 = 0x66778899;
+
+}
+
+void loop() {
+ // put your main code here, to run repeatedly:
+
+}
diff --git a/verilog/dv/arudino_risc_boot/arudino_risc_boot.ino.cpp b/verilog/dv/arudino_risc_boot/arudino_risc_boot.ino.cpp
new file mode 100644
index 0000000..ca5efa0
--- /dev/null
+++ b/verilog/dv/arudino_risc_boot/arudino_risc_boot.ino.cpp
@@ -0,0 +1,52 @@
+#include <Arduino.h>
+#define uint32_t long
+
+#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000)
+#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004)
+#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008)
+#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C)
+#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010)
+#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014)
+#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x10020018)
+#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x1002001C)
+#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x10020020)
+#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x10020024)
+#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x10020028)
+#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x1002002C)
+#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x10020030)
+#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x10020034)
+#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x10020038)
+#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x1002003C)
+#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x10020040)
+#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x10020044)
+#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x10020048)
+#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x1002004C)
+#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x10020050)
+#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x10020054)
+#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x10020058)
+#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x1002005C)
+#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x10020060)
+#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x10020064)
+#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x10020068)
+#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x1002006C)
+
+
+
+void setup();
+void loop();
+void setup() {
+ // put your setup code here, to run once:
+ reg_mprj_globl_reg22 = 0x11223344;
+ reg_mprj_globl_reg23 = 0x22334455;
+ reg_mprj_globl_reg24 = 0x33445566;
+ reg_mprj_globl_reg25 = 0x44556677;
+ reg_mprj_globl_reg26 = 0x55667788;
+ reg_mprj_globl_reg27 = 0x66778899;
+
+}
+
+void loop() {
+ // put your main code here, to run repeatedly:
+
+}
+
diff --git a/verilog/dv/arudino_risc_boot/arudino_risc_boot_tb.v b/verilog/dv/arudino_risc_boot/arudino_risc_boot_tb.v
new file mode 100644
index 0000000..d6362c1
--- /dev/null
+++ b/verilog/dv/arudino_risc_boot/arudino_risc_boot_tb.v
@@ -0,0 +1,423 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Standalone User validation Test bench ////
+//// ////
+//// This file is part of the YIFive cores project ////
+//// https://github.com/dineshannayya/yifive_r0.git ////
+//// http://www.opencores.org/cores/yifive/ ////
+//// ////
+//// Description ////
+//// This is a standalone test bench to validate the ////
+//// Digital core. ////
+//// 1. User Risc core is booted using compiled code of ////
+//// user_risc_boot.c ////
+//// 2. User Risc core uses Serial Flash and SDRAM to boot ////
+//// 3. After successful boot, Risc core will write signature ////
+//// in to user register from 0x1003_0058 to 0x1003_006C ////
+//// 4. Through the External Wishbone Interface we read back ////
+//// from 0x3003_0058 to 0x3003_006C ////
+//// and validate the user register to declared pass fail ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 16th Feb 2021, Dinesh A ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ns
+
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+module arudino_risc_boot_tb;
+ reg clock;
+ reg wb_rst_i;
+ reg power1, power2;
+ reg power3, power4;
+
+ reg wbd_ext_cyc_i; // strobe/request
+ reg wbd_ext_stb_i; // strobe/request
+ reg [31:0] wbd_ext_adr_i; // address
+ reg wbd_ext_we_i; // write
+ reg [31:0] wbd_ext_dat_i; // data output
+ reg [3:0] wbd_ext_sel_i; // byte enable
+
+ wire [31:0] wbd_ext_dat_o; // data input
+ wire wbd_ext_ack_o; // acknowlegement
+ wire wbd_ext_err_o; // error
+
+ // User I/O
+ wire [37:0] io_oeb;
+ wire [37:0] io_out;
+ wire [37:0] io_in;
+
+ wire gpio;
+ wire [37:0] mprj_io;
+ wire [7:0] mprj_io_0;
+ reg test_fail;
+ reg [31:0] read_data;
+ integer d_risc_id;
+
+
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #12.5 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ end
+
+ `ifdef WFDUMP
+ initial begin
+ $dumpfile("simx.vcd");
+ $dumpvars(3, arudino_risc_boot_tb);
+ end
+ `endif
+
+ initial begin
+
+ $value$plusargs("risc_core_id=%d", d_risc_id);
+
+ #200; // Wait for reset removal
+ repeat (10) @(posedge clock);
+ $display("Monitor: Standalone User Risc Boot Test Started");
+
+ // Remove Wb Reset
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+
+ repeat (2) @(posedge clock);
+ #1;
+ // Remove all the reset
+ if(d_risc_id == 0) begin
+ $display("STATUS: Working with Risc core 0");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
+ end else if(d_risc_id == 1) begin
+ $display("STATUS: Working with Risc core 1");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
+ end
+
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (30) begin
+ repeat (1000) @(posedge clock);
+ // $display("+1000 cycles");
+ end
+
+
+ $display("Monitor: Reading Back the expected value");
+ // User RISC core expect to write these value in global
+ // register, read back and decide on pass fail
+ // 0x30000018 = 0x11223344;
+ // 0x3000001C = 0x22334455;
+ // 0x30000020 = 0x33445566;
+ // 0x30000024 = 0x44556677;
+ // 0x30000028 = 0x55667788;
+ // 0x3000002C = 0x66778899;
+
+ test_fail = 0;
+ wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344);
+ wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455);
+ wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566);
+ wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677);
+ wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788);
+ wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899);
+
+
+
+ $display("###################################################");
+ if(test_fail == 0) begin
+ `ifdef GL
+ $display("Monitor: Standalone User Risc Boot (GL) Passed");
+ `else
+ $display("Monitor: Standalone User Risc Boot (RTL) Passed");
+ `endif
+ end else begin
+ `ifdef GL
+ $display("Monitor: Standalone User Risc Boot (GL) Failed");
+ `else
+ $display("Monitor: Standalone User Risc Boot (RTL) Failed");
+ `endif
+ end
+ $display("###################################################");
+ $finish;
+ end
+
+ initial begin
+ wb_rst_i <= 1'b1;
+ #100;
+ wb_rst_i <= 1'b0; // Release reset
+ end
+wire USER_VDD1V8 = 1'b1;
+wire VSS = 1'b0;
+
+user_project_wrapper u_top(
+`ifdef USE_POWER_PINS
+ .vccd1(USER_VDD1V8), // User area 1 1.8V supply
+ .vssd1(VSS), // User area 1 digital ground
+`endif
+ .wb_clk_i (clock), // System clock
+ .user_clock2 (1'b1), // Real-time clock
+ .wb_rst_i (wb_rst_i), // Regular Reset signal
+
+ .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
+ .wbs_stb_i (wbd_ext_stb_i), // strobe/request
+ .wbs_adr_i (wbd_ext_adr_i), // address
+ .wbs_we_i (wbd_ext_we_i), // write
+ .wbs_dat_i (wbd_ext_dat_i), // data output
+ .wbs_sel_i (wbd_ext_sel_i), // byte enable
+
+ .wbs_dat_o (wbd_ext_dat_o), // data input
+ .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
+
+
+ // Logic Analyzer Signals
+ .la_data_in ('1) ,
+ .la_data_out (),
+ .la_oenb ('0),
+
+
+ // IOs
+ .io_in (io_in) ,
+ .io_out (io_out) ,
+ .io_oeb (io_oeb) ,
+
+ .user_irq ()
+
+);
+
+`ifndef GL // Drive Power for Hold Fix Buf
+ // All standard cell need power hook-up for functionality work
+ initial begin
+
+ end
+`endif
+
+//------------------------------------------------------
+// Integrate the Serial flash with qurd support to
+// user core using the gpio pads
+// ----------------------------------------------------
+
+ wire flash_clk = io_out[24];
+ wire flash_csb = io_out[25];
+ // Creating Pad Delay
+ wire #1 io_oeb_29 = io_oeb[29];
+ wire #1 io_oeb_30 = io_oeb[30];
+ wire #1 io_oeb_31 = io_oeb[31];
+ wire #1 io_oeb_32 = io_oeb[32];
+ tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz;
+
+ assign io_in[29] = flash_io0;
+ assign io_in[30] = flash_io1;
+ assign io_in[31] = flash_io2;
+ assign io_in[32] = flash_io3;
+
+ // Quard flash
+ s25fl256s #(.mem_file_name("arudino_risc_boot.ino.hex"),
+ .otp_file_name("none"),
+ .TimingModel("S25FL512SAGMFI010_F_30pF"))
+ u_spi_flash_256mb (
+ // Data Inputs/Outputs
+ .SI (flash_io0),
+ .SO (flash_io1),
+ // Controls
+ .SCK (flash_clk),
+ .CSNeg (flash_csb),
+ .WPNeg (flash_io2),
+ .HOLDNeg (flash_io3),
+ .RSTNeg (!wb_rst_i)
+
+ );
+
+
+
+
+task wb_user_core_write;
+input [31:0] address;
+input [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h1; // write
+ wbd_ext_dat_i =data; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
+ repeat (2) @(posedge clock);
+end
+endtask
+
+task wb_user_core_read;
+input [31:0] address;
+output [31:0] data;
+reg [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='0; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
+ data = wbd_ext_dat_o;
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
+ repeat (2) @(posedge clock);
+end
+endtask
+
+task wb_user_core_read_check;
+input [31:0] address;
+output [31:0] data;
+input [31:0] cmp_data;
+reg [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='0; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
+ data = wbd_ext_dat_o;
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ if(data !== cmp_data) begin
+ $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
+ test_fail = 1;
+ end else begin
+ $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
+ end
+ repeat (2) @(posedge clock);
+end
+endtask
+
+`ifdef GL
+
+wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
+wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
+wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
+wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
+
+wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
+wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
+wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
+wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
+wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
+wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
+wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
+
+`endif
+
+/**
+`ifdef GL
+//-----------------------------------------------------------------------------
+// RISC IMEM amd DMEM Monitoring TASK
+//-----------------------------------------------------------------------------
+
+`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
+
+always@(posedge `RISC_CORE.wb_clk) begin
+ if(`RISC_CORE.wbd_imem_ack_i)
+ $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
+ if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
+ $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
+ if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
+ $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
+end
+
+`endif
+**/
+endmodule
+`include "s25fl256s.sv"
+`default_nettype wire
diff --git a/verilog/dv/common/riscduino_board b/verilog/dv/common/riscduino_board
new file mode 160000
index 0000000..151bdbe
--- /dev/null
+++ b/verilog/dv/common/riscduino_board
@@ -0,0 +1 @@
+Subproject commit 151bdbeadbbfbeda5fb8d0ce8ef5659704871c69
diff --git a/verilog/dv/user_mcore/user_mcore_tb.v b/verilog/dv/user_mcore/user_mcore_tb.v
index 7751a95..b43dcba 100644
--- a/verilog/dv/user_mcore/user_mcore_tb.v
+++ b/verilog/dv/user_mcore/user_mcore_tb.v
@@ -135,16 +135,8 @@
repeat (2) @(posedge clock);
#1;
// Remove all the reset
- if(d_risc_id == 0) begin
- $display("STATUS: Working with Risc core 0");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
- end else if(d_risc_id == 1) begin
- $display("STATUS: Working with Risc core 1");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
- end else begin
- $display("STATUS: Working with Both core Risc core 0 & 1 ");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h31F);
- end
+ $display("STATUS: Working with Both core Risc core 0 & 1 ");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h31F);
// Repeat cycles of 1000 clock edges as needed to complete testbench
