Risc 2core integration in sync with 4core
diff --git a/.gitmodules b/.gitmodules index 453828c..57ae809 100644 --- a/.gitmodules +++ b/.gitmodules
@@ -1,6 +1,6 @@ -[submodule "verilog/rtl/qspim"] - path = verilog/rtl/qspim - url = https://github.com/dineshannayya/qspim.git [submodule "verilog/rtl/yifive/ycr2c"] path = verilog/rtl/yifive/ycr2c url = https://github.com/dineshannayya/ycr2c.git +[submodule "verilog/rtl/qspim"] + path = verilog/rtl/qspim + url = https://github.com/dineshannayya/qspim.git
diff --git a/openlane/pinmux/pin_order.cfg b/openlane/pinmux/pin_order.cfg index 4c64993..5d8d756 100644 --- a/openlane/pinmux/pin_order.cfg +++ b/openlane/pinmux/pin_order.cfg
@@ -11,8 +11,22 @@ uart_rst_n i2cm_rst_n usb_rst_n -cfg_riscv_debug_sel\[1\] -cfg_riscv_debug_sel\[0\] +cfg_riscv_ctrl\[15\] +cfg_riscv_ctrl\[14\] +cfg_riscv_ctrl\[13\] +cfg_riscv_ctrl\[12\] +cfg_riscv_ctrl\[11\] +cfg_riscv_ctrl\[10\] +cfg_riscv_ctrl\[9\] +cfg_riscv_ctrl\[8\] +cfg_riscv_ctrl\[7\] +cfg_riscv_ctrl\[6\] +cfg_riscv_ctrl\[5\] +cfg_riscv_ctrl\[4\] +cfg_riscv_ctrl\[3\] +cfg_riscv_ctrl\[2\] +cfg_riscv_ctrl\[1\] +cfg_riscv_ctrl\[0\] user_irq\[0\] user_irq\[1\] user_irq\[2\]
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index 6cb3902..57127e1 100644 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl
@@ -73,8 +73,9 @@ $proj_dir/../../verilog/gl/pinmux.v \ $proj_dir/../../verilog/gl/uart_i2c_usb_spi_top.v \ $proj_dir/../../verilog/gl/wb_host.v \ - $proj_dir/../../verilog/gl/ycr2_mintf.v \ + $proj_dir/../../verilog/gl/ycr_intf.v \ $proj_dir/../../verilog/gl/ycr_core_top.v \ + $proj_dir/../../verilog/gl/ycr2_iconnect.v \ $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \ " @@ -84,8 +85,9 @@ $lef_root/wb_interconnect.lef \ $lef_root/uart_i2c_usb_spi_top.lef \ $lef_root/wb_host.lef \ - $lef_root/ycr2_mintf.lef \ + $lef_root/ycr_intf.lef \ $lef_root/ycr_core_top.lef \ + $lef_root/ycr2_iconnect.lef \ $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \ " @@ -95,8 +97,9 @@ $gds_root/wb_interconnect.gds \ $gds_root/uart_i2c_usb_spi_top.gds \ $gds_root/wb_host.gds \ - $gds_root/ycr2_mintf.gds \ + $gds_root/ycr_intf.gds \ $gds_root/ycr_core_top.gds \ + $gds_root/ycr2_iconnect.gds \ $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \ " @@ -122,20 +125,20 @@ set ::env(GND_PIN) "vssd1" set ::env(GLB_RT_OBS) " \ - li1 150 150 833.1 566.54,\ - met1 150 150 833.1 566.54,\ - met2 150 150 833.1 566.54,\ - met3 150 150 833.1 566.54,\ + li1 150 130 833.1 546.54,\ + met1 150 130 833.1 546.54,\ + met2 150 130 833.1 546.54,\ + met3 150 130 833.1 546.54,\ - li1 900 150 1583.1 566.54,\ - met1 900 150 1583.1 566.54,\ - met2 900 150 1583.1 566.54,\ - met3 900 150 1583.1 566.54,\ + li1 950 130 1633.1 546.54,\ + met1 950 130 1633.1 546.54,\ + met2 950 130 1633.1 546.54,\ + met3 950 130 1633.1 546.54,\ - li1 150 800 833.1 1216.54,\ - met1 150 800 833.1 1216.54,\ - met2 150 800 833.1 1216.54,\ - met3 150 800 833.1 1216.54,\ + li1 150 650 833.1 1066.54,\ + met1 150 650 833.1 1066.54,\ + met2 150 650 833.1 1066.54,\ + met3 150 650 833.1 1066.54,\ met5 0 0 2920 3520" set ::env(FP_PDN_POWER_STRAPS) "vccd1 vssd1 1, vccd2 vssd2 0, vdda1 vssa1 0, vdda2 vssa2 0" @@ -188,7 +191,7 @@ set ::env(FP_PDN_VWIDTH) "3.1" set ::env(FP_PDN_HOFFSET) "10" -set ::env(FP_PDN_HPITCH) "100" +set ::env(FP_PDN_HPITCH) "90" set ::env(FP_PDN_HSPACING) "10" set ::env(FP_PDN_HWIDTH) "3.1"
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg index b9d6ef1..409c58e 100644 --- a/openlane/user_project_wrapper/macro.cfg +++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,14 +1,15 @@ -u_qspi_master 2250 700 N -u_uart_i2c_usb_spi 2250 1400 N -u_pinmux 2250 2300 N +u_qspi_master 2250 650 N +u_uart_i2c_usb_spi 2250 1350 N +u_pinmux 2250 2150 N -u_riscv_top.i_core_top_0 150 1500 N -u_riscv_top.i_core_top_1 950 1500 N -u_riscv_top.u_mintf 925 700 N -u_icache_2kb 150 150 N -u_dcache_2kb 900 150 N -u_tsram0_2kb 150 800 N +u_riscv_top.i_core_top_0 50 1400 N +u_riscv_top.i_core_top_1 1200 1400 FN +u_riscv_top.u_connect 725 1400 N +u_riscv_top.u_intf 950 650 N +u_icache_2kb 150 130 N +u_dcache_2kb 950 130 N +u_tsram0_2kb 150 650 N -u_intercon 1850 700 N +u_intercon 1850 650 N u_wb_host 1750 100 N
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl index 097c11b..882273d 100755 --- a/openlane/wb_interconnect/config.tcl +++ b/openlane/wb_interconnect/config.tcl
@@ -70,7 +70,7 @@ set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 320 1800" +set ::env(DIE_AREA) "0 0 300 1800" # If you're going to use multiple power domains, then keep this disabled. @@ -82,7 +82,7 @@ set ::env(PL_TIME_DRIVEN) 1 set ::env(PL_TARGET_DENSITY) "0.20" -set ::env(CELL_PAD) "10" +set ::env(CELL_PAD) "8" # helps in anteena fix set ::env(USE_ARC_ANTENNA_CHECK) "0"
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg index f4bd653..565b205 100644 --- a/openlane/wb_interconnect/pin_order.cfg +++ b/openlane/wb_interconnect/pin_order.cfg
@@ -147,7 +147,7 @@ #W -ch_data_out\[36\] 0750 0 2 +ch_data_out\[36\] 000 0 2 ch_data_out\[35\] ch_data_out\[34\] ch_data_out\[33\] @@ -172,7 +172,7 @@ ch_clk_out\[0\] -m1_wbd_stb_i 0950 0 2 +m1_wbd_stb_i 100 0 2 m1_wbd_we_i m1_wbd_adr_i\[31\] m1_wbd_adr_i\[30\] @@ -279,7 +279,7 @@ m1_wbd_err_o m1_wbd_cyc_i -m2_wbd_stb_i 1150 0 2 +m2_wbd_stb_i 300 0 2 m2_wbd_we_i m2_wbd_adr_i\[31\] m2_wbd_adr_i\[30\] @@ -397,7 +397,7 @@ m2_wbd_err_o m2_wbd_cyc_i -m3_wbd_stb_i 1350 0 2 +m3_wbd_stb_i 500 0 2 m3_wbd_we_i m3_wbd_adr_i\[31\] m3_wbd_adr_i\[30\] @@ -700,7 +700,7 @@ s1_wbd_ack_i s1_wbd_cyc_o -ch_data_in\[36\] 1400 0 2 +ch_data_in\[36\] 1500 0 2 ch_data_in\[35\] ch_data_in\[34\] ch_data_in\[33\] @@ -724,7 +724,7 @@ ch_data_out\[12\] ch_clk_out\[3\] -s2_wbd_stb_o 1500 0 2 +s2_wbd_stb_o 1600 0 2 s2_wbd_we_o s2_wbd_adr_o\[7\] s2_wbd_adr_o\[6\]
diff --git a/openlane/ycr2_iconnect/base.sdc b/openlane/ycr2_iconnect/base.sdc new file mode 100644 index 0000000..00fe508 --- /dev/null +++ b/openlane/ycr2_iconnect/base.sdc
@@ -0,0 +1,32 @@ +############################################################################### +# Timing Constraints +############################################################################### +create_clock -name core_clk -period 20.0000 [get_ports {core_clk}] +create_clock -name rtc_clk -period 40.0000 [get_ports {rtc_clk}] +create_clock -name wb_clk -period 10.0000 [get_ports {wb_clk}] + +set_clock_transition 0.1500 [all_clocks] +set_clock_uncertainty -setup 0.2500 [all_clocks] +set_clock_uncertainty -hold 0.2500 [all_clocks] + +set ::env(SYNTH_TIMING_DERATE) 0.05 +puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %" +set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}] +set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}] + +set_clock_groups -name async_clock -asynchronous \ + -group [get_clocks {core_clk}]\ + -group [get_clocks {rtc_clk}]\ + -group [get_clocks {wb_clk}] -comment {Async Clock group} + +############################################################################### +# Environment +############################################################################### +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs] +set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0] +puts "\[INFO\]: Setting load to: $cap_load" +set_load $cap_load [all_outputs] + +############################################################################### +# Design Rules +###############################################################################
diff --git a/openlane/ycr2_iconnect/config.tcl b/openlane/ycr2_iconnect/config.tcl new file mode 100644 index 0000000..d938d00 --- /dev/null +++ b/openlane/ycr2_iconnect/config.tcl
@@ -0,0 +1,96 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 + +set script_dir [file dirname [file normalize [info script]]] + +set ::env(ROUTING_CORES) "6" + +set ::env(DESIGN_NAME) ycr2_iconnect +set ::env(DESIGN_IS_CORE) "0" +set ::env(FP_PDN_CORE_RING) "0" + +# Timing configuration +set ::env(CLOCK_PERIOD) "10" +set ::env(CLOCK_PORT) "core_clk rtc_clk" + +set ::env(SYNTH_MAX_FANOUT) 4 + +## CTS BUFFER +set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8" +set ::env(CTS_SINK_CLUSTERING_SIZE) "16" +set ::env(CLOCK_BUFFER_FANOUT) "8" +set ::env(LEC_ENABLE) 0 + +set ::env(VERILOG_FILES) "\ + $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr2_iconnect.sv \ + $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr2_cross_bar.sv \ + $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr2_router.sv \ + $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_dmem_router.sv \ + $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_sram_mux.sv \ + $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_tcm.sv \ + $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_timer.sv \ + $script_dir/../../verilog/rtl/yifive/ycr2c/src/lib/ycr_arb.sv \ + $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/primitives/ycr_reset_cells.sv \ + " +set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr2c/src/includes ] +set ::env(SYNTH_READ_BLACKBOX_LIB) 1 +set ::env(SYNTH_DEFINES) [list SYNTHESIS ] + + +set ::env(SDC_FILE) "$script_dir/base.sdc" +set ::env(BASE_SDC_FILE) "$script_dir/base.sdc" + +set ::env(LEC_ENABLE) 0 + +## Floorplan +set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg +set ::env(FP_SIZING) absolute +set ::env(DIE_AREA) "0 0 380 1000" + +#set ::env(PDN_CFG) $script_dir/pdn_cfg.tcl +#set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg +set ::env(PL_TARGET_DENSITY) 0.20 +set ::env(CELL_PAD) "14" + +#set ::env(PL_ROUTABILITY_DRIVEN) "1" +set ::env(PL_TIME_DRIVEN) "1" + +### PDN +#set ::env(FP_PDN_CHECK_NODES) "0" +#set ::env(FP_PDN_HORIZONTAL_HALO) "10" +#set ::env(FP_PDN_VERTICAL_HALO) "10" +# +#set ::env(FP_PDN_VOFFSET) "5" +#set ::env(FP_PDN_VPITCH) "80" +#set ::env(FP_PDN_VSPACING) "15.5" +#set ::env(FP_PDN_VWIDTH) "3.1" +# +#set ::env(FP_PDN_HOFFSET) "10" +#set ::env(FP_PDN_HPITCH) "100" +#set ::env(FP_PDN_HSPACING) "10" +#set ::env(FP_PDN_HWIDTH) "3.1" + + +set ::env(GLB_RT_MAXLAYER) 5 +set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 20 +set ::env(DIODE_INSERTION_STRATEGY) 3 + + +set ::env(QUIT_ON_TIMING_VIOLATIONS) "0" +set ::env(QUIT_ON_MAGIC_DRC) "1" +set ::env(QUIT_ON_LVS_ERROR) "0" +set ::env(QUIT_ON_SLEW_VIOLATIONS) "0" + +
diff --git a/openlane/ycr2_iconnect/drc_exclude.cells b/openlane/ycr2_iconnect/drc_exclude.cells new file mode 100644 index 0000000..0ecc9c0 --- /dev/null +++ b/openlane/ycr2_iconnect/drc_exclude.cells
@@ -0,0 +1,55 @@ +sky130_fd_sc_hd__a2111oi_0 +sky130_fd_sc_hd__a21boi_0 +sky130_fd_sc_hd__and2_0 +sky130_fd_sc_hd__buf_16 +sky130_fd_sc_hd__clkdlybuf4s15_1 +sky130_fd_sc_hd__clkdlybuf4s18_1 +sky130_fd_sc_hd__clkdlybuf4s25_1 +sky130_fd_sc_hd__clkdlybuf4s50_1 +sky130_fd_sc_hd__fa_4 +sky130_fd_sc_hd__lpflow_bleeder_1 +sky130_fd_sc_hd__lpflow_clkbufkapwr_1 +sky130_fd_sc_hd__lpflow_clkbufkapwr_16 +sky130_fd_sc_hd__lpflow_clkbufkapwr_2 +sky130_fd_sc_hd__lpflow_clkbufkapwr_4 +sky130_fd_sc_hd__lpflow_clkbufkapwr_8 +sky130_fd_sc_hd__lpflow_clkinvkapwr_1 +sky130_fd_sc_hd__lpflow_clkinvkapwr_16 +sky130_fd_sc_hd__lpflow_clkinvkapwr_2 +sky130_fd_sc_hd__lpflow_clkinvkapwr_4 +sky130_fd_sc_hd__lpflow_clkinvkapwr_8 +sky130_fd_sc_hd__lpflow_decapkapwr_12 +sky130_fd_sc_hd__lpflow_decapkapwr_3 +sky130_fd_sc_hd__lpflow_decapkapwr_4 +sky130_fd_sc_hd__lpflow_decapkapwr_6 +sky130_fd_sc_hd__lpflow_decapkapwr_8 +sky130_fd_sc_hd__lpflow_inputiso0n_1 +sky130_fd_sc_hd__lpflow_inputiso0p_1 +sky130_fd_sc_hd__lpflow_inputiso1n_1 +sky130_fd_sc_hd__lpflow_inputiso1p_1 +sky130_fd_sc_hd__lpflow_inputisolatch_1 +sky130_fd_sc_hd__lpflow_isobufsrc_1 +sky130_fd_sc_hd__lpflow_isobufsrc_16 +sky130_fd_sc_hd__lpflow_isobufsrc_2 +sky130_fd_sc_hd__lpflow_isobufsrc_4 +sky130_fd_sc_hd__lpflow_isobufsrc_8 +sky130_fd_sc_hd__lpflow_isobufsrckapwr_16 +sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 +sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 +sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 +sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4 +sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 +sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 +sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 +sky130_fd_sc_hd__mux4_4 +sky130_fd_sc_hd__o21ai_0 +sky130_fd_sc_hd__o311ai_0 +sky130_fd_sc_hd__or2_0 +sky130_fd_sc_hd__probe_p_8 +sky130_fd_sc_hd__probec_p_8 +sky130_fd_sc_hd__xor3_1 +sky130_fd_sc_hd__xor3_2 +sky130_fd_sc_hd__xor3_4 +sky130_fd_sc_hd__xnor3_1 +sky130_fd_sc_hd__xnor3_2 +sky130_fd_sc_hd__xnor3_4 \ No newline at end of file
diff --git a/openlane/ycr2_iconnect/pin_order.cfg b/openlane/ycr2_iconnect/pin_order.cfg new file mode 100644 index 0000000..178edb5 --- /dev/null +++ b/openlane/ycr2_iconnect/pin_order.cfg
@@ -0,0 +1,1136 @@ +#BUS_SORT +#MANUAL_PLACE + +#W +sram0_clk0 000 0 2 +sram0_csb0 +sram0_web0 +sram0_addr0\[8\] +sram0_addr0\[7\] +sram0_addr0\[6\] +sram0_addr0\[5\] +sram0_addr0\[4\] +sram0_addr0\[3\] +sram0_addr0\[2\] +sram0_addr0\[1\] +sram0_addr0\[0\] +sram0_wmask0\[3\] +sram0_wmask0\[2\] +sram0_wmask0\[1\] +sram0_wmask0\[0\] +sram0_din0\[31\] +sram0_din0\[30\] +sram0_din0\[29\] +sram0_din0\[28\] +sram0_din0\[27\] +sram0_din0\[26\] +sram0_din0\[25\] +sram0_din0\[24\] +sram0_din0\[23\] +sram0_din0\[22\] +sram0_din0\[21\] +sram0_din0\[20\] +sram0_din0\[19\] +sram0_din0\[18\] +sram0_din0\[17\] +sram0_din0\[16\] +sram0_din0\[15\] +sram0_din0\[14\] +sram0_din0\[13\] +sram0_din0\[12\] +sram0_din0\[11\] +sram0_din0\[10\] +sram0_din0\[9\] +sram0_din0\[8\] +sram0_din0\[7\] +sram0_din0\[6\] +sram0_din0\[5\] +sram0_din0\[4\] +sram0_din0\[3\] +sram0_din0\[2\] +sram0_din0\[1\] +sram0_din0\[0\] +sram0_dout0\[31\] +sram0_dout0\[30\] +sram0_dout0\[29\] +sram0_dout0\[28\] +sram0_dout0\[27\] +sram0_dout0\[26\] +sram0_dout0\[25\] +sram0_dout0\[24\] +sram0_dout0\[23\] +sram0_dout0\[22\] +sram0_dout0\[21\] +sram0_dout0\[20\] +sram0_dout0\[19\] +sram0_dout0\[18\] +sram0_dout0\[17\] +sram0_dout0\[16\] +sram0_dout0\[15\] +sram0_dout0\[14\] +sram0_dout0\[13\] +sram0_dout0\[12\] +sram0_dout0\[11\] +sram0_dout0\[10\] +sram0_dout0\[9\] +sram0_dout0\[8\] +sram0_dout0\[7\] +sram0_dout0\[6\] +sram0_dout0\[5\] +sram0_dout0\[4\] +sram0_dout0\[3\] +sram0_dout0\[2\] +sram0_dout0\[1\] +sram0_dout0\[0\] + + +sram0_clk1 110 0 2 +sram0_csb1 +sram0_addr1\[8\] +sram0_addr1\[7\] +sram0_addr1\[6\] +sram0_addr1\[5\] +sram0_addr1\[4\] +sram0_addr1\[3\] +sram0_addr1\[2\] +sram0_addr1\[1\] +sram0_addr1\[0\] +sram0_dout1\[31\] +sram0_dout1\[30\] +sram0_dout1\[29\] +sram0_dout1\[28\] +sram0_dout1\[27\] +sram0_dout1\[26\] +sram0_dout1\[25\] +sram0_dout1\[24\] +sram0_dout1\[23\] +sram0_dout1\[22\] +sram0_dout1\[21\] +sram0_dout1\[20\] +sram0_dout1\[19\] +sram0_dout1\[18\] +sram0_dout1\[17\] +sram0_dout1\[16\] +sram0_dout1\[15\] +sram0_dout1\[14\] +sram0_dout1\[13\] +sram0_dout1\[12\] +sram0_dout1\[11\] +sram0_dout1\[10\] +sram0_dout1\[9\] +sram0_dout1\[8\] +sram0_dout1\[7\] +sram0_dout1\[6\] +sram0_dout1\[5\] +sram0_dout1\[4\] +sram0_dout1\[3\] +sram0_dout1\[2\] +sram0_dout1\[1\] +sram0_dout1\[0\] + +core0_uid\[1\] 0200 00 2 +core0_uid\[0\] +core0_imem_req_ack +core0_imem_req +core0_imem_cmd +core0_imem_addr\[31\] +core0_imem_addr\[30\] +core0_imem_addr\[29\] +core0_imem_addr\[28\] +core0_imem_addr\[27\] +core0_imem_addr\[26\] +core0_imem_addr\[25\] +core0_imem_addr\[24\] +core0_imem_addr\[23\] +core0_imem_addr\[22\] +core0_imem_addr\[21\] +core0_imem_addr\[20\] +core0_imem_addr\[19\] +core0_imem_addr\[18\] +core0_imem_addr\[17\] +core0_imem_addr\[16\] +core0_imem_addr\[15\] +core0_imem_addr\[14\] +core0_imem_addr\[13\] +core0_imem_addr\[12\] +core0_imem_addr\[11\] +core0_imem_addr\[10\] +core0_imem_addr\[9\] +core0_imem_addr\[8\] +core0_imem_addr\[7\] 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+core1_irq_lines\[6\] +core1_irq_lines\[5\] +core1_irq_lines\[4\] +core1_irq_lines\[3\] +core1_irq_lines\[2\] +core1_irq_lines\[1\] +core1_irq_lines\[0\] +core1_irq_soft + + +#S +core_icache_req_ack 000 0 2 +core_icache_req +core_icache_cmd +core_icache_addr\[31\] +core_icache_addr\[30\] +core_icache_addr\[29\] +core_icache_addr\[28\] +core_icache_addr\[27\] +core_icache_addr\[26\] +core_icache_addr\[25\] +core_icache_addr\[24\] +core_icache_addr\[23\] +core_icache_addr\[22\] +core_icache_addr\[21\] +core_icache_addr\[20\] +core_icache_addr\[19\] +core_icache_addr\[18\] +core_icache_addr\[17\] +core_icache_addr\[16\] +core_icache_addr\[15\] +core_icache_addr\[14\] +core_icache_addr\[13\] +core_icache_addr\[12\] +core_icache_addr\[11\] +core_icache_addr\[10\] +core_icache_addr\[9\] +core_icache_addr\[8\] +core_icache_addr\[7\] +core_icache_addr\[6\] +core_icache_addr\[5\] +core_icache_addr\[4\] +core_icache_addr\[3\] +core_icache_addr\[2\] +core_icache_addr\[1\] +core_icache_addr\[0\] +core_icache_bl\[2\] +core_icache_bl\[1\] +core_icache_bl\[0\] +core_icache_width\[1\] +core_icache_width\[0\] +core_icache_rdata\[31\] +core_icache_rdata\[30\] +core_icache_rdata\[29\] +core_icache_rdata\[28\] +core_icache_rdata\[27\] +core_icache_rdata\[26\] +core_icache_rdata\[25\] +core_icache_rdata\[24\] +core_icache_rdata\[23\] +core_icache_rdata\[22\] +core_icache_rdata\[21\] +core_icache_rdata\[20\] +core_icache_rdata\[19\] +core_icache_rdata\[18\] +core_icache_rdata\[17\] +core_icache_rdata\[16\] +core_icache_rdata\[15\] +core_icache_rdata\[14\] +core_icache_rdata\[13\] +core_icache_rdata\[12\] +core_icache_rdata\[11\] +core_icache_rdata\[10\] +core_icache_rdata\[9\] +core_icache_rdata\[8\] +core_icache_rdata\[7\] +core_icache_rdata\[6\] +core_icache_rdata\[5\] +core_icache_rdata\[4\] +core_icache_rdata\[3\] +core_icache_rdata\[2\] +core_icache_rdata\[1\] +core_icache_rdata\[0\] +core_icache_resp\[1\] +core_icache_resp\[0\] + + +core_dcache_req_ack 100 0 2 +core_dcache_req +core_dcache_cmd +core_dcache_width\[1\] +core_dcache_width\[0\] +core_dcache_addr\[31\] +core_dcache_addr\[30\] +core_dcache_addr\[29\] +core_dcache_addr\[28\] +core_dcache_addr\[27\] +core_dcache_addr\[26\] +core_dcache_addr\[25\] +core_dcache_addr\[24\] +core_dcache_addr\[23\] +core_dcache_addr\[22\] +core_dcache_addr\[21\] +core_dcache_addr\[20\] +core_dcache_addr\[19\] +core_dcache_addr\[18\] +core_dcache_addr\[17\] +core_dcache_addr\[16\] +core_dcache_addr\[15\] +core_dcache_addr\[14\] +core_dcache_addr\[13\] +core_dcache_addr\[12\] +core_dcache_addr\[11\] +core_dcache_addr\[10\] +core_dcache_addr\[9\] +core_dcache_addr\[8\] +core_dcache_addr\[7\] +core_dcache_addr\[6\] +core_dcache_addr\[5\] +core_dcache_addr\[4\] +core_dcache_addr\[3\] +core_dcache_addr\[2\] +core_dcache_addr\[1\] +core_dcache_addr\[0\] +core_dcache_wdata\[31\] +core_dcache_wdata\[30\] +core_dcache_wdata\[29\] +core_dcache_wdata\[28\] +core_dcache_wdata\[27\] +core_dcache_wdata\[26\] +core_dcache_wdata\[25\] +core_dcache_wdata\[24\] +core_dcache_wdata\[23\] +core_dcache_wdata\[22\] +core_dcache_wdata\[21\] +core_dcache_wdata\[20\] +core_dcache_wdata\[19\] +core_dcache_wdata\[18\] +core_dcache_wdata\[17\] +core_dcache_wdata\[16\] +core_dcache_wdata\[15\] +core_dcache_wdata\[14\] +core_dcache_wdata\[13\] +core_dcache_wdata\[12\] +core_dcache_wdata\[11\] +core_dcache_wdata\[10\] +core_dcache_wdata\[9\] +core_dcache_wdata\[8\] +core_dcache_wdata\[7\] +core_dcache_wdata\[6\] +core_dcache_wdata\[5\] +core_dcache_wdata\[4\] +core_dcache_wdata\[3\] +core_dcache_wdata\[2\] +core_dcache_wdata\[1\] +core_dcache_wdata\[0\] +core_dcache_rdata\[31\] +core_dcache_rdata\[30\] +core_dcache_rdata\[29\] +core_dcache_rdata\[28\] +core_dcache_rdata\[27\] +core_dcache_rdata\[26\] +core_dcache_rdata\[25\] +core_dcache_rdata\[24\] +core_dcache_rdata\[23\] +core_dcache_rdata\[22\] +core_dcache_rdata\[21\] +core_dcache_rdata\[20\] +core_dcache_rdata\[19\] +core_dcache_rdata\[18\] +core_dcache_rdata\[17\] +core_dcache_rdata\[16\] +core_dcache_rdata\[15\] +core_dcache_rdata\[14\] +core_dcache_rdata\[13\] +core_dcache_rdata\[12\] +core_dcache_rdata\[11\] +core_dcache_rdata\[10\] +core_dcache_rdata\[9\] +core_dcache_rdata\[8\] +core_dcache_rdata\[7\] +core_dcache_rdata\[6\] +core_dcache_rdata\[5\] +core_dcache_rdata\[4\] +core_dcache_rdata\[3\] +core_dcache_rdata\[2\] +core_dcache_rdata\[1\] +core_dcache_rdata\[0\] +core_dcache_resp\[1\] +core_dcache_resp\[0\] + +core_dmem_req_ack 0200 0 2 +core_dmem_req +core_dmem_cmd +core_dmem_width\[1\] +core_dmem_width\[0\] +core_dmem_addr\[31\] +core_dmem_addr\[30\] +core_dmem_addr\[29\] +core_dmem_addr\[28\] +core_dmem_addr\[27\] +core_dmem_addr\[26\] +core_dmem_addr\[25\] +core_dmem_addr\[24\] +core_dmem_addr\[23\] +core_dmem_addr\[22\] +core_dmem_addr\[21\] +core_dmem_addr\[20\] +core_dmem_addr\[19\] +core_dmem_addr\[18\] +core_dmem_addr\[17\] +core_dmem_addr\[16\] +core_dmem_addr\[15\] +core_dmem_addr\[14\] +core_dmem_addr\[13\] +core_dmem_addr\[12\] +core_dmem_addr\[11\] +core_dmem_addr\[10\] +core_dmem_addr\[9\] +core_dmem_addr\[8\] +core_dmem_addr\[7\] +core_dmem_addr\[6\] +core_dmem_addr\[5\] +core_dmem_addr\[4\] +core_dmem_addr\[3\] +core_dmem_addr\[2\] +core_dmem_addr\[1\] +core_dmem_addr\[0\] +core_dmem_wdata\[31\] +core_dmem_wdata\[30\] +core_dmem_wdata\[29\] +core_dmem_wdata\[28\] +core_dmem_wdata\[27\] +core_dmem_wdata\[26\] +core_dmem_wdata\[25\] +core_dmem_wdata\[24\] +core_dmem_wdata\[23\] +core_dmem_wdata\[22\] +core_dmem_wdata\[21\] +core_dmem_wdata\[20\] +core_dmem_wdata\[19\] +core_dmem_wdata\[18\] +core_dmem_wdata\[17\] +core_dmem_wdata\[16\] +core_dmem_wdata\[15\] +core_dmem_wdata\[14\] +core_dmem_wdata\[13\] +core_dmem_wdata\[12\] +core_dmem_wdata\[11\] +core_dmem_wdata\[10\] +core_dmem_wdata\[9\] +core_dmem_wdata\[8\] +core_dmem_wdata\[7\] +core_dmem_wdata\[6\] +core_dmem_wdata\[5\] +core_dmem_wdata\[4\] +core_dmem_wdata\[3\] +core_dmem_wdata\[2\] +core_dmem_wdata\[1\] +core_dmem_wdata\[0\] +core_dmem_rdata\[31\] +core_dmem_rdata\[30\] +core_dmem_rdata\[29\] +core_dmem_rdata\[28\] +core_dmem_rdata\[27\] +core_dmem_rdata\[26\] +core_dmem_rdata\[25\] +core_dmem_rdata\[24\] +core_dmem_rdata\[23\] +core_dmem_rdata\[22\] +core_dmem_rdata\[21\] +core_dmem_rdata\[20\] +core_dmem_rdata\[19\] +core_dmem_rdata\[18\] +core_dmem_rdata\[17\] +core_dmem_rdata\[16\] +core_dmem_rdata\[15\] +core_dmem_rdata\[14\] +core_dmem_rdata\[13\] +core_dmem_rdata\[12\] +core_dmem_rdata\[11\] +core_dmem_rdata\[10\] +core_dmem_rdata\[9\] +core_dmem_rdata\[8\] +core_dmem_rdata\[7\] +core_dmem_rdata\[6\] +core_dmem_rdata\[5\] +core_dmem_rdata\[4\] +core_dmem_rdata\[3\] +core_dmem_rdata\[2\] +core_dmem_rdata\[1\] +core_dmem_rdata\[0\] +core_dmem_resp\[1\] +core_dmem_resp\[0\] + +cfg_dcache_force_flush +cfg_sram_lphase\[1\] +cfg_sram_lphase\[0\] + +core_debug_sel\[1\] 300 0 2 +core_debug_sel\[0\] + +riscv_debug\[63\] +riscv_debug\[62\] +riscv_debug\[61\] +riscv_debug\[60\] +riscv_debug\[59\] +riscv_debug\[58\] +riscv_debug\[57\] +riscv_debug\[56\] +riscv_debug\[55\] +riscv_debug\[54\] +riscv_debug\[53\] +riscv_debug\[52\] +riscv_debug\[51\] +riscv_debug\[50\] +riscv_debug\[49\] +riscv_debug\[48\] +riscv_debug\[47\] +riscv_debug\[46\] +riscv_debug\[45\] +riscv_debug\[44\] +riscv_debug\[43\] +riscv_debug\[42\] +riscv_debug\[41\] +riscv_debug\[40\] +riscv_debug\[39\] +riscv_debug\[38\] +riscv_debug\[37\] +riscv_debug\[36\] +riscv_debug\[35\] +riscv_debug\[34\] +riscv_debug\[33\] +riscv_debug\[32\] +riscv_debug\[31\] +riscv_debug\[30\] +riscv_debug\[29\] +riscv_debug\[28\] +riscv_debug\[27\] +riscv_debug\[26\] +riscv_debug\[25\] +riscv_debug\[24\] +riscv_debug\[23\] +riscv_debug\[22\] +riscv_debug\[21\] +riscv_debug\[20\] +riscv_debug\[19\] +riscv_debug\[18\] +riscv_debug\[17\] +riscv_debug\[16\] +riscv_debug\[15\] +riscv_debug\[14\] +riscv_debug\[13\] +riscv_debug\[12\] +riscv_debug\[11\] +riscv_debug\[10\] +riscv_debug\[9\] +riscv_debug\[8\] +riscv_debug\[7\] +riscv_debug\[6\] +riscv_debug\[5\] +riscv_debug\[4\] +riscv_debug\[3\] +riscv_debug\[2\] +riscv_debug\[1\] +riscv_debug\[0\] + +core_irq_lines_i\[15\] +core_irq_lines_i\[14\] +core_irq_lines_i\[13\] +core_irq_lines_i\[12\] +core_irq_lines_i\[11\] +core_irq_lines_i\[10\] +core_irq_lines_i\[9\] +core_irq_lines_i\[8\] +core_irq_lines_i\[7\] +core_irq_lines_i\[6\] +core_irq_lines_i\[5\] +core_irq_lines_i\[4\] +core_irq_lines_i\[3\] +core_irq_lines_i\[2\] +core_irq_lines_i\[1\] +core_irq_lines_i\[0\] +core_irq_soft_i + +core_clk +rtc_clk +pwrup_rst_n +cpu_intf_rst_n
diff --git a/openlane/ycr_core/base.sdc b/openlane/ycr_core_top/base.sdc similarity index 100% rename from openlane/ycr_core/base.sdc rename to openlane/ycr_core_top/base.sdc
diff --git a/openlane/ycr_core/config.tcl b/openlane/ycr_core_top/config.tcl similarity index 94% rename from openlane/ycr_core/config.tcl rename to openlane/ycr_core_top/config.tcl index a1aa12a..5325e7f 100644 --- a/openlane/ycr_core/config.tcl +++ b/openlane/ycr_core_top/config.tcl
@@ -18,7 +18,8 @@ set ::env(ROUTING_CORES) "6" set ::env(DESIGN_NAME) ycr_core_top -set ::env(DESIGN_IS_CORE) 0 +set ::env(DESIGN_IS_CORE) "0" +set ::env(FP_PDN_CORE_RING) "0" set ::env(CLOCK_PERIOD) "10" set ::env(CLOCK_PORT) "clk" @@ -71,15 +72,16 @@ ## Floorplan set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 700 850 " +set ::env(DIE_AREA) "0 0 590 960 " set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg -set ::env(PL_TARGET_DENSITY) 0.36 +set ::env(PL_TARGET_DENSITY) 0.37 +set ::env(CELL_PAD) "6" - +set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4} set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 -set ::env(DIODE_INSERTION_STRATEGY) 4 +set ::env(DIODE_INSERTION_STRATEGY) 3 set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
diff --git a/openlane/ycr_core/macro_placement.cfg b/openlane/ycr_core_top/macro_placement.cfg similarity index 100% rename from openlane/ycr_core/macro_placement.cfg rename to openlane/ycr_core_top/macro_placement.cfg
diff --git a/openlane/ycr_core/pin_order.cfg b/openlane/ycr_core_top/pin_order.cfg similarity index 97% rename from openlane/ycr_core/pin_order.cfg rename to openlane/ycr_core_top/pin_order.cfg index f8769e9..79b2c6f 100644 --- a/openlane/ycr_core/pin_order.cfg +++ b/openlane/ycr_core_top/pin_order.cfg
@@ -1,9 +1,8 @@ #BUS_SORT #MANUAL_PLACE -#S -core_uid\[1\] 0000 00 2 +#E +core_uid\[1\] 0200 00 2 core_uid\[0\] -cpu_rst_n imem2core_req_ack_i core2imem_req_o core2imem_cmd_o @@ -77,7 +76,7 @@ imem2core_resp_i\[1\] imem2core_resp_i\[0\] -dmem2core_req_ack_i 0100 0 2 +dmem2core_req_ack_i 0350 0 2 core2dmem_req_o core2dmem_cmd_o core2dmem_width_o\[1\] @@ -181,7 +180,7 @@ dmem2core_resp_i\[1\] dmem2core_resp_i\[0\] -core_debug\[48\] 0200 0 2 +core_debug\[48\] 0500 0 2 core_debug\[47\] core_debug\[46\] core_debug\[45\] @@ -231,7 +230,7 @@ core_debug\[1\] core_debug\[0\] -core_irq_mtimer_i 0300 0 2 +core_irq_mtimer_i 0600 0 2 core_mtimer_val_i\[63\] core_mtimer_val_i\[62\] core_mtimer_val_i\[61\] @@ -297,12 +296,6 @@ core_mtimer_val_i\[1\] core_mtimer_val_i\[0\] -pwrup_rst_n -rst_n -test_mode -test_rst_n - - core_irq_lines_i\[15\] core_irq_lines_i\[14\] core_irq_lines_i\[13\] @@ -320,7 +313,15 @@ core_irq_lines_i\[1\] core_irq_lines_i\[0\] core_irq_soft_i +cpu_rst_n + +#S +pwrup_rst_n +rst_n + + clk +clk_o core_rst_n_o core_rdc_qlfy_o
diff --git a/openlane/ycr_intf/base.sdc b/openlane/ycr_intf/base.sdc new file mode 100644 index 0000000..00fe508 --- /dev/null +++ b/openlane/ycr_intf/base.sdc
@@ -0,0 +1,32 @@ +############################################################################### +# Timing Constraints +############################################################################### +create_clock -name core_clk -period 20.0000 [get_ports {core_clk}] +create_clock -name rtc_clk -period 40.0000 [get_ports {rtc_clk}] +create_clock -name wb_clk -period 10.0000 [get_ports {wb_clk}] + +set_clock_transition 0.1500 [all_clocks] +set_clock_uncertainty -setup 0.2500 [all_clocks] +set_clock_uncertainty -hold 0.2500 [all_clocks] + +set ::env(SYNTH_TIMING_DERATE) 0.05 +puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %" +set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}] +set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}] + +set_clock_groups -name async_clock -asynchronous \ + -group [get_clocks {core_clk}]\ + -group [get_clocks {rtc_clk}]\ + -group [get_clocks {wb_clk}] -comment {Async Clock group} + +############################################################################### +# Environment +############################################################################### +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs] +set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0] +puts "\[INFO\]: Setting load to: $cap_load" +set_load $cap_load [all_outputs] + +############################################################################### +# Design Rules +###############################################################################
diff --git a/openlane/ycr_intf/config.tcl b/openlane/ycr_intf/config.tcl new file mode 100644 index 0000000..b6a0f68 --- /dev/null +++ b/openlane/ycr_intf/config.tcl
@@ -0,0 +1,87 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 + +set script_dir [file dirname [file normalize [info script]]] + +set ::env(ROUTING_CORES) "6" + +set ::env(DESIGN_NAME) ycr_intf +set ::env(DESIGN_IS_CORE) "0" +set ::env(FP_PDN_CORE_RING) "0" + +# Timing configuration +set ::env(CLOCK_PERIOD) "10" +set ::env(CLOCK_PORT) "wb_clk core_clk" + +set ::env(SYNTH_MAX_FANOUT) 4 + +## CTS BUFFER +set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8" +set ::env(CTS_SINK_CLUSTERING_SIZE) "16" +set ::env(CLOCK_BUFFER_FANOUT) "8" +set ::env(LEC_ENABLE) 0 + +set ::env(VERILOG_FILES) "\ + $script_dir/../../verilog/rtl/yifive/ycr2c/src/lib/clk_skew_adjust.gv \ + $script_dir/../../verilog/rtl/yifive/ycr2c/src/lib/ctech_cells.sv \ + $script_dir/../../verilog/rtl/yifive/ycr2c/src/cache/src/core/dcache_top.sv \ + $script_dir/../../verilog/rtl/yifive/ycr2c/src/cache/src/core/dcache_tag_fifo.sv \ + $script_dir/../../verilog/rtl/yifive/ycr2c/src/cache/src/core/icache_tag_fifo.sv \ + $script_dir/../../verilog/rtl/yifive/ycr2c/src/cache/src/core/icache_top.sv \ + $script_dir/../../verilog/rtl/yifive/ycr2c/src/cache/src/core/icache_app_fsm.sv \ + $script_dir/../../verilog/rtl/yifive/ycr2c/src/lib/ycr_async_wbb.sv \ + $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_dmem_wb.sv \ + $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_intf.sv \ + $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_sram_mux.sv \ + $script_dir/../../verilog/rtl/yifive/ycr2c/src/lib/async_fifo.sv \ + $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/primitives/ycr_reset_cells.sv \ + " +set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr2c/src/includes ] +set ::env(SYNTH_READ_BLACKBOX_LIB) 1 +set ::env(SYNTH_DEFINES) [list SYNTHESIS ] + + +set ::env(SDC_FILE) "$script_dir/base.sdc" +set ::env(BASE_SDC_FILE) "$script_dir/base.sdc" + +set ::env(LEC_ENABLE) 0 + +set ::env(VDD_PIN) [list {vccd1}] +set ::env(GND_PIN) [list {vssd1}] + +## Floorplan +set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg +set ::env(FP_SIZING) absolute +set ::env(DIE_AREA) "0 0 810 640 " +set ::env(CELL_PAD) "6" + +set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg +set ::env(PL_TARGET_DENSITY) 0.37 + + +set ::env(RT_MAX_LAYER) {met4} +set ::env(GLB_RT_MAXLAYER) "5" +set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 +set ::env(DIODE_INSERTION_STRATEGY) 3 + + +set ::env(QUIT_ON_TIMING_VIOLATIONS) "0" +set ::env(QUIT_ON_MAGIC_DRC) "1" +set ::env(QUIT_ON_LVS_ERROR) "0" +set ::env(QUIT_ON_SLEW_VIOLATIONS) "0" + +#Need to cross-check why global timing opimization creating setup vio with hugh hold fix +set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0" +
diff --git a/openlane/ycr_intf/pin_order.cfg b/openlane/ycr_intf/pin_order.cfg new file mode 100644 index 0000000..6b93ea3 --- /dev/null +++ b/openlane/ycr_intf/pin_order.cfg
@@ -0,0 +1,847 @@ +#BUS_SORT +#MANUAL_PLACE + +#N + +core_icache_req_ack 000 0 2 +core_icache_req +core_icache_cmd +core_icache_addr\[31\] +core_icache_addr\[30\] +core_icache_addr\[29\] +core_icache_addr\[28\] +core_icache_addr\[27\] +core_icache_addr\[26\] +core_icache_addr\[25\] +core_icache_addr\[24\] +core_icache_addr\[23\] +core_icache_addr\[22\] +core_icache_addr\[21\] +core_icache_addr\[20\] +core_icache_addr\[19\] +core_icache_addr\[18\] +core_icache_addr\[17\] +core_icache_addr\[16\] +core_icache_addr\[15\] +core_icache_addr\[14\] +core_icache_addr\[13\] +core_icache_addr\[12\] +core_icache_addr\[11\] +core_icache_addr\[10\] +core_icache_addr\[9\] +core_icache_addr\[8\] +core_icache_addr\[7\] +core_icache_addr\[6\] +core_icache_addr\[5\] +core_icache_addr\[4\] +core_icache_addr\[3\] +core_icache_addr\[2\] +core_icache_addr\[1\] +core_icache_addr\[0\] +core_icache_bl\[2\] +core_icache_bl\[1\] +core_icache_bl\[0\] +core_icache_width\[1\] +core_icache_width\[0\] +core_icache_rdata\[31\] +core_icache_rdata\[30\] +core_icache_rdata\[29\] +core_icache_rdata\[28\] +core_icache_rdata\[27\] +core_icache_rdata\[26\] +core_icache_rdata\[25\] +core_icache_rdata\[24\] +core_icache_rdata\[23\] +core_icache_rdata\[22\] +core_icache_rdata\[21\] +core_icache_rdata\[20\] +core_icache_rdata\[19\] +core_icache_rdata\[18\] +core_icache_rdata\[17\] +core_icache_rdata\[16\] +core_icache_rdata\[15\] +core_icache_rdata\[14\] +core_icache_rdata\[13\] +core_icache_rdata\[12\] +core_icache_rdata\[11\] +core_icache_rdata\[10\] +core_icache_rdata\[9\] +core_icache_rdata\[8\] +core_icache_rdata\[7\] +core_icache_rdata\[6\] +core_icache_rdata\[5\] +core_icache_rdata\[4\] +core_icache_rdata\[3\] +core_icache_rdata\[2\] +core_icache_rdata\[1\] +core_icache_rdata\[0\] +core_icache_resp\[1\] +core_icache_resp\[0\] + + +core_dcache_req_ack 100 0 2 +core_dcache_req +core_dcache_cmd +core_dcache_width\[1\] +core_dcache_width\[0\] +core_dcache_addr\[31\] +core_dcache_addr\[30\] +core_dcache_addr\[29\] +core_dcache_addr\[28\] +core_dcache_addr\[27\] +core_dcache_addr\[26\] +core_dcache_addr\[25\] +core_dcache_addr\[24\] +core_dcache_addr\[23\] +core_dcache_addr\[22\] +core_dcache_addr\[21\] +core_dcache_addr\[20\] +core_dcache_addr\[19\] +core_dcache_addr\[18\] +core_dcache_addr\[17\] +core_dcache_addr\[16\] +core_dcache_addr\[15\] +core_dcache_addr\[14\] +core_dcache_addr\[13\] +core_dcache_addr\[12\] +core_dcache_addr\[11\] +core_dcache_addr\[10\] +core_dcache_addr\[9\] +core_dcache_addr\[8\] +core_dcache_addr\[7\] +core_dcache_addr\[6\] +core_dcache_addr\[5\] +core_dcache_addr\[4\] +core_dcache_addr\[3\] +core_dcache_addr\[2\] +core_dcache_addr\[1\] +core_dcache_addr\[0\] +core_dcache_wdata\[31\] +core_dcache_wdata\[30\] +core_dcache_wdata\[29\] +core_dcache_wdata\[28\] +core_dcache_wdata\[27\] +core_dcache_wdata\[26\] +core_dcache_wdata\[25\] +core_dcache_wdata\[24\] +core_dcache_wdata\[23\] +core_dcache_wdata\[22\] +core_dcache_wdata\[21\] +core_dcache_wdata\[20\] +core_dcache_wdata\[19\] +core_dcache_wdata\[18\] +core_dcache_wdata\[17\] +core_dcache_wdata\[16\] +core_dcache_wdata\[15\] +core_dcache_wdata\[14\] +core_dcache_wdata\[13\] +core_dcache_wdata\[12\] +core_dcache_wdata\[11\] +core_dcache_wdata\[10\] +core_dcache_wdata\[9\] +core_dcache_wdata\[8\] +core_dcache_wdata\[7\] +core_dcache_wdata\[6\] +core_dcache_wdata\[5\] +core_dcache_wdata\[4\] +core_dcache_wdata\[3\] +core_dcache_wdata\[2\] +core_dcache_wdata\[1\] +core_dcache_wdata\[0\] +core_dcache_rdata\[31\] +core_dcache_rdata\[30\] +core_dcache_rdata\[29\] +core_dcache_rdata\[28\] +core_dcache_rdata\[27\] +core_dcache_rdata\[26\] +core_dcache_rdata\[25\] +core_dcache_rdata\[24\] +core_dcache_rdata\[23\] +core_dcache_rdata\[22\] +core_dcache_rdata\[21\] +core_dcache_rdata\[20\] +core_dcache_rdata\[19\] +core_dcache_rdata\[18\] +core_dcache_rdata\[17\] +core_dcache_rdata\[16\] +core_dcache_rdata\[15\] +core_dcache_rdata\[14\] +core_dcache_rdata\[13\] +core_dcache_rdata\[12\] +core_dcache_rdata\[11\] +core_dcache_rdata\[10\] +core_dcache_rdata\[9\] +core_dcache_rdata\[8\] +core_dcache_rdata\[7\] +core_dcache_rdata\[6\] +core_dcache_rdata\[5\] +core_dcache_rdata\[4\] +core_dcache_rdata\[3\] +core_dcache_rdata\[2\] +core_dcache_rdata\[1\] +core_dcache_rdata\[0\] +core_dcache_resp\[1\] +core_dcache_resp\[0\] + +core_dmem_req_ack 0200 0 2 +core_dmem_req +core_dmem_cmd +core_dmem_width\[1\] +core_dmem_width\[0\] +core_dmem_addr\[31\] +core_dmem_addr\[30\] +core_dmem_addr\[29\] +core_dmem_addr\[28\] +core_dmem_addr\[27\] +core_dmem_addr\[26\] +core_dmem_addr\[25\] +core_dmem_addr\[24\] +core_dmem_addr\[23\] +core_dmem_addr\[22\] +core_dmem_addr\[21\] +core_dmem_addr\[20\] +core_dmem_addr\[19\] +core_dmem_addr\[18\] +core_dmem_addr\[17\] +core_dmem_addr\[16\] +core_dmem_addr\[15\] +core_dmem_addr\[14\] +core_dmem_addr\[13\] +core_dmem_addr\[12\] +core_dmem_addr\[11\] +core_dmem_addr\[10\] +core_dmem_addr\[9\] +core_dmem_addr\[8\] +core_dmem_addr\[7\] +core_dmem_addr\[6\] +core_dmem_addr\[5\] +core_dmem_addr\[4\] +core_dmem_addr\[3\] +core_dmem_addr\[2\] +core_dmem_addr\[1\] +core_dmem_addr\[0\] +core_dmem_wdata\[31\] +core_dmem_wdata\[30\] +core_dmem_wdata\[29\] +core_dmem_wdata\[28\] +core_dmem_wdata\[27\] +core_dmem_wdata\[26\] +core_dmem_wdata\[25\] +core_dmem_wdata\[24\] +core_dmem_wdata\[23\] +core_dmem_wdata\[22\] +core_dmem_wdata\[21\] +core_dmem_wdata\[20\] +core_dmem_wdata\[19\] +core_dmem_wdata\[18\] +core_dmem_wdata\[17\] +core_dmem_wdata\[16\] +core_dmem_wdata\[15\] +core_dmem_wdata\[14\] +core_dmem_wdata\[13\] +core_dmem_wdata\[12\] +core_dmem_wdata\[11\] +core_dmem_wdata\[10\] +core_dmem_wdata\[9\] +core_dmem_wdata\[8\] +core_dmem_wdata\[7\] +core_dmem_wdata\[6\] +core_dmem_wdata\[5\] +core_dmem_wdata\[4\] +core_dmem_wdata\[3\] +core_dmem_wdata\[2\] +core_dmem_wdata\[1\] +core_dmem_wdata\[0\] +core_dmem_rdata\[31\] +core_dmem_rdata\[30\] +core_dmem_rdata\[29\] +core_dmem_rdata\[28\] +core_dmem_rdata\[27\] +core_dmem_rdata\[26\] +core_dmem_rdata\[25\] +core_dmem_rdata\[24\] +core_dmem_rdata\[23\] +core_dmem_rdata\[22\] +core_dmem_rdata\[21\] +core_dmem_rdata\[20\] +core_dmem_rdata\[19\] +core_dmem_rdata\[18\] +core_dmem_rdata\[17\] +core_dmem_rdata\[16\] +core_dmem_rdata\[15\] +core_dmem_rdata\[14\] +core_dmem_rdata\[13\] +core_dmem_rdata\[12\] +core_dmem_rdata\[11\] +core_dmem_rdata\[10\] +core_dmem_rdata\[9\] +core_dmem_rdata\[8\] +core_dmem_rdata\[7\] +core_dmem_rdata\[6\] +core_dmem_rdata\[5\] +core_dmem_rdata\[4\] +core_dmem_rdata\[3\] +core_dmem_rdata\[2\] +core_dmem_rdata\[1\] +core_dmem_rdata\[0\] +core_dmem_resp\[1\] +core_dmem_resp\[0\] + +cfg_dcache_force_flush + +#S +icache_mem_clk0 +icache_mem_csb0 +icache_mem_web0 +icache_mem_addr0\[0\] +icache_mem_addr0\[1\] +icache_mem_addr0\[2\] +icache_mem_addr0\[3\] +icache_mem_addr0\[4\] +icache_mem_addr0\[5\] +icache_mem_addr0\[6\] +icache_mem_addr0\[7\] +icache_mem_addr0\[8\] +icache_mem_wmask0\[0\] +icache_mem_wmask0\[1\] +icache_mem_wmask0\[2\] +icache_mem_wmask0\[3\] +icache_mem_din0\[0\] +icache_mem_din0\[1\] +icache_mem_din0\[2\] +icache_mem_din0\[3\] +icache_mem_din0\[4\] +icache_mem_din0\[5\] +icache_mem_din0\[6\] +icache_mem_din0\[7\] +icache_mem_din0\[8\] +icache_mem_din0\[9\] +icache_mem_din0\[10\] +icache_mem_din0\[11\] +icache_mem_din0\[12\] +icache_mem_din0\[13\] +icache_mem_din0\[14\] +icache_mem_din0\[15\] +icache_mem_din0\[16\] +icache_mem_din0\[17\] +icache_mem_din0\[18\] +icache_mem_din0\[19\] +icache_mem_din0\[20\] +icache_mem_din0\[21\] +icache_mem_din0\[22\] +icache_mem_din0\[23\] +icache_mem_din0\[24\] +icache_mem_din0\[25\] +icache_mem_din0\[26\] +icache_mem_din0\[27\] +icache_mem_din0\[28\] +icache_mem_din0\[29\] +icache_mem_din0\[30\] +icache_mem_din0\[31\] + +icache_mem_clk1 100 0 2 +icache_mem_csb1 +icache_mem_addr1\[8\] +icache_mem_addr1\[7\] +icache_mem_addr1\[6\] +icache_mem_addr1\[5\] +icache_mem_addr1\[4\] +icache_mem_addr1\[3\] +icache_mem_addr1\[2\] +icache_mem_addr1\[1\] +icache_mem_addr1\[0\] + +icache_mem_dout1\[0\] 150 0 2 +icache_mem_dout1\[1\] +icache_mem_dout1\[2\] +icache_mem_dout1\[3\] +icache_mem_dout1\[4\] +icache_mem_dout1\[5\] +icache_mem_dout1\[6\] +icache_mem_dout1\[7\] +icache_mem_dout1\[8\] +icache_mem_dout1\[9\] +icache_mem_dout1\[10\] +icache_mem_dout1\[11\] +icache_mem_dout1\[12\] +icache_mem_dout1\[13\] +icache_mem_dout1\[14\] +icache_mem_dout1\[15\] +icache_mem_dout1\[16\] +icache_mem_dout1\[17\] +icache_mem_dout1\[18\] +icache_mem_dout1\[19\] +icache_mem_dout1\[20\] +icache_mem_dout1\[21\] +icache_mem_dout1\[22\] +icache_mem_dout1\[23\] +icache_mem_dout1\[24\] +icache_mem_dout1\[25\] +icache_mem_dout1\[26\] +icache_mem_dout1\[27\] +icache_mem_dout1\[28\] +icache_mem_dout1\[29\] +icache_mem_dout1\[30\] +icache_mem_dout1\[31\] + +wb_rst_n 500 0 +pwrup_rst_n +core_clk +cpu_intf_rst_n + +#W +dcache_mem_clk0 000 0 2 +dcache_mem_csb0 +dcache_mem_web0 +dcache_mem_addr0\[0\] +dcache_mem_addr0\[1\] +dcache_mem_addr0\[2\] +dcache_mem_addr0\[3\] +dcache_mem_addr0\[4\] +dcache_mem_addr0\[5\] +dcache_mem_addr0\[6\] +dcache_mem_addr0\[7\] +dcache_mem_addr0\[8\] +dcache_mem_wmask0\[0\] +dcache_mem_wmask0\[1\] +dcache_mem_wmask0\[2\] +dcache_mem_wmask0\[3\] +dcache_mem_din0\[0\] +dcache_mem_din0\[1\] +dcache_mem_din0\[2\] +dcache_mem_din0\[3\] +dcache_mem_din0\[4\] +dcache_mem_din0\[5\] +dcache_mem_din0\[6\] +dcache_mem_din0\[7\] +dcache_mem_din0\[8\] +dcache_mem_din0\[9\] +dcache_mem_din0\[10\] +dcache_mem_din0\[11\] +dcache_mem_din0\[12\] +dcache_mem_din0\[13\] +dcache_mem_din0\[14\] +dcache_mem_din0\[15\] +dcache_mem_din0\[16\] +dcache_mem_din0\[17\] +dcache_mem_din0\[18\] +dcache_mem_din0\[19\] +dcache_mem_din0\[20\] +dcache_mem_din0\[21\] +dcache_mem_din0\[22\] +dcache_mem_din0\[23\] +dcache_mem_din0\[24\] +dcache_mem_din0\[25\] +dcache_mem_din0\[26\] +dcache_mem_din0\[27\] +dcache_mem_din0\[28\] +dcache_mem_din0\[29\] +dcache_mem_din0\[30\] +dcache_mem_din0\[31\] + + +dcache_mem_dout0\[0\] 100 0 2 +dcache_mem_dout0\[1\] +dcache_mem_dout0\[2\] +dcache_mem_dout0\[3\] +dcache_mem_dout0\[4\] +dcache_mem_dout0\[5\] +dcache_mem_dout0\[6\] +dcache_mem_dout0\[7\] +dcache_mem_dout0\[8\] +dcache_mem_dout0\[9\] +dcache_mem_dout0\[10\] +dcache_mem_dout0\[11\] +dcache_mem_dout0\[12\] +dcache_mem_dout0\[13\] +dcache_mem_dout0\[14\] +dcache_mem_dout0\[15\] +dcache_mem_dout0\[16\] +dcache_mem_dout0\[17\] +dcache_mem_dout0\[18\] +dcache_mem_dout0\[19\] +dcache_mem_dout0\[20\] +dcache_mem_dout0\[21\] +dcache_mem_dout0\[22\] +dcache_mem_dout0\[23\] +dcache_mem_dout0\[24\] +dcache_mem_dout0\[25\] +dcache_mem_dout0\[26\] +dcache_mem_dout0\[27\] +dcache_mem_dout0\[28\] +dcache_mem_dout0\[29\] +dcache_mem_dout0\[30\] +dcache_mem_dout0\[31\] + +dcache_mem_clk1 200 0 2 +dcache_mem_csb1 +dcache_mem_addr1\[8\] +dcache_mem_addr1\[7\] +dcache_mem_addr1\[6\] +dcache_mem_addr1\[5\] +dcache_mem_addr1\[4\] +dcache_mem_addr1\[3\] +dcache_mem_addr1\[2\] +dcache_mem_addr1\[1\] +dcache_mem_addr1\[0\] + +dcache_mem_dout1\[0\] 250 0 2 +dcache_mem_dout1\[1\] +dcache_mem_dout1\[2\] +dcache_mem_dout1\[3\] +dcache_mem_dout1\[4\] +dcache_mem_dout1\[5\] +dcache_mem_dout1\[6\] +dcache_mem_dout1\[7\] +dcache_mem_dout1\[8\] +dcache_mem_dout1\[9\] +dcache_mem_dout1\[10\] +dcache_mem_dout1\[11\] +dcache_mem_dout1\[12\] +dcache_mem_dout1\[13\] +dcache_mem_dout1\[14\] +dcache_mem_dout1\[15\] +dcache_mem_dout1\[16\] +dcache_mem_dout1\[17\] +dcache_mem_dout1\[18\] +dcache_mem_dout1\[19\] +dcache_mem_dout1\[20\] +dcache_mem_dout1\[21\] +dcache_mem_dout1\[22\] +dcache_mem_dout1\[23\] +dcache_mem_dout1\[24\] +dcache_mem_dout1\[25\] +dcache_mem_dout1\[26\] +dcache_mem_dout1\[27\] +dcache_mem_dout1\[28\] +dcache_mem_dout1\[29\] +dcache_mem_dout1\[30\] +dcache_mem_dout1\[31\] + + + + + +#E +cfg_cska_riscv\[3\] 0000 0 2 +cfg_cska_riscv\[2\] +cfg_cska_riscv\[1\] +cfg_cska_riscv\[0\] +wbd_clk_int +wbd_clk_riscv +wb_clk + +wbd_dmem_stb_o 0100 0 2 +wbd_dmem_we_o +wbd_dmem_adr_o\[31\] +wbd_dmem_adr_o\[30\] +wbd_dmem_adr_o\[29\] +wbd_dmem_adr_o\[28\] +wbd_dmem_adr_o\[27\] +wbd_dmem_adr_o\[26\] +wbd_dmem_adr_o\[25\] +wbd_dmem_adr_o\[24\] +wbd_dmem_adr_o\[23\] +wbd_dmem_adr_o\[22\] +wbd_dmem_adr_o\[21\] +wbd_dmem_adr_o\[20\] +wbd_dmem_adr_o\[19\] +wbd_dmem_adr_o\[18\] +wbd_dmem_adr_o\[17\] +wbd_dmem_adr_o\[16\] +wbd_dmem_adr_o\[15\] +wbd_dmem_adr_o\[14\] +wbd_dmem_adr_o\[13\] +wbd_dmem_adr_o\[12\] +wbd_dmem_adr_o\[11\] +wbd_dmem_adr_o\[10\] +wbd_dmem_adr_o\[9\] +wbd_dmem_adr_o\[8\] +wbd_dmem_adr_o\[7\] +wbd_dmem_adr_o\[6\] +wbd_dmem_adr_o\[5\] +wbd_dmem_adr_o\[4\] +wbd_dmem_adr_o\[3\] +wbd_dmem_adr_o\[2\] +wbd_dmem_adr_o\[1\] +wbd_dmem_adr_o\[0\] +wbd_dmem_sel_o\[3\] +wbd_dmem_sel_o\[2\] +wbd_dmem_sel_o\[1\] +wbd_dmem_sel_o\[0\] +wbd_dmem_dat_o\[31\] +wbd_dmem_dat_o\[30\] +wbd_dmem_dat_o\[29\] +wbd_dmem_dat_o\[28\] +wbd_dmem_dat_o\[27\] +wbd_dmem_dat_o\[26\] +wbd_dmem_dat_o\[25\] +wbd_dmem_dat_o\[24\] +wbd_dmem_dat_o\[23\] +wbd_dmem_dat_o\[22\] +wbd_dmem_dat_o\[21\] +wbd_dmem_dat_o\[20\] +wbd_dmem_dat_o\[19\] +wbd_dmem_dat_o\[18\] +wbd_dmem_dat_o\[17\] +wbd_dmem_dat_o\[16\] +wbd_dmem_dat_o\[15\] +wbd_dmem_dat_o\[14\] +wbd_dmem_dat_o\[13\] +wbd_dmem_dat_o\[12\] +wbd_dmem_dat_o\[11\] +wbd_dmem_dat_o\[10\] +wbd_dmem_dat_o\[9\] +wbd_dmem_dat_o\[8\] +wbd_dmem_dat_o\[7\] +wbd_dmem_dat_o\[6\] +wbd_dmem_dat_o\[5\] +wbd_dmem_dat_o\[4\] +wbd_dmem_dat_o\[3\] +wbd_dmem_dat_o\[2\] +wbd_dmem_dat_o\[1\] +wbd_dmem_dat_o\[0\] +wbd_dmem_dat_i\[31\] +wbd_dmem_dat_i\[30\] +wbd_dmem_dat_i\[29\] +wbd_dmem_dat_i\[28\] +wbd_dmem_dat_i\[27\] +wbd_dmem_dat_i\[26\] +wbd_dmem_dat_i\[25\] +wbd_dmem_dat_i\[24\] +wbd_dmem_dat_i\[23\] +wbd_dmem_dat_i\[22\] +wbd_dmem_dat_i\[21\] +wbd_dmem_dat_i\[20\] +wbd_dmem_dat_i\[19\] +wbd_dmem_dat_i\[18\] +wbd_dmem_dat_i\[17\] +wbd_dmem_dat_i\[16\] +wbd_dmem_dat_i\[15\] +wbd_dmem_dat_i\[14\] +wbd_dmem_dat_i\[13\] +wbd_dmem_dat_i\[12\] +wbd_dmem_dat_i\[11\] +wbd_dmem_dat_i\[10\] +wbd_dmem_dat_i\[9\] +wbd_dmem_dat_i\[8\] +wbd_dmem_dat_i\[7\] +wbd_dmem_dat_i\[6\] +wbd_dmem_dat_i\[5\] +wbd_dmem_dat_i\[4\] +wbd_dmem_dat_i\[3\] +wbd_dmem_dat_i\[2\] +wbd_dmem_dat_i\[1\] +wbd_dmem_dat_i\[0\] +wbd_dmem_ack_i +wbd_dmem_err_i + +wb_dcache_stb_o 0300 0 2 +wb_dcache_we_o +wb_dcache_adr_o\[31\] +wb_dcache_adr_o\[30\] +wb_dcache_adr_o\[29\] +wb_dcache_adr_o\[28\] +wb_dcache_adr_o\[27\] +wb_dcache_adr_o\[26\] +wb_dcache_adr_o\[25\] +wb_dcache_adr_o\[24\] +wb_dcache_adr_o\[23\] +wb_dcache_adr_o\[22\] +wb_dcache_adr_o\[21\] +wb_dcache_adr_o\[20\] +wb_dcache_adr_o\[19\] +wb_dcache_adr_o\[18\] +wb_dcache_adr_o\[17\] +wb_dcache_adr_o\[16\] +wb_dcache_adr_o\[15\] +wb_dcache_adr_o\[14\] +wb_dcache_adr_o\[13\] +wb_dcache_adr_o\[12\] +wb_dcache_adr_o\[11\] +wb_dcache_adr_o\[10\] +wb_dcache_adr_o\[9\] +wb_dcache_adr_o\[8\] +wb_dcache_adr_o\[7\] +wb_dcache_adr_o\[6\] +wb_dcache_adr_o\[5\] +wb_dcache_adr_o\[4\] +wb_dcache_adr_o\[3\] +wb_dcache_adr_o\[2\] +wb_dcache_adr_o\[1\] +wb_dcache_adr_o\[0\] +wb_dcache_sel_o\[3\] +wb_dcache_sel_o\[2\] +wb_dcache_sel_o\[1\] +wb_dcache_sel_o\[0\] +wb_dcache_bl_o\[9\] +wb_dcache_bl_o\[8\] +wb_dcache_bl_o\[7\] +wb_dcache_bl_o\[6\] +wb_dcache_bl_o\[5\] +wb_dcache_bl_o\[4\] +wb_dcache_bl_o\[3\] +wb_dcache_bl_o\[2\] +wb_dcache_bl_o\[1\] +wb_dcache_bl_o\[0\] +wb_dcache_bry_o +wb_dcache_dat_o\[31\] +wb_dcache_dat_o\[30\] +wb_dcache_dat_o\[29\] +wb_dcache_dat_o\[28\] +wb_dcache_dat_o\[27\] +wb_dcache_dat_o\[26\] +wb_dcache_dat_o\[25\] +wb_dcache_dat_o\[24\] +wb_dcache_dat_o\[23\] +wb_dcache_dat_o\[22\] +wb_dcache_dat_o\[21\] +wb_dcache_dat_o\[20\] +wb_dcache_dat_o\[19\] +wb_dcache_dat_o\[18\] +wb_dcache_dat_o\[17\] +wb_dcache_dat_o\[16\] +wb_dcache_dat_o\[15\] +wb_dcache_dat_o\[14\] +wb_dcache_dat_o\[13\] +wb_dcache_dat_o\[12\] +wb_dcache_dat_o\[11\] +wb_dcache_dat_o\[10\] +wb_dcache_dat_o\[9\] +wb_dcache_dat_o\[8\] +wb_dcache_dat_o\[7\] +wb_dcache_dat_o\[6\] +wb_dcache_dat_o\[5\] +wb_dcache_dat_o\[4\] +wb_dcache_dat_o\[3\] +wb_dcache_dat_o\[2\] +wb_dcache_dat_o\[1\] +wb_dcache_dat_o\[0\] +wb_dcache_dat_i\[31\] +wb_dcache_dat_i\[30\] +wb_dcache_dat_i\[29\] +wb_dcache_dat_i\[28\] +wb_dcache_dat_i\[27\] +wb_dcache_dat_i\[26\] +wb_dcache_dat_i\[25\] +wb_dcache_dat_i\[24\] +wb_dcache_dat_i\[23\] +wb_dcache_dat_i\[22\] +wb_dcache_dat_i\[21\] +wb_dcache_dat_i\[20\] +wb_dcache_dat_i\[19\] +wb_dcache_dat_i\[18\] +wb_dcache_dat_i\[17\] +wb_dcache_dat_i\[16\] +wb_dcache_dat_i\[15\] +wb_dcache_dat_i\[14\] +wb_dcache_dat_i\[13\] +wb_dcache_dat_i\[12\] +wb_dcache_dat_i\[11\] +wb_dcache_dat_i\[10\] +wb_dcache_dat_i\[9\] +wb_dcache_dat_i\[8\] +wb_dcache_dat_i\[7\] +wb_dcache_dat_i\[6\] +wb_dcache_dat_i\[5\] +wb_dcache_dat_i\[4\] +wb_dcache_dat_i\[3\] +wb_dcache_dat_i\[2\] +wb_dcache_dat_i\[1\] +wb_dcache_dat_i\[0\] +wb_dcache_ack_i +wb_dcache_lack_i +wb_dcache_err_i +wb_dcache_cyc_o + +wb_icache_stb_o 500 0 2 +wb_icache_we_o +wb_icache_adr_o\[31\] +wb_icache_adr_o\[30\] +wb_icache_adr_o\[29\] +wb_icache_adr_o\[28\] +wb_icache_adr_o\[27\] +wb_icache_adr_o\[26\] +wb_icache_adr_o\[25\] +wb_icache_adr_o\[24\] +wb_icache_adr_o\[23\] +wb_icache_adr_o\[22\] +wb_icache_adr_o\[21\] +wb_icache_adr_o\[20\] +wb_icache_adr_o\[19\] +wb_icache_adr_o\[18\] +wb_icache_adr_o\[17\] +wb_icache_adr_o\[16\] +wb_icache_adr_o\[15\] +wb_icache_adr_o\[14\] +wb_icache_adr_o\[13\] +wb_icache_adr_o\[12\] +wb_icache_adr_o\[11\] +wb_icache_adr_o\[10\] +wb_icache_adr_o\[9\] +wb_icache_adr_o\[8\] +wb_icache_adr_o\[7\] +wb_icache_adr_o\[6\] +wb_icache_adr_o\[5\] +wb_icache_adr_o\[4\] +wb_icache_adr_o\[3\] +wb_icache_adr_o\[2\] +wb_icache_adr_o\[1\] +wb_icache_adr_o\[0\] +wb_icache_sel_o\[3\] +wb_icache_sel_o\[2\] +wb_icache_sel_o\[1\] +wb_icache_sel_o\[0\] +wb_icache_bl_o\[9\] +wb_icache_bl_o\[8\] +wb_icache_bl_o\[7\] +wb_icache_bl_o\[6\] +wb_icache_bl_o\[5\] +wb_icache_bl_o\[4\] +wb_icache_bl_o\[3\] +wb_icache_bl_o\[2\] +wb_icache_bl_o\[1\] +wb_icache_bl_o\[0\] +wb_icache_bry_o +wb_icache_dat_i\[31\] +wb_icache_dat_i\[30\] +wb_icache_dat_i\[29\] +wb_icache_dat_i\[28\] +wb_icache_dat_i\[27\] +wb_icache_dat_i\[26\] +wb_icache_dat_i\[25\] +wb_icache_dat_i\[24\] +wb_icache_dat_i\[23\] +wb_icache_dat_i\[22\] +wb_icache_dat_i\[21\] +wb_icache_dat_i\[20\] +wb_icache_dat_i\[19\] +wb_icache_dat_i\[18\] +wb_icache_dat_i\[17\] +wb_icache_dat_i\[16\] +wb_icache_dat_i\[15\] +wb_icache_dat_i\[14\] +wb_icache_dat_i\[13\] +wb_icache_dat_i\[12\] +wb_icache_dat_i\[11\] +wb_icache_dat_i\[10\] +wb_icache_dat_i\[9\] +wb_icache_dat_i\[8\] +wb_icache_dat_i\[7\] +wb_icache_dat_i\[6\] +wb_icache_dat_i\[5\] +wb_icache_dat_i\[4\] +wb_icache_dat_i\[3\] +wb_icache_dat_i\[2\] +wb_icache_dat_i\[1\] +wb_icache_dat_i\[0\] +wb_icache_ack_i +wb_icache_lack_i +wb_icache_err_i +wb_icache_cyc_o + +cfg_icache_pfet_dis +cfg_icache_ntag_pfet_dis +cfg_dcache_pfet_dis +cfg_sram_lphase\[1\] +cfg_sram_lphase\[0\]
diff --git a/signoff/pinmux/final_summary_report.csv b/signoff/pinmux/final_summary_report.csv index eaac07f..95dfe93 100644 --- a/signoff/pinmux/final_summary_report.csv +++ b/signoff/pinmux/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/pinmux,pinmux,pinmux,flow completed,0h9m45s0ms,0h6m26s0ms,49349.494949494954,0.2475,24674.747474747477,29.39,954.58,6107,0,0,0,0,0,0,0,-1,0,-1,-1,458162,60438,-9.79,-17.09,-1,0.0,0.0,-11322.82,-19478.71,-1,0.0,0.0,363642601.0,0.0,61.71,47.76,26.72,20.99,-1,4043,9507,808,6272,0,0,0,4590,151,83,49,96,1013,154,18,283,1206,1171,12,314,3259,0,3573,100.0,10.0,10,AREA 0,4,50,1,100,100,0.3,0.3,sky130_fd_sc_hd,4,4 +0,/project/openlane/pinmux,pinmux,pinmux,flow completed,0h10m34s0ms,0h7m12s0ms,49462.62626262626,0.2475,24731.31313131313,29.42,907.76,6121,0,0,0,0,0,0,0,-1,0,-1,-1,479668,61682,-9.8,-17.24,-1,0.0,0.0,-11351.48,-19667.29,-1,0.0,0.0,379249279.0,0.0,61.45,48.02,33.52,24.16,-1,4043,9535,808,6300,0,0,0,4590,151,83,49,96,1013,154,18,283,1206,1171,12,314,3259,0,3573,100.0,10.0,10,AREA 0,4,50,1,100,100,0.3,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/qspim_top/final_summary_report.csv b/signoff/qspim_top/final_summary_report.csv index 65d79bc..0dcde5e 100644 --- a/signoff/qspim_top/final_summary_report.csv +++ b/signoff/qspim_top/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/qspim_top,qspim_top,qspim_top,flow completed,0h12m26s0ms,0h9m19s0ms,65696.9696969697,0.2475,32848.48484848485,37.92,1104.07,8130,0,0,0,0,0,0,0,-1,0,-1,-1,419590,71747,-0.55,-5.04,-1,0.0,0.0,-21.45,-1943.78,-1,0.0,0.0,256460720.0,0.0,50.47,49.05,23.05,22.36,-1,7374,11038,803,4466,0,0,0,8348,263,96,195,114,1420,214,34,1460,1553,1517,17,388,3234,0,3622,100.0,10.0,10,AREA 0,4,50,1,100,100,0.42,0.3,sky130_fd_sc_hd,4,4 +0,/project/openlane/qspim_top,qspim_top,qspim_top,flow completed,0h12m35s0ms,0h9m20s0ms,65696.9696969697,0.2475,32848.48484848485,37.92,1042.81,8130,0,0,0,0,0,0,0,-1,0,-1,-1,419590,71747,-0.55,-5.04,-1,0.0,0.0,-21.45,-1943.78,-1,0.0,0.0,256460720.0,0.0,50.47,49.05,23.05,22.36,-1,7374,11038,803,4466,0,0,0,8348,263,96,195,114,1420,214,34,1460,1553,1517,17,388,3234,0,3622,100.0,10.0,10,AREA 0,4,50,1,100,100,0.42,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/uart_i2cm_usb_spi_top/final_summary_report.csv b/signoff/uart_i2cm_usb_spi_top/final_summary_report.csv index 0ddfd92..8f28170 100644 --- a/signoff/uart_i2cm_usb_spi_top/final_summary_report.csv +++ b/signoff/uart_i2cm_usb_spi_top/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/uart_i2cm_usb_spi_top,uart_i2c_usb_spi_top,uart_i2cm_usb_spi_top,flow completed,0h30m53s0ms,0h23m11s0ms,69285.71428571429,0.35,34642.857142857145,39.21,1367.28,12125,0,0,0,0,0,0,0,-1,0,-1,-1,594439,103896,0.0,0.0,0.0,0.0,-0.02,0.0,0.0,0.0,0.0,-0.02,369917177.0,0.0,51.11,51.47,19.26,22.98,-1,8702,13067,1552,5853,0,0,0,9824,392,189,256,272,2200,354,88,807,2409,2348,18,498,4643,0,5141,99.8003992015968,10.02,10,AREA 0,4,50,1,100,100,0.45,0.3,sky130_fd_sc_hd,4,4 +0,/project/openlane/uart_i2cm_usb_spi_top,uart_i2c_usb_spi_top,uart_i2cm_usb_spi_top,flow completed,0h21m20s0ms,0h16m25s0ms,69285.71428571429,0.35,34642.857142857145,39.21,1388.79,12125,0,0,0,0,0,0,0,-1,0,-1,-1,594439,103896,0.0,0.0,0.0,0.0,-0.02,0.0,0.0,0.0,0.0,-0.02,369917177.0,0.0,51.11,51.47,19.26,22.98,-1,8702,13067,1552,5853,0,0,0,9824,392,189,256,272,2200,354,88,807,2409,2348,18,498,4643,0,5141,99.8003992015968,10.02,10,AREA 0,4,50,1,100,100,0.45,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv index 9cd6bea..8112563 100644 --- a/signoff/user_project_wrapper/final_summary_report.csv +++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,0h48m45s0ms,0h5m14s0ms,-2.0,-1,-1,-1,602.58,11,0,0,0,0,0,0,-1,0,0,-1,-1,2385046,17217,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,8.06,11.83,2.96,3.32,0.0,317,3274,317,3274,0,0,0,11,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,100,0.55,0.3,sky130_fd_sc_hd,4,0 +0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,0h48m17s0ms,0h3m48s0ms,-2.0,-1,-1,-1,569.73,12,0,0,0,0,0,0,-1,0,0,-1,-1,1426146,10402,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,5.6,6.54,1.16,1.88,0.0,349,3680,349,3680,0,0,0,12,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,90,0.55,0.3,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv index 898c873..e4f03bb 100644 --- a/signoff/wb_host/final_summary_report.csv +++ b/signoff/wb_host/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/wb_host,wb_host,wb_host,flow completed,0h5m10s0ms,0h3m26s0ms,61700.84033613445,0.14875,30850.420168067227,37.22,773.21,4589,0,0,0,0,0,0,0,11,0,0,-1,205225,36945,0.0,-0.19,0.0,0.0,0.0,0.0,-23.16,0.0,0.0,0.0,155719018.0,0.0,46.7,45.31,3.63,15.99,-1,3577,6294,1049,3622,0,0,0,3856,373,52,77,183,651,146,23,461,1023,1001,12,296,1950,0,2246,100.0,10.0,10,AREA 0,4,50,1,100,100,0.38,0.3,sky130_fd_sc_hd,4,4 +0,/project/openlane/wb_host,wb_host,wb_host,flow completed,0h5m29s0ms,0h3m38s0ms,61700.84033613445,0.14875,30850.420168067227,37.22,774.82,4589,0,0,0,0,0,0,0,11,0,0,-1,205225,36945,0.0,-0.19,0.0,0.0,0.0,0.0,-23.16,0.0,0.0,0.0,155719018.0,0.0,46.7,45.31,3.63,15.99,-1,3577,6294,1049,3622,0,0,0,3856,373,52,77,183,651,146,23,461,1023,1001,12,296,1950,0,2246,100.0,10.0,10,AREA 0,4,50,1,100,100,0.38,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/wb_interconnect/final_summary_report.csv b/signoff/wb_interconnect/final_summary_report.csv index 0106066..3be20a9 100644 --- a/signoff/wb_interconnect/final_summary_report.csv +++ b/signoff/wb_interconnect/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow completed,0h39m31s0ms,0h29m40s0ms,37826.38888888888,0.5760000000000001,18913.19444444444,16.95,1333.09,10894,0,0,0,0,0,0,0,-1,0,-1,-1,1010027,91907,-1.53,-3.35,-1,-3.07,-3.34,-106.67,-240.35,-1,-319.27,-324.23,794830726.0,0.0,23.63,45.8,2.76,26.56,-1,3846,12864,637,9652,0,0,0,5341,269,12,304,131,626,98,13,1402,1753,1688,16,1306,7532,0,8838,74.96251874062969,13.34,10,AREA 0,2,50,1,153.6,153.18,0.2,0,sky130_fd_sc_hd,10,4 +0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow completed,0h19m48s0ms,0h14m39s0ms,40348.14814814815,0.54,20174.074074074077,18.13,1318.06,10894,0,0,0,0,0,0,0,-1,0,-1,-1,949047,90644,-1.53,-2.29,-1,-2.25,-2.33,-106.67,-188.2,-1,-259.9,-259.66,793691221.0,0.0,20.02,51.61,1.99,21.92,-1,3846,12864,637,9652,0,0,0,5341,269,12,304,131,626,98,13,1402,1753,1688,16,1306,7205,0,8511,81.10300081103001,12.33,10,AREA 0,2,50,1,153.6,153.18,0.2,0,sky130_fd_sc_hd,8,4
diff --git a/signoff/ycr2_iconnect/OPENLANE_VERSION b/signoff/ycr2_iconnect/OPENLANE_VERSION new file mode 100644 index 0000000..80c7664 --- /dev/null +++ b/signoff/ycr2_iconnect/OPENLANE_VERSION
@@ -0,0 +1 @@ +openlane N/A
diff --git a/signoff/ycr2_iconnect/PDK_SOURCES b/signoff/ycr2_iconnect/PDK_SOURCES new file mode 100644 index 0000000..22e7dc1 --- /dev/null +++ b/signoff/ycr2_iconnect/PDK_SOURCES
@@ -0,0 +1,3 @@ +openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f +skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb +open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
diff --git a/signoff/ycr2_iconnect/final_summary_report.csv b/signoff/ycr2_iconnect/final_summary_report.csv new file mode 100644 index 0000000..73e1d26 --- /dev/null +++ b/signoff/ycr2_iconnect/final_summary_report.csv
@@ -0,0 +1,2 @@ +,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY +0,/project/openlane/ycr2_iconnect,ycr2_iconnect,ycr2_iconnect,flow completed,0h16m4s0ms,0h12m33s0ms,24394.736842105263,0.38,12197.368421052632,11.41,1190.28,4635,0,0,0,0,0,0,0,124,0,0,-1,707492,57833,0.0,-0.82,-1,0.0,0.0,0.0,-34.39,-1,0.0,0.0,532306334.0,0.0,39.01,55.4,18.98,40.67,-1,4809,10170,596,5894,0,0,0,5214,457,45,221,65,788,146,6,1661,783,796,18,718,5054,0,5772,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.2,0.3,sky130_fd_sc_hd,14,3
diff --git a/signoff/ycr_core_top/OPENLANE_VERSION b/signoff/ycr_core_top/OPENLANE_VERSION new file mode 100644 index 0000000..80c7664 --- /dev/null +++ b/signoff/ycr_core_top/OPENLANE_VERSION
@@ -0,0 +1 @@ +openlane N/A
diff --git a/signoff/ycr_core_top/PDK_SOURCES b/signoff/ycr_core_top/PDK_SOURCES new file mode 100644 index 0000000..22e7dc1 --- /dev/null +++ b/signoff/ycr_core_top/PDK_SOURCES
@@ -0,0 +1,3 @@ +openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f +skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb +open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
diff --git a/signoff/ycr_core_top/final_summary_report.csv b/signoff/ycr_core_top/final_summary_report.csv new file mode 100644 index 0000000..34d92ad --- /dev/null +++ b/signoff/ycr_core_top/final_summary_report.csv
@@ -0,0 +1,2 @@ +,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY +0,/project/openlane/ycr_core_top,ycr_core_top,ycr_core_top,flow completed,1h11m5s0ms,1h3m1s0ms,72524.7175141243,0.5664,36262.35875706215,36.42,2339.02,20539,0,0,0,0,0,0,0,149,0,0,-1,1331865,186774,0.0,-9.52,-1,0.0,0.0,0.0,-9015.79,-1,0.0,0.0,1033053596.0,0.0,51.08,69.94,24.69,50.9,-1,16396,22729,542,6775,0,0,0,19178,557,261,518,596,2917,897,259,4835,2528,2435,37,688,7612,0,8300,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.37,0.3,sky130_fd_sc_hd,6,3
diff --git a/signoff/ycr_intf/OPENLANE_VERSION b/signoff/ycr_intf/OPENLANE_VERSION new file mode 100644 index 0000000..80c7664 --- /dev/null +++ b/signoff/ycr_intf/OPENLANE_VERSION
@@ -0,0 +1 @@ +openlane N/A
diff --git a/signoff/ycr_intf/PDK_SOURCES b/signoff/ycr_intf/PDK_SOURCES new file mode 100644 index 0000000..22e7dc1 --- /dev/null +++ b/signoff/ycr_intf/PDK_SOURCES
@@ -0,0 +1,3 @@ +openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f +skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb +open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
diff --git a/signoff/ycr_intf/final_summary_report.csv b/signoff/ycr_intf/final_summary_report.csv new file mode 100644 index 0000000..555e682 --- /dev/null +++ b/signoff/ycr_intf/final_summary_report.csv
@@ -0,0 +1,2 @@ +,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY +0,/project/openlane/ycr_intf,ycr_intf,ycr_intf,flow completed,0h57m41s0ms,0h46m38s0ms,61454.47530864197,0.5184,30727.237654320987,34.83,2305.55,15929,0,0,0,0,0,0,0,112,0,0,-1,1063374,143989,-18.78,-32.57,-1,0.0,0.0,-14588.49,-36722.34,-1,0.0,0.0,842676749.0,0.0,54.83,48.23,29.76,25.87,-1,8905,18021,965,9748,0,0,0,11577,578,105,288,275,1939,889,376,1696,3103,2999,24,454,6984,0,7438,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.37,0.3,sky130_fd_sc_hd,6,3
diff --git a/verilog/dv/agents/uart_agent.v b/verilog/dv/agents/uart_agent.v index 72121e9..9d647c8 100644 --- a/verilog/dv/agents/uart_agent.v +++ b/verilog/dv/agents/uart_agent.v
@@ -14,6 +14,10 @@ // limitations under the License. // SPDX-License-Identifier: Apache-2.0 // SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> +// + +`timescale 1ns/1ps + module uart_agent ( mclk, txd,
diff --git a/verilog/dv/model/is62wvs1288.v b/verilog/dv/model/is62wvs1288.v index c938977..37bf718 100644 --- a/verilog/dv/model/is62wvs1288.v +++ b/verilog/dv/model/is62wvs1288.v
@@ -43,7 +43,8 @@ // module is62wvs1288 #( - parameter mem_file_name = "firmware.hex" + //parameter mem_file_name = "firmware.hex" + parameter mem_file_name = "none" )( input csb, input clk,
diff --git a/verilog/dv/risc_boot/Makefile b/verilog/dv/risc_boot/Makefile index 8df6ef7..4422d7d 100644 --- a/verilog/dv/risc_boot/Makefile +++ b/verilog/dv/risc_boot/Makefile
@@ -21,6 +21,7 @@ # ---- Include Partitioned Makefiles ---- +DESIGNS?=../../.. CONFIG = caravel_user_project ######################################################## @@ -51,7 +52,7 @@ export TOOLS ?= /opt/riscv64i export GCC_PATH ?= $(TOOLS)/bin -export GCC_PREFIX?= riscv32-unknown-linux-gnu +export GCC_PREFIX?= riscv64-unknown-linux-gnu ############## USER SPECIFIC DEFINE ################## @@ -126,7 +127,7 @@ # Comiple firmeware ############################################################################## %.elf: %.c $(LINKER_SCRIPT) $(SOURCE_FILES) - ${GCC_PATH}/${GCC_PREFIX}-gcc -g \ + ${GCC_PREFIX}-gcc -g \ -I$(FIRMWARE_PATH) \ -I$(VERILOG_PATH)/dv/generated \ -I$(VERILOG_PATH)/dv/ \ @@ -136,15 +137,15 @@ -ffreestanding -nostdlib -o $@ $(SOURCE_FILES) $< %.lst: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objdump -d -S $< > $@ + ${GCC_PREFIX}-objdump -d -S $< > $@ %.hex: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ + ${GCC_PREFIX}-objcopy -O verilog $< $@ # to fix flash base address sed -ie 's/@10/@00/g' $@ %.bin: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ + ${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ ############################################################################## @@ -152,11 +153,11 @@ ############################################################################## %.vvp: %_tb.v %.hex - ${GCC_PATH}/${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_uart.c -o user_uart.o - ${GCC_PATH}/${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o - ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -T $(YIFIVE_FIRMWARE_PATH)/link.ld user_uart.o crt.o -nostartfiles -nostdlib -lc -lgcc -o user_uart.elf -N - ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog user_uart.elf user_uart.hex - ${GCC_PATH}/${GCC_PREFIX}-objdump -D user_uart.elf > user_uart.dump + ${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_uart.c -o user_uart.o + ${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o + ${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -T $(YIFIVE_FIRMWARE_PATH)/link.ld user_uart.o crt.o -nostartfiles -nostdlib -lc -lgcc -o user_uart.elf -N + ${GCC_PREFIX}-objcopy -O verilog user_uart.elf user_uart.hex + ${GCC_PREFIX}-objdump -D user_uart.elf > user_uart.dump rm crt.o user_uart.o ## RTL @@ -215,8 +216,8 @@ ifeq (,$(wildcard $(PDK_ROOT)/sky130A)) $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make) endif -ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc )) - $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make) +ifeq (,$(wildcard $(GCC_PREFIX)-gcc )) + $(error $(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make) endif # check for efabless style installation ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
diff --git a/verilog/dv/risc_boot/risc_boot.c b/verilog/dv/risc_boot/risc_boot.c index bc41e1b..7de5444 100644 --- a/verilog/dv/risc_boot/risc_boot.c +++ b/verilog/dv/risc_boot/risc_boot.c
@@ -98,7 +98,7 @@ reg_mprj_xfer = 1; while (reg_mprj_xfer == 1); - reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64] + reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF; // [31:0] // Flag start of the test reg_mprj_datal = 0xAB600000;
diff --git a/verilog/dv/riscv_regress/Makefile b/verilog/dv/riscv_regress/Makefile index 2c853fa..f2e318f 100644 --- a/verilog/dv/riscv_regress/Makefile +++ b/verilog/dv/riscv_regress/Makefile
@@ -1,10 +1,32 @@ -#------------------------------------------------------------------------------ -# Makefile for SCR1 -#------------------------------------------------------------------------------ -SIM ?= RTL -DUMP ?= OFF -RISC_CORE ?=0 +# ---- Include Partitioned Makefiles ---- + +CONFIG = caravel_user_project + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### + +export root_dir := $(shell pwd) +export bld_dir := $(root_dir)/build/$(current_goal)_$(BUS)_$(CFG)_$(ARCH)_IPIC_$(IPIC)_TCM_$(TCM)_VIRQ_$(VECT_IRQ)_TRACE_$(TRACE) +DESIGNS?=${root_dir}/../../.. + +UPRJ_TESTS_PATH = $(root_dir) + +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog +## YIFIVE FIRMWARE +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware +GCC64_PREFIX?=riscv64-unknown-elf + + +## Simulation mode: RTL/GL +SIM?=RTL +DUMP?=OFF +RISC_CORE?=0 + +### To Enable IVERILOG FST DUMP +export IVERILOG_DUMPER = fst + # PARAMETERS @@ -118,38 +140,16 @@ endif -export root_dir := $(shell pwd) -export bld_dir := $(root_dir)/build/$(current_goal)_$(BUS)_$(CFG)_$(ARCH)_IPIC_$(IPIC)_TCM_$(TCM)_VIRQ_$(VECT_IRQ)_TRACE_$(TRACE) - -## Caravel Pointers related to build directory -CARAVEL_ROOT ?= $(root_dir)/../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel - ## User Project Pointers -UPRJ_VERILOG_PATH ?= $(root_dir)/../../../verilog -UPRJ_TESTS_PATH = $(root_dir) -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl -UPRJ_BEHAVIOURAL_MODELS = $(root_dir)/../model -UPRJ_BEHAVIOURAL_AGENTS = $(root_dir)/../agents -UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes -UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs -UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes -UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes -UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include -sv_list = ../../user_risc_regress_tb.v +sv_list = $(root_dir)/user_risc_regress_tb.v top_module = user_risc_regress_tb # TB Paths -export sim_dir := $(UPRJ_TESTS_PATH) +export sim_dir := $(root_dir) export tst_dir := $(sim_dir)/tests -export inc_dir := $(UPRJ_VERILOG_PATH)/dv/firmware +export inc_dir := $(sim_dir)/../firmware test_results := $(bld_dir)/test_results.txt test_info := $(bld_dir)/test_info @@ -274,11 +274,8 @@ run_iverilog: $(test_info) cd $(bld_dir); \ iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) -I $(UPRJ_TESTS_PATH) \ + -I $(UPRJ_TESTS_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $(sv_list) \ -o $(top_module).vvp; \ printf "" > $(test_results); \ @@ -295,11 +292,8 @@ run_iverilog_wf: $(test_info) cd $(bld_dir); \ iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) -I $(UPRJ_TESTS_PATH) \ + -I $(UPRJ_TESTS_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $(sv_list) \ -o $(top_module).vvp; \ printf "" > $(test_results); \
diff --git a/verilog/dv/riscv_regress/riscv_runtests.sv b/verilog/dv/riscv_regress/riscv_runtests.sv index 9a798ff..a487c7a 100644 --- a/verilog/dv/riscv_regress/riscv_runtests.sv +++ b/verilog/dv/riscv_regress/riscv_runtests.sv
@@ -107,9 +107,9 @@ // Flush the content of dcache for signature validation at app // memory - force u_top.u_riscv_top.u_mintf.u_intf.u_dcache.cfg_force_flush = 1'b1; - wait(u_top.u_riscv_top.u_mintf.u_intf.u_dcache.force_flush_done == 1'b1); - release u_top.u_riscv_top.u_mintf.u_intf.u_dcache.cfg_force_flush; + force u_top.u_riscv_top.u_intf.u_dcache.cfg_force_flush = 1'b1; + wait(u_top.u_riscv_top.u_intf.u_dcache.force_flush_done == 1'b1); + release u_top.u_riscv_top.u_intf.u_dcache.cfg_force_flush; repeat (2000) @(posedge clock); // wait data to flush in pipe $display("STATUS: Checking Complaince Test Status .... "); test_running <= 1'b0;
diff --git a/verilog/dv/riscv_regress/user_risc_regress_tb.v b/verilog/dv/riscv_regress/user_risc_regress_tb.v index d915a3d..2fc3ce8 100644 --- a/verilog/dv/riscv_regress/user_risc_regress_tb.v +++ b/verilog/dv/riscv_regress/user_risc_regress_tb.v
@@ -73,10 +73,8 @@ `timescale 1 ns / 1 ns -`include "uprj_netlists.v" -`include "mt48lc8m8a2.v" +`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" `include "is62wvs1288.v" -`include "user_reg_map.v"
diff --git a/verilog/dv/uart_master/Makefile b/verilog/dv/uart_master/Makefile index 9be6ff7..0746413 100644 --- a/verilog/dv/uart_master/Makefile +++ b/verilog/dv/uart_master/Makefile
@@ -14,88 +14,191 @@ # # SPDX-License-Identifier: Apache-2.0 -## PDK -PDK_PATH = $(PDK_ROOT)/sky130A -## Caravel Pointers -CARAVEL_ROOT ?= ../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel + +PWDD := $(shell pwd) +BLOCKS := $(shell basename $(PWDD)) -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl -UPRJ_BEHAVIOURAL_MODELS = ../model -UPRJ_BEHAVIOURAL_AGENTS = ../agents -UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes -UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs -UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes -UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes -UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include -## RISCV GCC -GCC_PATH?=/ef/apps/bin -GCC_PREFIX?=riscv32-unknown-elf -GCC64_PREFIX?=riscv64-unknown-elf +# ---- Include Partitioned Makefiles ---- -## Simulation mode: RTL/GL -SIM_DEFINES = -DFUNCTIONAL -DSIM +DESIGNS?=../../.. +CONFIG = caravel_user_project + +######################################################## +#include $(MCW_ROOT)/verilog/dv/make/env.makefile +######################################################## +####################################################################### +## Global Environment Variables for local repo +####################################################################### + +export PDK_PATH = $(PDK_ROOT)/sky130A +export VIP_PATH = $(CORE_VERILOG_PATH)/dv/vip +export FIRMWARE_PATH = $(CORE_VERILOG_PATH)/dv/firmware + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### + +export CARAVEL_VERILOG_PATH ?= $(CARAVEL_ROOT)/verilog +export CORE_VERILOG_PATH ?= $(CARAVEL_ROOT)/mgmt_core_wrapper/verilog +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog + +export CARAVEL_PATH = $(CARAVEL_VERILOG_PATH) +export VERILOG_PATH = $(CORE_VERILOG_PATH) + +####################################################################### +## Compiler Information +####################################################################### + +export GCC_PATH?= $(TOOLS)/bin +export GCC_PREFIX?= riscv64-unknown-linux-gnu + + +############## USER SPECIFIC DEFINE ################## + +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware + +###################################################### + + + + + +######################################################## +#include $(MCW_ROOT)/verilog/dv/make/var.makefile +######################################################## + +CPU=vexriscv +CPUFAMILY=riscv +CPUFLAGS=-march=rv32i -mabi=ilp32 -D__vexriscv__ +CPUENDIANNESS=little +CLANG=0 + + +###################################################### +# include $(MCW_ROOT)/verilog/dv/make/cpu.makefile +###################################################### + +ifeq ($(CPU),picorv32) + LINKER_SCRIPT=$(FIRMWARE_PATH)/sections.lds + SOURCE_FILES=$(FIRMWARE_PATH)/start.s + VERILOG_FILES= +endif + +ifeq ($(CPU),ibex) + LINKER_SCRIPT=$(FIRMWARE_PATH)/link_ibex.ld + SOURCE_FILES=$(FIRMWARE_PATH)/crt0_ibex.S $(FIRMWARE_PATH)/simple_system_common.c +# VERILOG_FILES=../ibex/* + VERILOG_FILES= +endif + +ifeq ($(CPU),vexriscv) +# LINKER_SCRIPT=$(FIRMWARE_PATH)/sections_vexriscv.lds +# SOURCE_FILES=$(FIRMWARE_PATH)/start_caravel_vexriscv.s + LINKER_SCRIPT=$(FIRMWARE_PATH)/sections.lds + SOURCE_FILES=$(FIRMWARE_PATH)/crt0_vex.S $(FIRMWARE_PATH)/isr.c + VERILOG_FILES= +endif + + + +##################################################### +#include $(MCW_ROOT)/verilog/dv/make/sim.makefile +###################################################### + +export IVERILOG_DUMPER = fst + +# RTL/GL/GL_SDF SIM?=RTL DUMP?=OFF + .SUFFIXES: -PATTERN = uart_master -all: ${PATTERN:=.vcd} +all: ${BLOCKS:=.vcd} ${BLOCKS:=.lst} -hex: ${PATTERN:=.hex} +hex: ${BLOCKS:=.hex} -vvp: ${PATTERN:=.vvp} +#.SUFFIXES: + +############################################################################## +# Comiple firmeware +############################################################################## +%.elf: %.c $(LINKER_SCRIPT) $(SOURCE_FILES) + ${GCC_PREFIX}-gcc -g \ + -I$(FIRMWARE_PATH) \ + -I$(VERILOG_PATH)/dv/generated \ + -I$(VERILOG_PATH)/dv/ \ + -I$(VERILOG_PATH)/common \ + $(CPUFLAGS) \ + -Wl,-Bstatic,-T,$(LINKER_SCRIPT),--strip-debug \ + -ffreestanding -nostdlib -o $@ $(SOURCE_FILES) $< + +%.lst: %.elf + ${GCC_PREFIX}-objdump -d -S $< > $@ + +%.hex: %.elf + ${GCC_PREFIX}-objcopy -O verilog $< $@ + # to fix flash base address + sed -ie 's/@10/@00/g' $@ + +%.bin: %.elf + ${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ + + +############################################################################## +# Runing the simulations +############################################################################## %.vvp: %_tb.v %.hex ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2005-sv $(SIM_DEFINES) -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ - $< -o $@ + iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ + -f$(VERILOG_PATH)/includes/includes.rtl.caravel \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $< else - iverilog -g2005-sv -DWFDUMP $(SIM_DEFINES) -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ - $< -o $@ + iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ + -f$(VERILOG_PATH)/includes/includes.rtl.caravel \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $< endif -else - iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_GL_PATH) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - $< -o $@ +endif + +## GL +ifeq ($(SIM),GL) + ifeq ($(CONFIG),caravel_user_project) + iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ + -f$(VERILOG_PATH)/includes/includes.gl.caravel \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $< + else + iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ + -f$(VERILOG_PATH)/includes/includes.gl.$(CONFIG) \ + -f$(CARAVEL_PATH)/gl/__user_project_wrapper.v -o $@ $< + endif +endif + +## GL+SDF +ifeq ($(SIM),GL_SDF) + ifeq ($(CONFIG),caravel_user_project) + cvc64 +interp \ + +define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY +define+ENABLE_SDF \ + +change_port_type +dump2fst +fst+parallel2=on +nointeractive +notimingchecks +mipdopt \ + -f $(VERILOG_PATH)/includes/includes.gl+sdf.caravel \ + -f $(USER_PROJECT_VERILOG)/includes/includes.gl+sdf.$(CONFIG) $< + else + cvc64 +interp \ + +define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY +define+ENABLE_SDF \ + +change_port_type +dump2fst +fst+parallel2=on +nointeractive +notimingchecks +mipdopt \ + -f $(VERILOG_PATH)/includes/includes.gl+sdf.$(CONFIG) \ + -f $CARAVEL_PATH/gl/__user_project_wrapper.v $< + endif endif %.vcd: %.vvp - vvp $< + vvp $< -%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env - ${GCC64_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $< - -%.hex: %.elf - ${GCC64_PREFIX}-objcopy -O verilog $< $@ - # to fix flash base address - sed -i 's/@10000000/@00000000/g' $@ - -%.bin: %.elf - ${GCC64_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ +# twinwave: RTL-%.vcd GL-%.vcd +# twinwave RTL-$@ * + GL-$@ * check-env: ifndef PDK_ROOT @@ -104,17 +207,18 @@ ifeq (,$(wildcard $(PDK_ROOT)/sky130A)) $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make) endif -#ifeq (,$(wildcard $(GCC64_PREFIX)-gcc )) -# $(error $(GCC64_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make) -#endif +ifeq (,$(wildcard $(GCC_PREFIX)-gcc )) + $(error $(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make) +endif # check for efabless style installation ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog)) SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE endif + # ---- Clean ---- clean: - rm -f *.elf *.hex *.bin *.vvp *.vcd *.log + \rm -f *.elf *.hex *.bin *.vvp *.log *.vcd *.lst *.hexe .PHONY: clean hex all
diff --git a/verilog/dv/uart_master/uart_master.c b/verilog/dv/uart_master/uart_master.c index 1f5912a..46d6e97 100644 --- a/verilog/dv/uart_master/uart_master.c +++ b/verilog/dv/uart_master/uart_master.c
@@ -16,8 +16,9 @@ */ // This include is relative to $CARAVEL_PATH (see Makefile) -#include "verilog/dv/caravel/defs.h" -#include "verilog/dv/caravel/stub.c" +#include <defs.h> +#include <stub.c> +#include "../c_func/inc/user_reg_map.h" // User Project Slaves (0x3000_0000) @@ -61,37 +62,40 @@ /* Set up the housekeeping SPI to be connected internally so */ /* that external pin changes don't affect it. */ - reg_spimaster_config = 0xa002; // Enable, prescaler = 2, + reg_spi_enable = 1; + reg_wb_enable = 1; + // reg_spimaster_config = 0xa002; // Enable, prescaler = 2, // connect to housekeeping SPI // Connect the housekeeping SPI to the SPI master // so that the CSB line is not left floating. This allows // all of the GPIO pins to be used for user functions. - reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_la0_oenb = reg_la0_iena = 0x0000000; /* Apply configuration */ reg_mprj_xfer = 1; while (reg_mprj_xfer == 1); - reg_mprj_datal = 0xAB600000; - reg_la0_oenb = reg_la0_iena = 0x0000000; + reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF; // [31:0] + + // Flag start of the test + reg_mprj_datal = 0xAB600000; //----------------------------------------------------- // Start of User Functionality and take over the GPIO Pins
diff --git a/verilog/dv/uart_master/uart_master_tb.v b/verilog/dv/uart_master/uart_master_tb.v index 1442c8c..2b021ee 100644 --- a/verilog/dv/uart_master/uart_master_tb.v +++ b/verilog/dv/uart_master/uart_master_tb.v
@@ -16,14 +16,7 @@ `default_nettype none `timescale 1 ns / 1 ps - -`define FULL_CHIP_SIM - -`include "uprj_netlists.v" -`include "caravel_netlists.v" -`include "spiflash.v" `include "uart_agent.v" -`include "user_reg_map.v" module uart_master_tb; reg clock; @@ -116,13 +109,16 @@ uart_timeout = 600;// wait time limit uart_fifo_enable = 0; // fifo mode disable tb_master_uart.debug_mode = 0; // disable debug display + + #200; // Wait for reset removal + + wait(checkbits == 16'h AB60); + $display("Monitor: UART Master Test Started"); + + repeat (50000) @(posedge clock); tb_master_uart.uart_init; tb_master_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor); - wait(checkbits == 16'h AB60); - $display("Monitor: UART Master Test Started"); - - repeat (4000) @(posedge clock); //$write ("\n(%t)Response:\n",$time); flag = 0; while(flag == 0) @@ -279,4 +275,7 @@ `include "uart_master_tasks.sv" endmodule + +// SSFLASH has 1ps/1ps time scale +`include "s25fl256s.sv" `default_nettype wire
diff --git a/verilog/dv/user_basic/Makefile b/verilog/dv/user_basic/Makefile index 6ef2620..37feef0 100644 --- a/verilog/dv/user_basic/Makefile +++ b/verilog/dv/user_basic/Makefile
@@ -14,35 +14,19 @@ # # SPDX-License-Identifier: Apache-2.0 -## Caravel Pointers -CARAVEL_ROOT ?= ../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel +# ---- Include Partitioned Makefiles ---- -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl -UPRJ_BEHAVIOURAL_MODELS = ../model -UPRJ_BEHAVIOURAL_AGENTS = ../agents -UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes -UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs -UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes -UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes -UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include +CONFIG = caravel_user_project + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### -## YIFIVE FIRMWARE -YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware -GCC64_PREFIX?=riscv64-unknown-elf +DESIGNS?=../../.. -## RISCV GCC -GCC_PATH?=/ef/apps/bin -GCC_PREFIX?=riscv32-unknown-elf -PDK_PATH?=/ef/tech/SW/sky130A +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog + ## Simulation mode: RTL/GL SIM?=RTL @@ -66,40 +50,22 @@ ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ else iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif else iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif %.vcd: %.vvp vvp $< -%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s - ${GCC64_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $< - -%.hex: - echo @"This is user boot test, noting to compile the mangment core code" - -%.bin: %.elf - ${GCC64_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ # ---- Clean ----
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v index 9ee701c..ef02603 100644 --- a/verilog/dv/user_basic/user_basic_tb.v +++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -74,9 +74,7 @@ `timescale 1 ns/10 ps -`include "uprj_netlists.v" -`include "user_reg_map.v" - +`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" module user_basic_tb; parameter CLK1_PERIOD = 10; @@ -242,8 +240,8 @@ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h8273_8343); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h1603_2022); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0003_9000); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h0104_2022); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0004_1000); end
diff --git a/verilog/dv/user_i2cm/Makefile b/verilog/dv/user_i2cm/Makefile index a0aac1a..e7d9b13 100644 --- a/verilog/dv/user_i2cm/Makefile +++ b/verilog/dv/user_i2cm/Makefile
@@ -14,35 +14,22 @@ # # SPDX-License-Identifier: Apache-2.0 -## Caravel Pointers -CARAVEL_ROOT ?= ../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel +# ---- Include Partitioned Makefiles ---- -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl -UPRJ_BEHAVIOURAL_MODELS = ../model -UPRJ_BEHAVIOURAL_AGENTS = ../agents -UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes -UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs -UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes -UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes -UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include +CONFIG = caravel_user_project + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### +DESIGNS?=../../.. + +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE -YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware GCC64_PREFIX?=riscv64-unknown-elf -## RISCV GCC -GCC_PATH?=/ef/apps/bin -GCC_PREFIX?=riscv32-unknown-elf -PDK_PATH?=/ef/tech/SW/sky130A ## Simulation mode: RTL/GL SIM?=RTL @@ -63,49 +50,25 @@ vvp: ${PATTERN:=.vvp} %.vvp: %_tb.v - ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_uart.c -o user_uart.o - ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt_tcm.S -o crt_tcm.o - ${GCC64_PREFIX}-gcc -o user_uart.elf -T $(YIFIVE_FIRMWARE_PATH)/link_tcm.ld user_uart.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 - ${GCC64_PREFIX}-objcopy -O verilog user_uart.elf user_uart.hex - ${GCC64_PREFIX}-objdump -D user_uart.elf > user_uart.dump - rm crt_tcm.o user_uart.o ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ else - iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif else - iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif %.vcd: %.vvp vvp $< -%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s - ${GCC64_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $< - -%.hex: - echo @"This is user boot test, noting to compile the mangment core code" - -%.bin: %.elf - ${GCC64_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ # ---- Clean ----
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v index c9bcd8b..6be9759 100644 --- a/verilog/dv/user_i2cm/user_i2cm_tb.v +++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -65,9 +65,8 @@ `timescale 1 ns / 1 ns -`include "uprj_netlists.v" +`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" `include "i2c_slave_model.v" -`include "user_reg_map.v" module tb_top;
diff --git a/verilog/dv/user_pwm/Makefile b/verilog/dv/user_pwm/Makefile index 80c35a0..96815e2 100644 --- a/verilog/dv/user_pwm/Makefile +++ b/verilog/dv/user_pwm/Makefile
@@ -14,37 +14,27 @@ # # SPDX-License-Identifier: Apache-2.0 -## Caravel Pointers -CARAVEL_ROOT ?= ../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel +# ---- Include Partitioned Makefiles ---- -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl -UPRJ_BEHAVIOURAL_MODELS = ../model -UPRJ_BEHAVIOURAL_AGENTS = ../agents -UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes -UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/i2cm/src/includes -UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/usb1_host/src/includes +CONFIG = caravel_user_project + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### +DESIGNS?=../../.. + +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE -YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware GCC64_PREFIX?=riscv64-unknown-elf -## RISCV GCC -GCC_PATH?=/ef/apps/bin -GCC_PREFIX?=riscv32-unknown-elf -PDK_PATH?=/opt/pdk/sky130A ## Simulation mode: RTL/GL SIM?=RTL DUMP?=OFF +RISC_CORE?=0 ### To Enable IVERILOG FST DUMP export IVERILOG_DUMPER = fst @@ -62,36 +52,23 @@ %.vvp: %_tb.v ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) \ - -I $(UPRJ_INCLUDE_PATH3) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ else - iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) \ - -I $(UPRJ_INCLUDE_PATH3) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif else - iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif %.vcd: %.vvp vvp $< -%.hex: - echo @"This is user boot test, noting to compile the mangment core code" - # ---- Clean ----
diff --git a/verilog/dv/user_pwm/user_pwm_tb.v b/verilog/dv/user_pwm/user_pwm_tb.v index 575d604..cbe03cb 100644 --- a/verilog/dv/user_pwm/user_pwm_tb.v +++ b/verilog/dv/user_pwm/user_pwm_tb.v
@@ -64,13 +64,12 @@ `default_nettype wire -`timescale 1 ns / 1 ns +`timescale 1 ns / 1 ps `define TB_GLBL user_pwm_tb -`include "uprj_netlists.v" -`include "user_reg_map.v" +`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" module user_pwm_tb;
diff --git a/verilog/dv/user_qspi/Makefile b/verilog/dv/user_qspi/Makefile index 4447c1c..1932afc 100644 --- a/verilog/dv/user_qspi/Makefile +++ b/verilog/dv/user_qspi/Makefile
@@ -14,39 +14,27 @@ # # SPDX-License-Identifier: Apache-2.0 -## Caravel Pointers -CARAVEL_ROOT ?= ../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel +# ---- Include Partitioned Makefiles ---- -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl -UPRJ_BEHAVIOURAL_MODELS = ../model -UPRJ_BEHAVIOURAL_AGENTS = ../agents -UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes -UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs -UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes -UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes -UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include +CONFIG = caravel_user_project + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### +DESIGNS?=../../.. + +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE -YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware GCC64_PREFIX?=riscv64-unknown-elf -## RISCV GCC -GCC_PATH?=/ef/apps/bin -GCC_PREFIX?=riscv32-unknown-elf -PDK_PATH?=/ef/tech/SW/sky130A ## Simulation mode: RTL/GL SIM?=RTL DUMP?=OFF +RISC_CORE?=0 ### To Enable IVERILOG FST DUMP export IVERILOG_DUMPER = fst @@ -64,36 +52,23 @@ %.vvp: %_tb.v ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ else - iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif else - iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif %.vcd: %.vvp vvp $< -%.hex: - echo @"This is user boot test, noting to compile the mangment core code" - # ---- Clean ----
diff --git a/verilog/dv/user_qspi/user_qspi_tb.v b/verilog/dv/user_qspi/user_qspi_tb.v index 3b4d47a..fdac089 100644 --- a/verilog/dv/user_qspi/user_qspi_tb.v +++ b/verilog/dv/user_qspi/user_qspi_tb.v
@@ -77,13 +77,10 @@ `default_nettype wire -`timescale 1 ns / 1 ns +`timescale 1 ns/1 ps -`include "uprj_netlists.v" -`include "mt48lc8m8a2.v" +`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" `include "is62wvs1288.v" -`include "user_reg_map.v" - module user_qspi_tb; reg clock;
diff --git a/verilog/dv/user_risc_boot/Makefile b/verilog/dv/user_risc_boot/Makefile index 7476457..4a0c488 100644 --- a/verilog/dv/user_risc_boot/Makefile +++ b/verilog/dv/user_risc_boot/Makefile
@@ -14,35 +14,22 @@ # # SPDX-License-Identifier: Apache-2.0 -## Caravel Pointers -CARAVEL_ROOT ?= ../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel +# ---- Include Partitioned Makefiles ---- -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl -UPRJ_BEHAVIOURAL_MODELS = ../model -UPRJ_BEHAVIOURAL_AGENTS = ../agents -UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes -UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs -UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes -UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes -UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include +CONFIG = caravel_user_project + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### +DESIGNS?=../../.. + +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE -YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware GCC64_PREFIX?=riscv64-unknown-elf -## RISCV GCC -GCC_PATH?=/ef/apps/bin -GCC_PREFIX?=riscv32-unknown-elf -PDK_PATH?=/ef/tech/SW/sky130A ## Simulation mode: RTL/GL SIM?=RTL @@ -72,41 +59,23 @@ rm crt.o user_risc_boot.o ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ else - iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif else - iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif %.vcd: %.vvp vvp $< +risc_core_id=$(RISC_CORE) -%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s - ${GCC64_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $< - -%.hex: - echo @"This is user boot test, noting to compile the mangment core code" - -%.bin: %.elf - ${GCC64_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ # ---- Clean ----
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v index c9e68da..6f177dd 100644 --- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v +++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -74,11 +74,7 @@ `timescale 1 ns / 1 ns -`include "uprj_netlists.v" -`include "mt48lc8m8a2.v" -`include "user_reg_map.v" - -`define ADDR_SPACE_PINMUX 32'h3002_0000 +`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" module user_risc_boot_tb; reg clock; reg wb_rst_i;
diff --git a/verilog/dv/user_sspi/Makefile b/verilog/dv/user_sspi/Makefile index db60fd3..9d8bd45 100644 --- a/verilog/dv/user_sspi/Makefile +++ b/verilog/dv/user_sspi/Makefile
@@ -14,39 +14,27 @@ # # SPDX-License-Identifier: Apache-2.0 -## Caravel Pointers -CARAVEL_ROOT ?= ../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel +# ---- Include Partitioned Makefiles ---- -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl -UPRJ_BEHAVIOURAL_MODELS = ../model -UPRJ_BEHAVIOURAL_AGENTS = ../agents -UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes -UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs -UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes -UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes -UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include +CONFIG = caravel_user_project + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### +DESIGNS?=../../.. + +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE -YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware GCC64_PREFIX?=riscv64-unknown-elf -## RISCV GCC -GCC_PATH?=/ef/apps/bin -GCC_PREFIX?=riscv32-unknown-elf -PDK_PATH?=/opt/pdk/sky130A ## Simulation mode: RTL/GL SIM?=RTL DUMP?=OFF +RISC_CORE?=0 ### To Enable IVERILOG FST DUMP export IVERILOG_DUMPER = fst @@ -64,36 +52,23 @@ %.vvp: %_tb.v ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ else - iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif else - iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif %.vcd: %.vvp vvp $< -%.hex: - echo @"This is user boot test, noting to compile the mangment core code" - # ---- Clean ----
diff --git a/verilog/dv/user_sspi/user_sspi_tb.v b/verilog/dv/user_sspi/user_sspi_tb.v index 512e40d..6b6cbb4 100644 --- a/verilog/dv/user_sspi/user_sspi_tb.v +++ b/verilog/dv/user_sspi/user_sspi_tb.v
@@ -64,14 +64,13 @@ `default_nettype wire -`timescale 1 ns / 1 ns +`timescale 1 ns/1 ps +`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" +`include "is62wvs1288.v" `define TB_GLBL user_sspi_tb -`include "uprj_netlists.v" -`include "is62wvs1288.v" -`include "user_reg_map.v"
diff --git a/verilog/dv/user_timer/Makefile b/verilog/dv/user_timer/Makefile index 9e7660a..6520c31 100644 --- a/verilog/dv/user_timer/Makefile +++ b/verilog/dv/user_timer/Makefile
@@ -14,37 +14,27 @@ # # SPDX-License-Identifier: Apache-2.0 -## Caravel Pointers -CARAVEL_ROOT ?= ../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel +# ---- Include Partitioned Makefiles ---- -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl -UPRJ_BEHAVIOURAL_MODELS = ../model -UPRJ_BEHAVIOURAL_AGENTS = ../agents -UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes -UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/i2cm/src/includes -UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/usb1_host/src/includes +CONFIG = caravel_user_project + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### +DESIGNS?=../../.. + +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE -YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware GCC64_PREFIX?=riscv64-unknown-elf -## RISCV GCC -GCC_PATH?=/ef/apps/bin -GCC_PREFIX?=riscv32-unknown-elf -PDK_PATH?=/opt/pdk/sky130A ## Simulation mode: RTL/GL SIM?=RTL DUMP?=OFF +RISC_CORE?=0 ### To Enable IVERILOG FST DUMP export IVERILOG_DUMPER = fst @@ -62,36 +52,23 @@ %.vvp: %_tb.v ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) \ - -I $(UPRJ_INCLUDE_PATH3) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ else - iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) \ - -I $(UPRJ_INCLUDE_PATH3) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif else - iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif %.vcd: %.vvp vvp $< -%.hex: - echo @"This is user boot test, noting to compile the mangment core code" - # ---- Clean ----
diff --git a/verilog/dv/user_timer/user_timer_tb.v b/verilog/dv/user_timer/user_timer_tb.v index f2d7f11..d7ef5e6 100644 --- a/verilog/dv/user_timer/user_timer_tb.v +++ b/verilog/dv/user_timer/user_timer_tb.v
@@ -64,12 +64,11 @@ `default_nettype wire -`timescale 1 ns / 1 ns +`timescale 1 ns / 1 ps `define TB_GLBL user_timer_tb -`include "uprj_netlists.v" -`include "user_reg_map.v" +`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" module user_timer_tb;
diff --git a/verilog/dv/user_uart/Makefile b/verilog/dv/user_uart/Makefile index 7d5a495..97726ee 100644 --- a/verilog/dv/user_uart/Makefile +++ b/verilog/dv/user_uart/Makefile
@@ -14,35 +14,22 @@ # # SPDX-License-Identifier: Apache-2.0 -## Caravel Pointers -CARAVEL_ROOT ?= ../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel +# ---- Include Partitioned Makefiles ---- -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl -UPRJ_BEHAVIOURAL_MODELS = ../model -UPRJ_BEHAVIOURAL_AGENTS = ../agents -UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes -UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs -UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes -UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes -UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include +CONFIG = caravel_user_project + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### +DESIGNS?=../../.. + +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE -YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware GCC64_PREFIX?=riscv64-unknown-elf -## RISCV GCC -GCC_PATH?=/ef/apps/bin -GCC_PREFIX?=riscv32-unknown-elf -PDK_PATH?=/ef/tech/SW/sky130A ## Simulation mode: RTL/GL SIM?=RTL @@ -59,7 +46,6 @@ all: ${PATTERN:=.vcd} -hex: ${PATTERN:=.hex} vvp: ${PATTERN:=.vvp} @@ -72,41 +58,23 @@ rm crt.o user_uart.o ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ else - iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif else - iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif %.vcd: %.vvp vvp $< +risc_core_id=$(RISC_CORE) -%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s - ${GCC64_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $< - -%.hex: - echo @"This is user boot test, noting to compile the mangment core code" - -%.bin: %.elf - ${GCC64_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ # ---- Clean ----
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v index b4bfa74..ad07b17 100644 --- a/verilog/dv/user_uart/user_uart_tb.v +++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -72,11 +72,10 @@ `default_nettype wire -`timescale 1 ns / 1 ns +`timescale 1 ns/1 ps -`include "uprj_netlists.v" +`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" `include "uart_agent.v" -`include "user_reg_map.v" module user_uart_tb;
diff --git a/verilog/dv/user_uart_master/Makefile b/verilog/dv/user_uart_master/Makefile index eca6304..7f9bc7b 100644 --- a/verilog/dv/user_uart_master/Makefile +++ b/verilog/dv/user_uart_master/Makefile
@@ -14,29 +14,21 @@ # # SPDX-License-Identifier: Apache-2.0 -## Caravel Pointers -CARAVEL_ROOT ?= ../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel +# ---- Include Partitioned Makefiles ---- -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl -UPRJ_BEHAVIOURAL_MODELS = ../model -UPRJ_BEHAVIOURAL_AGENTS = ../agents -UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes -UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs -UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes -UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes -UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include +CONFIG = caravel_user_project + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### +DESIGNS?=../../.. + +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE -YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware +GCC64_PREFIX?=riscv64-unknown-elf ## Simulation mode: RTL/GL @@ -59,27 +51,17 @@ %.vvp: %_tb.v ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ else - iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif else - iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif
diff --git a/verilog/dv/user_uart_master/user_uart_master_tb.v b/verilog/dv/user_uart_master/user_uart_master_tb.v index 3f4f16e..40d7b07 100644 --- a/verilog/dv/user_uart_master/user_uart_master_tb.v +++ b/verilog/dv/user_uart_master/user_uart_master_tb.v
@@ -64,17 +64,10 @@ `default_nettype wire -`timescale 1 ns / 1 ns +`timescale 1 ns / 1 ps -`include "uprj_netlists.v" +`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" `include "uart_agent.v" -`include "user_reg_map.v" - - - -`define ADDR_SPACE_UART 32'h3001_0000 -`define ADDR_SPACE_PINMUX 32'h3002_0000 - module user_uart_master_tb;
diff --git a/verilog/dv/user_usb/Makefile b/verilog/dv/user_usb/Makefile index 2a70c4c..a25bc69 100644 --- a/verilog/dv/user_usb/Makefile +++ b/verilog/dv/user_usb/Makefile
@@ -14,36 +14,22 @@ # # SPDX-License-Identifier: Apache-2.0 -## Caravel Pointers -CARAVEL_ROOT ?= ../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel +# ---- Include Partitioned Makefiles ---- -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl -UPRJ_BEHAVIOURAL_MODELS = ../model -UPRJ_BEHAVIOURAL_AGENTS = ../agents -UPRJ_BEHAVIOURAL_BFM = ../bfm -UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes -UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs -UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes -UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes -UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include +CONFIG = caravel_user_project + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### +DESIGNS?=../../.. + +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE -YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware GCC64_PREFIX?=riscv64-unknown-elf -## RISCV GCC -GCC_PATH?=/ef/apps/bin -GCC_PREFIX?=riscv32-unknown-elf -PDK_PATH?=/opt/pdk/sky130A ## Simulation mode: RTL/GL SIM?=RTL @@ -66,36 +52,23 @@ %.vvp: %_tb.v ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) -I $(UPRJ_BEHAVIOURAL_BFM) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ else - iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) -I $(UPRJ_BEHAVIOURAL_BFM) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif else - iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif %.vcd: %.vvp vvp $< -%.hex: - echo @"This is user boot test, noting to compile the mangment core code" - # ---- Clean ----
diff --git a/verilog/dv/user_usb/user_usb_tb.v b/verilog/dv/user_usb/user_usb_tb.v index 96f1446..d2e37b4 100644 --- a/verilog/dv/user_usb/user_usb_tb.v +++ b/verilog/dv/user_usb/user_usb_tb.v
@@ -38,18 +38,18 @@ `default_nettype wire -`timescale 1 ns / 1 ns +`timescale 1 ns / 1 ps `define TB_GLBL user_usb_tb `define USB_BFM u_usb_agent -`include "user_reg_map.v" -`include "uprj_netlists.v" `include "usb_agents.v" `include "test_control.v" `include "usb1d_defines.v" `include "usbd_files.v" +`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" + module user_usb_tb; parameter USB_HPER = 10.4167; // 48Mhz Half cycle
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile index 887f270..633a369 100644 --- a/verilog/dv/wb_port/Makefile +++ b/verilog/dv/wb_port/Makefile
@@ -21,6 +21,7 @@ # ---- Include Partitioned Makefiles ---- +DESIGNS?=../../.. CONFIG = caravel_user_project ######################################################## @@ -50,7 +51,7 @@ ####################################################################### export GCC_PATH?= $(TOOLS)/bin -export GCC_PREFIX?= riscv32-unknown-linux-gnu +export GCC_PREFIX?= riscv64-unknown-linux-gnu @@ -121,7 +122,7 @@ # Comiple firmeware ############################################################################## %.elf: %.c $(LINKER_SCRIPT) $(SOURCE_FILES) - ${GCC_PATH}/${GCC_PREFIX}-gcc -g \ + ${GCC_PREFIX}-gcc -g \ -I$(FIRMWARE_PATH) \ -I$(VERILOG_PATH)/dv/generated \ -I$(VERILOG_PATH)/dv/ \ @@ -131,15 +132,15 @@ -ffreestanding -nostdlib -o $@ $(SOURCE_FILES) $< %.lst: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objdump -d -S $< > $@ + ${GCC_PREFIX}-objdump -d -S $< > $@ %.hex: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ + ${GCC_PREFIX}-objcopy -O verilog $< $@ # to fix flash base address sed -ie 's/@10/@00/g' $@ %.bin: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ + ${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ ############################################################################## @@ -204,8 +205,8 @@ ifeq (,$(wildcard $(PDK_ROOT)/sky130A)) $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make) endif -ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc )) - $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make) +ifeq (,$(wildcard $(GCC_PREFIX)-gcc )) + $(error $(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make) endif # check for efabless style installation ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c index 910e933..d3d63fe 100644 --- a/verilog/dv/wb_port/wb_port.c +++ b/verilog/dv/wb_port/wb_port.c
@@ -87,7 +87,7 @@ reg_mprj_xfer = 1; while (reg_mprj_xfer == 1); - reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64] + reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF; // [31:0] reg_la0_data = 0x000; reg_la0_data = 0x001; // Remove Soft Reset
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project index 5d917ec..35cfe60 100644 --- a/verilog/includes/includes.rtl.caravel_user_project +++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -1,9 +1,12 @@ # Caravel user project includes ++incdir+$(USER_PROJECT_VERILOG)/rtl/ +incdir+$(USER_PROJECT_VERILOG)/rtl/i2cm/src/includes +incdir+$(USER_PROJECT_VERILOG)/rtl/usb1_host/src/includes +incdir+$(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/includes ++incdir+$(USER_PROJECT_VERILOG)/dv/bfm +incdir+$(USER_PROJECT_VERILOG)/dv/model +incdir+$(USER_PROJECT_VERILOG)/dv/agents +$(USER_PROJECT_VERILOG)/rtl/user_reg_map.v -v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux.sv -v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux_reg.sv -v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/gpio_intr.sv @@ -87,9 +90,11 @@ -v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_timer.sv -v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_dmem_wb.sv -v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_imem_wb.sv --v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr2_mcore_router.sv --v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr2_intf.sv --v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr2_mintf.sv +-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_intf.sv +-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_sram_mux.sv +-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr2_router.sv +-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr2_iconnect.sv +-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr2_cross_bar.sv -v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr2_top_wb.sv -v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_icache_router.sv -v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_dcache_router.sv
diff --git a/verilog/rtl/lib/async_fifo.sv b/verilog/rtl/lib/async_fifo.sv index fd59cfa..cedffdb 100755 --- a/verilog/rtl/lib/async_fifo.sv +++ b/verilog/rtl/lib/async_fifo.sv
@@ -58,7 +58,7 @@ //------------------------------------------- // async FIFO //----------------------------------------------- -//`timescale 1ns/1ps +`timescale 1ns/1ps module async_fifo (wr_clk, wr_reset_n,
diff --git a/verilog/rtl/lib/async_fifo_th.sv b/verilog/rtl/lib/async_fifo_th.sv index 05860f8..5162802 100755 --- a/verilog/rtl/lib/async_fifo_th.sv +++ b/verilog/rtl/lib/async_fifo_th.sv
@@ -70,6 +70,7 @@ // rd_total_aval --> Indicate total no of transfer available //----------------------------------------------- +`timescale 1ns/1ps module async_fifo_th ( wr_clk, wr_reset_n,
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv index aed3a9d..c26bbe4 100755 --- a/verilog/rtl/pinmux/src/pinmux.sv +++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -59,7 +59,7 @@ output logic i2cm_rst_n , output logic usb_rst_n , - output logic [1:0] cfg_riscv_debug_sel, + output logic [15:0] cfg_riscv_ctrl, // Reg Bus Interface Signal input logic reg_cs, @@ -365,7 +365,7 @@ .i2cm_rst_n (i2cm_rst_n ), .usb_rst_n (usb_rst_n ), - .cfg_riscv_debug_sel (cfg_riscv_debug_sel ), + .cfg_riscv_ctrl (cfg_riscv_ctrl ), // Reg read/write Interface Inputs
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv index d340fc6..131207f 100644 --- a/verilog/rtl/pinmux/src/pinmux_reg.sv +++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -72,7 +72,7 @@ input logic i2cm_intr, output logic [9:0] cfg_pulse_1us, - output logic [1:0] cfg_riscv_debug_sel, + output logic [15:0] cfg_riscv_ctrl, //--------------------------------------------------- // 6 PWM Configuration @@ -317,7 +317,7 @@ ); assign cfg_pulse_1us = reg_2[9:0]; -assign cfg_riscv_debug_sel = reg_2[31:30]; +assign cfg_riscv_ctrl = reg_2[31:16]; //----------------------------------------------------------------------- // reg-3 : Global Interrupt Mask @@ -715,7 +715,7 @@ //----------------------------------------- // Software Reg-2, Release date: <DAY><MONTH><YEAR> // ---------------------------------------- -gen_32b_reg #(32'h1603_2022) u_reg_23 ( +gen_32b_reg #(32'h0104_2022) u_reg_23 ( //List of Inputs .reset_n (h_reset_n ), .clk (mclk ), @@ -728,9 +728,9 @@ ); //----------------------------------------- -// Software Reg-3: Poject Revison 3.9 = 0003900 +// Software Reg-3: Poject Revison 4.1 = 0004100 // ---------------------------------------- -gen_32b_reg #(32'h0003_9000) u_reg_24 ( +gen_32b_reg #(32'h0004_1000) u_reg_24 ( //List of Inputs .reset_n (h_reset_n ), .clk (mclk ),
diff --git a/verilog/rtl/qspim b/verilog/rtl/qspim index efa1519..201a604 160000 --- a/verilog/rtl/qspim +++ b/verilog/rtl/qspim
@@ -1 +1 @@ -Subproject commit efa151915f9d00cb329388845356c5b734601571 +Subproject commit 201a6047f18db8ec792d948a52327b070013ab53
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 1f9418b..0c341d6 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -196,6 +196,8 @@ //// 3. Risc fuse_mhartid is removed and internal tied //// //// inside risc core //// //// 4. caravel wb addressing issue restrict to 0x300FFFFF//// +//// 4.1 April 1 2022, Dinesh A //// +//// 1. sram lanuch phase control added inside risc core //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// @@ -581,7 +583,14 @@ wire [3:0] spi_csn ; -wire [1:0] cfg_riscv_debug_sel ; + +//-------------------------------------------------------------------------- +// Pinmux Risc core config +// ------------------------------------------------------------------------- +wire [15:0] cfg_riscv_ctrl; +wire [3:0] cfg_riscv_sram_lphase = cfg_riscv_ctrl[3:0]; +wire [2:0] cfg_riscv_cache_ctrl = cfg_riscv_ctrl[6:4]; +wire [1:0] cfg_riscv_debug_sel = cfg_riscv_ctrl[9:8]; ///////////////////////////////////////////////////////// // Clock Skew Ctrl @@ -677,6 +686,8 @@ .cpu_core_rst_n (cpu_core_rst_n ), .riscv_debug (riscv_debug ), .core_debug_sel (cfg_riscv_debug_sel ), + .cfg_sram_lphase (cfg_riscv_sram_lphase ), + .cfg_cache_ctrl (cfg_riscv_cache_ctrl ), // Clock .core_clk (cpu_clk ), @@ -1151,7 +1162,7 @@ .i2cm_rst_n (i2c_rst_n ), .usb_rst_n (usb_rst_n ), - .cfg_riscv_debug_sel (cfg_riscv_debug_sel ), + .cfg_riscv_ctrl (cfg_riscv_ctrl ), // Reg Bus Interface Signal .reg_cs (wbd_glbl_stb_o ),
diff --git a/verilog/rtl/yifive/ycr2c b/verilog/rtl/yifive/ycr2c index 4705007..83c2d4a 160000 --- a/verilog/rtl/yifive/ycr2c +++ b/verilog/rtl/yifive/ycr2c
@@ -1 +1 @@ -Subproject commit 47050074fbe8e3c452e8072ef40e4270488575e6 +Subproject commit 83c2d4af3c2fb7591bef0cdca61e4930498cae8a