commit e25073a29ddaa423e8df65a5976758de5aaefc1a
author Anton Blanchard <anton@linux.ibm.com> Tue Jun 07 12:15:58 2022 +1000
committer Anton Blanchard <anton@ozlabs.org> Tue Jun 07 12:15:58 2022 +1000
tree 8a65433626b4334377a5c00c7ccca5fb3fbe0bff
parent f07a52bceae8944877fb04f2ebc38176a25f7e79

Fix multiplier behavioural

It wasn't updated for the 2 cycle multiplier.

verilog/rtl/multiply_add_64x64.v

diff --git a/verilog/rtl/multiply_add_64x64.v b/verilog/rtl/multiply_add_64x64.v
index 303ed24..6bffb9a 100644
--- a/verilog/rtl/multiply_add_64x64.v
+++ b/verilog/rtl/multiply_add_64x64.v
@@ -12,13 +12,11 @@
     input [BITS*2-1:0] c,
     output [BITS*2-1:0] o
 );
-    reg [BITS*2-1:0] o_tmp[2:0];
+    reg [BITS*2-1:0] o_tmp;
 
     always @(posedge clk) begin
-        o_tmp[2] = o_tmp[1];
-        o_tmp[1] = o_tmp[0];
-	o_tmp[0] = (a * b) + c;
+	o_tmp = (a * b) + c;
     end
 
-    assign o = o_tmp[2];
+    assign o = o_tmp;
 endmodule