Hardwire CSB
diff --git a/verilog/dv/microwatt/jtag/jtag_tb.v b/verilog/dv/microwatt/jtag/jtag_tb.v
index b5a45b6..5a97237 100644
--- a/verilog/dv/microwatt/jtag/jtag_tb.v
+++ b/verilog/dv/microwatt/jtag/jtag_tb.v
@@ -66,7 +66,6 @@
reg clock;
reg RSTB;
reg microwatt_reset;
- reg CSB;
reg power1, power2;
reg power3, power4;
@@ -95,7 +94,7 @@
assign checkbits = mprj_io[31:16];
- assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+ assign mprj_io[3] = 1'b1; // Force CSB high.
assign jtag_tdo = mprj_io[12];
assign mprj_io[13] = jtag_tms;
@@ -124,7 +123,6 @@
initial begin
RSTB <= 1'b0;
- CSB <= 1'b1; // Force CSB high
microwatt_reset <= 1'b1;
#1000;
microwatt_reset <= 1'b0;
diff --git a/verilog/dv/microwatt/memory_test/memory_test_tb.v b/verilog/dv/microwatt/memory_test/memory_test_tb.v
index ab28aec..c793e30 100644
--- a/verilog/dv/microwatt/memory_test/memory_test_tb.v
+++ b/verilog/dv/microwatt/memory_test/memory_test_tb.v
@@ -29,7 +29,6 @@
reg clock;
reg RSTB;
reg microwatt_reset;
- reg CSB;
reg power1, power2;
reg power3, power4;
@@ -56,7 +55,7 @@
assign uart_tx = mprj_io[6];
assign mprj_io[5] = 1'b1;
- assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+ assign mprj_io[3] = 1'b1; // Force CSB high.
// 100 MHz clock
always #5 clock <= (clock === 1'b0);
@@ -78,7 +77,6 @@
initial begin
RSTB <= 1'b0;
- CSB <= 1'b1; // Force CSB high
microwatt_reset <= 1'b1;
#1000;
microwatt_reset <= 1'b0;
diff --git a/verilog/dv/microwatt/minimal/minimal_tb.v b/verilog/dv/microwatt/minimal/minimal_tb.v
index 803a0a1..f1d2bcd 100644
--- a/verilog/dv/microwatt/minimal/minimal_tb.v
+++ b/verilog/dv/microwatt/minimal/minimal_tb.v
@@ -28,7 +28,6 @@
reg clock;
reg RSTB;
reg microwatt_reset;
- reg CSB;
reg power1, power2;
reg power3, power4;
@@ -51,7 +50,7 @@
assign checkbits = mprj_io[31:16];
- assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+ assign mprj_io[3] = 1'b1; // Force CSB high.
// tie uart RX high
assign mprj_io[5] = 1;
@@ -84,7 +83,6 @@
initial begin
RSTB <= 1'b0;
- CSB <= 1'b1; // Force CSB high
microwatt_reset <= 1'b1;
#2000;
// Keep the management engine in reset
diff --git a/verilog/dv/microwatt/simplebus_micropython/simplebus_micropython_tb.v b/verilog/dv/microwatt/simplebus_micropython/simplebus_micropython_tb.v
index a3ee185..2fa8dda 100644
--- a/verilog/dv/microwatt/simplebus_micropython/simplebus_micropython_tb.v
+++ b/verilog/dv/microwatt/simplebus_micropython/simplebus_micropython_tb.v
@@ -234,7 +234,6 @@
reg clock;
reg RSTB;
reg microwatt_reset;
- reg CSB;
reg power1, power2;
reg power3, power4;
@@ -264,7 +263,7 @@
assign checkbits = mprj_io[25:16];
- assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+ assign mprj_io[3] = 1'b1; // Force CSB high.
// tie uart RX high
assign mprj_io[5] = 1;
@@ -303,7 +302,6 @@
initial begin
RSTB <= 1'b0;
- CSB <= 1'b1; // Force CSB high
microwatt_reset <= 1'b1;
#2000;
// Keep the management engine in reset
diff --git a/verilog/dv/microwatt/simplebus_minimal/simplebus_minimal_tb.v b/verilog/dv/microwatt/simplebus_minimal/simplebus_minimal_tb.v
index 0d468e0..2a98791 100644
--- a/verilog/dv/microwatt/simplebus_minimal/simplebus_minimal_tb.v
+++ b/verilog/dv/microwatt/simplebus_minimal/simplebus_minimal_tb.v
@@ -182,7 +182,6 @@
reg clock;
reg RSTB;
reg microwatt_reset;
- reg CSB;
reg power1, power2;
reg power3, power4;
@@ -211,7 +210,7 @@
assign checkbits = mprj_io[17:16];
- assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+ assign mprj_io[3] = 1'b1; // Force CSB high.
// tie uart RX high
assign mprj_io[5] = 1;
@@ -248,7 +247,6 @@
initial begin
RSTB <= 1'b0;
- CSB <= 1'b1; // Force CSB high
microwatt_reset <= 1'b1;
#2000;
// Would prefer to keep the management engine in reset
diff --git a/verilog/dv/microwatt/spi_flash/spi_flash_tb.v b/verilog/dv/microwatt/spi_flash/spi_flash_tb.v
index 251573d..e0ed0c4 100644
--- a/verilog/dv/microwatt/spi_flash/spi_flash_tb.v
+++ b/verilog/dv/microwatt/spi_flash/spi_flash_tb.v
@@ -29,7 +29,6 @@
reg clock;
reg RSTB;
reg microwatt_reset;
- reg CSB;
reg power1, power2;
reg power3, power4;
@@ -56,7 +55,7 @@
assign uart_tx = mprj_io[6];
assign mprj_io[5] = 1'b1;
- assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+ assign mprj_io[3] = 1'b1; // Force CSB high.
// 100 MHz clock
always #5 clock <= (clock === 1'b0);
@@ -78,7 +77,6 @@
initial begin
RSTB <= 1'b0;
- CSB <= 1'b1; // Force CSB high
microwatt_reset <= 1'b1;
#1000;
microwatt_reset <= 1'b0;
diff --git a/verilog/dv/microwatt/uart/uart_tb.v b/verilog/dv/microwatt/uart/uart_tb.v
index bb9c9a6..1042382 100644
--- a/verilog/dv/microwatt/uart/uart_tb.v
+++ b/verilog/dv/microwatt/uart/uart_tb.v
@@ -87,7 +87,6 @@
reg clock;
reg RSTB;
reg microwatt_reset;
- reg CSB;
reg power1, power2;
reg power3, power4;
reg uart_rx;
@@ -115,7 +114,7 @@
assign uart_tx = mprj_io[6];
assign mprj_io[5] = uart_rx;
- assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+ assign mprj_io[3] = 1'b1; // Force CSB high.
// 100 MHz clock
always #5 clock <= (clock === 1'b0);
@@ -136,7 +135,6 @@
initial begin
RSTB <= 1'b0;
- CSB <= 1'b1; // Force CSB high
microwatt_reset <= 1'b1;
#1000;
microwatt_reset <= 1'b0;
