commit df70bc468479ee71ea1bc9bb07fe4e429a0a9a06
author Anton Blanchard <anton@linux.ibm.com> Fri Apr 29 10:47:58 2022 +1000
committer Anton Blanchard <anton@ozlabs.org> Fri Apr 29 21:32:16 2022 +1000
tree 618b73f75715d12669a54d75eca041683a78bbcd
parent 79e84bf2a3cc7e9d60dcb56f55fca9d747b6bca1

disable waveform files by default

verilog/dv/microwatt/jtag/jtag_tb.v

diff --git a/verilog/dv/microwatt/jtag/jtag_tb.v b/verilog/dv/microwatt/jtag/jtag_tb.v
index 5a97237..440c3ce 100644
--- a/verilog/dv/microwatt/jtag/jtag_tb.v
+++ b/verilog/dv/microwatt/jtag/jtag_tb.v
@@ -109,8 +109,8 @@
 	end
 
 	initial begin
-		$dumpfile("jtag.vcd");
-		$dumpvars(0, jtag_tb);
+		//$dumpfile("jtag.vcd");
+		//$dumpvars(0, jtag_tb);
 
 		$display("Microwatt JTAG IDCODE test");
 

verilog/dv/microwatt/memory_test/memory_test_tb.v

diff --git a/verilog/dv/microwatt/memory_test/memory_test_tb.v b/verilog/dv/microwatt/memory_test/memory_test_tb.v
index c793e30..99929ce 100644
--- a/verilog/dv/microwatt/memory_test/memory_test_tb.v
+++ b/verilog/dv/microwatt/memory_test/memory_test_tb.v
@@ -65,8 +65,8 @@
 	end
 
 	initial begin
-		$dumpfile("memory_test.vcd");
-		$dumpvars(0, memory_test);
+		//$dumpfile("memory_test.vcd");
+		//$dumpvars(0, memory_test);
 
 		$display("Microwatt memory test");
 

verilog/dv/microwatt/minimal/minimal_tb.v

diff --git a/verilog/dv/microwatt/minimal/minimal_tb.v b/verilog/dv/microwatt/minimal/minimal_tb.v
index f1d2bcd..9fdfebf 100644
--- a/verilog/dv/microwatt/minimal/minimal_tb.v
+++ b/verilog/dv/microwatt/minimal/minimal_tb.v
@@ -66,8 +66,8 @@
 	end
 
 	initial begin
-		$dumpfile("minimal.vcd");
-		$dumpvars(0, minimal);
+		//$dumpfile("minimal.vcd");
+		//$dumpvars(0, minimal);
 
 		$display("Microwatt minimal test");
 

verilog/dv/microwatt/simplebus_micropython/simplebus_micropython_tb.v

diff --git a/verilog/dv/microwatt/simplebus_micropython/simplebus_micropython_tb.v b/verilog/dv/microwatt/simplebus_micropython/simplebus_micropython_tb.v
index 2fa8dda..51f647e 100644
--- a/verilog/dv/microwatt/simplebus_micropython/simplebus_micropython_tb.v
+++ b/verilog/dv/microwatt/simplebus_micropython/simplebus_micropython_tb.v
@@ -287,8 +287,8 @@
 	end
 
 	initial begin
-		$dumpfile("simplebus_micropython.vcd");
-		$dumpvars(0, simplebus_micropython_tb);
+		//$dumpfile("simplebus_micropython.vcd");
+		//$dumpvars(0, simplebus_micropython_tb);
 
 		$display("Microwatt external bus minimal test");
 

verilog/dv/microwatt/simplebus_minimal/simplebus_minimal_tb.v

diff --git a/verilog/dv/microwatt/simplebus_minimal/simplebus_minimal_tb.v b/verilog/dv/microwatt/simplebus_minimal/simplebus_minimal_tb.v
index 0e7b493..8045e0a 100644
--- a/verilog/dv/microwatt/simplebus_minimal/simplebus_minimal_tb.v
+++ b/verilog/dv/microwatt/simplebus_minimal/simplebus_minimal_tb.v
@@ -232,8 +232,8 @@
 	end
 
 	initial begin
-		$dumpfile("simplebus_minimal.vcd");
-		$dumpvars(0, simplebus_minimal_tb);
+		//$dumpfile("simplebus_minimal.vcd");
+		//$dumpvars(0, simplebus_minimal_tb);
 
 		$display("Microwatt external bus minimal test");
 

verilog/dv/microwatt/spi_flash/spi_flash_tb.v

diff --git a/verilog/dv/microwatt/spi_flash/spi_flash_tb.v b/verilog/dv/microwatt/spi_flash/spi_flash_tb.v
index e0ed0c4..20cdbbb 100644
--- a/verilog/dv/microwatt/spi_flash/spi_flash_tb.v
+++ b/verilog/dv/microwatt/spi_flash/spi_flash_tb.v
@@ -65,8 +65,8 @@
 	end
 
 	initial begin
-		$dumpfile("spi_flash.vcd");
-		$dumpvars(0, spi_flash);
+		//$dumpfile("spi_flash.vcd");
+		//$dumpvars(0, spi_flash);
 
 		$display("Microwatt SPI flash test");
 

verilog/dv/microwatt/uart/uart_tb.v

diff --git a/verilog/dv/microwatt/uart/uart_tb.v b/verilog/dv/microwatt/uart/uart_tb.v
index 1042382..f39e3c5 100644
--- a/verilog/dv/microwatt/uart/uart_tb.v
+++ b/verilog/dv/microwatt/uart/uart_tb.v
@@ -124,8 +124,8 @@
 	end
 
 	initial begin
-		$dumpfile("uart.vcd");
-		$dumpvars(0, uart_tb);
+		//$dumpfile("uart.vcd");
+		//$dumpvars(0, uart_tb);
 
 		$display("Microwatt UART rx -> tx test");