Modify register file constraints file
The read ports are asynchronous, so don't represent them as referenced
to the clock.
diff --git a/openlane/Microwatt_FP_DFFRFile/base.sdc b/openlane/Microwatt_FP_DFFRFile/base.sdc
new file mode 100644
index 0000000..053b981
--- /dev/null
+++ b/openlane/Microwatt_FP_DFFRFile/base.sdc
@@ -0,0 +1,33 @@
+create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
+set_propagated_clock [get_clocks $::env(CLOCK_PORT)]
+
+set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+puts "\[INFO\]: Setting output delay to: $output_delay_value"
+puts "\[INFO\]: Setting input delay to: $input_delay_value"
+
+set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
+
+set_max_delay 4 -from [get_ports R1] -to [get_ports D1]
+set_max_delay 4 -from [get_ports R2] -to [get_ports D2]
+set_max_delay 4 -from [get_ports R3] -to [get_ports D3]
+
+set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] -add_delay [get_ports WE]
+set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] -add_delay [get_ports RW]
+set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] -add_delay [get_ports DW]
+
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load $cap_load [all_outputs]
+
+puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINITY)"
+set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks $::env(CLOCK_PORT)]
+
+puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
+set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks $::env(CLOCK_PORT)]
+
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
diff --git a/openlane/Microwatt_FP_DFFRFile/config.tcl b/openlane/Microwatt_FP_DFFRFile/config.tcl
index 9de5f97..f5ca6fb 100644
--- a/openlane/Microwatt_FP_DFFRFile/config.tcl
+++ b/openlane/Microwatt_FP_DFFRFile/config.tcl
@@ -8,6 +8,7 @@
set ::env(CLOCK_PORT) "CLK"
set ::env(CLOCK_PERIOD) "10"
set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+set ::env(BASE_SDC_FILE) $script_dir/base.sdc
set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 1150 1150"
