Update register file config.tcl
Instead of constraining the period of register file significantly more
than the rest of the design, increase the input and output I/O delay so
that top level logic and routing has more margin to play with.
diff --git a/openlane/Microwatt_FP_DFFRFile/config.tcl b/openlane/Microwatt_FP_DFFRFile/config.tcl
index 0ed8cab..9de5f97 100644
--- a/openlane/Microwatt_FP_DFFRFile/config.tcl
+++ b/openlane/Microwatt_FP_DFFRFile/config.tcl
@@ -6,7 +6,7 @@
$script_dir/../../verilog/rtl/Microwatt_FP_DFFRFile.v"
set ::env(CLOCK_PORT) "CLK"
-set ::env(CLOCK_PERIOD) "8"
+set ::env(CLOCK_PERIOD) "10"
set ::env(CLOCK_NET) $::env(CLOCK_PORT)
set ::env(FP_SIZING) absolute
@@ -21,7 +21,7 @@
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
# Macro input/output delay - must match liberty file
-set ::env(IO_PCT) 0.2
+set ::env(IO_PCT) 0.3
# Handle PDN
set ::env(VDD_NETS) [list {VPWR} ]
