commit: 41d7fa1b8415845789cf4e5dcf6ea0ac3f422124
[log] [tgz]
author: Anton Blanchard <anton@ozlabs.org>
Sat Oct 30 07:08:50 2021 +1100
committer: Anton Blanchard <anton@ozlabs.org>
Wed Apr 20 21:00:09 2022 +1000
tree: b21c4a844997bdcb850d70795b23d364804ada41
parent: 5f75561d73b53471791584f67617ba9a773c8147 [diff]

Add Microwatt

This adds the Microwatt 64 bit OpenPOWER core with the FPU enabled
and 4kB of DFFRAM.

README.md[diff]
openlane/Microwatt_FP_DFFRFile/config.tcl[Added - diff]
openlane/Microwatt_FP_DFFRFile/pin_order.cfg[Added - diff]
openlane/multiply_add_64x64/config.tcl[Added - diff]
openlane/multiply_add_64x64/pin_order.cfg[Added - diff]
openlane/multiply_add_64x64/src/multiply_add_64x64.v[Added - diff]
openlane/user_project_wrapper/Microwatt_FP_DFFRFile.lib[Added - diff]
openlane/user_project_wrapper/RAM32_1RW1R.lib[Added - diff]
openlane/user_project_wrapper/RAM512.lib[Added - diff]
openlane/user_project_wrapper/base.sdc[Added - diff]
openlane/user_project_wrapper/config.tcl[diff]
openlane/user_project_wrapper/macro.cfg[diff]
openlane/user_project_wrapper/multiply_add_64x64.lib[Added - diff]
openlane/user_project_wrapper/pin_order.cfg[diff]
openlane/user_project_wrapper/scripts/layout.py[Added - diff]
verilog/dv/microwatt/README.md[Added - diff]
verilog/dv/microwatt/include/console.h[Added - diff]
verilog/dv/microwatt/include/io.h[Added - diff]
verilog/dv/microwatt/include/microwatt_soc.h[Added - diff]
verilog/dv/microwatt/include/microwatt_util.h[Added - diff]
verilog/dv/microwatt/jtag/Makefile[Added - diff]
verilog/dv/microwatt/jtag/jtag_tb.v[Added - diff]
verilog/dv/microwatt/jtag/microwatt.c[Added - diff]
verilog/dv/microwatt/lib/console.c[Added - diff]
verilog/dv/microwatt/lib/head.S[Added - diff]
verilog/dv/microwatt/make.env[Added - diff]
verilog/dv/microwatt/make.rules[Added - diff]
verilog/dv/microwatt/memory_test/Makefile[Added - diff]
verilog/dv/microwatt/memory_test/hash.h[Added - diff]
verilog/dv/microwatt/memory_test/memory_test_tb.v[Added - diff]
verilog/dv/microwatt/memory_test/microwatt.c[Added - diff]
verilog/dv/microwatt/memory_test/tbuart_modified.v[Added - diff]
verilog/dv/microwatt/microwatt.lds[Added - diff]
verilog/dv/microwatt/minimal/Makefile[Added - diff]
verilog/dv/microwatt/minimal/head.S[Added - diff]
verilog/dv/microwatt/minimal/minimal_tb.v[Added - diff]
verilog/dv/microwatt/simplebus_micropython/Makefile[Added - diff]
verilog/dv/microwatt/simplebus_micropython/bin2hex.py[Added - diff]
verilog/dv/microwatt/simplebus_micropython/micropython.bin[Added - diff]
verilog/dv/microwatt/simplebus_micropython/microwatt.c[Added - diff]
verilog/dv/microwatt/simplebus_micropython/simplebus_micropython_tb.v[Added - diff]
verilog/dv/microwatt/simplebus_micropython/tbuart_modified.v[Added - diff]
verilog/dv/microwatt/simplebus_minimal/Makefile[Added - diff]
verilog/dv/microwatt/simplebus_minimal/microwatt.c[Added - diff]
verilog/dv/microwatt/simplebus_minimal/simplebus_minimal_tb.v[Added - diff]
verilog/dv/microwatt/spi_flash/Makefile[Added - diff]
verilog/dv/microwatt/spi_flash/gen_hash.c[Added - diff]
verilog/dv/microwatt/spi_flash/hash.h[Added - diff]
verilog/dv/microwatt/spi_flash/lfsr32.c[Added - diff]
verilog/dv/microwatt/spi_flash/lfsr32.h[Added - diff]
verilog/dv/microwatt/spi_flash/microwatt.c[Added - diff]
verilog/dv/microwatt/spi_flash/spi_flash_tb.v[Added - diff]
verilog/dv/microwatt/spi_flash/tbuart_modified.v[Added - diff]
verilog/dv/microwatt/uart/Makefile[Added - diff]
verilog/dv/microwatt/uart/microwatt.c[Added - diff]
verilog/dv/microwatt/uart/uart_tb.v[Added - diff]
verilog/rtl/Microwatt_FP_DFFRFile.v[Added - diff]
verilog/rtl/RAM32_1RW1R.v[Added - diff]
verilog/rtl/RAM512.v[Added - diff]
verilog/rtl/microwatt.v[Added - diff]
verilog/rtl/multiply_add_64x64.v[Added - diff]
verilog/rtl/raminfr.v[Added - diff]
verilog/rtl/simplebus_host.v[Added - diff]
verilog/rtl/tap_top.v[Added - diff]
verilog/rtl/uart_defines.v[Added - diff]
verilog/rtl/uart_receiver.v[Added - diff]
verilog/rtl/uart_regs.v[Added - diff]
verilog/rtl/uart_rfifo.v[Added - diff]
verilog/rtl/uart_sync_flops.v[Added - diff]
verilog/rtl/uart_tfifo.v[Added - diff]
verilog/rtl/uart_top.v[Added - diff]
verilog/rtl/uart_transmitter.v[Added - diff]
verilog/rtl/uart_wb.v[Added - diff]
verilog/rtl/uprj_netlists.v[diff]
verilog/rtl/user_defines.v[Added - diff]
verilog/rtl/user_project_wrapper.v[diff]
verilog/rtl/wrapper/Microwatt_FP_DFFRFile.v[Added - diff]
verilog/rtl/wrapper/RAM32_1RW1R.v[Added - diff]
verilog/rtl/wrapper/RAM512.v[Added - diff]
verilog/rtl/wrapper/multiply_add_64x64.v[Added - diff]

80 files changed

tree: b21c4a844997bdcb850d70795b23d364804ada41

README.md

Caravel User Project

Microwatt on Caravel

The Microwatt 64 bit OpenPOWER core integrated into the Caravel SKY130 shuttles.

Tests

Check out verilog/dv/caravel/microwatt/README.md