Add paths and defines to allow partial GL sim
diff --git a/verilog/dv/microwatt/make.env b/verilog/dv/microwatt/make.env
index 07e8925..5ada673 100644
--- a/verilog/dv/microwatt/make.env
+++ b/verilog/dv/microwatt/make.env
@@ -36,7 +36,7 @@
POWERPC_CFLAGS=-static -Os -g -Wall -std=c99 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -ffreestanding -fdata-sections -ffunction-sections -nostdlib -I../include
## Simulation mode: RTL/GL
-SIM_DEFINES = -DFUNCTIONAL -DSIM
+SIM_DEFINES = -DFUNCTIONAL -DSIM -DUNIT_DELAY=\#1 -DUSE_POWER_PINS
SIM?=RTL
.SUFFIXES:
diff --git a/verilog/dv/microwatt/make.rules b/verilog/dv/microwatt/make.rules
index 17cf027..3d17955 100644
--- a/verilog/dv/microwatt/make.rules
+++ b/verilog/dv/microwatt/make.rules
@@ -22,8 +22,8 @@
%.vvp: %_tb.v microwatt.hex check-env
ifeq ($(SIM),RTL)
iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
- -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
-I $(CARAVEL_MGMT_RTL_PATH) \
$< -o $@
else
