Update liberty files
diff --git a/openlane/user_project_wrapper/Microwatt_FP_DFFRFile.lib b/openlane/user_project_wrapper/Microwatt_FP_DFFRFile.lib
index 15ab21d..cfe317c 100644
--- a/openlane/user_project_wrapper/Microwatt_FP_DFFRFile.lib
+++ b/openlane/user_project_wrapper/Microwatt_FP_DFFRFile.lib
@@ -1,3 +1,4 @@
+
library (Microwatt_FP_DFFRFile_lib) {
delay_model : "table_lookup";
time_unit : "1ns";
@@ -65,205 +66,43 @@
voltage_name : "VGND";
}
- pin(WE) {
- direction : input;
- related_ground_pin : "VGND";
- related_power_pin : "VPWR";
-
- /* sky130_fd_sc_hd__buf_1 */
- capacitance : 0.0021030000;
- rise_capacitance : 0.0021910000;
- fall_capacitance : 0.0020150000;
- max_transition : 1.5;
-
- timing() {
- timing_type : setup_rising;
- related_pin : "CLK";
- rise_constraint(scalar) {
- values("8.0");
- }
- fall_constraint(scalar) {
- values("8.0");
- }
- }
- timing() {
- timing_type : hold_rising;
- related_pin : "CLK";
- rise_constraint(scalar) {
- values("2.0");
- }
- fall_constraint(scalar) {
- values("2.0");
- }
- }
- }
-
bus(R1) {
bus_type : bits_7;
+ clock : false;
direction : input;
related_ground_pin : "VGND";
related_power_pin : "VPWR";
- /* sky130_fd_sc_hd__buf_1 */
- capacitance : 0.0021030000;
- rise_capacitance : 0.0021910000;
- fall_capacitance : 0.0020150000;
+ capacitance : 0.002103;
+ rise_capacitance : 0.002191;
+ fall_capacitance : 0.002015;
max_transition : 1.5;
-
- timing() {
- timing_type : setup_rising;
- related_pin : "CLK";
- rise_constraint(scalar) {
- values("8.0");
- }
- fall_constraint(scalar) {
- values("8.0");
- }
- }
- timing() {
- timing_type : hold_rising;
- related_pin : "CLK";
- rise_constraint(scalar) {
- values("2.0");
- }
- fall_constraint(scalar) {
- values("2.0");
- }
- }
}
bus(R2) {
bus_type : bits_7;
+ clock : false;
direction : input;
+ related_ground_pin : "VGND";
+ related_power_pin : "VPWR";
- /* sky130_fd_sc_hd__buf_1 */
- capacitance : 0.0021030000;
- rise_capacitance : 0.0021910000;
- fall_capacitance : 0.0020150000;
+ capacitance : 0.002103;
+ rise_capacitance : 0.002191;
+ fall_capacitance : 0.002015;
max_transition : 1.5;
-
- timing() {
- timing_type : setup_rising;
- related_pin : "CLK";
- rise_constraint(scalar) {
- values("8.0");
- }
- fall_constraint(scalar) {
- values("8.0");
- }
- }
- timing() {
- timing_type : hold_rising;
- related_pin : "CLK";
- rise_constraint(scalar) {
- values("2.0");
- }
- fall_constraint(scalar) {
- values("2.0");
- }
- }
}
bus(R3) {
bus_type : bits_7;
+ clock : false;
direction : input;
related_ground_pin : "VGND";
related_power_pin : "VPWR";
- /* sky130_fd_sc_hd__buf_1 */
- capacitance : 0.0021030000;
- rise_capacitance : 0.0021910000;
- fall_capacitance : 0.0020150000;
+ capacitance : 0.002103;
+ rise_capacitance : 0.002191;
+ fall_capacitance : 0.002015;
max_transition : 1.5;
-
- timing() {
- timing_type : setup_rising;
- related_pin : "CLK";
- rise_constraint(scalar) {
- values("8.0");
- }
- fall_constraint(scalar) {
- values("8.0");
- }
- }
- timing() {
- timing_type : hold_rising;
- related_pin : "CLK";
- rise_constraint(scalar) {
- values("2.0");
- }
- fall_constraint(scalar) {
- values("2.0");
- }
- }
- }
-
- bus(RW) {
- bus_type : bits_7;
- direction : input;
- related_ground_pin : "VGND";
- related_power_pin : "VPWR";
-
- /* sky130_fd_sc_hd__buf_1 */
- capacitance : 0.0021030000;
- rise_capacitance : 0.0021910000;
- fall_capacitance : 0.0020150000;
- max_transition : 1.5;
-
- timing() {
- timing_type : setup_rising;
- related_pin : "CLK";
- rise_constraint(scalar) {
- values("8.0");
- }
- fall_constraint(scalar) {
- values("8.0");
- }
- }
- timing() {
- timing_type : hold_rising;
- related_pin : "CLK";
- rise_constraint(scalar) {
- values("2.0");
- }
- fall_constraint(scalar) {
- values("2.0");
- }
- }
- }
-
- bus(DW) {
- bus_type : bits_64;
- direction : input;
- related_ground_pin : "VGND";
- related_power_pin : "VPWR";
-
- /* sky130_fd_sc_hd__buf_1 */
- capacitance : 0.0021030000;
- rise_capacitance : 0.0021910000;
- fall_capacitance : 0.0020150000;
- max_transition : 1.5;
-
- timing() {
- timing_type : setup_rising;
- related_pin : "CLK";
- rise_constraint(scalar) {
- values("8.0");
- }
- fall_constraint(scalar) {
- values("8.0");
- }
- }
- timing() {
- timing_type : hold_rising;
- related_pin : "CLK";
- rise_constraint(scalar) {
- values("2.0");
- }
- fall_constraint(scalar) {
- values("2.0");
- }
- }
}
bus(D1) {
@@ -272,27 +111,25 @@
related_ground_pin : "VGND";
related_power_pin : "VPWR";
- /* sky130_fd_sc_hd__buf_1 */
- max_capacitance : 0.1300150000;
- max_transition : 1.5061030000;
-
+ max_capacitance : 0.130015;
+ max_transition : 1.5;
timing() {
- related_pin : "CLK";
- timing_sense : non_unate
+ related_pin : "D1";
timing_type : rising_edge
cell_rise(scalar) {
- values("8.0");
+ values("3.2700");
}
cell_fall(scalar) {
- values("8.0");
+ values("3.2700");
}
rise_transition(scalar) {
- values("0.75");
+ values("0.7500");
}
fall_transition(scalar) {
- values("0.75");
+ values("0.7500");
}
}
+
}
bus(D2) {
@@ -301,68 +138,167 @@
related_ground_pin : "VGND";
related_power_pin : "VPWR";
- /* sky130_fd_sc_hd__buf_1 */
- max_capacitance : 0.1300150000;
- max_transition : 1.5061030000;
-
+ max_capacitance : 0.130015;
+ max_transition : 1.5;
timing() {
- related_pin : "CLK";
- timing_sense : non_unate
+ related_pin : "D1";
timing_type : rising_edge
cell_rise(scalar) {
- values("8.0");
+ values("3.4100");
}
cell_fall(scalar) {
- values("8.0");
+ values("3.4100");
}
rise_transition(scalar) {
- values("0.75");
+ values("0.7500");
}
fall_transition(scalar) {
- values("0.75");
+ values("0.7500");
}
}
+
}
-
+
bus(D3) {
bus_type : bits_64;
direction : output;
related_ground_pin : "VGND";
related_power_pin : "VPWR";
- /* sky130_fd_sc_hd__buf_1 */
- max_capacitance : 0.1300150000;
- max_transition : 1.5061030000;
-
+ max_capacitance : 0.130015;
+ max_transition : 1.5;
timing() {
- related_pin : "CLK";
- timing_sense : non_unate
+ related_pin : "D1";
timing_type : rising_edge
cell_rise(scalar) {
- values("8.0");
+ values("3.3000");
}
cell_fall(scalar) {
- values("8.0");
+ values("3.3000");
}
rise_transition(scalar) {
- values("0.75");
+ values("0.7500");
}
fall_transition(scalar) {
- values("0.75");
+ values("0.7500");
}
}
+
}
-
+
+ bus(RW) {
+ bus_type : bits_7;
+ clock : false;
+ direction : input;
+ related_ground_pin : "VGND";
+ related_power_pin : "VPWR";
+
+ capacitance : 0.002103;
+ rise_capacitance : 0.002191;
+ fall_capacitance : 0.002015;
+ max_transition : 1.5;
+ timing() {
+ timing_type : setup_rising;
+ related_pin : "CLK";
+ rise_constraint(scalar) {
+ values("1.3300");
+ }
+ fall_constraint(scalar) {
+ values("1.3300");
+ }
+ }
+
+ timing() {
+ timing_type : hold_rising;
+ related_pin : "CLK";
+ rise_constraint(scalar) {
+ values("1.6800");
+ }
+ fall_constraint(scalar) {
+ values("1.6800");
+ }
+ }
+
+ }
+
+ pin(WE) {
+ clock : false;
+ direction : input;
+ related_ground_pin : "VGND";
+ related_power_pin : "VPWR";
+
+ capacitance : 0.002103;
+ rise_capacitance : 0.002191;
+ fall_capacitance : 0.002015;
+ max_transition : 1.5;
+ timing() {
+ timing_type : setup_rising;
+ related_pin : "CLK";
+ rise_constraint(scalar) {
+ values("1.2800");
+ }
+ fall_constraint(scalar) {
+ values("1.2800");
+ }
+ }
+
+ timing() {
+ timing_type : hold_rising;
+ related_pin : "CLK";
+ rise_constraint(scalar) {
+ values("1.7000");
+ }
+ fall_constraint(scalar) {
+ values("1.7000");
+ }
+ }
+
+ }
+
+ bus(DW) {
+ bus_type : bits_64;
+ clock : false;
+ direction : input;
+ related_ground_pin : "VGND";
+ related_power_pin : "VPWR";
+
+ capacitance : 0.002103;
+ rise_capacitance : 0.002191;
+ fall_capacitance : 0.002015;
+ max_transition : 1.5;
+ timing() {
+ timing_type : setup_rising;
+ related_pin : "CLK";
+ rise_constraint(scalar) {
+ values("-0.3400");
+ }
+ fall_constraint(scalar) {
+ values("-0.3400");
+ }
+ }
+
+ timing() {
+ timing_type : hold_rising;
+ related_pin : "CLK";
+ rise_constraint(scalar) {
+ values("1.6700");
+ }
+ fall_constraint(scalar) {
+ values("1.6700");
+ }
+ }
+
+ }
+
pin(CLK) {
clock : true;
direction : input;
related_ground_pin : "VGND";
related_power_pin : "VPWR";
- /* sky130_fd_sc_hd__buf_1 */
- capacitance : 0.0021030000;
- rise_capacitance : 0.0021910000;
- fall_capacitance : 0.0020150000;
+ capacitance : 0.002103;
+ rise_capacitance : 0.002191;
+ fall_capacitance : 0.002015;
max_transition : 1.5;
}
}
diff --git a/openlane/user_project_wrapper/RAM32_1RW1R.lib b/openlane/user_project_wrapper/RAM32_1RW1R.lib
index e8c61c1..990c680 100644
--- a/openlane/user_project_wrapper/RAM32_1RW1R.lib
+++ b/openlane/user_project_wrapper/RAM32_1RW1R.lib
@@ -1,3 +1,4 @@
+
library (RAM32_1RW1R_lib) {
delay_model : "table_lookup";
time_unit : "1ns";
@@ -74,204 +75,212 @@
}
pin(EN0) {
+ clock : false;
direction : input;
related_ground_pin : "VGND";
related_power_pin : "VPWR";
- /* sky130_fd_sc_hd__buf_1 */
- capacitance : 0.0021030000;
- rise_capacitance : 0.0021910000;
- fall_capacitance : 0.0020150000;
+ capacitance : 0.002103;
+ rise_capacitance : 0.002191;
+ fall_capacitance : 0.002015;
max_transition : 1.5;
-
timing() {
- timing_type : setup_rising;
+ timing_type : setup_falling;
related_pin : "CLK";
rise_constraint(scalar) {
- values("10.9");
+ values("1.0600");
}
fall_constraint(scalar) {
- values("10.9");
+ values("1.0600");
}
}
+
timing() {
timing_type : hold_rising;
related_pin : "CLK";
rise_constraint(scalar) {
- values("3.7");
+ values("1.5700");
}
fall_constraint(scalar) {
- values("3.7");
+ values("1.5700");
}
}
- }
- pin(EN1) {
- direction : input;
- related_ground_pin : "VGND";
- related_power_pin : "VPWR";
-
- /* sky130_fd_sc_hd__buf_1 */
- capacitance : 0.0021030000;
- rise_capacitance : 0.0021910000;
- fall_capacitance : 0.0020150000;
- max_transition : 1.5;
-
- timing() {
- timing_type : setup_rising;
- related_pin : "CLK";
- rise_constraint(scalar) {
- values("10.9");
- }
- fall_constraint(scalar) {
- values("10.9");
- }
- }
- timing() {
- timing_type : hold_rising;
- related_pin : "CLK";
- rise_constraint(scalar) {
- values("3.7");
- }
- fall_constraint(scalar) {
- values("3.7");
- }
- }
}
bus(WE0) {
bus_type : bits_8;
+ clock : false;
direction : input;
related_ground_pin : "VGND";
related_power_pin : "VPWR";
- /* sky130_fd_sc_hd__buf_1 */
- capacitance : 0.0021030000;
- rise_capacitance : 0.0021910000;
- fall_capacitance : 0.0020150000;
+ capacitance : 0.002103;
+ rise_capacitance : 0.002191;
+ fall_capacitance : 0.002015;
max_transition : 1.5;
-
timing() {
- timing_type : setup_rising;
+ timing_type : setup_falling;
related_pin : "CLK";
rise_constraint(scalar) {
- values("10.9");
+ values("-0.2200");
}
fall_constraint(scalar) {
- values("10.9");
+ values("-0.2200");
}
}
+
timing() {
timing_type : hold_rising;
related_pin : "CLK";
rise_constraint(scalar) {
- values("3.7");
+ values("0.0000");
}
fall_constraint(scalar) {
- values("3.7");
+ values("0.0000");
}
}
+
}
+
bus(Di0) {
bus_type : bits_64;
+ clock : false;
direction : input;
+ related_ground_pin : "VGND";
+ related_power_pin : "VPWR";
- /* sky130_fd_sc_hd__buf_1 */
- capacitance : 0.0021030000;
- rise_capacitance : 0.0021910000;
- fall_capacitance : 0.0020150000;
+ capacitance : 0.002103;
+ rise_capacitance : 0.002191;
+ fall_capacitance : 0.002015;
max_transition : 1.5;
-
timing() {
timing_type : setup_rising;
related_pin : "CLK";
rise_constraint(scalar) {
- values("10.9");
+ values("-0.9800");
}
fall_constraint(scalar) {
- values("10.9");
+ values("-0.9800");
}
}
+
timing() {
timing_type : hold_rising;
related_pin : "CLK";
rise_constraint(scalar) {
- values("3.7");
+ values("2.1200");
}
fall_constraint(scalar) {
- values("3.7");
+ values("2.1200");
}
}
+
}
bus(A0) {
bus_type : bits_5;
+ clock : false;
direction : input;
related_ground_pin : "VGND";
related_power_pin : "VPWR";
- /* sky130_fd_sc_hd__buf_1 */
- capacitance : 0.0021030000;
- rise_capacitance : 0.0021910000;
- fall_capacitance : 0.0020150000;
+ capacitance : 0.002103;
+ rise_capacitance : 0.002191;
+ fall_capacitance : 0.002015;
max_transition : 1.5;
-
timing() {
- timing_type : setup_rising;
+ timing_type : setup_falling;
related_pin : "CLK";
rise_constraint(scalar) {
- values("10.9");
+ values("0.8800");
}
fall_constraint(scalar) {
- values("10.9");
+ values("0.8800");
}
}
+
timing() {
timing_type : hold_rising;
related_pin : "CLK";
rise_constraint(scalar) {
- values("3.7");
+ values("1.5700");
}
fall_constraint(scalar) {
- values("3.7");
+ values("1.5700");
}
}
+
+ }
+
+ pin(EN1) {
+ clock : false;
+ direction : input;
+ related_ground_pin : "VGND";
+ related_power_pin : "VPWR";
+
+ capacitance : 0.002103;
+ rise_capacitance : 0.002191;
+ fall_capacitance : 0.002015;
+ max_transition : 1.5;
+ timing() {
+ timing_type : setup_rising;
+ related_pin : "CLK";
+ rise_constraint(scalar) {
+ values("4.1200");
+ }
+ fall_constraint(scalar) {
+ values("4.1200");
+ }
+ }
+
+ timing() {
+ timing_type : hold_rising;
+ related_pin : "CLK";
+ rise_constraint(scalar) {
+ values("1.5300");
+ }
+ fall_constraint(scalar) {
+ values("1.5300");
+ }
+ }
+
}
bus(A1) {
bus_type : bits_5;
+ clock : false;
direction : input;
related_ground_pin : "VGND";
related_power_pin : "VPWR";
- /* sky130_fd_sc_hd__buf_1 */
- capacitance : 0.0021030000;
- rise_capacitance : 0.0021910000;
- fall_capacitance : 0.0020150000;
+ capacitance : 0.002103;
+ rise_capacitance : 0.002191;
+ fall_capacitance : 0.002015;
max_transition : 1.5;
-
timing() {
timing_type : setup_rising;
related_pin : "CLK";
rise_constraint(scalar) {
- values("10.9");
+ values("4.0300");
}
fall_constraint(scalar) {
- values("10.9");
+ values("4.0300");
}
}
+
timing() {
timing_type : hold_rising;
related_pin : "CLK";
rise_constraint(scalar) {
- values("3.7");
+ values("1.5400");
}
fall_constraint(scalar) {
- values("3.7");
+ values("1.5400");
}
}
- }
+ }
bus(Do0) {
bus_type : bits_64;
@@ -279,27 +288,25 @@
related_ground_pin : "VGND";
related_power_pin : "VPWR";
- /* sky130_fd_sc_hd__buf_1 */
- max_capacitance : 0.1300150000;
- max_transition : 1.5061030000;
-
+ max_capacitance : 0.130015;
+ max_transition : 1.5;
timing() {
related_pin : "CLK";
- timing_sense : non_unate
timing_type : rising_edge
cell_rise(scalar) {
- values("10.9");
+ values("2.2000");
}
cell_fall(scalar) {
- values("10.9");
+ values("2.2000");
}
rise_transition(scalar) {
- values("0.75");
+ values("0.7500");
}
fall_transition(scalar) {
- values("0.75");
+ values("0.7500");
}
}
+
}
bus(Do1) {
@@ -308,39 +315,36 @@
related_ground_pin : "VGND";
related_power_pin : "VPWR";
- /* sky130_fd_sc_hd__buf_1 */
- max_capacitance : 0.1300150000;
- max_transition : 1.5061030000;
-
+ max_capacitance : 0.130015;
+ max_transition : 1.5;
timing() {
related_pin : "CLK";
- timing_sense : non_unate
timing_type : rising_edge
cell_rise(scalar) {
- values("10.9");
+ values("2.4400");
}
cell_fall(scalar) {
- values("10.9");
+ values("2.4400");
}
rise_transition(scalar) {
- values("0.75");
+ values("0.7500");
}
fall_transition(scalar) {
- values("0.75");
+ values("0.7500");
}
}
+
}
-
+
pin(CLK) {
clock : true;
direction : input;
related_ground_pin : "VGND";
related_power_pin : "VPWR";
- /* sky130_fd_sc_hd__buf_1 */
- capacitance : 0.0021030000;
- rise_capacitance : 0.0021910000;
- fall_capacitance : 0.0020150000;
+ capacitance : 0.002103;
+ rise_capacitance : 0.002191;
+ fall_capacitance : 0.002015;
max_transition : 1.5;
}
}
diff --git a/openlane/user_project_wrapper/RAM512.lib b/openlane/user_project_wrapper/RAM512.lib
index cd9120f..45242c8 100644
--- a/openlane/user_project_wrapper/RAM512.lib
+++ b/openlane/user_project_wrapper/RAM512.lib
@@ -1,3 +1,4 @@
+
library (RAM512_lib) {
delay_model : "table_lookup";
time_unit : "1ns";
@@ -74,135 +75,142 @@
}
pin(EN0) {
+ clock : false;
direction : input;
related_ground_pin : "VGND";
related_power_pin : "VPWR";
- /* sky130_fd_sc_hd__buf_1 */
- capacitance : 0.0021030000;
- rise_capacitance : 0.0021910000;
- fall_capacitance : 0.0020150000;
+ capacitance : 0.002103;
+ rise_capacitance : 0.002191;
+ fall_capacitance : 0.002015;
max_transition : 1.5;
-
timing() {
- timing_type : setup_rising;
+ timing_type : setup_falling;
related_pin : "CLK";
rise_constraint(scalar) {
- values("11.25");
+ values("2.4000");
}
fall_constraint(scalar) {
- values("11.25");
+ values("2.4000");
}
}
+
timing() {
timing_type : hold_rising;
related_pin : "CLK";
rise_constraint(scalar) {
- values("1.00");
+ values("2.8400");
}
fall_constraint(scalar) {
- values("1.00");
+ values("2.8400");
}
}
+
}
bus(WE0) {
bus_type : bits_8;
+ clock : false;
direction : input;
related_ground_pin : "VGND";
related_power_pin : "VPWR";
- /* sky130_fd_sc_hd__buf_1 */
- capacitance : 0.0021030000;
- rise_capacitance : 0.0021910000;
- fall_capacitance : 0.0020150000;
+ capacitance : 0.002103;
+ rise_capacitance : 0.002191;
+ fall_capacitance : 0.002015;
max_transition : 1.5;
-
timing() {
- timing_type : setup_rising;
+ timing_type : setup_falling;
related_pin : "CLK";
rise_constraint(scalar) {
- values("11.25");
+ values("0.4500");
}
fall_constraint(scalar) {
- values("4.0");
+ values("0.4500");
}
}
+
timing() {
timing_type : hold_rising;
related_pin : "CLK";
rise_constraint(scalar) {
- values("3.75");
+ values("0.0000");
}
fall_constraint(scalar) {
- values("3.75");
+ values("0.0000");
}
}
+
}
+
bus(Di0) {
bus_type : bits_64;
+ clock : false;
direction : input;
+ related_ground_pin : "VGND";
+ related_power_pin : "VPWR";
- /* sky130_fd_sc_hd__buf_1 */
- capacitance : 0.0021030000;
- rise_capacitance : 0.0021910000;
- fall_capacitance : 0.0020150000;
+ capacitance : 0.002103;
+ rise_capacitance : 0.002191;
+ fall_capacitance : 0.002015;
max_transition : 1.5;
-
timing() {
timing_type : setup_rising;
related_pin : "CLK";
rise_constraint(scalar) {
- values("11.25");
+ values("-0.6900");
}
fall_constraint(scalar) {
- values("4.0");
+ values("-0.6900");
}
}
+
timing() {
timing_type : hold_rising;
related_pin : "CLK";
rise_constraint(scalar) {
- values("3.75");
+ values("3.2000");
}
fall_constraint(scalar) {
- values("3.75");
+ values("3.2000");
}
}
+
}
bus(A0) {
bus_type : bits_9;
+ clock : false;
direction : input;
related_ground_pin : "VGND";
related_power_pin : "VPWR";
- /* sky130_fd_sc_hd__buf_1 */
- capacitance : 0.0021030000;
- rise_capacitance : 0.0021910000;
- fall_capacitance : 0.0020150000;
+ capacitance : 0.002103;
+ rise_capacitance : 0.002191;
+ fall_capacitance : 0.002015;
max_transition : 1.5;
-
timing() {
- timing_type : setup_rising;
+ timing_type : setup_falling;
related_pin : "CLK";
rise_constraint(scalar) {
- values("11.25");
+ values("3.2500");
}
fall_constraint(scalar) {
- values("11.25");
+ values("3.2500");
}
}
+
timing() {
timing_type : hold_rising;
related_pin : "CLK";
rise_constraint(scalar) {
- values("3.75");
+ values("3.1200");
}
fall_constraint(scalar) {
- values("3.75");
+ values("3.1200");
}
}
+
}
bus(Do0) {
@@ -211,39 +219,36 @@
related_ground_pin : "VGND";
related_power_pin : "VPWR";
- /* sky130_fd_sc_hd__buf_1 */
- max_capacitance : 0.1300150000;
- max_transition : 1.5061030000;
-
+ max_capacitance : 0.130015;
+ max_transition : 1.5;
timing() {
- related_pin : "CLK";
- timing_sense : non_unate
+ related_pin : "A0";
timing_type : rising_edge
cell_rise(scalar) {
- values("11.25");
+ values("4.9300");
}
cell_fall(scalar) {
- values("11.25");
+ values("4.9300");
}
rise_transition(scalar) {
- values("0.75");
+ values("0.7500");
}
fall_transition(scalar) {
- values("0.75");
+ values("0.7500");
}
}
+
}
-
+
pin(CLK) {
clock : true;
direction : input;
related_ground_pin : "VGND";
related_power_pin : "VPWR";
- /* sky130_fd_sc_hd__buf_1 */
- capacitance : 0.0021030000;
- rise_capacitance : 0.0021910000;
- fall_capacitance : 0.0020150000;
+ capacitance : 0.002103;
+ rise_capacitance : 0.002191;
+ fall_capacitance : 0.002015;
max_transition : 1.5;
}
}
diff --git a/openlane/user_project_wrapper/multiply_add_64x64.lib b/openlane/user_project_wrapper/multiply_add_64x64.lib
index e3a1b54..82a6da9 100644
--- a/openlane/user_project_wrapper/multiply_add_64x64.lib
+++ b/openlane/user_project_wrapper/multiply_add_64x64.lib
@@ -1,3 +1,4 @@
+
library (multiply_add_64x64_lib) {
delay_model : "table_lookup";
time_unit : "1ns";
@@ -66,136 +67,142 @@
}
pin(rst) {
+ clock : false;
direction : input;
related_ground_pin : "VGND";
related_power_pin : "VPWR";
- /* sky130_fd_sc_hd__buf_1 */
- capacitance : 0.0021030000;
- rise_capacitance : 0.0021910000;
- fall_capacitance : 0.0020150000;
+ capacitance : 0.002103;
+ rise_capacitance : 0.002191;
+ fall_capacitance : 0.002015;
max_transition : 1.5;
-
timing() {
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(scalar) {
- values("8.0");
+ values("0.0000");
}
fall_constraint(scalar) {
- values("8.0");
+ values("0.0000");
}
}
+
timing() {
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(scalar) {
- values("2.0");
+ values("0.0000");
}
fall_constraint(scalar) {
- values("2.0");
+ values("0.0000");
}
}
+
}
bus(a) {
bus_type : bits_64;
+ clock : false;
direction : input;
related_ground_pin : "VGND";
related_power_pin : "VPWR";
- /* sky130_fd_sc_hd__buf_1 */
- capacitance : 0.0021030000;
- rise_capacitance : 0.0021910000;
- fall_capacitance : 0.0020150000;
+ capacitance : 0.002103;
+ rise_capacitance : 0.002191;
+ fall_capacitance : 0.002015;
max_transition : 1.5;
-
timing() {
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(scalar) {
- values("8.0");
+ values("5.0900");
}
fall_constraint(scalar) {
- values("8.0");
+ values("5.0900");
}
}
+
timing() {
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(scalar) {
- values("2.0");
+ values("0.8300");
}
fall_constraint(scalar) {
- values("2.0");
+ values("0.8300");
}
}
+
}
bus(b) {
bus_type : bits_64;
- direction : input;
-
- /* sky130_fd_sc_hd__buf_1 */
- capacitance : 0.0021030000;
- rise_capacitance : 0.0021910000;
- fall_capacitance : 0.0020150000;
- max_transition : 1.5;
-
- timing() {
- timing_type : setup_rising;
- related_pin : "clk";
- rise_constraint(scalar) {
- values("8.0");
- }
- fall_constraint(scalar) {
- values("8.0");
- }
- }
- timing() {
- timing_type : hold_rising;
- related_pin : "clk";
- rise_constraint(scalar) {
- values("2.0");
- }
- fall_constraint(scalar) {
- values("2.0");
- }
- }
- }
-
- bus(c) {
- bus_type : bits_128;
+ clock : false;
direction : input;
related_ground_pin : "VGND";
related_power_pin : "VPWR";
- /* sky130_fd_sc_hd__buf_1 */
- capacitance : 0.0021030000;
- rise_capacitance : 0.0021910000;
- fall_capacitance : 0.0020150000;
+ capacitance : 0.002103;
+ rise_capacitance : 0.002191;
+ fall_capacitance : 0.002015;
max_transition : 1.5;
-
timing() {
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(scalar) {
- values("8.0");
+ values("4.7000");
}
fall_constraint(scalar) {
- values("8.0");
+ values("4.7000");
}
}
+
timing() {
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(scalar) {
- values("2.0");
+ values("0.8600");
}
fall_constraint(scalar) {
- values("2.0");
+ values("0.8600");
}
}
+
+ }
+
+ bus(c) {
+ bus_type : bits_128;
+ clock : false;
+ direction : input;
+ related_ground_pin : "VGND";
+ related_power_pin : "VPWR";
+
+ capacitance : 0.002103;
+ rise_capacitance : 0.002191;
+ fall_capacitance : 0.002015;
+ max_transition : 1.5;
+ timing() {
+ timing_type : setup_rising;
+ related_pin : "clk";
+ rise_constraint(scalar) {
+ values("2.9700");
+ }
+ fall_constraint(scalar) {
+ values("2.9700");
+ }
+ }
+
+ timing() {
+ timing_type : hold_rising;
+ related_pin : "clk";
+ rise_constraint(scalar) {
+ values("0.8500");
+ }
+ fall_constraint(scalar) {
+ values("0.8500");
+ }
+ }
+
}
bus(o) {
@@ -204,39 +211,36 @@
related_ground_pin : "VGND";
related_power_pin : "VPWR";
- /* sky130_fd_sc_hd__buf_1 */
- max_capacitance : 0.1300150000;
- max_transition : 1.5061030000;
-
+ max_capacitance : 0.130015;
+ max_transition : 1.5;
timing() {
related_pin : "clk";
- timing_sense : non_unate
timing_type : rising_edge
cell_rise(scalar) {
- values("8.0");
+ values("3.9600");
}
cell_fall(scalar) {
- values("8.0");
+ values("3.9600");
}
rise_transition(scalar) {
- values("0.75");
+ values("0.7500");
}
fall_transition(scalar) {
- values("0.75");
+ values("0.7500");
}
}
+
}
-
+
pin(clk) {
clock : true;
direction : input;
related_ground_pin : "VGND";
related_power_pin : "VPWR";
- /* sky130_fd_sc_hd__buf_1 */
- capacitance : 0.0021030000;
- rise_capacitance : 0.0021910000;
- fall_capacitance : 0.0020150000;
+ capacitance : 0.002103;
+ rise_capacitance : 0.002191;
+ fall_capacitance : 0.002015;
max_transition : 1.5;
}
}
