test fixed
diff --git a/openlane/aes/config.tcl b/openlane/aes/config.tcl
index bdec18d..971f604 100755
--- a/openlane/aes/config.tcl
+++ b/openlane/aes/config.tcl
@@ -28,20 +28,20 @@
set ::env(CLOCK_PORT) "clock"
set ::env(CLOCK_NET) "aes.clock"
-set ::env(CLOCK_PERIOD) "50"
+set ::env(CLOCK_PERIOD) "15"
#Specifies a time margin for the slack when fixing hold violations.
#Normally the resizer will stop when it reaches zero slack.
# This option allows you to overfix. (Default: 0.1ns)
-set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) {0.6}
-set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) {0.6}
+set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) {0.9}
+set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) {0.9}
#area
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 800 1000"
+set ::env(DIE_AREA) "0 0 800 800"
set ::env(PL_TARGET_DENSITY) 0.3
#set ::env(PL_BASIC_PLACEMENT) 1
set ::env(GLB_RT_ALLOW_CONGESTION) 1
@@ -63,6 +63,6 @@
set ::env(VDD_NETS) [list {vccd1}]
set ::env(GND_NETS) [list {vssd1}]
-set ::env(DIODE_INSERTION_STRATEGY) 4
+set ::env(DIODE_INSERTION_STRATEGY) 1
# If you're going to use multiple power domains, then disable cvc run.
set ::env(RUN_CVC) 1
diff --git a/openlane/aes/config.tcl.gold b/openlane/aes/config.tcl.gold
deleted file mode 100644
index 711143c..0000000
--- a/openlane/aes/config.tcl.gold
+++ /dev/null
@@ -1,58 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-set ::env(PDK) "sky130A"
-set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
-
-set script_dir [file dirname [file normalize [info script]]]
-
-set ::env(DESIGN_NAME) aes
-
-
-set ::env(VERILOG_FILES) "\
- $script_dir/../../verilog/rtl/aes/generated/*.v"
-
-set ::env(DESIGN_IS_CORE) 0
-
-set ::env(CLOCK_PORT) "clock"
-set ::env(CLOCK_NET) "aes.clock"
-set ::env(CLOCK_PERIOD) "100"
-
-set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 1000 1000"
-
-#set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
-#set ::env(PL_SKIP_INITIAL_PLACEMENT) 0
-#set ::env(PL_BASIC_PLACEMENT) 1
-set ::env(PL_TARGET_DENSITY) 0.1
-set ::env(GLB_RT_ALLOW_CONGESTION) 1
-#set ::env(ROUTING_CORES) 4
-
-# Maximum layer used for routing is metal 4.
-# This is because this macro will be inserted in a top level (user_project_wrapper)
-# where the PDN is planned on metal 5. So, to avoid having shorts between routes
-# in this macro and the top level metal 5 stripes, we have to restrict routes to metal4.
-#
-# set ::env(GLB_RT_MAXLAYER) 5
-
-set ::env(RT_MAX_LAYER) {met4}
-
-# You can draw more power domains if you need to
-set ::env(VDD_NETS) [list {vccd1}]
-set ::env(GND_NETS) [list {vssd1}]
-
-set ::env(DIODE_INSERTION_STRATEGY) 4
-# If you're going to use multiple power domains, then disable cvc run.
-set ::env(RUN_CVC) 1
diff --git a/verilog/dv/aes_test/Makefile b/verilog/dv/aes_test/Makefile
index 483de8e..82d9c65 100644
--- a/verilog/dv/aes_test/Makefile
+++ b/verilog/dv/aes_test/Makefile
@@ -24,11 +24,13 @@
CONFIG = caravel_user_project
+
include $(MCW_ROOT)/verilog/dv/make/env.makefile
include $(MCW_ROOT)/verilog/dv/make/var.makefile
include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
-SOURCE_FILES := $(SOURCE_FILES) $(shell pwd)/tiny-AES-c/aes.c
-$(info SOURCE_FILES=$(SOURCE_FILES) )
+
+SOURCE_FILES := $(SOURCE_FILES) $(shell pwd)/tiny-AES-c_lite/aes.c
+
include $(MCW_ROOT)/verilog/dv/make/sim.makefile
diff --git a/verilog/dv/aes_test/aes_test.c b/verilog/dv/aes_test/aes_test.c
index 9cb985d..5c22f02 100644
--- a/verilog/dv/aes_test/aes_test.c
+++ b/verilog/dv/aes_test/aes_test.c
@@ -19,6 +19,12 @@
aes[8] = 0x1;
while(aes[9]==0x00000000); //aes finish
+
+ //Word
+ word[0] = aes[0];
+ word[1] = aes[1];
+ word[2] = aes[2];
+ word[3] = aes[3];
}
void caravel_setup(){
@@ -56,37 +62,40 @@
void main(int argc, char** argv) {
caravel_setup();
+
+//AES HARDWARE
int key[] = {0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f};
int word[] = {0x00112233, 0x44556677, 0x8899aabb, 0xccddeeff};
aes_crypt(key , word);
- uint8_t i, j;
- for (i = 0; i < 4; ++i)
- {
- for (j = 0; j < 4; ++j)
- {
- // (*state)[j][i] = getSBoxValue((*state)[j][i]);
- }
- }
+
reg_mprj_datal = 0xCAFE0000;
+//AES SOFTWARE
struct AES_ctx ctx;
- uint8_t aeskey[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f };
- uint8_t str[] = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff };
- reg_mprj_datal = 0x12340000;
- reg_mprj_datal = 0xBEEF0000;
+ uint8_t aeskey[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f };
+ uint8_t str[] = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff };
AES_init_ctx(&ctx, aeskey);
-
- reg_mprj_datal = 0x12340000;
- reg_mprj_datal = 0xBEEF0000;
- AES_CBC_encrypt_buffer(&ctx, str, 16);
-
- int k;
- for ( k= 0; k < 16; ++k) {
- reg_mprj_datal = (int)str[i];
+ AES_ECB_encrypt(&ctx, str);
+
+ reg_mprj_datal= 0;
+ bool pass=true;
+ char count=0;
+ int a,b;
+ uint8_t i, k;
+ for ( k= 0; (k < 4) && pass; ++k) {
+ for ( i= 3; (i >= 0) && pass; --i) {
+ reg_mprj_datal = a = (( word[k] >> i*8 ) & 0xFF) << 24;
+ reg_mprj_datal = 0;
+ reg_mprj_datal = b = ((int) str[count]) << 24;
+ if(a!=b) pass = false;
+ count++;
+ }
}
-
+
+
+
// Flag end of the test
- reg_mprj_datal = 0xAB610000;
+ if(pass) reg_mprj_datal = 0xAB610000;
}
diff --git a/verilog/dv/aes_test/aes_test_tb.v b/verilog/dv/aes_test/aes_test_tb.v
index fee53e2..18da711 100644
--- a/verilog/dv/aes_test/aes_test_tb.v
+++ b/verilog/dv/aes_test/aes_test_tb.v
@@ -42,7 +42,7 @@
initial begin
clock = 0;
end
- parameter ncycles= 1000;
+ parameter ncycles= 70;
initial begin
$dumpfile("aes_test.vcd");
$dumpvars(0, aes_test_tb);
