Merge pull request #84 from efabless/dv-documentation-update
Documentation update
diff --git a/Makefile b/Makefile
index f629bd0..4482176 100644
--- a/Makefile
+++ b/Makefile
@@ -58,7 +58,7 @@
.PHONY: dv_all
dv_all:$(DV_PATTERNS)
-$(DV_PATTERNS): verify-% : ./verilog/dv/% check-env
+$(DV_PATTERNS): verify-% : ./verilog/dv/% check-env simenv
docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \
-v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
-e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \
diff --git a/README.md b/README.md
index a44bb1f..3077244 100644
--- a/README.md
+++ b/README.md
@@ -7,6 +7,6 @@
## Please fill in your project documentation in this README.md file
-Refer to [README](docs/source/roundtrip.rst) for a complete roundtrip of how to use caravel_user_project
+Refer to [README](docs/source/quickstart.rst) for a quick start of how to use caravel_user_project
Refer to [README](docs/source/index.rst) for this sample project documentation.
diff --git a/docs/source/quickstart.rst b/docs/source/quickstart.rst
new file mode 100644
index 0000000..051bcbf
--- /dev/null
+++ b/docs/source/quickstart.rst
@@ -0,0 +1,140 @@
+.. raw:: html
+
+ <!---
+ # SPDX-FileCopyrightText: 2020 Efabless Corporation
+ #
+ # Licensed under the Apache License, Version 2.0 (the "License");
+ # you may not use this file except in compliance with the License.
+ # You may obtain a copy of the License at
+ #
+ # http://www.apache.org/licenses/LICENSE-2.0
+ #
+ # Unless required by applicable law or agreed to in writing, software
+ # distributed under the License is distributed on an "AS IS" BASIS,
+ # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ # See the License for the specific language governing permissions and
+ # limitations under the License.
+ #
+ # SPDX-License-Identifier: Apache-2.0
+ -->
+
+Quick start for caravel_user_project
+====================================
+
+------------
+Dependencies
+------------
+
+- Docker: `Linux <https://hub.docker.com/search?q=&type=edition&offering=community&operating_system=linux&utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header>`_ || `Windows <https://desktop.docker.com/win/main/amd64/Docker%20Desktop%20Installer.exe?utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header>`_ || `Mac with Intel Chip <https://desktop.docker.com/mac/main/amd64/Docker.dmg?utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header>`_ || `Mac with M1 Chip <https://desktop.docker.com/mac/main/arm64/Docker.dmg?utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header>`_
+
+===============================================================================================================================================================
+
+---------------------
+Starting your project
+---------------------
+
+
+#. To start the project you need to first create an empty Git project on Github and make sure your repo is public and includes a README
+
+#. Open your Terminal. Create an empty folder to use as your Caravel workspace, and navigate to it.
+
+ .. code:: bash
+
+ # Create a directory and call it anything you want
+ mkdir -p caravel_tutorial
+
+ # navigate into the directory
+ cd caravel_tutorial
+
+#. Clone caravel_user_project and setup the git environment as follows
+
+ .. code:: bash
+
+ # Make sure that "caravel_example" matches the empty github repo name in step 1
+ git clone -b mpw-5c https://github.com/efabless/caravel_user_project caravel_example
+ cd caravel_example
+ git remote rename origin upstream
+
+ # You need to put your empty github repo URL from step 1
+ git remote add origin <your github repo URL>
+
+ # Create a new branch, you can name it anything
+ git checkout -b <my_branch>
+ git push -u origin <my_branch>
+
+#. Now that your git environment is setup, it's time to setup your local environment by running.
+
+ .. code:: bash
+
+ # make sure to change <directory_name> with the directory you created in step 2
+ # in this case it is caravel_tutorial
+ export OPENLANE_ROOT=~/<directory_name>/openlane # you need to export this whenever you start a new shell
+
+ export PDK_ROOT=~/<directory_name>/pdks # you need to export this whenever you start a new shell
+
+ make setup
+
+ * This command will setup your environment by installing the following:
+
+ - caravel_lite (a lite version of caravel)
+ - management core for simulation
+ - openlane to harden your design
+ - pdk
+
+
+#. Now you can start hardening your design
+
+ * To start hardening you project you need
+ - RTL verilog model for your design for OpenLane to harden
+ - A subdirectory for each macro in your project under ``openlane/`` directory, each subdirectory should include openlane configuration files for the macro
+
+ .. code:: bash
+
+ make <module_name>
+ ..
+
+ For an example of hardening a project please refer to `user_project_example <https://github.com/efabless/caravel_user_project/blob/dv-documentation-update/docs/source/index.rst#running-openlane>`_
+
+#. Integrate modules into the user_project_wrapper
+
+ * Change the environment variables ``VERILOG_FILES_BLACKBOX``, ``EXTRA_LEFS`` and ``EXTRA_GDS_FILES`` in ``openlane/user_project_wrapper/config.tcl`` to point to your module
+ * Instantiate your module(s) in ``verilog/rtl/user_project_wrapper.v``
+ * Harden the user_project_wrapper including your module(s), using this command:
+
+ .. code:: bash
+
+ make user_project_wrapper
+
+#. Run simulation on your design
+
+ * You need to include your rtl/gl/gl+sdf files in ``verilog/includes/includes.<rtl/gl/gl+sdf>.caravel_user_project``
+
+ **NOTE:** You shouldn't include the files inside the verilog code
+
+ .. code:: bash
+
+ # you can then run RTL simulations using
+ make verify-<testbench-name>-rtl
+
+ # OR GL simulation using
+ make verify-<testbench-name>-gl
+
+ # for example
+ make verify-io_ports-rtl
+
+#. Run the precheck locally
+
+ .. code:: bash
+
+ make precheck
+ make run-precheck
+
+#. You are done! now go to www.efabless.com to submit your project!
+
+
+.. |License| image:: https://img.shields.io/badge/License-Apache%202.0-blue.svg
+ :target: https://opensource.org/licenses/Apache-2.0
+.. |User CI| image:: https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml/badge.svg
+ :target: https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml
+.. |Caravel Build| image:: https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml/badge.svg
+ :target: https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml
diff --git a/docs/source/roundtrip.rst b/docs/source/roundtrip.rst
deleted file mode 100644
index eaeb478..0000000
--- a/docs/source/roundtrip.rst
+++ /dev/null
@@ -1,114 +0,0 @@
-.. raw:: html
-
- <!---
- # SPDX-FileCopyrightText: 2020 Efabless Corporation
- #
- # Licensed under the Apache License, Version 2.0 (the "License");
- # you may not use this file except in compliance with the License.
- # You may obtain a copy of the License at
- #
- # http://www.apache.org/licenses/LICENSE-2.0
- #
- # Unless required by applicable law or agreed to in writing, software
- # distributed under the License is distributed on an "AS IS" BASIS,
- # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- # See the License for the specific language governing permissions and
- # limitations under the License.
- #
- # SPDX-License-Identifier: Apache-2.0
- -->
-
-Complete roundtrip for caravel_user_project
-===========================================
-
-1. To start the project you need to first create an empty Git project on Github and make sure your repo is public and includes a README
-
-2. Open your Terminal. Create an empty folder to use as your Caravel workspace, and navigate to it.
-
-.. code:: bash
-
- # Create a directory and call it anything you want
- mkdir -p caravel_tutorial
-
- # navigate into the directory
- cd caravel_tutorial
-
-3. Clone caravel_user_project and setup the git environment as follows
-
-.. code:: bash
-
- # Make sure that ``caravel_example`` matches the empty github repo name in step 1
- git clone -b mpw-5a https://github.com/efabless/caravel_user_project caravel_example
- cd caravel_example
- git remote rename origin upstream
-
- # You need to put your empty github repo URL from step 1
- git remote add origin <your github repo URL>
-
- # Create a new branch, you can name it anything
- git checkout -b <my_branch>
- git push -u origin <my_branch>
-
-4. Now that your git environment is setup, it's time to setup your local environment. (NOTE: docker is a prerequisite to setting up your environment)
-
-.. code:: bash
-
- # to install caravel-lite into your caravel_user_project
- # you can install full caravel (not recommended) use ``export CARAVEL_LITE=0``
- make install
-
- # To install the management core for simulation
- make install_mcw
-
- # Install openlane for hardening your project
- # make sure to change <directory_name> with the directory you created in step 1
- # in this case it is caravel_tutorial
- export OPENLANE_ROOT=~/<directory_name>/openlane # you need to export this whenever you start a new shell
- make openlane
-
- # Build the pdk
- # make sure to change <directory_name> with the directory you created in step 1
- # in this case it is caravel_tutorial
-
- export PDK_ROOT=~/<directory_name>/pdks # you need to export this whenever you start a new shell
- make pdk
-
-5. Now you can start hardening your design, for example
-
-.. code:: bash
-
- make user_proj_example
- make user_project_wrapper
-
-6. To run simulation on your design
-
-.. code:: bash
-
- make simenv
- # you can run RTL/GL simulations by using
- export SIM=RTL
- # OR
- export SIM=GL
-
- # you can then run the simulations using
- make verify-<testbench-name>
-
- # for example
- make verify-io_ports
-
-7. To run the precheck locally
-
-.. code:: bash
-
- make precheck
- make run-precheck
-
-17. You are done! now go to www.efabless.com to submit your project!
-
-
-.. |License| image:: https://img.shields.io/badge/License-Apache%202.0-blue.svg
- :target: https://opensource.org/licenses/Apache-2.0
-.. |User CI| image:: https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml/badge.svg
- :target: https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml
-.. |Caravel Build| image:: https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml/badge.svg
- :target: https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml
diff --git a/verilog/dv/README.md b/verilog/dv/README.md
index 1a834f7..402000e 100644
--- a/verilog/dv/README.md
+++ b/verilog/dv/README.md
@@ -16,14 +16,50 @@
# SPDX-License-Identifier: Apache-2.0
-->
-# Simulation Environment Setup
+# Table of Contents
+* [Quick Start](./README.md#quick-start)
+* [For advanced users](./README.md#for-advanced-users)
+ * [Simulation Environment Setup](./README.md#simulation-environment-setup)
+ * [Docker](./README.md#1-docker)
+ * [Running Simulation](./README.md#running-simulation)
+ * [User Project Example DV](./README.md#user-project-example-dv)
+ * [IO Ports Test](./README.md#io-ports-test)
+ * [Logic Analyzer Test 1](./README.md#logic-analyzer-test-1)
+ * [Logic Analyzer Test 2](./README.md#logic-analyzer-test-2)
+ * [MPRJ Stimulus](./README.md#mprj_stimulus)
+ * [Wishbone Test](./README.md#wishbone-test)
+
+# Quick Launch for Designers
+
+## Dependencies
+
+- Docker: [Linux](https://hub.docker.com/search?q=&type=edition&offering=community&operating_system=linux&utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header) || [Windows](https://desktop.docker.com/win/main/amd64/Docker%20Desktop%20Installer.exe?utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header) || [Mac with Intel Chip](https://desktop.docker.com/mac/main/amd64/Docker.dmg?utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header) || [Mac with Apple Chip](https://desktop.docker.com/mac/main/arm64/Docker.dmg?utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header)
+
+## Running the simulation
+
+Assuming you already:
+- went throught the [quick start](https://github.com/efabless/caravel_user_project/blob/main/docs/source/quickstart.rst) for setting up your environemnt,
+- integrated your design into the user's wrapper and
+- hardenned your design as well as the user's wrapper (for GL simulation)
+
+````
+make simenv
+SIM=RTL make verify-<dv-test>
+# OR
+SIM=GL make verify-<dv-test>
+````
+``<dv-test>``: io_ports, mprj_stimulus, la_test1, la_test2 or wb_port.
+
+# For advanced users
+
+## Simulation Environment Setup
There are two options for setting up the simulation environment:
* Pulling a pre-built docker image
-* Installing the dependecies locally
+* Installing the dependecies locally. Instructions to setting up the environment locally can be found [here](https://github.com/efabless/caravel_user_project/verilog/dv/local-install.md)
-## 1. Docker
+### Docker
There is an available docker setup with the needed tools at [efabless/dockerized-verification-setup](https://github.com/efabless/dockerized-verification-setup)
@@ -33,102 +69,55 @@
docker pull efabless/dv_setup:latest
```
-## 2. Local Installion (Linux)
-
-You will need to fullfil these dependecies:
-
-* Icarus Verilog (10.2+)
-* RV32I Toolchain
-
-Using apt, you can install Icarus Verilog:
-
-```bash
-sudo apt-get install iverilog
-```
-
-Next, you will need to build the RV32I toolchain. Firstly, export the installation path for the RV32I toolchain,
-
-```bash
-export GCC_PATH=<gcc-installation-path>
-```
-
-Then, run the following:
-
-```bash
-# packages needed:
-sudo apt-get install autoconf automake autotools-dev curl libmpc-dev \
- libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo \
- gperf libtool patchutils bc zlib1g-dev git libexpat1-dev
-
-sudo mkdir $GCC_PATH
-sudo chown $USER $GCC_PATH
-
-git clone https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain-rv32i
-cd riscv-gnu-toolchain-rv32i
-git checkout 411d134
-git submodule update --init --recursive
-
-mkdir build; cd build
-../configure --with-arch=rv32i --prefix=$GCC_PATH
-make -j$(nproc)
-```
-
-# Running Simulation
-
-## Docker
+## Running Simulation
First, you will need to export a number of environment variables:
```bash
export PDK_PATH=<pdk-location/sky130A>
export CARAVEL_ROOT=<caravel_root>
-export UPRJ_ROOT=<user_project_root>
+export TARGET_PATH=<caravel_user_project>
```
Then, run the following command to start the docker container :
```
-docker run -it -v $CARAVEL_ROOT:$CARAVEL_ROOT -v $PDK_PATH:$PDK_PATH -v $UPRJ_ROOT:$UPRJ_ROOT -e CARAVEL_ROOT=$CARAVEL_ROOT -e PDK_PATH=$PDK_PATH -e UPRJ_ROOT=$UPRJ_ROOT -u $(id -u $USER):$(id -g $USER) efabless/dv_setup:latest
+docker run -it -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \
+ -v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
+ -e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \
+ -e CARAVEL_ROOT=${CARAVEL_ROOT} \
+ -e TOOLS=/foss/tools/riscv-gnu-toolchain-rv32i/411d134 \
+ -e DESIGNS=$(TARGET_PATH) \
+ -e CORE_VERILOG_PATH=$(TARGET_PATH)/mgmt_core_wrapper/verilog \
+ -e MCW_ROOT=$(MCW_ROOT) \
+ efabless/dv_setup:latest
```
Then, navigate to the directory where the DV tests reside :
```bash
-cd $UPRJ_ROOT/verilog/dv/
+cd $TARGET_PATH/verilog/dv/
```
-Then, follow the instructions at [Both](#both) to run RTL/GL simulation.
-
-## Local
-
-You will need to export these environment variables:
-
-```bash
-export GCC_PATH=<gcc-installation-path>
-export PDK_PATH=<pdk-location/sky130A>
-```
-
-Then, follow the instruction at [Both](#both) to run RTL/GL simulation.
-
-## Both
+To run any simulation, you need to be on the top level or caravel_user_project.
To run RTL simulation for one of the DV tests,
```bash
-cd <dv-test>
-make
+SIM=RTL make verify-<dv-test>
```
To run gate level simulation for one of the DV tests,
```bash
-cd <dv-test>
-SIM=GL make
+SIM=GL make verify-<dv-test>
```
# User Project Example DV
-The directory includes four tests for the counter user-project example:
+A discription of the example testbenches
+
+The directory includes five tests for the counter user-project example:
### IO Ports Test
@@ -168,6 +157,13 @@
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
.....
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+ .....
+ reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
+
+ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
@@ -187,23 +183,27 @@
```c
- reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF; // [31:0] inputs to mgmt_soc
- reg_la1_oenb = reg_la1_iena = 0x00000000; // [63:32] outputs from mgmt_soc
+ reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0]
+ reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF; // [63:32]
+ reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
+ reg_la3_oenb = reg_la3_iena = 0x00000000; // [127:96]
```
* Then, the firmware writes an initial value to the counter through the LA1 data register. Afte writing the counter value, the LA probes are disabled to prevent the counter write signal from being always set to one.
```c
reg_la1_data = 0x00000000; // Write zero to count register
- reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF; // Disable probes
+ reg_la1_oenb = reg_la1_iena = 0x00000000; // Disable probes
```
* The firmware then waits until the count value exceeds 500 and flags the success of the test by writing `0xAB41` to pads 16 to 31. The firmware reads the count value through the logic analyzer probes `[31:0]`
```c
- if (reg_la0_data > 0x1F4) { // Read current count value through LA
- reg_mprj_datal = 0xAB410000; // Flag success of the test
- break;
+ while (1) {
+ if (reg_la0_data > 0x1F4) { // Read current count value through LA
+ reg_mprj_datal = 0xAB410000; // Flag success of the test
+ break;
+ }
}
```
@@ -212,7 +212,10 @@
* This test is meant to verify that we can drive the clock and reset signals for the user project example through the logic analyzer. In the [user_proj_example](verilog/rtl/user_proj_example.v) RTL, the clock can either be supplied from the `wb_clk_i` or from the logic analyzer through bit `[64]`. Similarly, the reset signal can be supplied from the `wb_rst_i` or through `LA[65]`. The firmware configures the clk and reset LA probes as outputs from the management SoC by writing to the LA2 enable register.
```c
- reg_la2_oenb = reg_la2_iena = 0xFFFFFFFC; // Configure LA[64] LA[65] as outputs from the cpu
+ reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0]
+ reg_la1_oenb = reg_la1_iena = 0x00000000; // [63:32]
+ reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
+ reg_la3_oenb = reg_la3_iena = 0x00000000; // [127:96]
```
* Then, the firmware supplies both clock reset signals through LA2 data register. First, both are set to one. Then, reset is driven to zero and the clock is toggled for 6 clock cycles.
@@ -226,11 +229,45 @@
```
* The testbench success criteria is that the firmware reads a count value of five through the LA probes.
```c
- if (reg_la0_data == 0x05) {
- reg_mprj_datal = 0xAB610000; // FLag success of the test
+ while (1){
+ if (reg_la0_data == 0x05) {
+ reg_mprj_datal = 0xAB610000; // FLag success of the test
+ }
}
```
+### MPRJ_stimulus
+
+* This test is meant to verify that we can read data generated from the user project on the gpio outputs. This is done by configuring the LA probes as inputs to the cpu, except for LA probes [63:32] as output from the cpu
+
+ ```c
+ reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0]
+ reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF; // [63:32]
+ reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
+ reg_la3_oenb = reg_la3_iena = 0x00000000; // [127:96]
+ ```
+* Then tests the ability to force data on the gpio through channel 37
+
+ ```c
+ reg_mprj_datah = 0x0f0f0fc0;
+ reg_mprj_datah = 0x00000000;
+ reg_mprj_datah = 0x0f0f0fca;
+ reg_mprj_datah = 0x0000000a;
+ reg_mprj_datah = 0x0f0f0fc0;
+ reg_mprj_datah = 0x00000000;
+ reg_mprj_datah = 0x0f0f0fc5;
+ reg_mprj_datah = 0x00000005;
+ ```
+* It then tests the ability to read back the data generated by the user project on the gpio
+
+ ```c
+ testval = reg_mprj_datal;
+ reg_mprj_datal = (testval << 16);
+ testval = reg_mprj_datal;
+ reg_mprj_datal = (testval << 16);
+ ```
+
+
### Wishbone Test
-* This test is meant to verify that we can read and write to the count register through the wishbone port. The firmware writes a value of `0x2710` to the count register, then reads back the count value after some time. The read and write transactions happen through the management SoC wishbone bus and are initiated by either writing or reading from the user project address on the wishbone bus.
+* This test is meant to verify that we can read and write to the count register through the wishbone port. The firmware writes a value of `0x2710` to the count register, then reads back the count value after some time. The read and write transactions happen through the management SoC wishbone bus and are initiated by either writing or reading from the user project address on the wishbone bus. The ``reg_wb_enable`` needs to be set to 1 in order to enable the wishbone bus.
diff --git a/verilog/dv/local-install.md b/verilog/dv/local-install.md
new file mode 100644
index 0000000..7cd54c1
--- /dev/null
+++ b/verilog/dv/local-install.md
@@ -0,0 +1,65 @@
+# Local Installation (Linux)
+
+Instructions to install the dv setup locally (dockerless install).
+
+## You will need to fullfil these dependecies:
+
+* Icarus Verilog (10.2+)
+* RV32I Toolchain
+
+Using apt, you can install Icarus Verilog:
+
+```bash
+sudo apt-get install iverilog
+```
+
+Next, you will need to build the RV32I toolchain. Firstly, export the installation path for the RV32I toolchain,
+
+```bash
+export GCC_PATH=<gcc-installation-path>
+```
+
+Then, run the following:
+
+```bash
+# packages needed:
+sudo apt-get install autoconf automake autotools-dev curl libmpc-dev \
+ libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo \
+ gperf libtool patchutils bc zlib1g-dev git libexpat1-dev
+
+sudo mkdir $GCC_PATH
+sudo chown $USER $GCC_PATH
+
+git clone https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain-rv32i
+cd riscv-gnu-toolchain-rv32i
+git checkout 411d134
+git submodule update --init --recursive
+
+mkdir build; cd build
+../configure --with-arch=rv32i --prefix=$GCC_PATH
+make -j$(nproc)
+```
+
+# Running Simulation
+
+You will need to export these environment variables:
+
+```bash
+export GCC_PATH=<gcc-installation-path>
+export PDK_PATH=<pdk-location/sky130A>
+```
+
+To run any simulation, you need to be on the top level or caravel_user_project.
+
+To run RTL simulation for one of the DV tests,
+
+```bash
+SIM=RTL make verify-<dv-test>
+```
+
+To run gate level simulation for one of the DV tests,
+
+```bash
+SIM=GL make verify-<dv-test>
+```
+
