| commit | c3f6bc978db69d3ff8142c5d545aef66a57344aa | [log] [tgz] |
|---|---|---|
| author | HexKotnk <gnadrag@gmail.com> | Tue Mar 22 06:08:12 2022 +0100 |
| committer | HexKotnk <gnadrag@gmail.com> | Tue Mar 22 06:08:12 2022 +0100 |
| tree | 54db7b78f438bcf6d339e6afd160af55d1668b84 | |
| parent | 74137e96b896379b222309eded1d43a4fd7660b2 [diff] |
Disabled optimization
Asynchronous Fibonacci counter
The counter uses two phase dual rail logic. An asynchronous sequential logic circuit does not rely on the assumption that logic values only need to be valid within a window around the clock edge. Instead, the circuit needs to be valid all the time.
Two phase means that data is represented using edges (both a positive and negative edge are equivalent). These edges are called events. Dual rail means that for each bit, we use two wires, one for 0 and one for 1. An event is sent on only one of these two wires to send a binary digit.
To transfer data between components, we need to know whether the component we are sending data to is ready to accept new data and when the data has been sent. A component signals it is ready to accept new data by sending an event on its acknowledge signal. We know that data has been sent once one event is detected on every pair of wires in a bus.
Excellent book about asynchronous design: https://orbit.dtu.dk/en/publications/introduction-to-asynchronous-circuit-design