commit	1d231e853a5a19c2f7781378b3093a6e90e9869c	[log] [tgz]
author	Tim Edwards <tim@opencircuitdesign.com>	Sun Dec 19 17:03:41 2021 -0500
committer	Tim Edwards <tim@opencircuitdesign.com>	Sun Dec 19 17:03:41 2021 -0500
tree	686edc225872336525566264f1e19560d81e6419
parent	ea5ff7d937a3422c805b506215ae5242935638b2 [diff]

Modified the xschem schematics so that the wrapper level correctly
represents the metal resistors that were added to the layout to
maintain all the pins on isolated nets.  The LVS with the xschem
netlist is now correct with the modified layout.  The verilog
netlist has not yet been updated.

netgen/comp.out[diff]
netgen/user_analog_project_wrapper.spice[diff]
verilog/rtl/user_analog_project_wrapper.v[diff]
xschem/analog_wrapper_tb.sch[diff]
xschem/analog_wrapper_tb.spice[diff]
xschem/user_analog_project_wrapper.sch[diff]
xschem/user_analog_project_wrapper.spice[diff]

7 files changed

tree: 686edc225872336525566264f1e19560d81e6419

.github/
docs/
gds/
mag/
netgen/
openlane/
verilog/
xschem/
caravel
.gitignore
LICENSE
Makefile
README.md

README.md

Caravel Analog User

:exclamation: Important Note

Please fill in your project documentation in this README.md file

:warning:	Use this sample project for analog user projects.

Refer to README for this sample project documentation.