| |
| /----------------------------------------------------------------------------\ |
| | | |
| | yosys -- Yosys Open SYnthesis Suite | |
| | | |
| | Copyright (C) 2012 - 2020 Claire Xenia Wolf <claire@yosyshq.com> | |
| | | |
| | Permission to use, copy, modify, and/or distribute this software for any | |
| | purpose with or without fee is hereby granted, provided that the above | |
| | copyright notice and this permission notice appear in all copies. | |
| | | |
| | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
| | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
| | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
| | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
| | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
| | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
| | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
| | | |
| \----------------------------------------------------------------------------/ |
| |
| Yosys 0.12+45 (git sha1 UNKNOWN, gcc 8.3.1 -fPIC -Os) |
| |
| [TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip. |
| [TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip. |
| [TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip. |
| [TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip. |
| [TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip. |
| |
| 1. Executing Verilog-2005 frontend: /home/ali112000/mpw5/UETRV-ECORE/caravel/verilog/rtl/defines.v |
| Parsing SystemVerilog input from `/home/ali112000/mpw5/UETRV-ECORE/caravel/verilog/rtl/defines.v' to AST representation. |
| Successfully finished Verilog frontend. |
| |
| 2. Executing Verilog-2005 frontend: /home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v |
| Parsing SystemVerilog input from `/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v' to AST representation. |
| Generating RTLIL representation for module `\CSR'. |
| Generating RTLIL representation for module `\RegFile'. |
| Generating RTLIL representation for module `\ALU'. |
| Generating RTLIL representation for module `\ImmGen'. |
| Generating RTLIL representation for module `\Branch'. |
| Generating RTLIL representation for module `\LS_Unit'. |
| Generating RTLIL representation for module `\Datapath'. |
| Generating RTLIL representation for module `\Control'. |
| Generating RTLIL representation for module `\Core'. |
| Successfully finished Verilog frontend. |
| |
| 3. Generating Graphviz representation of design. |
| Writing dot description to `/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/runs/Core/tmp/synthesis/hierarchy.dot'. |
| Dumping module Core to page 1. |
| |
| 4. Executing HIERARCHY pass (managing design hierarchy). |
| |
| 4.1. Analyzing design hierarchy.. |
| Top module: \Core |
| Used module: \Control |
| Used module: \Datapath |
| Used module: \LS_Unit |
| Used module: \Branch |
| Used module: \ImmGen |
| Used module: \ALU |
| Used module: \RegFile |
| Used module: \CSR |
| |
| 4.2. Analyzing design hierarchy.. |
| Top module: \Core |
| Used module: \Control |
| Used module: \Datapath |
| Used module: \LS_Unit |
| Used module: \Branch |
| Used module: \ImmGen |
| Used module: \ALU |
| Used module: \RegFile |
| Used module: \CSR |
| Removed 0 unused modules. |
| |
| 5. Executing TRIBUF pass. |
| |
| 6. Executing SYNTH pass. |
| |
| 6.1. Executing HIERARCHY pass (managing design hierarchy). |
| |
| 6.1.1. Analyzing design hierarchy.. |
| Top module: \Core |
| Used module: \Control |
| Used module: \Datapath |
| Used module: \LS_Unit |
| Used module: \Branch |
| Used module: \ImmGen |
| Used module: \ALU |
| Used module: \RegFile |
| Used module: \CSR |
| |
| 6.1.2. Analyzing design hierarchy.. |
| Top module: \Core |
| Used module: \Control |
| Used module: \Datapath |
| Used module: \LS_Unit |
| Used module: \Branch |
| Used module: \ImmGen |
| Used module: \ALU |
| Used module: \RegFile |
| Used module: \CSR |
| Removed 0 unused modules. |
| |
| 6.2. Executing PROC pass (convert processes to netlists). |
| |
| 6.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). |
| Cleaned up 0 empty switches. |
| |
| 6.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). |
| Marked 16 switch rules as full_case in process $proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2390$578 in module Datapath. |
| Marked 1 switch rules as full_case in process $proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1414$339 in module RegFile. |
| Marked 62 switch rules as full_case in process $proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288 in module CSR. |
| Removed a total of 0 dead cases. |
| |
| 6.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). |
| Removed 4 redundant assignments. |
| Promoted 7 assignments to connections. |
| |
| 6.2.4. Executing PROC_INIT pass (extract init attributes). |
| |
| 6.2.5. Executing PROC_ARST pass (detect async resets in processes). |
| |
| 6.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers). |
| Creating decoders for process `\Datapath.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2390$578'. |
| 1/14: $0\pc[31:0] |
| 2/14: $0\ctrl_pc_check[0:0] |
| 3/14: $0\ctrl_illegal[0:0] |
| 4/14: $0\ctrl_csr_cmd[2:0] |
| 5/14: $0\ctrl_wb_en[0:0] |
| 6/14: $0\ctrl_wb_mux_sel[1:0] |
| 7/14: $0\ctrl_ld_type[2:0] |
| 8/14: $0\ctrl_st_type[1:0] |
| 9/14: $0\csr_in[31:0] |
| 10/14: $0\exe_wb_alu[31:0] |
| 11/14: $0\exe_wb_pc[31:0] |
| 12/14: $0\exe_wb_inst[31:0] |
| 13/14: $0\fet_exe_pc[31:0] |
| 14/14: $0\fet_exe_inst[31:0] |
| Creating decoders for process `\RegFile.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1414$339'. |
| 1/3: $1$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$346 |
| 2/3: $1$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_DATA[31:0]$345 |
| 3/3: $1$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_ADDR[4:0]$344 |
| Creating decoders for process `\CSR.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288'. |
| 1/25: $0\wasEret[0:0] |
| 2/25: $0\cycle[31:0] |
| 3/25: $0\time$[31:0]$289 |
| 4/25: $0\mtval[31:0] |
| 5/25: $0\mcause[31:0] |
| 6/25: $0\mscratch[31:0] |
| 7/25: $0\mtvec[31:0] |
| 8/25: $0\mip_msip[0:0] |
| 9/25: $0\mip_mtip[0:0] |
| 10/25: $0\mip_uartip[0:0] |
| 11/25: $0\mip_spiip[0:0] |
| 12/25: $0\mip_motorip[0:0] |
| 13/25: $0\mie_msie[0:0] |
| 14/25: $0\mie_mtie[0:0] |
| 15/25: $0\mie_uartie[0:0] |
| 16/25: $0\mie_spiie[0:0] |
| 17/25: $0\mie_motorie[0:0] |
| 18/25: $0\mstatus_mie[0:0] |
| 19/25: $0\mstatus_mpie[0:0] |
| 20/25: $0\mstatus_mpp[1:0] |
| 21/25: $0\mstatus_prv[1:0] |
| 22/25: $0\instreth[31:0] |
| 23/25: $0\instret[31:0] |
| 24/25: $0\cycleh[31:0] |
| 25/25: $0\timeh[31:0] |
| |
| 6.2.7. Executing PROC_DLATCH pass (convert process syncs to latches). |
| |
| 6.2.8. Executing PROC_DFF pass (convert process syncs to FFs). |
| Creating register for signal `\Datapath.\fet_exe_inst' using process `\Datapath.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2390$578'. |
| created $dff cell `$procdff$1629' with positive edge clock. |
| Creating register for signal `\Datapath.\fet_exe_pc' using process `\Datapath.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2390$578'. |
| created $dff cell `$procdff$1630' with positive edge clock. |
| Creating register for signal `\Datapath.\exe_wb_inst' using process `\Datapath.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2390$578'. |
| created $dff cell `$procdff$1631' with positive edge clock. |
| Creating register for signal `\Datapath.\exe_wb_pc' using process `\Datapath.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2390$578'. |
| created $dff cell `$procdff$1632' with positive edge clock. |
| Creating register for signal `\Datapath.\exe_wb_alu' using process `\Datapath.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2390$578'. |
| created $dff cell `$procdff$1633' with positive edge clock. |
| Creating register for signal `\Datapath.\csr_in' using process `\Datapath.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2390$578'. |
| created $dff cell `$procdff$1634' with positive edge clock. |
| Creating register for signal `\Datapath.\ctrl_st_type' using process `\Datapath.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2390$578'. |
| created $dff cell `$procdff$1635' with positive edge clock. |
| Creating register for signal `\Datapath.\ctrl_ld_type' using process `\Datapath.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2390$578'. |
| created $dff cell `$procdff$1636' with positive edge clock. |
| Creating register for signal `\Datapath.\ctrl_wb_mux_sel' using process `\Datapath.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2390$578'. |
| created $dff cell `$procdff$1637' with positive edge clock. |
| Creating register for signal `\Datapath.\ctrl_wb_en' using process `\Datapath.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2390$578'. |
| created $dff cell `$procdff$1638' with positive edge clock. |
| Creating register for signal `\Datapath.\ctrl_csr_cmd' using process `\Datapath.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2390$578'. |
| created $dff cell `$procdff$1639' with positive edge clock. |
| Creating register for signal `\Datapath.\ctrl_illegal' using process `\Datapath.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2390$578'. |
| created $dff cell `$procdff$1640' with positive edge clock. |
| Creating register for signal `\Datapath.\ctrl_pc_check' using process `\Datapath.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2390$578'. |
| created $dff cell `$procdff$1641' with positive edge clock. |
| Creating register for signal `\Datapath.\notstarted' using process `\Datapath.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2390$578'. |
| created $dff cell `$procdff$1642' with positive edge clock. |
| Creating register for signal `\Datapath.\pc' using process `\Datapath.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2390$578'. |
| created $dff cell `$procdff$1643' with positive edge clock. |
| Creating register for signal `\RegFile.$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_ADDR' using process `\RegFile.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1414$339'. |
| created $dff cell `$procdff$1644' with positive edge clock. |
| Creating register for signal `\RegFile.$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_DATA' using process `\RegFile.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1414$339'. |
| created $dff cell `$procdff$1645' with positive edge clock. |
| Creating register for signal `\RegFile.$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN' using process `\RegFile.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1414$339'. |
| created $dff cell `$procdff$1646' with positive edge clock. |
| Creating register for signal `\CSR.\time$' using process `\CSR.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288'. |
| created $dff cell `$procdff$1647' with positive edge clock. |
| Creating register for signal `\CSR.\timeh' using process `\CSR.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288'. |
| created $dff cell `$procdff$1648' with positive edge clock. |
| Creating register for signal `\CSR.\cycle' using process `\CSR.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288'. |
| created $dff cell `$procdff$1649' with positive edge clock. |
| Creating register for signal `\CSR.\cycleh' using process `\CSR.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288'. |
| created $dff cell `$procdff$1650' with positive edge clock. |
| Creating register for signal `\CSR.\instret' using process `\CSR.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288'. |
| created $dff cell `$procdff$1651' with positive edge clock. |
| Creating register for signal `\CSR.\instreth' using process `\CSR.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288'. |
| created $dff cell `$procdff$1652' with positive edge clock. |
| Creating register for signal `\CSR.\mstatus_prv' using process `\CSR.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288'. |
| created $dff cell `$procdff$1653' with positive edge clock. |
| Creating register for signal `\CSR.\mstatus_mpp' using process `\CSR.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288'. |
| created $dff cell `$procdff$1654' with positive edge clock. |
| Creating register for signal `\CSR.\mstatus_mpie' using process `\CSR.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288'. |
| created $dff cell `$procdff$1655' with positive edge clock. |
| Creating register for signal `\CSR.\mstatus_mie' using process `\CSR.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288'. |
| created $dff cell `$procdff$1656' with positive edge clock. |
| Creating register for signal `\CSR.\mie_motorie' using process `\CSR.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288'. |
| created $dff cell `$procdff$1657' with positive edge clock. |
| Creating register for signal `\CSR.\mie_spiie' using process `\CSR.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288'. |
| created $dff cell `$procdff$1658' with positive edge clock. |
| Creating register for signal `\CSR.\mie_uartie' using process `\CSR.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288'. |
| created $dff cell `$procdff$1659' with positive edge clock. |
| Creating register for signal `\CSR.\mie_mtie' using process `\CSR.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288'. |
| created $dff cell `$procdff$1660' with positive edge clock. |
| Creating register for signal `\CSR.\mie_msie' using process `\CSR.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288'. |
| created $dff cell `$procdff$1661' with positive edge clock. |
| Creating register for signal `\CSR.\mip_motorip' using process `\CSR.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288'. |
| created $dff cell `$procdff$1662' with positive edge clock. |
| Creating register for signal `\CSR.\mip_spiip' using process `\CSR.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288'. |
| created $dff cell `$procdff$1663' with positive edge clock. |
| Creating register for signal `\CSR.\mip_uartip' using process `\CSR.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288'. |
| created $dff cell `$procdff$1664' with positive edge clock. |
| Creating register for signal `\CSR.\mip_mtip' using process `\CSR.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288'. |
| created $dff cell `$procdff$1665' with positive edge clock. |
| Creating register for signal `\CSR.\mip_msip' using process `\CSR.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288'. |
| created $dff cell `$procdff$1666' with positive edge clock. |
| Creating register for signal `\CSR.\mtvec' using process `\CSR.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288'. |
| created $dff cell `$procdff$1667' with positive edge clock. |
| Creating register for signal `\CSR.\mscratch' using process `\CSR.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288'. |
| created $dff cell `$procdff$1668' with positive edge clock. |
| Creating register for signal `\CSR.\mepc' using process `\CSR.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288'. |
| created $dff cell `$procdff$1669' with positive edge clock. |
| Creating register for signal `\CSR.\mcause' using process `\CSR.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288'. |
| created $dff cell `$procdff$1670' with positive edge clock. |
| Creating register for signal `\CSR.\mtval' using process `\CSR.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288'. |
| created $dff cell `$procdff$1671' with positive edge clock. |
| Creating register for signal `\CSR.\wasEret' using process `\CSR.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288'. |
| created $dff cell `$procdff$1672' with positive edge clock. |
| Creating register for signal `\CSR.\br_taken' using process `\CSR.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288'. |
| created $dff cell `$procdff$1673' with positive edge clock. |
| Creating register for signal `\CSR.\br_taken_delayed' using process `\CSR.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288'. |
| created $dff cell `$procdff$1674' with positive edge clock. |
| |
| 6.2.9. Executing PROC_MEMWR pass (convert process memory writes to cells). |
| |
| 6.2.10. Executing PROC_CLEAN pass (remove empty switches from decision trees). |
| Found and cleaned up 35 empty switches in `\Datapath.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2390$578'. |
| Removing empty process `Datapath.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2390$578'. |
| Found and cleaned up 1 empty switch in `\RegFile.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1414$339'. |
| Removing empty process `RegFile.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1414$339'. |
| Found and cleaned up 158 empty switches in `\CSR.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288'. |
| Removing empty process `CSR.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:876$288'. |
| Cleaned up 194 empty switches. |
| |
| 6.2.11. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Core. |
| Optimizing module Control. |
| Optimizing module Datapath. |
| <suppressed ~24 debug messages> |
| Optimizing module LS_Unit. |
| Optimizing module Branch. |
| <suppressed ~4 debug messages> |
| Optimizing module ImmGen. |
| Optimizing module ALU. |
| <suppressed ~11 debug messages> |
| Optimizing module RegFile. |
| <suppressed ~4 debug messages> |
| Optimizing module CSR. |
| <suppressed ~85 debug messages> |
| |
| 6.3. Executing FLATTEN pass (flatten design). |
| Deleting now unused module Control. |
| Deleting now unused module Datapath. |
| Deleting now unused module LS_Unit. |
| Deleting now unused module Branch. |
| Deleting now unused module ImmGen. |
| Deleting now unused module ALU. |
| Deleting now unused module RegFile. |
| Deleting now unused module CSR. |
| <suppressed ~8 debug messages> |
| |
| 6.4. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Core. |
| |
| 6.5. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Core.. |
| Removed 187 unused cells and 1574 unused wires. |
| <suppressed ~370 debug messages> |
| |
| 6.6. Executing CHECK pass (checking for obvious problems). |
| Checking module Core... |
| Found and reported 0 problems. |
| |
| 6.7. Executing OPT pass (performing simple optimizations). |
| |
| 6.7.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Core. |
| |
| 6.7.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Core'. |
| <suppressed ~30 debug messages> |
| Removed a total of 10 cells. |
| |
| 6.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \Core.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~86 debug messages> |
| |
| 6.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \Core. |
| Consolidated identical input bits for $mux cell $flatten\dpath.\reg_file.$procmux$1243: |
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 |
| New ports: A=1'0, B=1'1, Y=$flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] |
| New connections: $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [31:1] = { $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] $flatten\dpath.\reg_file.$0$memwr$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1416$330_EN[31:0]$342 [0] } |
| Optimizing cells in module \Core. |
| Performed a total of 1 changes. |
| |
| 6.7.5. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Core'. |
| <suppressed ~93 debug messages> |
| Removed a total of 31 cells. |
| |
| 6.7.6. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 6.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Core.. |
| Removed 0 unused cells and 28 unused wires. |
| <suppressed ~1 debug messages> |
| |
| 6.7.8. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Core. |
| |
| 6.7.9. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 6.7.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \Core.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~86 debug messages> |
| |
| 6.7.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \Core. |
| Performed a total of 0 changes. |
| |
| 6.7.12. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Core'. |
| Removed a total of 0 cells. |
| |
| 6.7.13. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 6.7.14. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Core.. |
| |
| 6.7.15. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Core. |
| |
| 6.7.16. Finished OPT passes. (There is nothing left to do.) |
| |
| 6.8. Executing FSM pass (extract and optimize FSM). |
| |
| 6.8.1. Executing FSM_DETECT pass (finding FSMs in design). |
| Not marking Core.dpath.ctrl_csr_cmd as FSM state register: |
| Users of register don't seem to benefit from recoding. |
| Found FSM state register Core.dpath.ctrl_wb_mux_sel. |
| |
| 6.8.2. Executing FSM_EXTRACT pass (extracting FSM from design). |
| Extracting FSM `\dpath.ctrl_wb_mux_sel' from module `\Core'. |
| found $dff cell for state register: $flatten\dpath.$procdff$1637 |
| root of input selection tree: $flatten\dpath.$0\ctrl_wb_mux_sel[1:0] |
| found ctrl input: \dpath._T_233 |
| found ctrl input: \dpath._T_244 |
| found ctrl input: \ctrl._T_40 |
| found ctrl input: \ctrl._T_44 |
| found ctrl input: \ctrl._T_48 |
| found ctrl input: \ctrl._T_52 |
| found ctrl input: \ctrl._T_56 |
| found ctrl input: \ctrl._T_60 |
| found ctrl input: \ctrl._T_64 |
| found ctrl input: \ctrl._T_68 |
| found ctrl input: \ctrl._T_72 |
| found ctrl input: \ctrl._T_76 |
| found ctrl input: \ctrl._T_80 |
| found ctrl input: \ctrl._T_84 |
| found ctrl input: \ctrl._T_88 |
| found ctrl input: \ctrl._T_92 |
| found ctrl input: \ctrl._T_96 |
| found ctrl input: \ctrl._T_100 |
| found ctrl input: \ctrl._T_104 |
| found ctrl input: \ctrl._T_108 |
| found ctrl input: \ctrl._T_112 |
| found ctrl input: \ctrl._T_116 |
| found ctrl input: \ctrl._T_120 |
| found ctrl input: \ctrl._T_124 |
| found ctrl input: \ctrl._T_128 |
| found ctrl input: \ctrl._T_132 |
| found ctrl input: \ctrl._T_136 |
| found ctrl input: \ctrl._T_140 |
| found ctrl input: \ctrl._T_144 |
| found ctrl input: \ctrl._T_148 |
| found ctrl input: \ctrl._T_152 |
| found ctrl input: \ctrl._T_156 |
| found ctrl input: \ctrl._T_160 |
| found ctrl input: \ctrl._T_164 |
| found ctrl input: \ctrl._T_168 |
| found ctrl input: \ctrl._T_172 |
| found ctrl input: \ctrl._T_176 |
| found ctrl input: \ctrl._T_180 |
| found ctrl input: \ctrl._T_184 |
| found ctrl input: \ctrl._T_188 |
| found ctrl input: \ctrl._T_192 |
| found ctrl input: \ctrl._T_196 |
| found ctrl input: \ctrl._T_200 |
| found ctrl input: \ctrl._T_204 |
| found ctrl input: \ctrl._T_208 |
| found ctrl input: \ctrl._T_212 |
| found ctrl input: \ctrl._T_216 |
| found ctrl input: \ctrl._T_220 |
| found ctrl input: \ctrl._T_224 |
| found ctrl input: \ctrl._T_228 |
| found state code: 2'00 |
| found state code: 2'11 |
| found state code: 2'01 |
| found state code: 2'10 |
| found ctrl output: \dpath._T_259 |
| found ctrl output: \dpath._T_257 |
| found ctrl output: \dpath._T_255 |
| found ctrl output: \dpath._T_191 |
| ctrl inputs: { \ctrl._T_40 \ctrl._T_44 \ctrl._T_48 \ctrl._T_52 \ctrl._T_56 \ctrl._T_60 \ctrl._T_64 \ctrl._T_68 \ctrl._T_72 \ctrl._T_76 \ctrl._T_80 \ctrl._T_84 \ctrl._T_88 \ctrl._T_92 \ctrl._T_96 \ctrl._T_100 \ctrl._T_104 \ctrl._T_108 \ctrl._T_112 \ctrl._T_116 \ctrl._T_120 \ctrl._T_124 \ctrl._T_128 \ctrl._T_132 \ctrl._T_136 \ctrl._T_140 \ctrl._T_144 \ctrl._T_148 \ctrl._T_152 \ctrl._T_156 \ctrl._T_160 \ctrl._T_164 \ctrl._T_168 \ctrl._T_172 \ctrl._T_176 \ctrl._T_180 \ctrl._T_184 \ctrl._T_188 \ctrl._T_192 \ctrl._T_196 \ctrl._T_200 \ctrl._T_204 \ctrl._T_208 \ctrl._T_212 \ctrl._T_216 \ctrl._T_220 \ctrl._T_224 \ctrl._T_228 \dpath._T_233 \dpath._T_244 } |
| ctrl outputs: { \dpath._T_191 \dpath._T_255 \dpath._T_257 \dpath._T_259 $flatten\dpath.$0\ctrl_wb_mux_sel[1:0] } |
| transition: 2'00 50'------------------------------------------------00 -> 2'00 6'100000 |
| transition: 2'00 50'00000000000000000000000000000000000000000000000001 -> 2'00 6'100000 |
| transition: 2'00 50'00000000000000000000000000000000000000000000000101 -> 2'11 6'100011 |
| transition: 2'00 50'00000000000000000000000000000000000000000000001-01 -> 2'11 6'100011 |
| transition: 2'00 50'0000000000000000000000000000000000000000000001--01 -> 2'11 6'100011 |
| transition: 2'00 50'000000000000000000000000000000000000000000001---01 -> 2'11 6'100011 |
| transition: 2'00 50'00000000000000000000000000000000000000000001----01 -> 2'11 6'100011 |
| transition: 2'00 50'0000000000000000000000000000000000000000001-----01 -> 2'11 6'100011 |
| transition: 2'00 50'000000000000000000000000000000000000000001------01 -> 2'11 6'100011 |
| transition: 2'00 50'00000000000000000000000000000000000000001-------01 -> 2'11 6'100011 |
| transition: 2'00 50'0000000000000000000000000000000000000001--------01 -> 2'11 6'100011 |
| transition: 2'00 50'000000000000000000000000000000000000001---------01 -> 2'00 6'100000 |
| transition: 2'00 50'00000000000000000000000000000000000001----------01 -> 2'00 6'100000 |
| transition: 2'00 50'0000000000000000000000000000000000001-----------01 -> 2'00 6'100000 |
| transition: 2'00 50'000000000000000000000000000000000001------------01 -> 2'00 6'100000 |
| transition: 2'00 50'00000000000000000000000000000000001-------------01 -> 2'00 6'100000 |
| transition: 2'00 50'0000000000000000000000000000000001--------------01 -> 2'00 6'100000 |
| transition: 2'00 50'000000000000000000000000000000001---------------01 -> 2'00 6'100000 |
| transition: 2'00 50'00000000000000000000000000000001----------------01 -> 2'00 6'100000 |
| transition: 2'00 50'0000000000000000000000000000001-----------------01 -> 2'00 6'100000 |
| transition: 2'00 50'000000000000000000000000000001------------------01 -> 2'00 6'100000 |
| transition: 2'00 50'00000000000000000000000000001-------------------01 -> 2'00 6'100000 |
| transition: 2'00 50'0000000000000000000000000001--------------------01 -> 2'00 6'100000 |
| transition: 2'00 50'000000000000000000000000001---------------------01 -> 2'00 6'100000 |
| transition: 2'00 50'00000000000000000000000001----------------------01 -> 2'00 6'100000 |
| transition: 2'00 50'0000000000000000000000001-----------------------01 -> 2'00 6'100000 |
| transition: 2'00 50'000000000000000000000001------------------------01 -> 2'00 6'100000 |
| transition: 2'00 50'00000000000000000000001-------------------------01 -> 2'00 6'100000 |
| transition: 2'00 50'0000000000000000000001--------------------------01 -> 2'00 6'100000 |
| transition: 2'00 50'000000000000000000001---------------------------01 -> 2'00 6'100000 |
| transition: 2'00 50'00000000000000000001----------------------------01 -> 2'00 6'100000 |
| transition: 2'00 50'0000000000000000001-----------------------------01 -> 2'00 6'100000 |
| transition: 2'00 50'000000000000000001------------------------------01 -> 2'00 6'100000 |
| transition: 2'00 50'00000000000000001-------------------------------01 -> 2'00 6'100000 |
| transition: 2'00 50'0000000000000001--------------------------------01 -> 2'00 6'100000 |
| transition: 2'00 50'000000000000001---------------------------------01 -> 2'01 6'100001 |
| transition: 2'00 50'00000000000001----------------------------------01 -> 2'01 6'100001 |
| transition: 2'00 50'0000000000001-----------------------------------01 -> 2'01 6'100001 |
| transition: 2'00 50'000000000001------------------------------------01 -> 2'01 6'100001 |
| transition: 2'00 50'00000000001-------------------------------------01 -> 2'01 6'100001 |
| transition: 2'00 50'0000000001--------------------------------------01 -> 2'00 6'100000 |
| transition: 2'00 50'000000001---------------------------------------01 -> 2'00 6'100000 |
| transition: 2'00 50'00000001----------------------------------------01 -> 2'00 6'100000 |
| transition: 2'00 50'0000001-----------------------------------------01 -> 2'00 6'100000 |
| transition: 2'00 50'000001------------------------------------------01 -> 2'00 6'100000 |
| transition: 2'00 50'00001-------------------------------------------01 -> 2'00 6'100000 |
| transition: 2'00 50'0001--------------------------------------------01 -> 2'10 6'100010 |
| transition: 2'00 50'001---------------------------------------------01 -> 2'10 6'100010 |
| transition: 2'00 50'01----------------------------------------------01 -> 2'00 6'100000 |
| transition: 2'00 50'1-----------------------------------------------01 -> 2'00 6'100000 |
| transition: 2'00 50'------------------------------------------------1- -> 2'00 6'100000 |
| transition: 2'10 50'------------------------------------------------00 -> 2'10 6'001010 |
| transition: 2'10 50'00000000000000000000000000000000000000000000000001 -> 2'00 6'001000 |
| transition: 2'10 50'00000000000000000000000000000000000000000000000101 -> 2'11 6'001011 |
| transition: 2'10 50'00000000000000000000000000000000000000000000001-01 -> 2'11 6'001011 |
| transition: 2'10 50'0000000000000000000000000000000000000000000001--01 -> 2'11 6'001011 |
| transition: 2'10 50'000000000000000000000000000000000000000000001---01 -> 2'11 6'001011 |
| transition: 2'10 50'00000000000000000000000000000000000000000001----01 -> 2'11 6'001011 |
| transition: 2'10 50'0000000000000000000000000000000000000000001-----01 -> 2'11 6'001011 |
| transition: 2'10 50'000000000000000000000000000000000000000001------01 -> 2'11 6'001011 |
| transition: 2'10 50'00000000000000000000000000000000000000001-------01 -> 2'11 6'001011 |
| transition: 2'10 50'0000000000000000000000000000000000000001--------01 -> 2'11 6'001011 |
| transition: 2'10 50'000000000000000000000000000000000000001---------01 -> 2'00 6'001000 |
| transition: 2'10 50'00000000000000000000000000000000000001----------01 -> 2'00 6'001000 |
| transition: 2'10 50'0000000000000000000000000000000000001-----------01 -> 2'00 6'001000 |
| transition: 2'10 50'000000000000000000000000000000000001------------01 -> 2'00 6'001000 |
| transition: 2'10 50'00000000000000000000000000000000001-------------01 -> 2'00 6'001000 |
| transition: 2'10 50'0000000000000000000000000000000001--------------01 -> 2'00 6'001000 |
| transition: 2'10 50'000000000000000000000000000000001---------------01 -> 2'00 6'001000 |
| transition: 2'10 50'00000000000000000000000000000001----------------01 -> 2'00 6'001000 |
| transition: 2'10 50'0000000000000000000000000000001-----------------01 -> 2'00 6'001000 |
| transition: 2'10 50'000000000000000000000000000001------------------01 -> 2'00 6'001000 |
| transition: 2'10 50'00000000000000000000000000001-------------------01 -> 2'00 6'001000 |
| transition: 2'10 50'0000000000000000000000000001--------------------01 -> 2'00 6'001000 |
| transition: 2'10 50'000000000000000000000000001---------------------01 -> 2'00 6'001000 |
| transition: 2'10 50'00000000000000000000000001----------------------01 -> 2'00 6'001000 |
| transition: 2'10 50'0000000000000000000000001-----------------------01 -> 2'00 6'001000 |
| transition: 2'10 50'000000000000000000000001------------------------01 -> 2'00 6'001000 |
| transition: 2'10 50'00000000000000000000001-------------------------01 -> 2'00 6'001000 |
| transition: 2'10 50'0000000000000000000001--------------------------01 -> 2'00 6'001000 |
| transition: 2'10 50'000000000000000000001---------------------------01 -> 2'00 6'001000 |
| transition: 2'10 50'00000000000000000001----------------------------01 -> 2'00 6'001000 |
| transition: 2'10 50'0000000000000000001-----------------------------01 -> 2'00 6'001000 |
| transition: 2'10 50'000000000000000001------------------------------01 -> 2'00 6'001000 |
| transition: 2'10 50'00000000000000001-------------------------------01 -> 2'00 6'001000 |
| transition: 2'10 50'0000000000000001--------------------------------01 -> 2'00 6'001000 |
| transition: 2'10 50'000000000000001---------------------------------01 -> 2'01 6'001001 |
| transition: 2'10 50'00000000000001----------------------------------01 -> 2'01 6'001001 |
| transition: 2'10 50'0000000000001-----------------------------------01 -> 2'01 6'001001 |
| transition: 2'10 50'000000000001------------------------------------01 -> 2'01 6'001001 |
| transition: 2'10 50'00000000001-------------------------------------01 -> 2'01 6'001001 |
| transition: 2'10 50'0000000001--------------------------------------01 -> 2'00 6'001000 |
| transition: 2'10 50'000000001---------------------------------------01 -> 2'00 6'001000 |
| transition: 2'10 50'00000001----------------------------------------01 -> 2'00 6'001000 |
| transition: 2'10 50'0000001-----------------------------------------01 -> 2'00 6'001000 |
| transition: 2'10 50'000001------------------------------------------01 -> 2'00 6'001000 |
| transition: 2'10 50'00001-------------------------------------------01 -> 2'00 6'001000 |
| transition: 2'10 50'0001--------------------------------------------01 -> 2'10 6'001010 |
| transition: 2'10 50'001---------------------------------------------01 -> 2'10 6'001010 |
| transition: 2'10 50'01----------------------------------------------01 -> 2'00 6'001000 |
| transition: 2'10 50'1-----------------------------------------------01 -> 2'00 6'001000 |
| transition: 2'10 50'------------------------------------------------1- -> 2'10 6'001010 |
| transition: 2'01 50'------------------------------------------------00 -> 2'01 6'000101 |
| transition: 2'01 50'00000000000000000000000000000000000000000000000001 -> 2'00 6'000100 |
| transition: 2'01 50'00000000000000000000000000000000000000000000000101 -> 2'11 6'000111 |
| transition: 2'01 50'00000000000000000000000000000000000000000000001-01 -> 2'11 6'000111 |
| transition: 2'01 50'0000000000000000000000000000000000000000000001--01 -> 2'11 6'000111 |
| transition: 2'01 50'000000000000000000000000000000000000000000001---01 -> 2'11 6'000111 |
| transition: 2'01 50'00000000000000000000000000000000000000000001----01 -> 2'11 6'000111 |
| transition: 2'01 50'0000000000000000000000000000000000000000001-----01 -> 2'11 6'000111 |
| transition: 2'01 50'000000000000000000000000000000000000000001------01 -> 2'11 6'000111 |
| transition: 2'01 50'00000000000000000000000000000000000000001-------01 -> 2'11 6'000111 |
| transition: 2'01 50'0000000000000000000000000000000000000001--------01 -> 2'11 6'000111 |
| transition: 2'01 50'000000000000000000000000000000000000001---------01 -> 2'00 6'000100 |
| transition: 2'01 50'00000000000000000000000000000000000001----------01 -> 2'00 6'000100 |
| transition: 2'01 50'0000000000000000000000000000000000001-----------01 -> 2'00 6'000100 |
| transition: 2'01 50'000000000000000000000000000000000001------------01 -> 2'00 6'000100 |
| transition: 2'01 50'00000000000000000000000000000000001-------------01 -> 2'00 6'000100 |
| transition: 2'01 50'0000000000000000000000000000000001--------------01 -> 2'00 6'000100 |
| transition: 2'01 50'000000000000000000000000000000001---------------01 -> 2'00 6'000100 |
| transition: 2'01 50'00000000000000000000000000000001----------------01 -> 2'00 6'000100 |
| transition: 2'01 50'0000000000000000000000000000001-----------------01 -> 2'00 6'000100 |
| transition: 2'01 50'000000000000000000000000000001------------------01 -> 2'00 6'000100 |
| transition: 2'01 50'00000000000000000000000000001-------------------01 -> 2'00 6'000100 |
| transition: 2'01 50'0000000000000000000000000001--------------------01 -> 2'00 6'000100 |
| transition: 2'01 50'000000000000000000000000001---------------------01 -> 2'00 6'000100 |
| transition: 2'01 50'00000000000000000000000001----------------------01 -> 2'00 6'000100 |
| transition: 2'01 50'0000000000000000000000001-----------------------01 -> 2'00 6'000100 |
| transition: 2'01 50'000000000000000000000001------------------------01 -> 2'00 6'000100 |
| transition: 2'01 50'00000000000000000000001-------------------------01 -> 2'00 6'000100 |
| transition: 2'01 50'0000000000000000000001--------------------------01 -> 2'00 6'000100 |
| transition: 2'01 50'000000000000000000001---------------------------01 -> 2'00 6'000100 |
| transition: 2'01 50'00000000000000000001----------------------------01 -> 2'00 6'000100 |
| transition: 2'01 50'0000000000000000001-----------------------------01 -> 2'00 6'000100 |
| transition: 2'01 50'000000000000000001------------------------------01 -> 2'00 6'000100 |
| transition: 2'01 50'00000000000000001-------------------------------01 -> 2'00 6'000100 |
| transition: 2'01 50'0000000000000001--------------------------------01 -> 2'00 6'000100 |
| transition: 2'01 50'000000000000001---------------------------------01 -> 2'01 6'000101 |
| transition: 2'01 50'00000000000001----------------------------------01 -> 2'01 6'000101 |
| transition: 2'01 50'0000000000001-----------------------------------01 -> 2'01 6'000101 |
| transition: 2'01 50'000000000001------------------------------------01 -> 2'01 6'000101 |
| transition: 2'01 50'00000000001-------------------------------------01 -> 2'01 6'000101 |
| transition: 2'01 50'0000000001--------------------------------------01 -> 2'00 6'000100 |
| transition: 2'01 50'000000001---------------------------------------01 -> 2'00 6'000100 |
| transition: 2'01 50'00000001----------------------------------------01 -> 2'00 6'000100 |
| transition: 2'01 50'0000001-----------------------------------------01 -> 2'00 6'000100 |
| transition: 2'01 50'000001------------------------------------------01 -> 2'00 6'000100 |
| transition: 2'01 50'00001-------------------------------------------01 -> 2'00 6'000100 |
| transition: 2'01 50'0001--------------------------------------------01 -> 2'10 6'000110 |
| transition: 2'01 50'001---------------------------------------------01 -> 2'10 6'000110 |
| transition: 2'01 50'01----------------------------------------------01 -> 2'00 6'000100 |
| transition: 2'01 50'1-----------------------------------------------01 -> 2'00 6'000100 |
| transition: 2'01 50'------------------------------------------------1- -> 2'01 6'000101 |
| transition: 2'11 50'------------------------------------------------00 -> 2'11 6'010011 |
| transition: 2'11 50'00000000000000000000000000000000000000000000000001 -> 2'00 6'010000 |
| transition: 2'11 50'00000000000000000000000000000000000000000000000101 -> 2'11 6'010011 |
| transition: 2'11 50'00000000000000000000000000000000000000000000001-01 -> 2'11 6'010011 |
| transition: 2'11 50'0000000000000000000000000000000000000000000001--01 -> 2'11 6'010011 |
| transition: 2'11 50'000000000000000000000000000000000000000000001---01 -> 2'11 6'010011 |
| transition: 2'11 50'00000000000000000000000000000000000000000001----01 -> 2'11 6'010011 |
| transition: 2'11 50'0000000000000000000000000000000000000000001-----01 -> 2'11 6'010011 |
| transition: 2'11 50'000000000000000000000000000000000000000001------01 -> 2'11 6'010011 |
| transition: 2'11 50'00000000000000000000000000000000000000001-------01 -> 2'11 6'010011 |
| transition: 2'11 50'0000000000000000000000000000000000000001--------01 -> 2'11 6'010011 |
| transition: 2'11 50'000000000000000000000000000000000000001---------01 -> 2'00 6'010000 |
| transition: 2'11 50'00000000000000000000000000000000000001----------01 -> 2'00 6'010000 |
| transition: 2'11 50'0000000000000000000000000000000000001-----------01 -> 2'00 6'010000 |
| transition: 2'11 50'000000000000000000000000000000000001------------01 -> 2'00 6'010000 |
| transition: 2'11 50'00000000000000000000000000000000001-------------01 -> 2'00 6'010000 |
| transition: 2'11 50'0000000000000000000000000000000001--------------01 -> 2'00 6'010000 |
| transition: 2'11 50'000000000000000000000000000000001---------------01 -> 2'00 6'010000 |
| transition: 2'11 50'00000000000000000000000000000001----------------01 -> 2'00 6'010000 |
| transition: 2'11 50'0000000000000000000000000000001-----------------01 -> 2'00 6'010000 |
| transition: 2'11 50'000000000000000000000000000001------------------01 -> 2'00 6'010000 |
| transition: 2'11 50'00000000000000000000000000001-------------------01 -> 2'00 6'010000 |
| transition: 2'11 50'0000000000000000000000000001--------------------01 -> 2'00 6'010000 |
| transition: 2'11 50'000000000000000000000000001---------------------01 -> 2'00 6'010000 |
| transition: 2'11 50'00000000000000000000000001----------------------01 -> 2'00 6'010000 |
| transition: 2'11 50'0000000000000000000000001-----------------------01 -> 2'00 6'010000 |
| transition: 2'11 50'000000000000000000000001------------------------01 -> 2'00 6'010000 |
| transition: 2'11 50'00000000000000000000001-------------------------01 -> 2'00 6'010000 |
| transition: 2'11 50'0000000000000000000001--------------------------01 -> 2'00 6'010000 |
| transition: 2'11 50'000000000000000000001---------------------------01 -> 2'00 6'010000 |
| transition: 2'11 50'00000000000000000001----------------------------01 -> 2'00 6'010000 |
| transition: 2'11 50'0000000000000000001-----------------------------01 -> 2'00 6'010000 |
| transition: 2'11 50'000000000000000001------------------------------01 -> 2'00 6'010000 |
| transition: 2'11 50'00000000000000001-------------------------------01 -> 2'00 6'010000 |
| transition: 2'11 50'0000000000000001--------------------------------01 -> 2'00 6'010000 |
| transition: 2'11 50'000000000000001---------------------------------01 -> 2'01 6'010001 |
| transition: 2'11 50'00000000000001----------------------------------01 -> 2'01 6'010001 |
| transition: 2'11 50'0000000000001-----------------------------------01 -> 2'01 6'010001 |
| transition: 2'11 50'000000000001------------------------------------01 -> 2'01 6'010001 |
| transition: 2'11 50'00000000001-------------------------------------01 -> 2'01 6'010001 |
| transition: 2'11 50'0000000001--------------------------------------01 -> 2'00 6'010000 |
| transition: 2'11 50'000000001---------------------------------------01 -> 2'00 6'010000 |
| transition: 2'11 50'00000001----------------------------------------01 -> 2'00 6'010000 |
| transition: 2'11 50'0000001-----------------------------------------01 -> 2'00 6'010000 |
| transition: 2'11 50'000001------------------------------------------01 -> 2'00 6'010000 |
| transition: 2'11 50'00001-------------------------------------------01 -> 2'00 6'010000 |
| transition: 2'11 50'0001--------------------------------------------01 -> 2'10 6'010010 |
| transition: 2'11 50'001---------------------------------------------01 -> 2'10 6'010010 |
| transition: 2'11 50'01----------------------------------------------01 -> 2'00 6'010000 |
| transition: 2'11 50'1-----------------------------------------------01 -> 2'00 6'010000 |
| transition: 2'11 50'------------------------------------------------1- -> 2'11 6'010011 |
| |
| 6.8.3. Executing FSM_OPT pass (simple optimizations of FSMs). |
| Optimizing FSM `$fsm$\dpath.ctrl_wb_mux_sel$1676' from module `\Core'. |
| |
| 6.8.4. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Core.. |
| Removed 54 unused cells and 57 unused wires. |
| <suppressed ~105 debug messages> |
| |
| 6.8.5. Executing FSM_OPT pass (simple optimizations of FSMs). |
| Optimizing FSM `$fsm$\dpath.ctrl_wb_mux_sel$1676' from module `\Core'. |
| Removing unused output signal $flatten\dpath.$0\ctrl_wb_mux_sel[1:0] [0]. |
| Removing unused output signal $flatten\dpath.$0\ctrl_wb_mux_sel[1:0] [1]. |
| |
| 6.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). |
| Recoding FSM `$fsm$\dpath.ctrl_wb_mux_sel$1676' from module `\Core' using `auto' encoding: |
| mapping auto encoding to `one-hot` for this FSM. |
| 00 -> ---1 |
| 10 -> --1- |
| 01 -> -1-- |
| 11 -> 1--- |
| |
| 6.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells). |
| |
| FSM `$fsm$\dpath.ctrl_wb_mux_sel$1676' from module `Core': |
| ------------------------------------- |
| |
| Information on FSM $fsm$\dpath.ctrl_wb_mux_sel$1676 (\dpath.ctrl_wb_mux_sel): |
| |
| Number of input signals: 50 |
| Number of output signals: 4 |
| Number of state bits: 4 |
| |
| Input signals: |
| 0: \dpath._T_244 |
| 1: \dpath._T_233 |
| 2: \ctrl._T_228 |
| 3: \ctrl._T_224 |
| 4: \ctrl._T_220 |
| 5: \ctrl._T_216 |
| 6: \ctrl._T_212 |
| 7: \ctrl._T_208 |
| 8: \ctrl._T_204 |
| 9: \ctrl._T_200 |
| 10: \ctrl._T_196 |
| 11: \ctrl._T_192 |
| 12: \ctrl._T_188 |
| 13: \ctrl._T_184 |
| 14: \ctrl._T_180 |
| 15: \ctrl._T_176 |
| 16: \ctrl._T_172 |
| 17: \ctrl._T_168 |
| 18: \ctrl._T_164 |
| 19: \ctrl._T_160 |
| 20: \ctrl._T_156 |
| 21: \ctrl._T_152 |
| 22: \ctrl._T_148 |
| 23: \ctrl._T_144 |
| 24: \ctrl._T_140 |
| 25: \ctrl._T_136 |
| 26: \ctrl._T_132 |
| 27: \ctrl._T_128 |
| 28: \ctrl._T_124 |
| 29: \ctrl._T_120 |
| 30: \ctrl._T_116 |
| 31: \ctrl._T_112 |
| 32: \ctrl._T_108 |
| 33: \ctrl._T_104 |
| 34: \ctrl._T_100 |
| 35: \ctrl._T_96 |
| 36: \ctrl._T_92 |
| 37: \ctrl._T_88 |
| 38: \ctrl._T_84 |
| 39: \ctrl._T_80 |
| 40: \ctrl._T_76 |
| 41: \ctrl._T_72 |
| 42: \ctrl._T_68 |
| 43: \ctrl._T_64 |
| 44: \ctrl._T_60 |
| 45: \ctrl._T_56 |
| 46: \ctrl._T_52 |
| 47: \ctrl._T_48 |
| 48: \ctrl._T_44 |
| 49: \ctrl._T_40 |
| |
| Output signals: |
| 0: \dpath._T_259 |
| 1: \dpath._T_257 |
| 2: \dpath._T_255 |
| 3: \dpath._T_191 |
| |
| State encoding: |
| 0: 4'---1 |
| 1: 4'--1- |
| 2: 4'-1-- |
| 3: 4'1--- |
| |
| Transition Table (state_in, ctrl_in, state_out, ctrl_out): |
| 0: 0 50'------------------------------------------------00 -> 0 4'1000 |
| 1: 0 50'00000000000000000000000000000000000000000000000001 -> 0 4'1000 |
| 2: 0 50'000000000000000000000000000000000000001---------01 -> 0 4'1000 |
| 3: 0 50'00000000000000000000000000000000000001----------01 -> 0 4'1000 |
| 4: 0 50'0000000000000000000000000000000000001-----------01 -> 0 4'1000 |
| 5: 0 50'000000000000000000000000000000000001------------01 -> 0 4'1000 |
| 6: 0 50'00000000000000000000000000000000001-------------01 -> 0 4'1000 |
| 7: 0 50'0000000000000000000000000000000001--------------01 -> 0 4'1000 |
| 8: 0 50'000000000000000000000000000000001---------------01 -> 0 4'1000 |
| 9: 0 50'00000000000000000000000000000001----------------01 -> 0 4'1000 |
| 10: 0 50'0000000000000000000000000000001-----------------01 -> 0 4'1000 |
| 11: 0 50'000000000000000000000000000001------------------01 -> 0 4'1000 |
| 12: 0 50'00000000000000000000000000001-------------------01 -> 0 4'1000 |
| 13: 0 50'0000000000000000000000000001--------------------01 -> 0 4'1000 |
| 14: 0 50'000000000000000000000000001---------------------01 -> 0 4'1000 |
| 15: 0 50'00000000000000000000000001----------------------01 -> 0 4'1000 |
| 16: 0 50'0000000000000000000000001-----------------------01 -> 0 4'1000 |
| 17: 0 50'000000000000000000000001------------------------01 -> 0 4'1000 |
| 18: 0 50'00000000000000000000001-------------------------01 -> 0 4'1000 |
| 19: 0 50'0000000000000000000001--------------------------01 -> 0 4'1000 |
| 20: 0 50'000000000000000000001---------------------------01 -> 0 4'1000 |
| 21: 0 50'00000000000000000001----------------------------01 -> 0 4'1000 |
| 22: 0 50'0000000000000000001-----------------------------01 -> 0 4'1000 |
| 23: 0 50'000000000000000001------------------------------01 -> 0 4'1000 |
| 24: 0 50'00000000000000001-------------------------------01 -> 0 4'1000 |
| 25: 0 50'0000000000000001--------------------------------01 -> 0 4'1000 |
| 26: 0 50'0000000001--------------------------------------01 -> 0 4'1000 |
| 27: 0 50'000000001---------------------------------------01 -> 0 4'1000 |
| 28: 0 50'00000001----------------------------------------01 -> 0 4'1000 |
| 29: 0 50'0000001-----------------------------------------01 -> 0 4'1000 |
| 30: 0 50'000001------------------------------------------01 -> 0 4'1000 |
| 31: 0 50'00001-------------------------------------------01 -> 0 4'1000 |
| 32: 0 50'01----------------------------------------------01 -> 0 4'1000 |
| 33: 0 50'1-----------------------------------------------01 -> 0 4'1000 |
| 34: 0 50'------------------------------------------------1- -> 0 4'1000 |
| 35: 0 50'0001--------------------------------------------01 -> 1 4'1000 |
| 36: 0 50'001---------------------------------------------01 -> 1 4'1000 |
| 37: 0 50'000000000000001---------------------------------01 -> 2 4'1000 |
| 38: 0 50'00000000000001----------------------------------01 -> 2 4'1000 |
| 39: 0 50'0000000000001-----------------------------------01 -> 2 4'1000 |
| 40: 0 50'000000000001------------------------------------01 -> 2 4'1000 |
| 41: 0 50'00000000001-------------------------------------01 -> 2 4'1000 |
| 42: 0 50'00000000000000000000000000000000000000000000000101 -> 3 4'1000 |
| 43: 0 50'00000000000000000000000000000000000000000000001-01 -> 3 4'1000 |
| 44: 0 50'0000000000000000000000000000000000000000000001--01 -> 3 4'1000 |
| 45: 0 50'000000000000000000000000000000000000000000001---01 -> 3 4'1000 |
| 46: 0 50'00000000000000000000000000000000000000000001----01 -> 3 4'1000 |
| 47: 0 50'0000000000000000000000000000000000000000001-----01 -> 3 4'1000 |
| 48: 0 50'000000000000000000000000000000000000000001------01 -> 3 4'1000 |
| 49: 0 50'00000000000000000000000000000000000000001-------01 -> 3 4'1000 |
| 50: 0 50'0000000000000000000000000000000000000001--------01 -> 3 4'1000 |
| 51: 1 50'00000000000000000000000000000000000000000000000001 -> 0 4'0010 |
| 52: 1 50'000000000000000000000000000000000000001---------01 -> 0 4'0010 |
| 53: 1 50'00000000000000000000000000000000000001----------01 -> 0 4'0010 |
| 54: 1 50'0000000000000000000000000000000000001-----------01 -> 0 4'0010 |
| 55: 1 50'000000000000000000000000000000000001------------01 -> 0 4'0010 |
| 56: 1 50'00000000000000000000000000000000001-------------01 -> 0 4'0010 |
| 57: 1 50'0000000000000000000000000000000001--------------01 -> 0 4'0010 |
| 58: 1 50'000000000000000000000000000000001---------------01 -> 0 4'0010 |
| 59: 1 50'00000000000000000000000000000001----------------01 -> 0 4'0010 |
| 60: 1 50'0000000000000000000000000000001-----------------01 -> 0 4'0010 |
| 61: 1 50'000000000000000000000000000001------------------01 -> 0 4'0010 |
| 62: 1 50'00000000000000000000000000001-------------------01 -> 0 4'0010 |
| 63: 1 50'0000000000000000000000000001--------------------01 -> 0 4'0010 |
| 64: 1 50'000000000000000000000000001---------------------01 -> 0 4'0010 |
| 65: 1 50'00000000000000000000000001----------------------01 -> 0 4'0010 |
| 66: 1 50'0000000000000000000000001-----------------------01 -> 0 4'0010 |
| 67: 1 50'000000000000000000000001------------------------01 -> 0 4'0010 |
| 68: 1 50'00000000000000000000001-------------------------01 -> 0 4'0010 |
| 69: 1 50'0000000000000000000001--------------------------01 -> 0 4'0010 |
| 70: 1 50'000000000000000000001---------------------------01 -> 0 4'0010 |
| 71: 1 50'00000000000000000001----------------------------01 -> 0 4'0010 |
| 72: 1 50'0000000000000000001-----------------------------01 -> 0 4'0010 |
| 73: 1 50'000000000000000001------------------------------01 -> 0 4'0010 |
| 74: 1 50'00000000000000001-------------------------------01 -> 0 4'0010 |
| 75: 1 50'0000000000000001--------------------------------01 -> 0 4'0010 |
| 76: 1 50'0000000001--------------------------------------01 -> 0 4'0010 |
| 77: 1 50'000000001---------------------------------------01 -> 0 4'0010 |
| 78: 1 50'00000001----------------------------------------01 -> 0 4'0010 |
| 79: 1 50'0000001-----------------------------------------01 -> 0 4'0010 |
| 80: 1 50'000001------------------------------------------01 -> 0 4'0010 |
| 81: 1 50'00001-------------------------------------------01 -> 0 4'0010 |
| 82: 1 50'01----------------------------------------------01 -> 0 4'0010 |
| 83: 1 50'1-----------------------------------------------01 -> 0 4'0010 |
| 84: 1 50'------------------------------------------------00 -> 1 4'0010 |
| 85: 1 50'0001--------------------------------------------01 -> 1 4'0010 |
| 86: 1 50'001---------------------------------------------01 -> 1 4'0010 |
| 87: 1 50'------------------------------------------------1- -> 1 4'0010 |
| 88: 1 50'000000000000001---------------------------------01 -> 2 4'0010 |
| 89: 1 50'00000000000001----------------------------------01 -> 2 4'0010 |
| 90: 1 50'0000000000001-----------------------------------01 -> 2 4'0010 |
| 91: 1 50'000000000001------------------------------------01 -> 2 4'0010 |
| 92: 1 50'00000000001-------------------------------------01 -> 2 4'0010 |
| 93: 1 50'00000000000000000000000000000000000000000000000101 -> 3 4'0010 |
| 94: 1 50'00000000000000000000000000000000000000000000001-01 -> 3 4'0010 |
| 95: 1 50'0000000000000000000000000000000000000000000001--01 -> 3 4'0010 |
| 96: 1 50'000000000000000000000000000000000000000000001---01 -> 3 4'0010 |
| 97: 1 50'00000000000000000000000000000000000000000001----01 -> 3 4'0010 |
| 98: 1 50'0000000000000000000000000000000000000000001-----01 -> 3 4'0010 |
| 99: 1 50'000000000000000000000000000000000000000001------01 -> 3 4'0010 |
| 100: 1 50'00000000000000000000000000000000000000001-------01 -> 3 4'0010 |
| 101: 1 50'0000000000000000000000000000000000000001--------01 -> 3 4'0010 |
| 102: 2 50'00000000000000000000000000000000000000000000000001 -> 0 4'0001 |
| 103: 2 50'000000000000000000000000000000000000001---------01 -> 0 4'0001 |
| 104: 2 50'00000000000000000000000000000000000001----------01 -> 0 4'0001 |
| 105: 2 50'0000000000000000000000000000000000001-----------01 -> 0 4'0001 |
| 106: 2 50'000000000000000000000000000000000001------------01 -> 0 4'0001 |
| 107: 2 50'00000000000000000000000000000000001-------------01 -> 0 4'0001 |
| 108: 2 50'0000000000000000000000000000000001--------------01 -> 0 4'0001 |
| 109: 2 50'000000000000000000000000000000001---------------01 -> 0 4'0001 |
| 110: 2 50'00000000000000000000000000000001----------------01 -> 0 4'0001 |
| 111: 2 50'0000000000000000000000000000001-----------------01 -> 0 4'0001 |
| 112: 2 50'000000000000000000000000000001------------------01 -> 0 4'0001 |
| 113: 2 50'00000000000000000000000000001-------------------01 -> 0 4'0001 |
| 114: 2 50'0000000000000000000000000001--------------------01 -> 0 4'0001 |
| 115: 2 50'000000000000000000000000001---------------------01 -> 0 4'0001 |
| 116: 2 50'00000000000000000000000001----------------------01 -> 0 4'0001 |
| 117: 2 50'0000000000000000000000001-----------------------01 -> 0 4'0001 |
| 118: 2 50'000000000000000000000001------------------------01 -> 0 4'0001 |
| 119: 2 50'00000000000000000000001-------------------------01 -> 0 4'0001 |
| 120: 2 50'0000000000000000000001--------------------------01 -> 0 4'0001 |
| 121: 2 50'000000000000000000001---------------------------01 -> 0 4'0001 |
| 122: 2 50'00000000000000000001----------------------------01 -> 0 4'0001 |
| 123: 2 50'0000000000000000001-----------------------------01 -> 0 4'0001 |
| 124: 2 50'000000000000000001------------------------------01 -> 0 4'0001 |
| 125: 2 50'00000000000000001-------------------------------01 -> 0 4'0001 |
| 126: 2 50'0000000000000001--------------------------------01 -> 0 4'0001 |
| 127: 2 50'0000000001--------------------------------------01 -> 0 4'0001 |
| 128: 2 50'000000001---------------------------------------01 -> 0 4'0001 |
| 129: 2 50'00000001----------------------------------------01 -> 0 4'0001 |
| 130: 2 50'0000001-----------------------------------------01 -> 0 4'0001 |
| 131: 2 50'000001------------------------------------------01 -> 0 4'0001 |
| 132: 2 50'00001-------------------------------------------01 -> 0 4'0001 |
| 133: 2 50'01----------------------------------------------01 -> 0 4'0001 |
| 134: 2 50'1-----------------------------------------------01 -> 0 4'0001 |
| 135: 2 50'0001--------------------------------------------01 -> 1 4'0001 |
| 136: 2 50'001---------------------------------------------01 -> 1 4'0001 |
| 137: 2 50'------------------------------------------------00 -> 2 4'0001 |
| 138: 2 50'000000000000001---------------------------------01 -> 2 4'0001 |
| 139: 2 50'00000000000001----------------------------------01 -> 2 4'0001 |
| 140: 2 50'0000000000001-----------------------------------01 -> 2 4'0001 |
| 141: 2 50'000000000001------------------------------------01 -> 2 4'0001 |
| 142: 2 50'00000000001-------------------------------------01 -> 2 4'0001 |
| 143: 2 50'------------------------------------------------1- -> 2 4'0001 |
| 144: 2 50'00000000000000000000000000000000000000000000000101 -> 3 4'0001 |
| 145: 2 50'00000000000000000000000000000000000000000000001-01 -> 3 4'0001 |
| 146: 2 50'0000000000000000000000000000000000000000000001--01 -> 3 4'0001 |
| 147: 2 50'000000000000000000000000000000000000000000001---01 -> 3 4'0001 |
| 148: 2 50'00000000000000000000000000000000000000000001----01 -> 3 4'0001 |
| 149: 2 50'0000000000000000000000000000000000000000001-----01 -> 3 4'0001 |
| 150: 2 50'000000000000000000000000000000000000000001------01 -> 3 4'0001 |
| 151: 2 50'00000000000000000000000000000000000000001-------01 -> 3 4'0001 |
| 152: 2 50'0000000000000000000000000000000000000001--------01 -> 3 4'0001 |
| 153: 3 50'00000000000000000000000000000000000000000000000001 -> 0 4'0100 |
| 154: 3 50'000000000000000000000000000000000000001---------01 -> 0 4'0100 |
| 155: 3 50'00000000000000000000000000000000000001----------01 -> 0 4'0100 |
| 156: 3 50'0000000000000000000000000000000000001-----------01 -> 0 4'0100 |
| 157: 3 50'000000000000000000000000000000000001------------01 -> 0 4'0100 |
| 158: 3 50'00000000000000000000000000000000001-------------01 -> 0 4'0100 |
| 159: 3 50'0000000000000000000000000000000001--------------01 -> 0 4'0100 |
| 160: 3 50'000000000000000000000000000000001---------------01 -> 0 4'0100 |
| 161: 3 50'00000000000000000000000000000001----------------01 -> 0 4'0100 |
| 162: 3 50'0000000000000000000000000000001-----------------01 -> 0 4'0100 |
| 163: 3 50'000000000000000000000000000001------------------01 -> 0 4'0100 |
| 164: 3 50'00000000000000000000000000001-------------------01 -> 0 4'0100 |
| 165: 3 50'0000000000000000000000000001--------------------01 -> 0 4'0100 |
| 166: 3 50'000000000000000000000000001---------------------01 -> 0 4'0100 |
| 167: 3 50'00000000000000000000000001----------------------01 -> 0 4'0100 |
| 168: 3 50'0000000000000000000000001-----------------------01 -> 0 4'0100 |
| 169: 3 50'000000000000000000000001------------------------01 -> 0 4'0100 |
| 170: 3 50'00000000000000000000001-------------------------01 -> 0 4'0100 |
| 171: 3 50'0000000000000000000001--------------------------01 -> 0 4'0100 |
| 172: 3 50'000000000000000000001---------------------------01 -> 0 4'0100 |
| 173: 3 50'00000000000000000001----------------------------01 -> 0 4'0100 |
| 174: 3 50'0000000000000000001-----------------------------01 -> 0 4'0100 |
| 175: 3 50'000000000000000001------------------------------01 -> 0 4'0100 |
| 176: 3 50'00000000000000001-------------------------------01 -> 0 4'0100 |
| 177: 3 50'0000000000000001--------------------------------01 -> 0 4'0100 |
| 178: 3 50'0000000001--------------------------------------01 -> 0 4'0100 |
| 179: 3 50'000000001---------------------------------------01 -> 0 4'0100 |
| 180: 3 50'00000001----------------------------------------01 -> 0 4'0100 |
| 181: 3 50'0000001-----------------------------------------01 -> 0 4'0100 |
| 182: 3 50'000001------------------------------------------01 -> 0 4'0100 |
| 183: 3 50'00001-------------------------------------------01 -> 0 4'0100 |
| 184: 3 50'01----------------------------------------------01 -> 0 4'0100 |
| 185: 3 50'1-----------------------------------------------01 -> 0 4'0100 |
| 186: 3 50'0001--------------------------------------------01 -> 1 4'0100 |
| 187: 3 50'001---------------------------------------------01 -> 1 4'0100 |
| 188: 3 50'000000000000001---------------------------------01 -> 2 4'0100 |
| 189: 3 50'00000000000001----------------------------------01 -> 2 4'0100 |
| 190: 3 50'0000000000001-----------------------------------01 -> 2 4'0100 |
| 191: 3 50'000000000001------------------------------------01 -> 2 4'0100 |
| 192: 3 50'00000000001-------------------------------------01 -> 2 4'0100 |
| 193: 3 50'------------------------------------------------00 -> 3 4'0100 |
| 194: 3 50'00000000000000000000000000000000000000000000000101 -> 3 4'0100 |
| 195: 3 50'00000000000000000000000000000000000000000000001-01 -> 3 4'0100 |
| 196: 3 50'0000000000000000000000000000000000000000000001--01 -> 3 4'0100 |
| 197: 3 50'000000000000000000000000000000000000000000001---01 -> 3 4'0100 |
| 198: 3 50'00000000000000000000000000000000000000000001----01 -> 3 4'0100 |
| 199: 3 50'0000000000000000000000000000000000000000001-----01 -> 3 4'0100 |
| 200: 3 50'000000000000000000000000000000000000000001------01 -> 3 4'0100 |
| 201: 3 50'00000000000000000000000000000000000000001-------01 -> 3 4'0100 |
| 202: 3 50'0000000000000000000000000000000000000001--------01 -> 3 4'0100 |
| 203: 3 50'------------------------------------------------1- -> 3 4'0100 |
| |
| ------------------------------------- |
| |
| 6.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic). |
| Mapping FSM `$fsm$\dpath.ctrl_wb_mux_sel$1676' from module `\Core'. |
| |
| 6.9. Executing OPT pass (performing simple optimizations). |
| |
| 6.9.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Core. |
| <suppressed ~8 debug messages> |
| |
| 6.9.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Core'. |
| <suppressed ~9 debug messages> |
| Removed a total of 3 cells. |
| |
| 6.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \Core.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~84 debug messages> |
| |
| 6.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \Core. |
| Performed a total of 0 changes. |
| |
| 6.9.5. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Core'. |
| Removed a total of 0 cells. |
| |
| 6.9.6. Executing OPT_DFF pass (perform DFF optimizations). |
| Adding SRST signal on $flatten\dpath.\csr.$procdff$1672 ($dff) from module Core (D = \dpath.csr.isEret, Q = \dpath.csr.wasEret, rval = 1'0). |
| Adding EN signal on $flatten\dpath.\csr.$procdff$1671 ($dff) from module Core (D = $flatten\dpath.\csr.$procmux$1292_Y, Q = \dpath.csr.mtval). |
| Adding EN signal on $flatten\dpath.\csr.$procdff$1670 ($dff) from module Core (D = $flatten\dpath.\csr.$procmux$1315_Y, Q = \dpath.csr.mcause). |
| Adding SRST signal on $auto$ff.cc:262:slice$1848 ($dffe) from module Core (D = $flatten\dpath.\csr.$procmux$1312_Y [30], Q = \dpath.csr.mcause [30], rval = 1'0). |
| Adding EN signal on $flatten\dpath.\csr.$procdff$1669 ($dff) from module Core (D = \dpath.csr._GEN_109 [31:0], Q = \dpath.csr.mepc). |
| Adding EN signal on $flatten\dpath.\csr.$procdff$1668 ($dff) from module Core (D = \dpath.csr.wdata, Q = \dpath.csr.mscratch). |
| Adding SRST signal on $flatten\dpath.\csr.$procdff$1667 ($dff) from module Core (D = $flatten\dpath.\csr.$procmux$1369_Y, Q = \dpath.csr.mtvec, rval = 9). |
| Adding EN signal on $auto$ff.cc:262:slice$1913 ($sdff) from module Core (D = \dpath.csr.wdata, Q = \dpath.csr.mtvec). |
| Adding SRST signal on $flatten\dpath.\csr.$procdff$1666 ($dff) from module Core (D = $flatten\dpath.\csr.$procmux$1384_Y, Q = \dpath.csr.mip_msip, rval = 1'0). |
| Adding EN signal on $auto$ff.cc:262:slice$1929 ($sdff) from module Core (D = \dpath.csr.wdata [3], Q = \dpath.csr.mip_msip). |
| Adding SRST signal on $flatten\dpath.\csr.$procdff$1665 ($dff) from module Core (D = $flatten\dpath.\csr.$procmux$1399_Y, Q = \dpath.csr.mip_mtip, rval = 1'0). |
| Adding EN signal on $auto$ff.cc:262:slice$1941 ($sdff) from module Core (D = \dpath.csr.wdata [7], Q = \dpath.csr.mip_mtip). |
| Adding SRST signal on $flatten\dpath.\csr.$procdff$1664 ($dff) from module Core (D = $flatten\dpath.\csr.$procmux$1404_Y, Q = \dpath.csr.mip_uartip, rval = 1'0). |
| Adding EN signal on $auto$ff.cc:262:slice$1953 ($sdff) from module Core (D = \io_irq_uart_irq, Q = \dpath.csr.mip_uartip). |
| Adding SRST signal on $flatten\dpath.\csr.$procdff$1663 ($dff) from module Core (D = $flatten\dpath.\csr.$procmux$1409_Y, Q = \dpath.csr.mip_spiip, rval = 1'0). |
| Adding EN signal on $auto$ff.cc:262:slice$1955 ($sdff) from module Core (D = \io_irq_spi_irq, Q = \dpath.csr.mip_spiip). |
| Adding SRST signal on $flatten\dpath.\csr.$procdff$1662 ($dff) from module Core (D = $flatten\dpath.\csr.$procmux$1414_Y, Q = \dpath.csr.mip_motorip, rval = 1'0). |
| Adding EN signal on $auto$ff.cc:262:slice$1957 ($sdff) from module Core (D = \io_irq_motor_irq, Q = \dpath.csr.mip_motorip). |
| Adding EN signal on $flatten\dpath.\csr.$procdff$1661 ($dff) from module Core (D = \dpath.csr.wdata [3], Q = \dpath.csr.mie_msie). |
| Adding EN signal on $flatten\dpath.\csr.$procdff$1660 ($dff) from module Core (D = \dpath.csr.wdata [7], Q = \dpath.csr.mie_mtie). |
| Adding EN signal on $flatten\dpath.\csr.$procdff$1655 ($dff) from module Core (D = $flatten\dpath.\csr.$procmux$1563_Y, Q = \dpath.csr.mstatus_mpie). |
| Adding SRST signal on $flatten\dpath.\csr.$procdff$1652 ($dff) from module Core (D = $flatten\dpath.\csr.$procmux$1609_Y, Q = \dpath.csr.instreth, rval = 0). |
| Adding EN signal on $auto$ff.cc:262:slice$1994 ($sdff) from module Core (D = \dpath.csr._T_490, Q = \dpath.csr.instreth). |
| Adding SRST signal on $flatten\dpath.\csr.$procdff$1651 ($dff) from module Core (D = $flatten\dpath.\csr.$procmux$1614_Y, Q = \dpath.csr.instret, rval = 0). |
| Adding EN signal on $auto$ff.cc:262:slice$1996 ($sdff) from module Core (D = \dpath.csr._T_483, Q = \dpath.csr.instret). |
| Adding SRST signal on $flatten\dpath.\csr.$procdff$1650 ($dff) from module Core (D = $flatten\dpath.\csr.$procmux$1619_Y, Q = \dpath.csr.cycleh, rval = 0). |
| Adding EN signal on $auto$ff.cc:262:slice$1998 ($sdff) from module Core (D = \dpath.csr._T_471, Q = \dpath.csr.cycleh). |
| Adding SRST signal on $flatten\dpath.\csr.$procdff$1649 ($dff) from module Core (D = \dpath.csr._T_465, Q = \dpath.csr.cycle, rval = 0). |
| Adding SRST signal on $flatten\dpath.\csr.$procdff$1648 ($dff) from module Core (D = $flatten\dpath.\csr.$procmux$1624_Y, Q = \dpath.csr.timeh, rval = 0). |
| Adding EN signal on $auto$ff.cc:262:slice$2001 ($sdff) from module Core (D = \dpath.csr._T_462, Q = \dpath.csr.timeh). |
| Adding SRST signal on $flatten\dpath.\csr.$procdff$1647 ($dff) from module Core (D = \dpath.csr._T_456, Q = \dpath.csr.time$, rval = 0). |
| Adding SRST signal on $flatten\dpath.$procdff$1643 ($dff) from module Core (D = \dpath._T_170 [31:0], Q = \dpath.pc, rval = 28668). |
| Adding SRST signal on $flatten\dpath.$procdff$1641 ($dff) from module Core (D = $flatten\dpath.$procmux$1159_Y, Q = \dpath.ctrl_pc_check, rval = 1'0). |
| Adding EN signal on $auto$ff.cc:262:slice$2005 ($sdff) from module Core (D = \dpath._T_156, Q = \dpath.ctrl_pc_check). |
| Adding SRST signal on $flatten\dpath.$procdff$1640 ($dff) from module Core (D = $flatten\dpath.$procmux$1164_Y, Q = \dpath.ctrl_illegal, rval = 1'0). |
| Adding EN signal on $auto$ff.cc:262:slice$2007 ($sdff) from module Core (D = \dpath.io_ctrl_illegal, Q = \dpath.ctrl_illegal). |
| Adding SRST signal on $flatten\dpath.$procdff$1639 ($dff) from module Core (D = $flatten\dpath.$procmux$1172_Y, Q = \dpath.ctrl_csr_cmd, rval = 3'000). |
| Adding EN signal on $auto$ff.cc:262:slice$2009 ($sdff) from module Core (D = $flatten\dpath.$procmux$1172_Y, Q = \dpath.ctrl_csr_cmd). |
| Adding SRST signal on $flatten\dpath.$procdff$1638 ($dff) from module Core (D = $flatten\dpath.$procmux$1180_Y, Q = \dpath.ctrl_wb_en, rval = 1'0). |
| Adding EN signal on $auto$ff.cc:262:slice$2013 ($sdff) from module Core (D = $flatten\dpath.$procmux$1180_Y, Q = \dpath.ctrl_wb_en). |
| Adding SRST signal on $flatten\dpath.$procdff$1636 ($dff) from module Core (D = $flatten\dpath.$procmux$1192_Y, Q = \dpath.ctrl_ld_type, rval = 3'000). |
| Adding EN signal on $auto$ff.cc:262:slice$2017 ($sdff) from module Core (D = $flatten\dpath.$procmux$1192_Y, Q = \dpath.ctrl_ld_type). |
| Adding SRST signal on $flatten\dpath.$procdff$1635 ($dff) from module Core (D = $flatten\dpath.$procmux$1200_Y, Q = \dpath.ctrl_st_type, rval = 2'00). |
| Adding EN signal on $auto$ff.cc:262:slice$2021 ($sdff) from module Core (D = $flatten\dpath.$procmux$1200_Y, Q = \dpath.ctrl_st_type). |
| Adding EN signal on $flatten\dpath.$procdff$1634 ($dff) from module Core (D = $flatten\dpath.$procmux$1209_Y, Q = \dpath.csr_in). |
| Adding EN signal on $flatten\dpath.$procdff$1633 ($dff) from module Core (D = \dpath.alu_io_out, Q = \dpath.exe_wb_alu). |
| Adding EN signal on $flatten\dpath.$procdff$1632 ($dff) from module Core (D = \dpath.fet_exe_pc, Q = \dpath.exe_wb_pc). |
| Adding SRST signal on $flatten\dpath.$procdff$1631 ($dff) from module Core (D = $flatten\dpath.$procmux$1225_Y, Q = \dpath.exe_wb_inst, rval = 19). |
| Adding EN signal on $auto$ff.cc:262:slice$2040 ($sdff) from module Core (D = \dpath.fet_exe_inst, Q = \dpath.exe_wb_inst). |
| Adding EN signal on $flatten\dpath.$procdff$1630 ($dff) from module Core (D = \dpath.pc, Q = \dpath.fet_exe_pc). |
| Adding SRST signal on $flatten\dpath.$procdff$1629 ($dff) from module Core (D = $flatten\dpath.$procmux$1237_Y, Q = \dpath.fet_exe_inst, rval = 19). |
| Adding EN signal on $auto$ff.cc:262:slice$2053 ($sdff) from module Core (D = $flatten\dpath.$procmux$1235_Y, Q = \dpath.fet_exe_inst). |
| |
| 6.9.7. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Core.. |
| Removed 89 unused cells and 99 unused wires. |
| <suppressed ~91 debug messages> |
| |
| 6.9.8. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Core. |
| <suppressed ~8 debug messages> |
| |
| 6.9.9. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 6.9.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \Core.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~64 debug messages> |
| |
| 6.9.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \Core. |
| Performed a total of 0 changes. |
| |
| 6.9.12. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Core'. |
| <suppressed ~177 debug messages> |
| Removed a total of 59 cells. |
| |
| 6.9.13. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 6.9.14. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Core.. |
| Removed 0 unused cells and 59 unused wires. |
| <suppressed ~1 debug messages> |
| |
| 6.9.15. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Core. |
| |
| 6.9.16. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 6.9.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \Core.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~65 debug messages> |
| |
| 6.9.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \Core. |
| Performed a total of 0 changes. |
| |
| 6.9.19. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Core'. |
| Removed a total of 0 cells. |
| |
| 6.9.20. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 6.9.21. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Core.. |
| |
| 6.9.22. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Core. |
| |
| 6.9.23. Finished OPT passes. (There is nothing left to do.) |
| |
| 6.10. Executing WREDUCE pass (reducing word size of cells). |
| Removed top 47 bits (of 50) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1798 ($eq). |
| Removed top 46 bits (of 49) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1800 ($eq). |
| Removed top 45 bits (of 48) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1802 ($eq). |
| Removed top 44 bits (of 47) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1804 ($eq). |
| Removed top 43 bits (of 46) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1806 ($eq). |
| Removed top 42 bits (of 45) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1808 ($eq). |
| Removed top 41 bits (of 44) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1810 ($eq). |
| Removed top 40 bits (of 43) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1812 ($eq). |
| Removed top 1 bits (of 2) from port A of cell Core.$flatten\dpath.\lsu.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1882$474 ($eq). |
| Removed top 1 bits (of 9) from mux cell Core.$flatten\dpath.\lsu.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1891$476 ($mux). |
| Removed top 1 bits (of 17) from mux cell Core.$flatten\dpath.\lsu.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1893$478 ($mux). |
| Removed top 1 bits (of 3) from port A of cell Core.$flatten\dpath.\lsu.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1894$479 ($eq). |
| Removed top 1 bits (of 33) from mux cell Core.$flatten\dpath.\lsu.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1899$484 ($mux). |
| Removed top 1 bits (of 3) from port B of cell Core.$flatten\dpath.\cond_br.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1825$453 ($eq). |
| Removed top 1 bits (of 3) from port B of cell Core.$flatten\dpath.\cond_br.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1830$458 ($eq). |
| Removed top 2 bits (of 3) from port B of cell Core.$flatten\dpath.\cond_br.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1836$464 ($eq). |
| Removed top 1 bits (of 3) from port B of cell Core.$flatten\dpath.\gen_imm.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1734$423 ($eq). |
| Removed top 1 bits (of 3) from port B of cell Core.$flatten\dpath.\gen_imm.$ne$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1738$425 ($ne). |
| Removed top 1 bits (of 3) from port B of cell Core.$flatten\dpath.\gen_imm.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1756$436 ($eq). |
| Removed top 2 bits (of 3) from port B of cell Core.$flatten\dpath.\gen_imm.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1764$441 ($eq). |
| Removed top 16 bits (of 32) from port A of cell Core.$flatten\dpath.\alu.$or$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1574$356 ($or). |
| Removed top 8 bits (of 32) from port A of cell Core.$flatten\dpath.\alu.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1577$357 ($and). |
| Removed top 8 bits (of 32) from port B of cell Core.$flatten\dpath.\alu.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1577$357 ($and). |
| Removed top 8 bits (of 32) from port Y of cell Core.$flatten\dpath.\alu.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1577$357 ($and). |
| Removed top 8 bits (of 32) from port A of cell Core.$flatten\dpath.\alu.$or$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1582$360 ($or). |
| Removed top 4 bits (of 32) from port A of cell Core.$flatten\dpath.\alu.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1585$361 ($and). |
| Removed top 4 bits (of 32) from port B of cell Core.$flatten\dpath.\alu.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1585$361 ($and). |
| Removed top 4 bits (of 32) from port Y of cell Core.$flatten\dpath.\alu.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1585$361 ($and). |
| Removed top 4 bits (of 32) from port A of cell Core.$flatten\dpath.\alu.$or$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1590$364 ($or). |
| Removed top 2 bits (of 32) from port A of cell Core.$flatten\dpath.\alu.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1593$365 ($and). |
| Removed top 2 bits (of 32) from port B of cell Core.$flatten\dpath.\alu.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1593$365 ($and). |
| Removed top 2 bits (of 32) from port Y of cell Core.$flatten\dpath.\alu.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1593$365 ($and). |
| Removed top 2 bits (of 32) from port A of cell Core.$flatten\dpath.\alu.$or$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1598$368 ($or). |
| Removed top 1 bits (of 32) from port A of cell Core.$flatten\dpath.\alu.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1601$369 ($and). |
| Removed top 1 bits (of 32) from port B of cell Core.$flatten\dpath.\alu.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1601$369 ($and). |
| Removed top 1 bits (of 32) from port Y of cell Core.$flatten\dpath.\alu.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1601$369 ($and). |
| Removed top 1 bits (of 32) from port A of cell Core.$flatten\dpath.\alu.$or$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1606$372 ($or). |
| Removed top 1 bits (of 33) from port Y of cell Core.$flatten\dpath.\alu.$sshr$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1612$375 ($sshr). |
| Removed top 16 bits (of 32) from port A of cell Core.$flatten\dpath.\alu.$or$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1620$378 ($or). |
| Removed top 8 bits (of 32) from port A of cell Core.$flatten\dpath.\alu.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1623$379 ($and). |
| Removed top 8 bits (of 32) from port B of cell Core.$flatten\dpath.\alu.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1623$379 ($and). |
| Removed top 8 bits (of 32) from port Y of cell Core.$flatten\dpath.\alu.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1623$379 ($and). |
| Removed top 8 bits (of 32) from port A of cell Core.$flatten\dpath.\alu.$or$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1628$382 ($or). |
| Removed top 4 bits (of 32) from port A of cell Core.$flatten\dpath.\alu.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1631$383 ($and). |
| Removed top 4 bits (of 32) from port B of cell Core.$flatten\dpath.\alu.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1631$383 ($and). |
| Removed top 4 bits (of 32) from port Y of cell Core.$flatten\dpath.\alu.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1631$383 ($and). |
| Removed top 4 bits (of 32) from port A of cell Core.$flatten\dpath.\alu.$or$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1636$386 ($or). |
| Removed top 2 bits (of 32) from port A of cell Core.$flatten\dpath.\alu.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1639$387 ($and). |
| Removed top 2 bits (of 32) from port B of cell Core.$flatten\dpath.\alu.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1639$387 ($and). |
| Removed top 2 bits (of 32) from port Y of cell Core.$flatten\dpath.\alu.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1639$387 ($and). |
| Removed top 2 bits (of 32) from port A of cell Core.$flatten\dpath.\alu.$or$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1644$390 ($or). |
| Removed top 1 bits (of 32) from port A of cell Core.$flatten\dpath.\alu.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1647$391 ($and). |
| Removed top 1 bits (of 32) from port B of cell Core.$flatten\dpath.\alu.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1647$391 ($and). |
| Removed top 1 bits (of 32) from port Y of cell Core.$flatten\dpath.\alu.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1647$391 ($and). |
| Removed top 1 bits (of 32) from port A of cell Core.$flatten\dpath.\alu.$or$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1652$394 ($or). |
| Removed top 3 bits (of 4) from port B of cell Core.$flatten\dpath.\alu.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1654$396 ($eq). |
| Removed top 1 bits (of 4) from port B of cell Core.$flatten\dpath.\alu.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1656$398 ($eq). |
| Removed top 1 bits (of 4) from port B of cell Core.$flatten\dpath.\alu.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1657$399 ($eq). |
| Removed top 1 bits (of 4) from port B of cell Core.$flatten\dpath.\alu.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1662$404 ($eq). |
| Removed top 2 bits (of 4) from port B of cell Core.$flatten\dpath.\alu.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1663$405 ($eq). |
| Removed top 2 bits (of 4) from port B of cell Core.$flatten\dpath.\alu.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1665$407 ($eq). |
| Removed top 1 bits (of 4) from port B of cell Core.$flatten\dpath.\alu.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1667$409 ($eq). |
| Removed cell Core.$flatten\dpath.\reg_file.$procmux$1246 ($mux). |
| Removed cell Core.$flatten\dpath.\reg_file.$procmux$1249 ($mux). |
| Removed top 2 bits (of 12) from port A of cell Core.$flatten\dpath.\csr.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:434$13 ($eq). |
| Removed top 2 bits (of 12) from port A of cell Core.$flatten\dpath.\csr.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:435$14 ($eq). |
| Removed top 2 bits (of 12) from port A of cell Core.$flatten\dpath.\csr.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:436$15 ($eq). |
| Removed top 2 bits (of 12) from port A of cell Core.$flatten\dpath.\csr.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:437$16 ($eq). |
| Removed top 2 bits (of 12) from port A of cell Core.$flatten\dpath.\csr.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:438$17 ($eq). |
| Removed top 2 bits (of 12) from port A of cell Core.$flatten\dpath.\csr.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:439$18 ($eq). |
| Removed top 2 bits (of 12) from port A of cell Core.$flatten\dpath.\csr.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:440$19 ($eq). |
| Removed top 2 bits (of 12) from port A of cell Core.$flatten\dpath.\csr.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:441$20 ($eq). |
| Removed top 2 bits (of 12) from port A of cell Core.$flatten\dpath.\csr.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:442$21 ($eq). |
| Removed top 1 bits (of 32) from mux cell Core.$flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:443$22 ($mux). |
| Removed top 1 bits (of 32) from mux cell Core.$flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:444$23 ($mux). |
| Removed top 1 bits (of 32) from mux cell Core.$flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:445$24 ($mux). |
| Removed top 1 bits (of 3) from port A of cell Core.$flatten\dpath.\csr.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:476$49 ($eq). |
| Removed top 2 bits (of 3) from port A of cell Core.$flatten\dpath.\csr.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:478$51 ($eq). |
| Removed top 1 bits (of 2) from port A of cell Core.$flatten\dpath.\csr.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:482$55 ($eq). |
| Removed top 2 bits (of 3) from port B of cell Core.$flatten\dpath.\csr.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:506$78 ($eq). |
| Removed top 1 bits (of 3) from port A of cell Core.$flatten\dpath.\csr.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:514$85 ($eq). |
| Removed top 1 bits (of 3) from port A of cell Core.$flatten\dpath.\csr.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:516$87 ($eq). |
| Removed top 2 bits (of 3) from port A of cell Core.$flatten\dpath.\csr.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:518$89 ($eq). |
| Removed top 39 bits (of 42) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1814 ($eq). |
| Removed top 26 bits (of 30) from port A of cell Core.$flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:522$92 ($add). |
| Removed top 28 bits (of 30) from port B of cell Core.$flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:522$92 ($add). |
| Removed top 25 bits (of 30) from port Y of cell Core.$flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:522$92 ($add). |
| Removed top 29 bits (of 30) from mux cell Core.$flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:523$93 ($mux). |
| Removed top 25 bits (of 30) from mux cell Core.$flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:524$94 ($mux). |
| Removed top 25 bits (of 30) from mux cell Core.$flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:525$95 ($mux). |
| Removed top 25 bits (of 30) from mux cell Core.$flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:526$96 ($mux). |
| Removed top 25 bits (of 30) from mux cell Core.$flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:527$97 ($mux). |
| Removed top 28 bits (of 30) from mux cell Core.$flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:528$98 ($mux). |
| Removed top 28 bits (of 30) from mux cell Core.$flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:529$99 ($mux). |
| Removed top 25 bits (of 30) from mux cell Core.$flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:530$100 ($mux). |
| Removed top 25 bits (of 30) from mux cell Core.$flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:531$101 ($mux). |
| Removed top 25 bits (of 30) from mux cell Core.$flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:537$107 ($mux). |
| Removed top 25 bits (of 32) from port B of cell Core.$flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:547$112 ($add). |
| Removed top 31 bits (of 32) from port B of cell Core.$flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:565$129 ($add). |
| Removed top 31 bits (of 32) from port B of cell Core.$flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:569$133 ($add). |
| Removed top 31 bits (of 32) from port B of cell Core.$flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:572$136 ($add). |
| Removed top 31 bits (of 32) from port B of cell Core.$flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:576$140 ($add). |
| Removed top 27 bits (of 32) from port B of cell Core.$flatten\dpath.\csr.$ne$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:578$142 ($ne). |
| Removed top 31 bits (of 32) from port B of cell Core.$flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:586$150 ($add). |
| Removed top 31 bits (of 32) from port B of cell Core.$flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:592$156 ($add). |
| Removed top 29 bits (of 32) from port B of cell Core.$flatten\dpath.\csr.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:595$159 ($sub). |
| Removed top 1 bits (of 33) from port Y of cell Core.$flatten\dpath.\csr.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:595$159 ($sub). |
| Removed cell Core.$flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:602$162 ($mux). |
| Removed top 2 bits (of 12) from port B of cell Core.$flatten\dpath.\csr.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:607$166 ($eq). |
| Removed top 2 bits (of 12) from port B of cell Core.$flatten\dpath.\csr.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:612$167 ($eq). |
| Removed top 2 bits (of 12) from port B of cell Core.$flatten\dpath.\csr.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:616$168 ($eq). |
| Removed top 2 bits (of 12) from port B of cell Core.$flatten\dpath.\csr.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:617$169 ($eq). |
| Removed top 2 bits (of 12) from port B of cell Core.$flatten\dpath.\csr.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:618$170 ($eq). |
| Removed top 2 bits (of 12) from port B of cell Core.$flatten\dpath.\csr.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:619$171 ($eq). |
| Removed top 2 bits (of 12) from port B of cell Core.$flatten\dpath.\csr.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:623$174 ($eq). |
| Removed top 2 bits (of 12) from port B of cell Core.$flatten\dpath.\csr.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:625$176 ($eq). |
| Removed cell Core.$flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:629$180 ($mux). |
| Removed cell Core.$flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:633$184 ($mux). |
| Removed cell Core.$flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:638$189 ($mux). |
| Removed cell Core.$flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:648$199 ($mux). |
| Removed cell Core.$flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:660$211 ($mux). |
| Removed cell Core.$flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:676$227 ($mux). |
| Removed cell Core.$flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:692$243 ($mux). |
| Removed cell Core.$flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:708$259 ($mux). |
| Removed top 3 bits (of 35) from mux cell Core.$flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:711$262 ($mux). |
| Removed cell Core.$flatten\dpath.\csr.$procmux$1269 ($mux). |
| Removed cell Core.$flatten\dpath.\csr.$procmux$1271 ($mux). |
| Removed cell Core.$flatten\dpath.\csr.$procmux$1273 ($mux). |
| Removed cell Core.$flatten\dpath.\csr.$procmux$1275 ($mux). |
| Removed cell Core.$flatten\dpath.\csr.$procmux$1277 ($mux). |
| Removed cell Core.$flatten\dpath.\csr.$procmux$1279 ($mux). |
| Removed cell Core.$flatten\dpath.\csr.$procmux$1281 ($mux). |
| Removed cell Core.$flatten\dpath.\csr.$procmux$1283 ($mux). |
| Removed cell Core.$flatten\dpath.\csr.$procmux$1285 ($mux). |
| Removed cell Core.$flatten\dpath.\csr.$procmux$1287 ($mux). |
| Removed cell Core.$flatten\dpath.\csr.$procmux$1290 ($mux). |
| Removed cell Core.$flatten\dpath.\csr.$procmux$1296 ($mux). |
| Removed cell Core.$flatten\dpath.\csr.$procmux$1298 ($mux). |
| Removed cell Core.$flatten\dpath.\csr.$procmux$1300 ($mux). |
| Removed cell Core.$flatten\dpath.\csr.$procmux$1302 ($mux). |
| Removed cell Core.$flatten\dpath.\csr.$procmux$1304 ($mux). |
| Removed cell Core.$flatten\dpath.\csr.$procmux$1306 ($mux). |
| Removed cell Core.$flatten\dpath.\csr.$procmux$1308 ($mux). |
| Removed cell Core.$flatten\dpath.\csr.$procmux$1310 ($mux). |
| Removed cell Core.$flatten\dpath.\csr.$procmux$1312 ($mux). |
| Removed top 1 bits (of 2) from port B of cell Core.$auto$opt_dff.cc:198:make_patterns_logic$1843 ($ne). |
| Removed cell Core.$flatten\dpath.\csr.$procmux$1555 ($mux). |
| Removed cell Core.$flatten\dpath.\csr.$procmux$1557 ($mux). |
| Removed cell Core.$flatten\dpath.$procmux$1197 ($mux). |
| Removed cell Core.$flatten\dpath.$procmux$1177 ($mux). |
| Removed cell Core.$flatten\dpath.$procmux$1169 ($mux). |
| Removed top 7 bits (of 10) from port B of cell Core.$auto$opt_dff.cc:198:make_patterns_logic$1852 ($ne). |
| Removed top 1 bits (of 33) from mux cell Core.$flatten\dpath.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2259$568 ($mux). |
| Removed top 1 bits (of 33) from mux cell Core.$flatten\dpath.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2257$566 ($mux). |
| Removed top 10 bits (of 13) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1787 ($eq). |
| Removed top 1 bits (of 33) from mux cell Core.$flatten\dpath.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2255$564 ($mux). |
| Removed top 29 bits (of 32) from port B of cell Core.$flatten\dpath.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2251$562 ($add). |
| Removed top 11 bits (of 14) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1785 ($eq). |
| Removed top 1 bits (of 33) from mux cell Core.$flatten\dpath.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2210$522 ($mux). |
| Removed top 1 bits (of 33) from mux cell Core.$flatten\dpath.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2209$521 ($mux). |
| Removed top 1 bits (of 33) from mux cell Core.$flatten\dpath.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2208$520 ($mux). |
| Removed top 1 bits (of 33) from mux cell Core.$flatten\dpath.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2207$519 ($mux). |
| Removed top 29 bits (of 32) from port B of cell Core.$flatten\dpath.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2205$517 ($add). |
| Removed top 1 bits (of 2) from port B of cell Core.$flatten\dpath.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2198$511 ($eq). |
| Removed top 1 bits (of 33) from port Y of cell Core.$flatten\dpath.\cond_br.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1812$445 ($sub). |
| Removed top 31 bits (of 32) from port A of cell Core.$flatten\dpath.\alu.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1553$347 ($sub). |
| Removed top 1 bits (of 33) from port Y of cell Core.$flatten\dpath.\alu.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1553$347 ($sub). |
| Removed top 1 bits (of 4) from port B of cell Core.$auto$opt_dff.cc:198:make_patterns_logic$1989 ($ne). |
| Removed top 6 bits (of 9) from port B of cell Core.$auto$opt_dff.cc:198:make_patterns_logic$1877 ($ne). |
| Removed top 17 bits (of 20) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1735 ($eq). |
| Removed top 18 bits (of 21) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1733 ($eq). |
| Removed top 19 bits (of 22) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1731 ($eq). |
| Removed top 20 bits (of 23) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1729 ($eq). |
| Removed top 21 bits (of 24) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1727 ($eq). |
| Removed top 22 bits (of 25) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1725 ($eq). |
| Removed top 23 bits (of 26) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1723 ($eq). |
| Removed top 24 bits (of 27) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1721 ($eq). |
| Removed top 25 bits (of 28) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1719 ($eq). |
| Removed top 26 bits (of 29) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1717 ($eq). |
| Removed top 27 bits (of 30) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1715 ($eq). |
| Removed top 28 bits (of 31) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1713 ($eq). |
| Removed top 29 bits (of 32) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1711 ($eq). |
| Removed top 30 bits (of 33) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1709 ($eq). |
| Removed top 31 bits (of 34) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1707 ($eq). |
| Removed top 32 bits (of 35) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1705 ($eq). |
| Removed top 33 bits (of 36) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1703 ($eq). |
| Removed top 34 bits (of 37) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1701 ($eq). |
| Removed top 35 bits (of 38) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1699 ($eq). |
| Removed top 36 bits (of 39) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1697 ($eq). |
| Removed top 37 bits (of 40) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1695 ($eq). |
| Removed top 38 bits (of 41) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1693 ($eq). |
| Removed top 49 bits (of 50) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1691 ($eq). |
| Removed top 16 bits (of 19) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1737 ($eq). |
| Removed top 12 bits (of 15) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1783 ($eq). |
| Removed top 13 bits (of 16) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1781 ($eq). |
| Removed top 14 bits (of 17) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1779 ($eq). |
| Removed top 8 bits (of 11) from port B of cell Core.$auto$opt_dff.cc:198:make_patterns_logic$1825 ($ne). |
| Removed top 2 bits (of 5) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1768 ($eq). |
| Removed top 3 bits (of 6) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1766 ($eq). |
| Removed top 1 bits (of 4) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1753 ($eq). |
| Removed top 4 bits (of 7) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1751 ($eq). |
| Removed top 5 bits (of 8) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1749 ($eq). |
| Removed top 6 bits (of 9) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1747 ($eq). |
| Removed top 7 bits (of 10) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1745 ($eq). |
| Removed top 8 bits (of 11) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1743 ($eq). |
| Removed top 9 bits (of 12) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1741 ($eq). |
| Removed top 15 bits (of 18) from port B of cell Core.$auto$fsm_map.cc:77:implement_pattern_cache$1739 ($eq). |
| Removed top 1 bits (of 2) from mux cell Core.$flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3401$901 ($mux). |
| Removed top 1 bits (of 4) from mux cell Core.$flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3304$804 ($mux). |
| Removed top 3 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3137$637 ($eq). |
| Removed top 2 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3136$636 ($eq). |
| Removed top 11 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3135$635 ($eq). |
| Removed top 25 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3134$634 ($eq). |
| Removed top 17 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3133$633 ($eq). |
| Removed top 17 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3132$632 ($eq). |
| Removed top 17 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3131$631 ($eq). |
| Removed top 18 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3130$630 ($eq). |
| Removed top 18 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3129$629 ($eq). |
| Removed top 19 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3128$628 ($eq). |
| Removed top 19 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3127$627 ($eq). |
| Removed top 28 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3126$626 ($eq). |
| Removed top 17 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3124$624 ($eq). |
| Removed top 17 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3123$623 ($eq). |
| Removed top 1 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3122$622 ($eq). |
| Removed top 17 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3121$621 ($eq). |
| Removed top 17 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3120$620 ($eq). |
| Removed top 18 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3119$619 ($eq). |
| Removed top 18 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3118$618 ($eq). |
| Removed top 19 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3117$617 ($eq). |
| Removed top 1 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3116$616 ($eq). |
| Removed top 26 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3115$615 ($eq). |
| Removed top 1 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3114$614 ($eq). |
| Removed top 17 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3113$613 ($eq). |
| Removed top 19 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3112$612 ($eq). |
| Removed top 17 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3110$610 ($eq). |
| Removed top 17 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3109$609 ($eq). |
| Removed top 17 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3108$608 ($eq). |
| Removed top 18 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3107$607 ($eq). |
| Removed top 18 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3106$606 ($eq). |
| Removed top 27 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3105$605 ($eq). |
| Removed top 18 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3104$604 ($eq). |
| Removed top 19 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3103$603 ($eq). |
| Removed top 26 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3102$602 ($eq). |
| Removed top 17 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3101$601 ($eq). |
| Removed top 17 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3100$600 ($eq). |
| Removed top 18 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3099$599 ($eq). |
| Removed top 19 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3098$598 ($eq). |
| Removed top 30 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3097$597 ($eq). |
| Removed top 17 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3096$596 ($eq). |
| Removed top 17 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3095$595 ($eq). |
| Removed top 17 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3094$594 ($eq). |
| Removed top 17 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3093$593 ($eq). |
| Removed top 19 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3092$592 ($eq). |
| Removed top 25 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3091$591 ($eq). |
| Removed top 25 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3090$590 ($eq). |
| Removed top 17 bits (of 32) from port B of cell Core.$flatten\ctrl.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3089$589 ($and). |
| Removed top 25 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3088$588 ($eq). |
| Removed top 27 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3087$587 ($eq). |
| Removed top 26 bits (of 32) from port A of cell Core.$flatten\ctrl.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3086$586 ($eq). |
| Removed top 25 bits (of 32) from port B of cell Core.$flatten\ctrl.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3085$585 ($and). |
| |
| 6.11. Executing PEEPOPT pass (run peephole optimizers). |
| |
| 6.12. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Core.. |
| Removed 0 unused cells and 27 unused wires. |
| <suppressed ~1 debug messages> |
| |
| 6.13. Executing ALUMACC pass (create $alu and $macc cells). |
| Extracting $alu and $macc cells in module Core: |
| creating $macc model for $flatten\dpath.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2205$517 ($add). |
| creating $macc model for $flatten\dpath.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2251$562 ($add). |
| creating $macc model for $flatten\dpath.\alu.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1558$350 ($add). |
| creating $macc model for $flatten\dpath.\alu.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1553$347 ($sub). |
| creating $macc model for $flatten\dpath.\cond_br.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1812$445 ($sub). |
| creating $macc model for $flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:522$92 ($add). |
| creating $macc model for $flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:547$112 ($add). |
| creating $macc model for $flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:565$129 ($add). |
| creating $macc model for $flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:569$133 ($add). |
| creating $macc model for $flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:572$136 ($add). |
| creating $macc model for $flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:576$140 ($add). |
| creating $macc model for $flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:586$150 ($add). |
| creating $macc model for $flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:592$156 ($add). |
| creating $macc model for $flatten\dpath.\csr.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:595$159 ($sub). |
| creating $alu model for $macc $flatten\dpath.\csr.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:595$159. |
| creating $alu model for $macc $flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:592$156. |
| creating $alu model for $macc $flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:586$150. |
| creating $alu model for $macc $flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:576$140. |
| creating $alu model for $macc $flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:572$136. |
| creating $alu model for $macc $flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:569$133. |
| creating $alu model for $macc $flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:565$129. |
| creating $alu model for $macc $flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:547$112. |
| creating $alu model for $macc $flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:522$92. |
| creating $alu model for $macc $flatten\dpath.\cond_br.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1812$445. |
| creating $alu model for $macc $flatten\dpath.\alu.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1553$347. |
| creating $alu model for $macc $flatten\dpath.\alu.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1558$350. |
| creating $alu model for $macc $flatten\dpath.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2251$562. |
| creating $alu model for $macc $flatten\dpath.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2205$517. |
| creating $alu model for $flatten\dpath.\csr.$le$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:458$36 ($le): new $alu |
| creating $alu cell for $flatten\dpath.\csr.$le$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:458$36: $auto$alumacc.cc:485:replace_alu$2056 |
| creating $alu cell for $flatten\dpath.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2205$517: $auto$alumacc.cc:485:replace_alu$2065 |
| creating $alu cell for $flatten\dpath.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2251$562: $auto$alumacc.cc:485:replace_alu$2068 |
| creating $alu cell for $flatten\dpath.\alu.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1558$350: $auto$alumacc.cc:485:replace_alu$2071 |
| creating $alu cell for $flatten\dpath.\alu.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1553$347: $auto$alumacc.cc:485:replace_alu$2074 |
| creating $alu cell for $flatten\dpath.\cond_br.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1812$445: $auto$alumacc.cc:485:replace_alu$2077 |
| creating $alu cell for $flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:522$92: $auto$alumacc.cc:485:replace_alu$2080 |
| creating $alu cell for $flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:547$112: $auto$alumacc.cc:485:replace_alu$2083 |
| creating $alu cell for $flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:565$129: $auto$alumacc.cc:485:replace_alu$2086 |
| creating $alu cell for $flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:569$133: $auto$alumacc.cc:485:replace_alu$2089 |
| creating $alu cell for $flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:572$136: $auto$alumacc.cc:485:replace_alu$2092 |
| creating $alu cell for $flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:576$140: $auto$alumacc.cc:485:replace_alu$2095 |
| creating $alu cell for $flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:586$150: $auto$alumacc.cc:485:replace_alu$2098 |
| creating $alu cell for $flatten\dpath.\csr.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:592$156: $auto$alumacc.cc:485:replace_alu$2101 |
| creating $alu cell for $flatten\dpath.\csr.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:595$159: $auto$alumacc.cc:485:replace_alu$2104 |
| created 15 $alu and 0 $macc cells. |
| |
| 6.14. Executing SHARE pass (SAT-based resource sharing). |
| Found 3 cells in module Core that may be considered for resource sharing. |
| Analyzing resource sharing options for $flatten\dpath.\reg_file.$memrd$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1373$332 ($memrd): |
| Found 1 activation_patterns using ctrl signal { \dpath._T_188 \dpath._T_194 }. |
| Found 1 candidates: $flatten\dpath.\reg_file.$memrd$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1371$331 |
| Analyzing resource sharing with $flatten\dpath.\reg_file.$memrd$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1371$331 ($memrd): |
| Found 1 activation_patterns using ctrl signal { \dpath._T_184 \dpath._T_192 }. |
| Forbidden control signals for this pair of cells: { \dpath._T_157 \dpath._T_176 \dpath.alu._T_24 \dpath.cond_br.is_same_sign } |
| Activation pattern for cell $flatten\dpath.\reg_file.$memrd$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1373$332: { \dpath._T_188 \dpath._T_194 } = 2'10 |
| Activation pattern for cell $flatten\dpath.\reg_file.$memrd$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1371$331: { \dpath._T_184 \dpath._T_192 } = 2'10 |
| Size of SAT problem: 0 cells, 115 variables, 287 clauses |
| According to the SAT solver this pair of cells can not be shared. |
| Model from SAT solver: { \dpath._T_184 \dpath._T_188 \dpath._T_192 \dpath._T_194 } = 4'1100 |
| Analyzing resource sharing options for $flatten\dpath.\reg_file.$memrd$\regs$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1371$331 ($memrd): |
| Found 1 activation_patterns using ctrl signal { \dpath._T_184 \dpath._T_192 }. |
| No candidates found. |
| Analyzing resource sharing options for $flatten\dpath.\alu.$sshr$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:1612$375 ($sshr): |
| Found 2 activation_patterns using ctrl signal { \dpath.alu._T_160 \dpath.alu._T_159 \dpath.alu._T_156 \dpath.alu._T_153 }. |
| No candidates found. |
| |
| 6.15. Executing OPT pass (performing simple optimizations). |
| |
| 6.15.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Core. |
| |
| 6.15.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Core'. |
| Removed a total of 0 cells. |
| |
| 6.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \Core.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~62 debug messages> |
| |
| 6.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \Core. |
| Performed a total of 0 changes. |
| |
| 6.15.5. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Core'. |
| Removed a total of 0 cells. |
| |
| 6.15.6. Executing OPT_DFF pass (perform DFF optimizations). |
| Adding SRST signal on $auto$ff.cc:262:slice$1872 ($dffe) from module Core (D = \dpath.csr._T_542 [29:5], Q = \dpath.csr.mcause [29:5], rval = 25'0000000000000000000000000). |
| |
| 6.15.7. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Core.. |
| Removed 0 unused cells and 1 unused wires. |
| <suppressed ~1 debug messages> |
| |
| 6.15.8. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Core. |
| |
| 6.15.9. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 6.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \Core.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~62 debug messages> |
| |
| 6.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \Core. |
| Performed a total of 0 changes. |
| |
| 6.15.12. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Core'. |
| Removed a total of 0 cells. |
| |
| 6.15.13. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 6.15.14. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Core.. |
| |
| 6.15.15. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Core. |
| |
| 6.15.16. Finished OPT passes. (There is nothing left to do.) |
| |
| 6.16. Executing MEMORY pass. |
| |
| 6.16.1. Executing OPT_MEM pass (optimize memories). |
| Performed a total of 0 transformations. |
| |
| 6.16.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). |
| Performed a total of 0 transformations. |
| |
| 6.16.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). |
| Analyzing Core.dpath.reg_file.regs write port 0. |
| |
| 6.16.4. Executing MEMORY_DFF pass (merging $dff cells to $memrd). |
| Checking read port `\dpath.reg_file.regs'[0] in module `\Core': no output FF found. |
| Checking read port `\dpath.reg_file.regs'[1] in module `\Core': no output FF found. |
| Checking read port address `\dpath.reg_file.regs'[0] in module `\Core': merged address FF to cell. |
| Checking read port address `\dpath.reg_file.regs'[1] in module `\Core': merged address FF to cell. |
| |
| 6.16.5. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Core.. |
| |
| 6.16.6. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). |
| Consolidating read ports of memory Core.dpath.reg_file.regs by address: |
| |
| 6.16.7. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). |
| Performed a total of 0 transformations. |
| |
| 6.16.8. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Core.. |
| |
| 6.16.9. Executing MEMORY_COLLECT pass (generating $mem cells). |
| |
| 6.17. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Core.. |
| |
| 6.18. Executing OPT pass (performing simple optimizations). |
| |
| 6.18.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Core. |
| <suppressed ~353 debug messages> |
| |
| 6.18.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Core'. |
| Removed a total of 0 cells. |
| |
| 6.18.3. Executing OPT_DFF pass (perform DFF optimizations). |
| Setting constant 0-bit at position 0 on $auto$ff.cc:262:slice$1871 ($sdffce) from module Core. |
| Setting constant 0-bit at position 0 on $auto$ff.cc:262:slice$2107 ($sdffce) from module Core. |
| Setting constant 0-bit at position 1 on $auto$ff.cc:262:slice$2107 ($sdffce) from module Core. |
| Setting constant 0-bit at position 2 on $auto$ff.cc:262:slice$2107 ($sdffce) from module Core. |
| Setting constant 0-bit at position 3 on $auto$ff.cc:262:slice$2107 ($sdffce) from module Core. |
| Setting constant 0-bit at position 4 on $auto$ff.cc:262:slice$2107 ($sdffce) from module Core. |
| Setting constant 0-bit at position 5 on $auto$ff.cc:262:slice$2107 ($sdffce) from module Core. |
| Setting constant 0-bit at position 6 on $auto$ff.cc:262:slice$2107 ($sdffce) from module Core. |
| Setting constant 0-bit at position 7 on $auto$ff.cc:262:slice$2107 ($sdffce) from module Core. |
| Setting constant 0-bit at position 8 on $auto$ff.cc:262:slice$2107 ($sdffce) from module Core. |
| Setting constant 0-bit at position 9 on $auto$ff.cc:262:slice$2107 ($sdffce) from module Core. |
| Setting constant 0-bit at position 10 on $auto$ff.cc:262:slice$2107 ($sdffce) from module Core. |
| Setting constant 0-bit at position 11 on $auto$ff.cc:262:slice$2107 ($sdffce) from module Core. |
| Setting constant 0-bit at position 12 on $auto$ff.cc:262:slice$2107 ($sdffce) from module Core. |
| Setting constant 0-bit at position 13 on $auto$ff.cc:262:slice$2107 ($sdffce) from module Core. |
| Setting constant 0-bit at position 14 on $auto$ff.cc:262:slice$2107 ($sdffce) from module Core. |
| Setting constant 0-bit at position 15 on $auto$ff.cc:262:slice$2107 ($sdffce) from module Core. |
| Setting constant 0-bit at position 16 on $auto$ff.cc:262:slice$2107 ($sdffce) from module Core. |
| Setting constant 0-bit at position 17 on $auto$ff.cc:262:slice$2107 ($sdffce) from module Core. |
| Setting constant 0-bit at position 18 on $auto$ff.cc:262:slice$2107 ($sdffce) from module Core. |
| Setting constant 0-bit at position 19 on $auto$ff.cc:262:slice$2107 ($sdffce) from module Core. |
| Setting constant 0-bit at position 20 on $auto$ff.cc:262:slice$2107 ($sdffce) from module Core. |
| Setting constant 0-bit at position 21 on $auto$ff.cc:262:slice$2107 ($sdffce) from module Core. |
| Setting constant 0-bit at position 22 on $auto$ff.cc:262:slice$2107 ($sdffce) from module Core. |
| Setting constant 0-bit at position 23 on $auto$ff.cc:262:slice$2107 ($sdffce) from module Core. |
| Setting constant 0-bit at position 24 on $auto$ff.cc:262:slice$2107 ($sdffce) from module Core. |
| |
| 6.18.4. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Core.. |
| Removed 2 unused cells and 73 unused wires. |
| <suppressed ~5 debug messages> |
| |
| 6.18.5. Rerunning OPT passes. (Removed registers in this run.) |
| |
| 6.18.6. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Core. |
| |
| 6.18.7. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Core'. |
| Removed a total of 0 cells. |
| |
| 6.18.8. Executing OPT_DFF pass (perform DFF optimizations). |
| Adding SRST signal on $auto$ff.cc:262:slice$2108 ($dffe) from module Core (D = \dpath.csr.cause [4], Q = \dpath.csr.mcause [4], rval = 1'0). |
| |
| 6.18.9. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Core.. |
| |
| 6.18.10. Rerunning OPT passes. (Removed registers in this run.) |
| |
| 6.18.11. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Core. |
| |
| 6.18.12. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Core'. |
| Removed a total of 0 cells. |
| |
| 6.18.13. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 6.18.14. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Core.. |
| |
| 6.18.15. Finished fast OPT passes. |
| |
| 6.19. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). |
| Mapping memory \dpath.reg_file.regs in module \Core: |
| created 32 $dff cells and 0 static cells of width 32. |
| Extracted addr FF from read port 0 of Core.dpath.reg_file.regs: $\dpath.reg_file.regs$rdreg[0] |
| Extracted addr FF from read port 1 of Core.dpath.reg_file.regs: $\dpath.reg_file.regs$rdreg[1] |
| read interface: 2 $dff and 62 $mux cells. |
| write interface: 32 write mux blocks. |
| |
| 6.20. Executing OPT pass (performing simple optimizations). |
| |
| 6.20.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Core. |
| <suppressed ~10 debug messages> |
| |
| 6.20.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Core'. |
| Removed a total of 0 cells. |
| |
| 6.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \Core.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~99 debug messages> |
| |
| 6.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \Core. |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3138$638: |
| Old ports: A=2'00, B=2'11, Y=\ctrl._T_234 |
| New ports: A=1'0, B=1'1, Y=\ctrl._T_234 [0] |
| New connections: \ctrl._T_234 [1] = \ctrl._T_234 [0] |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3260$760: |
| Old ports: A=3'000, B=3'110, Y=\ctrl._T_381 |
| New ports: A=1'0, B=1'1, Y=\ctrl._T_381 [1] |
| New connections: { \ctrl._T_381 [2] \ctrl._T_381 [0] } = { \ctrl._T_381 [1] 1'0 } |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3304$804: |
| Old ports: A=3'111, B=3'010, Y=\ctrl._T_432 [2:0] |
| New ports: A=1'1, B=1'0, Y=\ctrl._T_432 [0] |
| New connections: \ctrl._T_432 [2:1] = { \ctrl._T_432 [0] 1'1 } |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3305$805: |
| Old ports: A={ 1'1 \ctrl._T_432 [2:0] }, B=4'1010, Y=\ctrl._T_433 |
| New ports: A=\ctrl._T_432 [2:0], B=3'010, Y=\ctrl._T_433 [2:0] |
| New connections: \ctrl._T_433 [3] = 1'1 |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3346$846: |
| Old ports: A=3'000, B=3'100, Y=\ctrl._T_512 |
| New ports: A=1'0, B=1'1, Y=\ctrl._T_512 [2] |
| New connections: \ctrl._T_512 [1:0] = 2'00 |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3418$918: |
| Old ports: A=3'000, B=3'100, Y=\ctrl._T_651 |
| New ports: A=1'0, B=1'1, Y=\ctrl._T_651 [2] |
| New connections: \ctrl._T_651 [1:0] = 2'00 |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3521$1021: |
| Old ports: A=3'000, B=3'100, Y=\ctrl._T_762 |
| New ports: A=1'0, B=1'1, Y=\ctrl._T_762 [2] |
| New connections: \ctrl._T_762 [1:0] = 2'00 |
| Consolidated identical input bits for $mux cell $flatten\dpath.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:2206$518: |
| Old ports: A={ \dpath._T_165 [31:2] \dpath.pc [1:0] }, B=\dpath.pc, Y=\dpath._T_166 |
| New ports: A=\dpath._T_165 [31:2], B=\dpath.pc [31:2], Y=\dpath._T_166 [31:2] |
| New connections: \dpath._T_166 [1:0] = \dpath.pc [1:0] |
| Consolidated identical input bits for $mux cell $flatten\dpath.\csr.$procmux$1315: |
| Old ports: A={ \dpath.csr.wdata [31] 27'000000000000000000000000000 \dpath.csr.wdata [3:0] }, B={ \dpath.csr.isInt 26'00000000000000000000000000 \dpath.csr.cause [4:0] }, Y=$flatten\dpath.\csr.$procmux$1315_Y |
| New ports: A={ \dpath.csr.wdata [31] 1'0 \dpath.csr.wdata [3:0] }, B={ \dpath.csr.isInt \dpath.csr.cause [4:0] }, Y={ $flatten\dpath.\csr.$procmux$1315_Y [31] $flatten\dpath.\csr.$procmux$1315_Y [4:0] } |
| New connections: $flatten\dpath.\csr.$procmux$1315_Y [30:5] = 26'00000000000000000000000000 |
| Consolidated identical input bits for $mux cell $flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:443$22: |
| Old ports: A=31'0000000000000000000000000000000, B=31'1000000000000000000000100000000, Y=\dpath.csr._T_255 [30:0] |
| New ports: A=1'0, B=1'1, Y=\dpath.csr._T_255 [8] |
| New connections: { \dpath.csr._T_255 [30:9] \dpath.csr._T_255 [7:0] } = { \dpath.csr._T_255 [8] 29'00000000000000000000000000000 } |
| Consolidated identical input bits for $mux cell $flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:524$94: |
| Old ports: A={ 4'0001 \dpath.csr.isEbreak }, B={ 3'010 \dpath.csr.mstatus_prv }, Y=\dpath.csr._T_413 [4:0] |
| New ports: A={ 2'01 \dpath.csr.isEbreak }, B={ 1'1 \dpath.csr.mstatus_prv }, Y={ \dpath.csr._T_413 [3] \dpath.csr._T_413 [1:0] } |
| New connections: { \dpath.csr._T_413 [4] \dpath.csr._T_413 [2] } = 2'00 |
| Consolidated identical input bits for $mux cell $flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:530$100: |
| Old ports: A={ 3'100 \dpath.csr._T_417 [1:0] }, B=5'00111, Y=\dpath.csr._T_418 [4:0] |
| New ports: A={ 2'10 \dpath.csr._T_417 [1:0] }, B=4'0111, Y={ \dpath.csr._T_418 [4] \dpath.csr._T_418 [2:0] } |
| New connections: \dpath.csr._T_418 [3] = 1'0 |
| Consolidated identical input bits for $mux cell $flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:598$160: |
| Old ports: A=\dpath.exe_wb_pc, B={ \dpath.csr._T_502 [31:2] \dpath.exe_wb_pc [1:0] }, Y=\dpath.csr._T_503 |
| New ports: A=\dpath.exe_wb_pc [31:2], B=\dpath.csr._T_502 [31:2], Y=\dpath.csr._T_503 [31:2] |
| New connections: \dpath.csr._T_503 [1:0] = \dpath.exe_wb_pc [1:0] |
| Consolidated identical input bits for $mux cell $flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:711$262: |
| Old ports: A={ \dpath.csr.wdata [31:2] 2'00 }, B={ \dpath.csr._T_503 [31:2] 2'00 }, Y=\dpath.csr._GEN_109 [31:0] |
| New ports: A=\dpath.csr.wdata [31:2], B=\dpath.csr._T_503 [31:2], Y=\dpath.csr._GEN_109 [31:2] |
| New connections: \dpath.csr._GEN_109 [1:0] = 2'00 |
| Consolidated identical input bits for $mux cell $flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:736$287: |
| Old ports: A={ \dpath.csr.mtvec [31:2] 2'00 }, B={ \dpath.csr._T_430 [31:2] 2'00 }, Y=\dpath.csr_io_evec |
| New ports: A=\dpath.csr.mtvec [31:2], B=\dpath.csr._T_430 [31:2], Y=\dpath.csr_io_evec [31:2] |
| New connections: \dpath.csr_io_evec [1:0] = 2'00 |
| Optimizing cells in module \Core. |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3139$639: |
| Old ports: A=\ctrl._T_234, B=2'00, Y=\ctrl._T_235 |
| New ports: A=\ctrl._T_234 [0], B=1'0, Y=\ctrl._T_235 [0] |
| New connections: \ctrl._T_235 [1] = \ctrl._T_235 [0] |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3261$761: |
| Old ports: A=\ctrl._T_381, B=3'110, Y=\ctrl._T_382 |
| New ports: A=\ctrl._T_381 [1], B=1'1, Y=\ctrl._T_382 [1] |
| New connections: { \ctrl._T_382 [2] \ctrl._T_382 [0] } = { \ctrl._T_382 [1] 1'0 } |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3305$805: |
| Old ports: A=\ctrl._T_432 [2:0], B=3'010, Y=\ctrl._T_433 [2:0] |
| New ports: A=\ctrl._T_432 [0], B=1'0, Y=\ctrl._T_433 [0] |
| New connections: \ctrl._T_433 [2:1] = { \ctrl._T_433 [0] 1'1 } |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3306$806: |
| Old ports: A=\ctrl._T_433, B=4'1010, Y=\ctrl._T_434 |
| New ports: A=\ctrl._T_433 [2:0], B=3'010, Y=\ctrl._T_434 [2:0] |
| New connections: \ctrl._T_434 [3] = 1'1 |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3347$847: |
| Old ports: A=\ctrl._T_512, B=3'001, Y=\ctrl._T_513 |
| New ports: A={ \ctrl._T_512 [2] 1'0 }, B=2'01, Y={ \ctrl._T_513 [2] \ctrl._T_513 [0] } |
| New connections: \ctrl._T_513 [1] = 1'0 |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3419$919: |
| Old ports: A=\ctrl._T_651, B=3'101, Y=\ctrl._T_652 |
| New ports: A={ \ctrl._T_651 [2] 1'0 }, B=2'11, Y={ \ctrl._T_652 [2] \ctrl._T_652 [0] } |
| New connections: \ctrl._T_652 [1] = 1'0 |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3522$1022: |
| Old ports: A=\ctrl._T_762, B=3'100, Y=\ctrl._T_763 |
| New ports: A=\ctrl._T_762 [2], B=1'1, Y=\ctrl._T_763 [2] |
| New connections: \ctrl._T_763 [1:0] = 2'00 |
| Consolidated identical input bits for $mux cell $flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:444$23: |
| Old ports: A=\dpath.csr._T_255 [30:0], B={ 6'000000 \dpath.csr.mstatus_prv 10'0000000000 \dpath.csr.mstatus_mpp 3'000 \dpath.csr.mstatus_mpie 3'000 \dpath.csr.mstatus_mie 3'000 }, Y=\dpath.csr._T_256 [30:0] |
| New ports: A={ 4'0000 \dpath.csr._T_255 [8] 2'00 }, B={ \dpath.csr.mstatus_prv \dpath.csr.mstatus_mpp 1'0 \dpath.csr.mstatus_mpie \dpath.csr.mstatus_mie }, Y={ \dpath.csr._T_256 [24:23] \dpath.csr._T_256 [12:11] \dpath.csr._T_256 [8:7] \dpath.csr._T_256 [3] } |
| New connections: { \dpath.csr._T_256 [30:25] \dpath.csr._T_256 [22:13] \dpath.csr._T_256 [10:9] \dpath.csr._T_256 [6:4] \dpath.csr._T_256 [2:0] } = { \dpath.csr._T_256 [8] 23'00000000000000000000000 } |
| Consolidated identical input bits for $mux cell $flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:525$95: |
| Old ports: A=\dpath.csr._T_413 [4:0], B=5'00110, Y=\dpath.csr._T_414 [4:0] |
| New ports: A={ \dpath.csr._T_413 [3] 1'0 \dpath.csr._T_413 [1:0] }, B=4'0110, Y=\dpath.csr._T_414 [3:0] |
| New connections: \dpath.csr._T_414 [4] = 1'0 |
| Consolidated identical input bits for $mux cell $flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:531$101: |
| Old ports: A=\dpath.csr._T_418 [4:0], B=5'00011, Y=\dpath.csr.causeInt [4:0] |
| New ports: A={ \dpath.csr._T_418 [4] \dpath.csr._T_418 [2:0] }, B=4'0011, Y={ \dpath.csr.causeInt [4] \dpath.csr.causeInt [2:0] } |
| New connections: \dpath.csr.causeInt [3] = 1'0 |
| Optimizing cells in module \Core. |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3140$640: |
| Old ports: A=\ctrl._T_235, B=2'00, Y=\ctrl._T_236 |
| New ports: A=\ctrl._T_235 [0], B=1'0, Y=\ctrl._T_236 [0] |
| New connections: \ctrl._T_236 [1] = \ctrl._T_236 [0] |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3262$762: |
| Old ports: A=\ctrl._T_382, B=3'110, Y=\ctrl._T_383 |
| New ports: A=\ctrl._T_382 [1], B=1'1, Y=\ctrl._T_383 [1] |
| New connections: { \ctrl._T_383 [2] \ctrl._T_383 [0] } = { \ctrl._T_383 [1] 1'0 } |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3306$806: |
| Old ports: A=\ctrl._T_433 [2:0], B=3'010, Y=\ctrl._T_434 [2:0] |
| New ports: A=\ctrl._T_433 [0], B=1'0, Y=\ctrl._T_434 [0] |
| New connections: \ctrl._T_434 [2:1] = { \ctrl._T_434 [0] 1'1 } |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3307$807: |
| Old ports: A=\ctrl._T_434, B=4'1111, Y=\ctrl._T_435 |
| New ports: A=\ctrl._T_434 [2:0], B=3'111, Y=\ctrl._T_435 [2:0] |
| New connections: \ctrl._T_435 [3] = 1'1 |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3348$848: |
| Old ports: A=\ctrl._T_513, B=3'101, Y=\ctrl._T_514 |
| New ports: A={ \ctrl._T_513 [2] \ctrl._T_513 [0] }, B=2'11, Y={ \ctrl._T_514 [2] \ctrl._T_514 [0] } |
| New connections: \ctrl._T_514 [1] = 1'0 |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3420$920: |
| Old ports: A=\ctrl._T_652, B=3'001, Y=\ctrl._T_653 |
| New ports: A={ \ctrl._T_652 [2] \ctrl._T_652 [0] }, B=2'01, Y={ \ctrl._T_653 [2] \ctrl._T_653 [0] } |
| New connections: \ctrl._T_653 [1] = 1'0 |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3523$1023: |
| Old ports: A=\ctrl._T_763, B=3'100, Y=\ctrl._T_764 |
| New ports: A=\ctrl._T_763 [2], B=1'1, Y=\ctrl._T_764 [2] |
| New connections: \ctrl._T_764 [1:0] = 2'00 |
| Consolidated identical input bits for $mux cell $flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:445$24: |
| Old ports: A=\dpath.csr._T_256 [30:0], B={ 12'000000000000 \dpath.csr.mip_motorip \dpath.csr.mip_spiip \dpath.csr.mip_uartip 8'00000000 \dpath.csr.mip_mtip 3'000 \dpath.csr.mip_msip 3'000 }, Y=\dpath.csr._T_257 [30:0] |
| New ports: A={ \dpath.csr._T_256 [24:23] 3'000 \dpath.csr._T_256 [12:11] \dpath.csr._T_256 [8:7] \dpath.csr._T_256 [3] }, B={ 2'00 \dpath.csr.mip_motorip \dpath.csr.mip_spiip \dpath.csr.mip_uartip 3'000 \dpath.csr.mip_mtip \dpath.csr.mip_msip }, Y={ \dpath.csr._T_257 [24:23] \dpath.csr._T_257 [18:16] \dpath.csr._T_257 [12:11] \dpath.csr._T_257 [8:7] \dpath.csr._T_257 [3] } |
| New connections: { \dpath.csr._T_257 [30:25] \dpath.csr._T_257 [22:19] \dpath.csr._T_257 [15:13] \dpath.csr._T_257 [10:9] \dpath.csr._T_257 [6:4] \dpath.csr._T_257 [2:0] } = { \dpath.csr._T_257 [8] 20'00000000000000000000 } |
| Consolidated identical input bits for $mux cell $flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:526$96: |
| Old ports: A=\dpath.csr._T_414 [4:0], B=5'00100, Y=\dpath.csr._T_415 [4:0] |
| New ports: A=\dpath.csr._T_414 [3:0], B=4'0100, Y=\dpath.csr._T_415 [3:0] |
| New connections: \dpath.csr._T_415 [4] = 1'0 |
| Optimizing cells in module \Core. |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3141$641: |
| Old ports: A=\ctrl._T_236, B=2'00, Y=\ctrl._T_237 |
| New ports: A=\ctrl._T_236 [0], B=1'0, Y=\ctrl._T_237 [0] |
| New connections: \ctrl._T_237 [1] = \ctrl._T_237 [0] |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3263$763: |
| Old ports: A=\ctrl._T_383, B=3'000, Y=\ctrl._T_384 |
| New ports: A=\ctrl._T_383 [1], B=1'0, Y=\ctrl._T_384 [1] |
| New connections: { \ctrl._T_384 [2] \ctrl._T_384 [0] } = { \ctrl._T_384 [1] 1'0 } |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3307$807: |
| Old ports: A=\ctrl._T_434 [2:0], B=3'111, Y=\ctrl._T_435 [2:0] |
| New ports: A=\ctrl._T_434 [0], B=1'1, Y=\ctrl._T_435 [0] |
| New connections: \ctrl._T_435 [2:1] = { \ctrl._T_435 [0] 1'1 } |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3308$808: |
| Old ports: A=\ctrl._T_435, B=4'1111, Y=\ctrl._T_436 |
| New ports: A=\ctrl._T_435 [2:0], B=3'111, Y=\ctrl._T_436 [2:0] |
| New connections: \ctrl._T_436 [3] = 1'1 |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3524$1024: |
| Old ports: A=\ctrl._T_764, B=3'011, Y=\ctrl._T_765 |
| New ports: A={ \ctrl._T_764 [2] 1'0 }, B=2'01, Y={ \ctrl._T_765 [2] \ctrl._T_765 [0] } |
| New connections: \ctrl._T_765 [1] = \ctrl._T_765 [0] |
| Consolidated identical input bits for $mux cell $flatten\dpath.\csr.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:527$97: |
| Old ports: A=\dpath.csr._T_415 [4:0], B=5'00000, Y=\dpath.csr.causeExpt [4:0] |
| New ports: A=\dpath.csr._T_415 [3:0], B=4'0000, Y=\dpath.csr.causeExpt [3:0] |
| New connections: \dpath.csr.causeExpt [4] = 1'0 |
| Optimizing cells in module \Core. |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3142$642: |
| Old ports: A=\ctrl._T_237, B=2'00, Y=\ctrl._T_238 |
| New ports: A=\ctrl._T_237 [0], B=1'0, Y=\ctrl._T_238 [0] |
| New connections: \ctrl._T_238 [1] = \ctrl._T_238 [0] |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3264$764: |
| Old ports: A=\ctrl._T_384, B=3'000, Y=\ctrl._T_385 |
| New ports: A=\ctrl._T_384 [1], B=1'0, Y=\ctrl._T_385 [1] |
| New connections: { \ctrl._T_385 [2] \ctrl._T_385 [0] } = { \ctrl._T_385 [1] 1'0 } |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3308$808: |
| Old ports: A=\ctrl._T_435 [2:0], B=3'111, Y=\ctrl._T_436 [2:0] |
| New ports: A=\ctrl._T_435 [0], B=1'1, Y=\ctrl._T_436 [0] |
| New connections: \ctrl._T_436 [2:1] = { \ctrl._T_436 [0] 1'1 } |
| Optimizing cells in module \Core. |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3143$643: |
| Old ports: A=\ctrl._T_238, B=2'00, Y=\ctrl._T_239 |
| New ports: A=\ctrl._T_238 [0], B=1'0, Y=\ctrl._T_239 [0] |
| New connections: \ctrl._T_239 [1] = \ctrl._T_239 [0] |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3265$765: |
| Old ports: A=\ctrl._T_385, B=3'000, Y=\ctrl._T_386 |
| New ports: A=\ctrl._T_385 [1], B=1'0, Y=\ctrl._T_386 [1] |
| New connections: { \ctrl._T_386 [2] \ctrl._T_386 [0] } = { \ctrl._T_386 [1] 1'0 } |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3309$809: |
| Old ports: A=\ctrl._T_436, B=4'0010, Y=\ctrl._T_437 |
| New ports: A={ 1'1 \ctrl._T_436 [0] }, B=2'00, Y={ \ctrl._T_437 [3] \ctrl._T_437 [0] } |
| New connections: \ctrl._T_437 [2:1] = { \ctrl._T_437 [0] 1'1 } |
| Optimizing cells in module \Core. |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3144$644: |
| Old ports: A=\ctrl._T_239, B=2'00, Y=\ctrl._T_240 |
| New ports: A=\ctrl._T_239 [0], B=1'0, Y=\ctrl._T_240 [0] |
| New connections: \ctrl._T_240 [1] = \ctrl._T_240 [0] |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3266$766: |
| Old ports: A=\ctrl._T_386, B=3'000, Y=\ctrl._T_387 |
| New ports: A=\ctrl._T_386 [1], B=1'0, Y=\ctrl._T_387 [1] |
| New connections: { \ctrl._T_387 [2] \ctrl._T_387 [0] } = { \ctrl._T_387 [1] 1'0 } |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3310$810: |
| Old ports: A=\ctrl._T_437, B=4'0011, Y=\ctrl._T_438 |
| New ports: A={ \ctrl._T_437 [3] \ctrl._T_437 [0] \ctrl._T_437 [0] }, B=3'001, Y={ \ctrl._T_438 [3:2] \ctrl._T_438 [0] } |
| New connections: \ctrl._T_438 [1] = 1'1 |
| Optimizing cells in module \Core. |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3145$645: |
| Old ports: A=\ctrl._T_240, B=2'00, Y=\ctrl._T_241 |
| New ports: A=\ctrl._T_240 [0], B=1'0, Y=\ctrl._T_241 [0] |
| New connections: \ctrl._T_241 [1] = \ctrl._T_241 [0] |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3267$767: |
| Old ports: A=\ctrl._T_387, B=3'000, Y=\ctrl._T_388 |
| New ports: A=\ctrl._T_387 [1], B=1'0, Y=\ctrl._T_388 [1] |
| New connections: { \ctrl._T_388 [2] \ctrl._T_388 [0] } = { \ctrl._T_388 [1] 1'0 } |
| Optimizing cells in module \Core. |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3146$646: |
| Old ports: A=\ctrl._T_241, B=2'00, Y=\ctrl._T_242 |
| New ports: A=\ctrl._T_241 [0], B=1'0, Y=\ctrl._T_242 [0] |
| New connections: \ctrl._T_242 [1] = \ctrl._T_242 [0] |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3268$768: |
| Old ports: A=\ctrl._T_388, B=3'000, Y=\ctrl._T_389 |
| New ports: A=\ctrl._T_388 [1], B=1'0, Y=\ctrl._T_389 [1] |
| New connections: { \ctrl._T_389 [2] \ctrl._T_389 [0] } = { \ctrl._T_389 [1] 1'0 } |
| Optimizing cells in module \Core. |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3269$769: |
| Old ports: A=\ctrl._T_389, B=3'000, Y=\ctrl._T_390 |
| New ports: A=\ctrl._T_389 [1], B=1'0, Y=\ctrl._T_390 [1] |
| New connections: { \ctrl._T_390 [2] \ctrl._T_390 [0] } = { \ctrl._T_390 [1] 1'0 } |
| Optimizing cells in module \Core. |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3270$770: |
| Old ports: A=\ctrl._T_390, B=3'000, Y=\ctrl._T_391 |
| New ports: A=\ctrl._T_390 [1], B=1'0, Y=\ctrl._T_391 [1] |
| New connections: { \ctrl._T_391 [2] \ctrl._T_391 [0] } = { \ctrl._T_391 [1] 1'0 } |
| Optimizing cells in module \Core. |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3271$771: |
| Old ports: A=\ctrl._T_391, B=3'000, Y=\ctrl._T_392 |
| New ports: A=\ctrl._T_391 [1], B=1'0, Y=\ctrl._T_392 [1] |
| New connections: { \ctrl._T_392 [2] \ctrl._T_392 [0] } = { \ctrl._T_392 [1] 1'0 } |
| Optimizing cells in module \Core. |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3272$772: |
| Old ports: A=\ctrl._T_392, B=3'000, Y=\ctrl._T_393 |
| New ports: A=\ctrl._T_392 [1], B=1'0, Y=\ctrl._T_393 [1] |
| New connections: { \ctrl._T_393 [2] \ctrl._T_393 [0] } = { \ctrl._T_393 [1] 1'0 } |
| Optimizing cells in module \Core. |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3273$773: |
| Old ports: A=\ctrl._T_393, B=3'000, Y=\ctrl._T_394 |
| New ports: A=\ctrl._T_393 [1], B=1'0, Y=\ctrl._T_394 [1] |
| New connections: { \ctrl._T_394 [2] \ctrl._T_394 [0] } = { \ctrl._T_394 [1] 1'0 } |
| Optimizing cells in module \Core. |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3274$774: |
| Old ports: A=\ctrl._T_394, B=3'000, Y=\ctrl._T_395 |
| New ports: A=\ctrl._T_394 [1], B=1'0, Y=\ctrl._T_395 [1] |
| New connections: { \ctrl._T_395 [2] \ctrl._T_395 [0] } = { \ctrl._T_395 [1] 1'0 } |
| Optimizing cells in module \Core. |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3275$775: |
| Old ports: A=\ctrl._T_395, B=3'000, Y=\ctrl._T_396 |
| New ports: A=\ctrl._T_395 [1], B=1'0, Y=\ctrl._T_396 [1] |
| New connections: { \ctrl._T_396 [2] \ctrl._T_396 [0] } = { \ctrl._T_396 [1] 1'0 } |
| Optimizing cells in module \Core. |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3276$776: |
| Old ports: A=\ctrl._T_396, B=3'000, Y=\ctrl._T_397 |
| New ports: A=\ctrl._T_396 [1], B=1'0, Y=\ctrl._T_397 [1] |
| New connections: { \ctrl._T_397 [2] \ctrl._T_397 [0] } = { \ctrl._T_397 [1] 1'0 } |
| Optimizing cells in module \Core. |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3277$777: |
| Old ports: A=\ctrl._T_397, B=3'000, Y=\ctrl._T_398 |
| New ports: A=\ctrl._T_397 [1], B=1'0, Y=\ctrl._T_398 [1] |
| New connections: { \ctrl._T_398 [2] \ctrl._T_398 [0] } = { \ctrl._T_398 [1] 1'0 } |
| Optimizing cells in module \Core. |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3278$778: |
| Old ports: A=\ctrl._T_398, B=3'001, Y=\ctrl._T_399 |
| New ports: A={ \ctrl._T_398 [1] 1'0 }, B=2'01, Y=\ctrl._T_399 [1:0] |
| New connections: \ctrl._T_399 [2] = \ctrl._T_399 [1] |
| Optimizing cells in module \Core. |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3279$779: |
| Old ports: A=\ctrl._T_399, B=3'001, Y=\ctrl._T_400 |
| New ports: A=\ctrl._T_399 [1:0], B=2'01, Y=\ctrl._T_400 [1:0] |
| New connections: \ctrl._T_400 [2] = \ctrl._T_400 [1] |
| Optimizing cells in module \Core. |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3280$780: |
| Old ports: A=\ctrl._T_400, B=3'001, Y=\ctrl._T_401 |
| New ports: A=\ctrl._T_400 [1:0], B=2'01, Y=\ctrl._T_401 [1:0] |
| New connections: \ctrl._T_401 [2] = \ctrl._T_401 [1] |
| Optimizing cells in module \Core. |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3281$781: |
| Old ports: A=\ctrl._T_401, B=3'001, Y=\ctrl._T_402 |
| New ports: A=\ctrl._T_401 [1:0], B=2'01, Y=\ctrl._T_402 [1:0] |
| New connections: \ctrl._T_402 [2] = \ctrl._T_402 [1] |
| Optimizing cells in module \Core. |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3282$782: |
| Old ports: A=\ctrl._T_402, B=3'001, Y=\ctrl._T_403 |
| New ports: A=\ctrl._T_402 [1:0], B=2'01, Y=\ctrl._T_403 [1:0] |
| New connections: \ctrl._T_403 [2] = \ctrl._T_403 [1] |
| Optimizing cells in module \Core. |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3283$783: |
| Old ports: A=\ctrl._T_403, B=3'001, Y=\ctrl._T_404 |
| New ports: A=\ctrl._T_403 [1:0], B=2'01, Y=\ctrl._T_404 [1:0] |
| New connections: \ctrl._T_404 [2] = \ctrl._T_404 [1] |
| Optimizing cells in module \Core. |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3284$784: |
| Old ports: A=\ctrl._T_404, B=3'001, Y=\ctrl._T_405 |
| New ports: A=\ctrl._T_404 [1:0], B=2'01, Y=\ctrl._T_405 [1:0] |
| New connections: \ctrl._T_405 [2] = \ctrl._T_405 [1] |
| Optimizing cells in module \Core. |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3285$785: |
| Old ports: A=\ctrl._T_405, B=3'001, Y=\ctrl._T_406 |
| New ports: A=\ctrl._T_405 [1:0], B=2'01, Y=\ctrl._T_406 [1:0] |
| New connections: \ctrl._T_406 [2] = \ctrl._T_406 [1] |
| Optimizing cells in module \Core. |
| Consolidated identical input bits for $mux cell $flatten\ctrl.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/../../verilog/rtl/Core.v:3286$786: |
| Old ports: A=\ctrl._T_406, B=3'001, Y=\ctrl._T_407 |
| New ports: A=\ctrl._T_406 [1:0], B=2'01, Y=\ctrl._T_407 [1:0] |
| New connections: \ctrl._T_407 [2] = \ctrl._T_407 [1] |
| Optimizing cells in module \Core. |
| Performed a total of 71 changes. |
| |
| 6.20.5. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Core'. |
| <suppressed ~3 debug messages> |
| Removed a total of 1 cells. |
| |
| 6.20.6. Executing OPT_SHARE pass. |
| |
| 6.20.7. Executing OPT_DFF pass (perform DFF optimizations). |
| Adding SRST signal on $\dpath.reg_file.regs$rdreg[0] ($dff) from module Core (D = $auto$rtlil.cc:2443:Mux$2113, Q = $\dpath.reg_file.regs$rdreg[0]$q, rval = 5'00000). |
| Adding SRST signal on $\dpath.reg_file.regs$rdreg[1] ($dff) from module Core (D = $auto$rtlil.cc:2443:Mux$2118, Q = $\dpath.reg_file.regs$rdreg[1]$q, rval = 5'00000). |
| |
| 6.20.8. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Core.. |
| Removed 2 unused cells and 103 unused wires. |
| <suppressed ~3 debug messages> |
| |
| 6.20.9. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Core. |
| <suppressed ~12 debug messages> |
| |
| 6.20.10. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 6.20.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \Core.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~100 debug messages> |
| |
| 6.20.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \Core. |
| Performed a total of 0 changes. |
| |
| 6.20.13. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Core'. |
| <suppressed ~30 debug messages> |
| Removed a total of 10 cells. |
| |
| 6.20.14. Executing OPT_SHARE pass. |
| |
| 6.20.15. Executing OPT_DFF pass (perform DFF optimizations). |
| Adding EN signal on $memory\dpath.reg_file.regs[9]$2248 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[9]). |
| Adding EN signal on $memory\dpath.reg_file.regs[8]$2246 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[8]). |
| Adding EN signal on $memory\dpath.reg_file.regs[7]$2244 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[7]). |
| Adding EN signal on $memory\dpath.reg_file.regs[6]$2242 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[6]). |
| Adding EN signal on $memory\dpath.reg_file.regs[5]$2240 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[5]). |
| Adding EN signal on $memory\dpath.reg_file.regs[4]$2238 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[4]). |
| Adding EN signal on $memory\dpath.reg_file.regs[3]$2236 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[3]). |
| Adding EN signal on $memory\dpath.reg_file.regs[31]$2292 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[31]). |
| Adding EN signal on $memory\dpath.reg_file.regs[30]$2290 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[30]). |
| Adding EN signal on $memory\dpath.reg_file.regs[2]$2234 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[2]). |
| Adding EN signal on $memory\dpath.reg_file.regs[29]$2288 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[29]). |
| Adding EN signal on $memory\dpath.reg_file.regs[28]$2286 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[28]). |
| Adding EN signal on $memory\dpath.reg_file.regs[27]$2284 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[27]). |
| Adding EN signal on $memory\dpath.reg_file.regs[26]$2282 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[26]). |
| Adding EN signal on $memory\dpath.reg_file.regs[25]$2280 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[25]). |
| Adding EN signal on $memory\dpath.reg_file.regs[24]$2278 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[24]). |
| Adding EN signal on $memory\dpath.reg_file.regs[23]$2276 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[23]). |
| Adding EN signal on $memory\dpath.reg_file.regs[22]$2274 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[22]). |
| Adding EN signal on $memory\dpath.reg_file.regs[21]$2272 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[21]). |
| Adding EN signal on $memory\dpath.reg_file.regs[20]$2270 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[20]). |
| Adding EN signal on $memory\dpath.reg_file.regs[1]$2232 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[1]). |
| Adding EN signal on $memory\dpath.reg_file.regs[19]$2268 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[19]). |
| Adding EN signal on $memory\dpath.reg_file.regs[18]$2266 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[18]). |
| Adding EN signal on $memory\dpath.reg_file.regs[17]$2264 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[17]). |
| Adding EN signal on $memory\dpath.reg_file.regs[16]$2262 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[16]). |
| Adding EN signal on $memory\dpath.reg_file.regs[15]$2260 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[15]). |
| Adding EN signal on $memory\dpath.reg_file.regs[14]$2258 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[14]). |
| Adding EN signal on $memory\dpath.reg_file.regs[13]$2256 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[13]). |
| Adding EN signal on $memory\dpath.reg_file.regs[12]$2254 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[12]). |
| Adding EN signal on $memory\dpath.reg_file.regs[11]$2252 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[11]). |
| Adding EN signal on $memory\dpath.reg_file.regs[10]$2250 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[10]). |
| Adding EN signal on $memory\dpath.reg_file.regs[0]$2230 ($dff) from module Core (D = \dpath.reg_file.io_wdata, Q = \dpath.reg_file.regs[0]). |
| Setting constant 0-bit at position 0 on $auto$ff.cc:262:slice$1873 ($dffe) from module Core. |
| Setting constant 0-bit at position 1 on $auto$ff.cc:262:slice$1873 ($dffe) from module Core. |
| |
| 6.20.16. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Core.. |
| Removed 32 unused cells and 32 unused wires. |
| <suppressed ~33 debug messages> |
| |
| 6.20.17. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Core. |
| |
| 6.20.18. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 6.20.19. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \Core.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~68 debug messages> |
| |
| 6.20.20. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \Core. |
| Performed a total of 0 changes. |
| |
| 6.20.21. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Core'. |
| Removed a total of 0 cells. |
| |
| 6.20.22. Executing OPT_SHARE pass. |
| |
| 6.20.23. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 6.20.24. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Core.. |
| |
| 6.20.25. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Core. |
| |
| 6.20.26. Finished OPT passes. (There is nothing left to do.) |
| |
| 6.21. Executing TECHMAP pass (map to technology primitives). |
| |
| 6.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v |
| Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation. |
| Generating RTLIL representation for module `\_90_simplemap_bool_ops'. |
| Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. |
| Generating RTLIL representation for module `\_90_simplemap_logic_ops'. |
| Generating RTLIL representation for module `\_90_simplemap_compare_ops'. |
| Generating RTLIL representation for module `\_90_simplemap_various'. |
| Generating RTLIL representation for module `\_90_simplemap_registers'. |
| Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. |
| Generating RTLIL representation for module `\_90_shift_shiftx'. |
| Generating RTLIL representation for module `\_90_fa'. |
| Generating RTLIL representation for module `\_90_lcu'. |
| Generating RTLIL representation for module `\_90_alu'. |
| Generating RTLIL representation for module `\_90_macc'. |
| Generating RTLIL representation for module `\_90_alumacc'. |
| Generating RTLIL representation for module `\$__div_mod_u'. |
| Generating RTLIL representation for module `\$__div_mod_trunc'. |
| Generating RTLIL representation for module `\_90_div'. |
| Generating RTLIL representation for module `\_90_mod'. |
| Generating RTLIL representation for module `\$__div_mod_floor'. |
| Generating RTLIL representation for module `\_90_divfloor'. |
| Generating RTLIL representation for module `\_90_modfloor'. |
| Generating RTLIL representation for module `\_90_pow'. |
| Generating RTLIL representation for module `\_90_pmux'. |
| Generating RTLIL representation for module `\_90_lut'. |
| Successfully finished Verilog frontend. |
| |
| 6.21.2. Continuing TECHMAP pass. |
| Using extmapper simplemap for cells of type $dff. |
| Using extmapper simplemap for cells of type $mux. |
| Using extmapper simplemap for cells of type $and. |
| Using extmapper simplemap for cells of type $sdff. |
| Using extmapper simplemap for cells of type $not. |
| Using extmapper simplemap for cells of type $reduce_and. |
| Using extmapper simplemap for cells of type $reduce_or. |
| Using extmapper simplemap for cells of type $dffe. |
| Using extmapper simplemap for cells of type $logic_not. |
| Using extmapper simplemap for cells of type $eq. |
| Using template $paramod$7e708ae28ab761f11d0fb59d3ffc72f6a4baf5d9\_90_alu for cells of type $alu. |
| Using extmapper simplemap for cells of type $reduce_bool. |
| Using extmapper simplemap for cells of type $or. |
| Using extmapper simplemap for cells of type $ne. |
| Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_90_alu for cells of type $alu. |
| Using template $paramod$constmap:87f69c0bea22f84de4bcd0314b57cb19e61b5eb7$paramod$455891ae50d34e43581a517459d55825f76fa58e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr. |
| Using extmapper simplemap for cells of type $xor. |
| Using template $paramod$44a13d10af618e7fbe7b9aad2f6151ffcee1e2fa\_90_alu for cells of type $alu. |
| Using template $paramod$3636e5d13d08d3cf711b7983cc61849c8abc3f53\_90_alu for cells of type $alu. |
| Using template $paramod$861f5302217787cd55fd1a501bc728125f176580\_90_alu for cells of type $alu. |
| Using extmapper simplemap for cells of type $sdffe. |
| Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_90_alu for cells of type $alu. |
| Using extmapper simplemap for cells of type $sdffce. |
| Using extmapper simplemap for cells of type $pos. |
| Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000100000 for cells of type $lcu. |
| Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000011110 for cells of type $lcu. |
| Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. |
| No more expansions possible. |
| <suppressed ~4106 debug messages> |
| |
| 6.22. Executing OPT pass (performing simple optimizations). |
| |
| 6.22.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Core. |
| <suppressed ~6503 debug messages> |
| |
| 6.22.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Core'. |
| <suppressed ~6645 debug messages> |
| Removed a total of 2215 cells. |
| |
| 6.22.3. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 6.22.4. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Core.. |
| Removed 286 unused cells and 2326 unused wires. |
| <suppressed ~313 debug messages> |
| |
| 6.22.5. Finished fast OPT passes. |
| |
| 6.23. Executing ABC pass (technology mapping using ABC). |
| |
| 6.23.1. Extracting gate netlist of module `\Core' to `<abc-temp-dir>/input.blif'.. |
| Extracted 7907 gates and 9592 wires to a netlist network with 1683 inputs and 610 outputs. |
| |
| 6.23.1.1. Executing ABC. |
| Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1 |
| ABC: ABC command line: "source <abc-temp-dir>/abc.script". |
| ABC: |
| ABC: + read_blif <abc-temp-dir>/input.blif |
| ABC: + read_library <abc-temp-dir>/stdcells.genlib |
| ABC: Entered genlib library with 13 gates from file "<abc-temp-dir>/stdcells.genlib". |
| ABC: + strash |
| ABC: + dretime |
| ABC: + map |
| ABC: + write_blif <abc-temp-dir>/output.blif |
| |
| 6.23.1.2. Re-integrating ABC results. |
| ABC RESULTS: AND cells: 207 |
| ABC RESULTS: ANDNOT cells: 848 |
| ABC RESULTS: MUX cells: 3528 |
| ABC RESULTS: NAND cells: 204 |
| ABC RESULTS: NOR cells: 352 |
| ABC RESULTS: NOT cells: 173 |
| ABC RESULTS: OR cells: 1509 |
| ABC RESULTS: ORNOT cells: 185 |
| ABC RESULTS: XNOR cells: 66 |
| ABC RESULTS: XOR cells: 443 |
| ABC RESULTS: internal signals: 7299 |
| ABC RESULTS: input signals: 1683 |
| ABC RESULTS: output signals: 610 |
| Removing temp directory. |
| |
| 6.24. Executing OPT pass (performing simple optimizations). |
| |
| 6.24.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Core. |
| <suppressed ~1129 debug messages> |
| |
| 6.24.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Core'. |
| <suppressed ~141 debug messages> |
| Removed a total of 47 cells. |
| |
| 6.24.3. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 6.24.4. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Core.. |
| Removed 15 unused cells and 4350 unused wires. |
| <suppressed ~764 debug messages> |
| |
| 6.24.5. Finished fast OPT passes. |
| |
| 6.25. Executing HIERARCHY pass (managing design hierarchy). |
| |
| 6.25.1. Analyzing design hierarchy.. |
| Top module: \Core |
| |
| 6.25.2. Analyzing design hierarchy.. |
| Top module: \Core |
| Removed 0 unused modules. |
| |
| 6.26. Printing statistics. |
| |
| === Core === |
| |
| Number of wires: 7548 |
| Number of wire bits: 16298 |
| Number of public wires: 523 |
| Number of public wire bits: 9265 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 9070 |
| $_ANDNOT_ 848 |
| $_AND_ 207 |
| $_DFFE_PP_ 1254 |
| $_DFF_P_ 15 |
| $_MUX_ 3528 |
| $_NAND_ 204 |
| $_NOR_ 351 |
| $_NOT_ 158 |
| $_ORNOT_ 185 |
| $_OR_ 1463 |
| $_SDFFCE_PP0P_ 1 |
| $_SDFFE_PN0P_ 11 |
| $_SDFFE_PP0N_ 96 |
| $_SDFFE_PP0P_ 125 |
| $_SDFFE_PP1N_ 3 |
| $_SDFFE_PP1P_ 5 |
| $_SDFF_PP0_ 95 |
| $_SDFF_PP1_ 12 |
| $_XNOR_ 66 |
| $_XOR_ 443 |
| |
| 6.27. Executing CHECK pass (checking for obvious problems). |
| Checking module Core... |
| Found and reported 0 problems. |
| |
| 7. Generating Graphviz representation of design. |
| Writing dot description to `/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/runs/Core/tmp/synthesis/post_techmap.dot'. |
| Dumping module Core to page 1. |
| |
| 8. Executing SHARE pass (SAT-based resource sharing). |
| |
| 9. Executing OPT pass (performing simple optimizations). |
| |
| 9.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Core. |
| |
| 9.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Core'. |
| Removed a total of 0 cells. |
| |
| 9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \Core.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Removed 0 multiplexer ports. |
| |
| 9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \Core. |
| Performed a total of 0 changes. |
| |
| 9.5. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Core'. |
| Removed a total of 0 cells. |
| |
| 9.6. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 9.7. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Core.. |
| |
| 9.8. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Core. |
| |
| 9.9. Finished OPT passes. (There is nothing left to do.) |
| |
| 10. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Core.. |
| Removed 0 unused cells and 384 unused wires. |
| <suppressed ~384 debug messages> |
| |
| 11. Printing statistics. |
| |
| === Core === |
| |
| Number of wires: 7164 |
| Number of wire bits: 9445 |
| Number of public wires: 139 |
| Number of public wire bits: 2412 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 9070 |
| $_ANDNOT_ 848 |
| $_AND_ 207 |
| $_DFFE_PP_ 1254 |
| $_DFF_P_ 15 |
| $_MUX_ 3528 |
| $_NAND_ 204 |
| $_NOR_ 351 |
| $_NOT_ 158 |
| $_ORNOT_ 185 |
| $_OR_ 1463 |
| $_SDFFCE_PP0P_ 1 |
| $_SDFFE_PN0P_ 11 |
| $_SDFFE_PP0N_ 96 |
| $_SDFFE_PP0P_ 125 |
| $_SDFFE_PP1N_ 3 |
| $_SDFFE_PP1P_ 5 |
| $_SDFF_PP0_ 95 |
| $_SDFF_PP1_ 12 |
| $_XNOR_ 66 |
| $_XOR_ 443 |
| |
| mapping tbuf |
| |
| 12. Executing TECHMAP pass (map to technology primitives). |
| |
| 12.1. Executing Verilog-2005 frontend: /home/ali112000/Desktop/mpw/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v |
| Parsing Verilog input from `/home/ali112000/Desktop/mpw/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v' to AST representation. |
| Generating RTLIL representation for module `\$_TBUF_'. |
| Successfully finished Verilog frontend. |
| |
| 12.2. Continuing TECHMAP pass. |
| No more expansions possible. |
| <suppressed ~3 debug messages> |
| |
| 13. Executing SIMPLEMAP pass (map simple cells to gate primitives). |
| |
| 14. Executing TECHMAP pass (map to technology primitives). |
| |
| 14.1. Executing Verilog-2005 frontend: /home/ali112000/Desktop/mpw/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/latch_map.v |
| Parsing Verilog input from `/home/ali112000/Desktop/mpw/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/latch_map.v' to AST representation. |
| Generating RTLIL representation for module `\$_DLATCH_P_'. |
| Generating RTLIL representation for module `\$_DLATCH_N_'. |
| Successfully finished Verilog frontend. |
| |
| 14.2. Continuing TECHMAP pass. |
| No more expansions possible. |
| <suppressed ~4 debug messages> |
| |
| 15. Executing SIMPLEMAP pass (map simple cells to gate primitives). |
| |
| 16. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file). |
| cell sky130_fd_sc_hd__dfxtp_2 (noninv, pins=3, area=21.27) is a direct match for cell type $_DFF_P_. |
| cell sky130_fd_sc_hd__dfrtp_2 (noninv, pins=4, area=26.28) is a direct match for cell type $_DFF_PN0_. |
| cell sky130_fd_sc_hd__dfstp_2 (noninv, pins=4, area=26.28) is a direct match for cell type $_DFF_PN1_. |
| cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_. |
| final dff cell mappings: |
| unmapped dff cell: $_DFF_N_ |
| \sky130_fd_sc_hd__dfxtp_2 _DFF_P_ (.CLK( C), .D( D), .Q( Q)); |
| unmapped dff cell: $_DFF_NN0_ |
| unmapped dff cell: $_DFF_NN1_ |
| unmapped dff cell: $_DFF_NP0_ |
| unmapped dff cell: $_DFF_NP1_ |
| \sky130_fd_sc_hd__dfrtp_2 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R)); |
| \sky130_fd_sc_hd__dfstp_2 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R)); |
| unmapped dff cell: $_DFF_PP0_ |
| unmapped dff cell: $_DFF_PP1_ |
| \sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S)); |
| unmapped dff cell: $_DFFSR_NNP_ |
| unmapped dff cell: $_DFFSR_NPN_ |
| unmapped dff cell: $_DFFSR_NPP_ |
| unmapped dff cell: $_DFFSR_PNN_ |
| unmapped dff cell: $_DFFSR_PNP_ |
| unmapped dff cell: $_DFFSR_PPN_ |
| unmapped dff cell: $_DFFSR_PPP_ |
| |
| 16.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). |
| Mapping DFF cells in module `\Core': |
| mapped 1617 $_DFF_P_ cells to \sky130_fd_sc_hd__dfxtp_2 cells. |
| |
| 17. Printing statistics. |
| |
| === Core === |
| |
| Number of wires: 9007 |
| Number of wire bits: 11288 |
| Number of public wires: 139 |
| Number of public wire bits: 2412 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 10913 |
| $_ANDNOT_ 848 |
| $_AND_ 207 |
| $_MUX_ 5371 |
| $_NAND_ 204 |
| $_NOR_ 351 |
| $_NOT_ 158 |
| $_ORNOT_ 185 |
| $_OR_ 1463 |
| $_XNOR_ 66 |
| $_XOR_ 443 |
| sky130_fd_sc_hd__dfxtp_2 1617 |
| |
| [INFO]: ABC: WireLoad : S_4 |
| |
| 18. Executing ABC pass (technology mapping using ABC). |
| |
| 18.1. Extracting gate netlist of module `\Core' to `/tmp/yosys-abc-R8whJD/input.blif'.. |
| Extracted 9296 gates and 10984 wires to a netlist network with 1686 inputs and 1718 outputs. |
| |
| 18.1.1. Executing ABC. |
| Running ABC command: /build/bin/yosys-abc -s -f /tmp/yosys-abc-R8whJD/abc.script 2>&1 |
| ABC: ABC command line: "source /tmp/yosys-abc-R8whJD/abc.script". |
| ABC: |
| ABC: + read_blif /tmp/yosys-abc-R8whJD/input.blif |
| ABC: + read_lib -w /home/ali112000/mpw5/UETRV-ECORE/openlane/Core/runs/Core/tmp/synthesis/trimmed.lib |
| ABC: Parsing finished successfully. Parsing time = 0.07 sec |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_1". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtp_1". |
| ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_2". |
| ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_4". |
| ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_8". |
| ABC: Library "sky130A_merged" from "/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/runs/Core/tmp/synthesis/trimmed.lib" has 175 cells (17 skipped: 14 seq; 3 tri-state; 0 no func; 0 dont_use). Time = 0.10 sec |
| ABC: Memory = 7.77 MB. Time = 0.10 sec |
| ABC: Warning: Detected 2 multi-output gates (for example, "sky130_fd_sc_hd__fa_1"). |
| ABC: + read_constr -v /home/ali112000/mpw5/UETRV-ECORE/openlane/Core/runs/Core/tmp/synthesis/synthesis.sdc |
| ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_2". |
| ABC: Setting output load to be 33.442001. |
| ABC: + read_constr /home/ali112000/mpw5/UETRV-ECORE/openlane/Core/runs/Core/tmp/synthesis/synthesis.sdc |
| ABC: + fx |
| ABC: + mfs |
| ABC: + strash |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + retime -D -D 20000 -M 5 |
| ABC: + scleanup |
| ABC: Error: The network is combinational. |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + fraig_restore |
| ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000 |
| ABC: + retime -D -D 20000 |
| ABC: + &get -n |
| ABC: + &st |
| ABC: + &dch |
| ABC: + &nf |
| ABC: + &put |
| ABC: + buffer -N 5 -S 750.0 |
| ABC: + upsize -D 20000 |
| ABC: Current delay (9084.48 ps) does not exceed the target delay (20000.00 ps). Upsizing is not performed. |
| ABC: + dnsize -D 20000 |
| ABC: + stime -p |
| ABC: WireLoad = "none" Gates = 9172 ( 36.4 %) Cap = 10.7 ff ( 11.3 %) Area = 73917.14 ( 58.7 %) Delay = 9486.79 ps ( 4.7 %) |
| ABC: Path 0 -- 296 : 0 5 pi A = 0.00 Df = 40.8 -22.8 ps S = 62.1 ps Cin = 0.0 ff Cout = 12.1 ff Cmax = 0.0 ff G = 0 |
| ABC: Path 1 -- 3949 : 1 5 sky130_fd_sc_hd__buf_1 A = 3.75 Df = 277.1 -106.6 ps S = 262.0 ps Cin = 2.1 ff Cout = 21.7 ff Cmax = 130.0 ff G = 978 |
| ABC: Path 2 -- 3950 : 1 5 sky130_fd_sc_hd__buf_1 A = 3.75 Df = 577.5 -201.7 ps S = 302.1 ps Cin = 2.1 ff Cout = 25.3 ff Cmax = 130.0 ff G = 1137 |
| ABC: Path 3 -- 3951 : 1 5 sky130_fd_sc_hd__buf_1 A = 3.75 Df = 882.0 -294.7 ps S = 301.9 ps Cin = 2.1 ff Cout = 25.3 ff Cmax = 130.0 ff G = 1137 |
| ABC: Path 4 -- 3952 : 1 5 sky130_fd_sc_hd__buf_1 A = 3.75 Df =1186.6 -387.5 ps S = 301.9 ps Cin = 2.1 ff Cout = 25.3 ff Cmax = 130.0 ff G = 1137 |
| ABC: Path 5 -- 3953 : 1 5 sky130_fd_sc_hd__buf_1 A = 3.75 Df =1472.0 -469.9 ps S = 274.3 ps Cin = 2.1 ff Cout = 22.8 ff Cmax = 130.0 ff G = 1030 |
| ABC: Path 6 -- 3954 : 1 5 sky130_fd_sc_hd__buf_1 A = 3.75 Df =1783.3 -569.1 ps S = 315.2 ps Cin = 2.1 ff Cout = 26.4 ff Cmax = 130.0 ff G = 1190 |
| ABC: Path 7 -- 5117 : 6 1 sky130_fd_sc_hd__mux4_2 A = 22.52 Df =2228.2 -498.0 ps S = 86.7 ps Cin = 2.6 ff Cout = 4.7 ff Cmax = 301.2 ff G = 169 |
| ABC: Path 8 -- 5118 : 2 1 sky130_fd_sc_hd__nor2_2 A = 6.26 Df =2259.2 -446.4 ps S = 61.9 ps Cin = 4.4 ff Cout = 2.4 ff Cmax = 141.9 ff G = 52 |
| ABC: Path 9 -- 5121 : 5 1 sky130_fd_sc_hd__o221a_2 A = 11.26 Df =2495.2 -507.6 ps S = 41.2 ps Cin = 2.3 ff Cout = 2.5 ff Cmax = 281.1 ff G = 97 |
| ABC: Path 10 -- 5123 : 5 4 sky130_fd_sc_hd__o32a_2 A = 11.26 Df =2847.8 -696.7 ps S = 80.6 ps Cin = 2.3 ff Cout = 12.6 ff Cmax = 300.3 ff G = 518 |
| ABC: Path 11 -- 5124 : 2 4 sky130_fd_sc_hd__or2_2 A = 6.26 Df =3172.2 -346.8 ps S = 85.7 ps Cin = 1.5 ff Cout = 14.0 ff Cmax = 299.4 ff G = 931 |
| ABC: Path 12 -- 5623 : 5 3 sky130_fd_sc_hd__a311o_2 A = 11.26 Df =3568.4 -316.2 ps S = 72.4 ps Cin = 2.3 ff Cout = 9.6 ff Cmax = 298.5 ff G = 399 |
| ABC: Path 13 -- 5673 : 5 3 sky130_fd_sc_hd__a41o_2 A = 11.26 Df =3872.6 -293.7 ps S = 87.5 ps Cin = 2.3 ff Cout = 13.4 ff Cmax = 325.0 ff G = 556 |
| ABC: Path 14 -- 5675 : 4 4 sky130_fd_sc_hd__a211o_2 A = 10.01 Df =4236.7 -494.4 ps S = 71.4 ps Cin = 2.4 ff Cout = 12.1 ff Cmax = 325.0 ff G = 490 |
| ABC: Path 15 -- 5677 : 5 4 sky130_fd_sc_hd__a311o_2 A = 11.26 Df =4660.2 -488.0 ps S = 84.5 ps Cin = 2.3 ff Cout = 12.1 ff Cmax = 298.5 ff G = 504 |
| ABC: Path 16 -- 5680 : 5 4 sky130_fd_sc_hd__a311o_2 A = 11.26 Df =5086.6 -464.6 ps S = 84.5 ps Cin = 2.3 ff Cout = 12.1 ff Cmax = 298.5 ff G = 504 |
| ABC: Path 17 -- 5683 : 5 4 sky130_fd_sc_hd__a311o_2 A = 11.26 Df =5513.1 -678.9 ps S = 84.5 ps Cin = 2.3 ff Cout = 12.1 ff Cmax = 298.5 ff G = 504 |
| ABC: Path 18 -- 5686 : 5 5 sky130_fd_sc_hd__a311o_2 A = 11.26 Df =5945.5 -653.5 ps S = 90.7 ps Cin = 2.3 ff Cout = 13.5 ff Cmax = 298.5 ff G = 563 |
| ABC: Path 19 -- 5756 : 5 1 sky130_fd_sc_hd__a32o_2 A = 11.26 Df =6213.0 -755.2 ps S = 44.3 ps Cin = 2.3 ff Cout = 2.5 ff Cmax = 264.6 ff G = 100 |
| ABC: Path 20 -- 5805 : 5 1 sky130_fd_sc_hd__a221o_2 A = 11.26 Df =6579.8 -425.7 ps S = 50.8 ps Cin = 2.3 ff Cout = 2.6 ff Cmax = 299.4 ff G = 105 |
| ABC: Path 21 -- 5807 : 5 1 sky130_fd_sc_hd__a2111o_2 A = 12.51 Df =6965.4 -556.1 ps S = 57.9 ps Cin = 2.4 ff Cout = 2.4 ff Cmax = 324.1 ff G = 93 |
| ABC: Path 22 -- 5808 : 5 2 sky130_fd_sc_hd__a221o_2 A = 11.26 Df =7264.8 -653.6 ps S = 56.0 ps Cin = 2.3 ff Cout = 4.1 ff Cmax = 299.4 ff G = 164 |
| ABC: Path 23 -- 5809 : 3 1 sky130_fd_sc_hd__or3b_2 A = 8.76 Df =7444.8 -415.0 ps S = 69.2 ps Cin = 1.5 ff Cout = 1.4 ff Cmax = 269.2 ff G = 94 |
| ABC: Path 24 -- 5822 : 3 5 sky130_fd_sc_hd__and3_2 A = 7.51 Df =7727.8 -81.5 ps S = 97.6 ps Cin = 1.5 ff Cout = 14.7 ff Cmax = 309.5 ff G = 958 |
| ABC: Path 25 -- 5875 : 2 3 sky130_fd_sc_hd__nand2_2 A = 6.26 Df =7797.1 -90.6 ps S = 55.5 ps Cin = 4.4 ff Cout = 6.6 ff Cmax = 295.7 ff G = 142 |
| ABC: Path 26 -- 5968 : 1 5 sky130_fd_sc_hd__buf_1 A = 3.75 Df =7964.8 -128.7 ps S = 165.4 ps Cin = 2.1 ff Cout = 13.3 ff Cmax = 130.0 ff G = 605 |
| ABC: Path 27 -- 5969 : 1 5 sky130_fd_sc_hd__buf_1 A = 3.75 Df =8178.6 -188.1 ps S = 197.5 ps Cin = 2.1 ff Cout = 16.1 ff Cmax = 130.0 ff G = 730 |
| ABC: Path 28 -- 5970 : 1 5 sky130_fd_sc_hd__buf_1 A = 3.75 Df =8417.8 -255.2 ps S = 227.3 ps Cin = 2.1 ff Cout = 18.7 ff Cmax = 130.0 ff G = 858 |
| ABC: Path 29 -- 6556 : 3 1 sky130_fd_sc_hd__or3_2 A = 7.51 Df =8641.2 -64.4 ps S = 73.5 ps Cin = 1.5 ff Cout = 2.5 ff Cmax = 310.4 ff G = 156 |
| ABC: Path 30 -- 6559 : 4 2 sky130_fd_sc_hd__a31o_2 A = 8.76 Df =8901.0 -168.1 ps S = 57.3 ps Cin = 2.4 ff Cout = 6.3 ff Cmax = 271.9 ff G = 252 |
| ABC: Path 31 -- 10621 : 5 1 sky130_fd_sc_hd__a221oi_2 A = 15.01 Df =9486.8 -627.9 ps S = 680.0 ps Cin = 4.5 ff Cout = 33.4 ff Cmax = 96.1 ff G = 746 |
| ABC: Start-point = pi295 ($\dpath.reg_file.regs$rdreg[0]$q [0]). End-point = po1273 ($auto$rtlil.cc:2515:MuxGate$32441). |
| ABC: + print_stats -m |
| ABC: netlist : i/o = 1686/ 1718 lat = 0 nd = 9172 edge = 22439 area =73910.09 delay =38.00 lev = 38 |
| ABC: + write_blif /tmp/yosys-abc-R8whJD/output.blif |
| |
| 18.1.2. Re-integrating ABC results. |
| ABC RESULTS: sky130_fd_sc_hd__a2111o_2 cells: 9 |
| ABC RESULTS: sky130_fd_sc_hd__a211o_2 cells: 93 |
| ABC RESULTS: sky130_fd_sc_hd__a211oi_2 cells: 5 |
| ABC RESULTS: sky130_fd_sc_hd__a21bo_2 cells: 13 |
| ABC RESULTS: sky130_fd_sc_hd__a21boi_2 cells: 8 |
| ABC RESULTS: sky130_fd_sc_hd__a21o_2 cells: 132 |
| ABC RESULTS: sky130_fd_sc_hd__a21oi_2 cells: 275 |
| ABC RESULTS: sky130_fd_sc_hd__a221o_2 cells: 123 |
| ABC RESULTS: sky130_fd_sc_hd__a221oi_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__a22o_2 cells: 90 |
| ABC RESULTS: sky130_fd_sc_hd__a22oi_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__a2bb2o_2 cells: 13 |
| ABC RESULTS: sky130_fd_sc_hd__a311o_2 cells: 54 |
| ABC RESULTS: sky130_fd_sc_hd__a31o_2 cells: 58 |
| ABC RESULTS: sky130_fd_sc_hd__a31oi_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__a32o_2 cells: 100 |
| ABC RESULTS: sky130_fd_sc_hd__a32oi_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__a41o_2 cells: 7 |
| ABC RESULTS: sky130_fd_sc_hd__and2_2 cells: 191 |
| ABC RESULTS: sky130_fd_sc_hd__and2b_2 cells: 27 |
| ABC RESULTS: sky130_fd_sc_hd__and3_2 cells: 114 |
| ABC RESULTS: sky130_fd_sc_hd__and3b_2 cells: 6 |
| ABC RESULTS: sky130_fd_sc_hd__and4_2 cells: 75 |
| ABC RESULTS: sky130_fd_sc_hd__and4b_2 cells: 5 |
| ABC RESULTS: sky130_fd_sc_hd__and4bb_2 cells: 5 |
| ABC RESULTS: sky130_fd_sc_hd__buf_1 cells: 3160 |
| ABC RESULTS: sky130_fd_sc_hd__inv_2 cells: 180 |
| ABC RESULTS: sky130_fd_sc_hd__mux2_2 cells: 1646 |
| ABC RESULTS: sky130_fd_sc_hd__mux4_2 cells: 448 |
| ABC RESULTS: sky130_fd_sc_hd__nand2_2 cells: 275 |
| ABC RESULTS: sky130_fd_sc_hd__nand2b_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__nand3_2 cells: 11 |
| ABC RESULTS: sky130_fd_sc_hd__nand3b_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__nand4_2 cells: 6 |
| ABC RESULTS: sky130_fd_sc_hd__nand4b_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__nor2_2 cells: 387 |
| ABC RESULTS: sky130_fd_sc_hd__nor3_2 cells: 71 |
| ABC RESULTS: sky130_fd_sc_hd__nor3b_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__nor4_2 cells: 4 |
| ABC RESULTS: sky130_fd_sc_hd__nor4b_2 cells: 3 |
| ABC RESULTS: sky130_fd_sc_hd__o2111a_2 cells: 6 |
| ABC RESULTS: sky130_fd_sc_hd__o211a_2 cells: 220 |
| ABC RESULTS: sky130_fd_sc_hd__o211ai_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__o21a_2 cells: 253 |
| ABC RESULTS: sky130_fd_sc_hd__o21ai_2 cells: 215 |
| ABC RESULTS: sky130_fd_sc_hd__o21ba_2 cells: 5 |
| ABC RESULTS: sky130_fd_sc_hd__o21bai_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__o221a_2 cells: 76 |
| ABC RESULTS: sky130_fd_sc_hd__o221ai_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__o22a_2 cells: 43 |
| ABC RESULTS: sky130_fd_sc_hd__o22ai_2 cells: 4 |
| ABC RESULTS: sky130_fd_sc_hd__o2bb2a_2 cells: 7 |
| ABC RESULTS: sky130_fd_sc_hd__o311a_2 cells: 25 |
| ABC RESULTS: sky130_fd_sc_hd__o31a_2 cells: 21 |
| ABC RESULTS: sky130_fd_sc_hd__o31ai_2 cells: 12 |
| ABC RESULTS: sky130_fd_sc_hd__o32a_2 cells: 35 |
| ABC RESULTS: sky130_fd_sc_hd__o32ai_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__or2_2 cells: 357 |
| ABC RESULTS: sky130_fd_sc_hd__or2b_2 cells: 20 |
| ABC RESULTS: sky130_fd_sc_hd__or3_2 cells: 66 |
| ABC RESULTS: sky130_fd_sc_hd__or3b_2 cells: 28 |
| ABC RESULTS: sky130_fd_sc_hd__or4_2 cells: 44 |
| ABC RESULTS: sky130_fd_sc_hd__or4b_2 cells: 18 |
| ABC RESULTS: sky130_fd_sc_hd__or4bb_2 cells: 6 |
| ABC RESULTS: sky130_fd_sc_hd__xnor2_2 cells: 73 |
| ABC RESULTS: sky130_fd_sc_hd__xor2_2 cells: 28 |
| ABC RESULTS: internal signals: 7580 |
| ABC RESULTS: input signals: 1686 |
| ABC RESULTS: output signals: 1718 |
| Removing temp directory. |
| |
| 19. Executing SETUNDEF pass (replace undef values with defined constants). |
| |
| 20. Executing HILOMAP pass (mapping to constant drivers). |
| |
| 21. Executing SPLITNETS pass (splitting up multi-bit signals). |
| |
| 22. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Core.. |
| Removed 156 unused cells and 11442 unused wires. |
| <suppressed ~787 debug messages> |
| |
| 23. Executing INSBUF pass (insert buffer cells for connected wires). |
| ERROR: Can't create file /home/ali112000/mpw5/UETRV-ECORE/openlane/Core/runs/Core/reports/synthesis/1-synthesis.chk.rpt.strategy4. |