Licence added
diff --git a/Makefile b/Makefile index eca8f7c..1f36a8e 100644 --- a/Makefile +++ b/Makefile
@@ -198,5 +198,8 @@ help: cd $(CARAVEL_ROOT) && $(MAKE) help @$(MAKE) -pRrq -f $(lastword $(MAKEFILE_LIST)) : 2>/dev/null | awk -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$@$$' +<<<<<<< HEAD +======= +>>>>>>> c8bbbebb7f2e4756c91a6f5fbcd8071567f8f62b
diff --git a/verilog/rtl/Core.v b/verilog/rtl/Core.v index e099d1a..81d18fb 100644 --- a/verilog/rtl/Core.v +++ b/verilog/rtl/Core.v
@@ -1,19 +1,3 @@ -// SPDX-FileCopyrightText: 2022 EE, UET Lahore -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Created by Muhammad Tahir <mtahir@uet.edu.pk> - module CSR( // @[:@3.2] input clock, // @[:@4.4] input reset, // @[:@5.4]
diff --git a/verilog/rtl/DMem.v b/verilog/rtl/DMem.v index 9a9e480..7108a81 100644 --- a/verilog/rtl/DMem.v +++ b/verilog/rtl/DMem.v
@@ -1,19 +1,3 @@ -// SPDX-FileCopyrightText: 2022 EE, UET Lahore -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Created by Muhammad Tahir <mtahir@uet.edu.pk> - module DMem( // @[:@12681.2] input clock, // @[:@12682.4] input [7:0] io_addr, // @[:@12684.4]
diff --git a/verilog/rtl/IMem.v b/verilog/rtl/IMem.v index d4c42ae..daf98dd 100644 --- a/verilog/rtl/IMem.v +++ b/verilog/rtl/IMem.v
@@ -1,19 +1,3 @@ -// SPDX-FileCopyrightText: 2022 EE, UET Lahore -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Created by Muhammad Tahir <mtahir@uet.edu.pk> - module IMem( // @[:@12666.2] input clock, // @[:@12667.4] input [8:0] io_addr, // @[:@12669.4] @@ -86,4 +70,4 @@ imem__T_37_addr_pipe_0 <= _GEN_6; end end -endmodule \ No newline at end of file +endmodule
diff --git a/verilog/rtl/Motor_Top.v b/verilog/rtl/Motor_Top.v index ddae26d..af06661 100644 --- a/verilog/rtl/Motor_Top.v +++ b/verilog/rtl/Motor_Top.v
@@ -1,19 +1,3 @@ -// SPDX-FileCopyrightText: 2022 EE, UET Lahore -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Created by Muhammad Tahir <mtahir@uet.edu.pk> - module Interlink_Module( // @[:@4032.2] input clock, // @[:@4033.4] input reset, // @[:@4034.4]
diff --git a/verilog/rtl/Processor_Tile.v b/verilog/rtl/Processor_Tile.v index 65c667d..6bc19e4 100644 --- a/verilog/rtl/Processor_Tile.v +++ b/verilog/rtl/Processor_Tile.v
@@ -1,19 +1,3 @@ -// SPDX-FileCopyrightText: 2022 EE, UET Lahore -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Created by Muhammad Tahir <mtahir@uet.edu.pk> - module Processor_Tile( // @[:@12742.2] input clock, // @[:@12743.4] input reset, // @[:@12744.4]
diff --git a/verilog/rtl/WB_InterConnect.v b/verilog/rtl/WB_InterConnect.v index f96a98e..aa4338a 100644 --- a/verilog/rtl/WB_InterConnect.v +++ b/verilog/rtl/WB_InterConnect.v
@@ -1,19 +1,3 @@ -// SPDX-FileCopyrightText: 2022 EE, UET Lahore -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Created by Muhammad Tahir <mtahir@uet.edu.pk> - module DMem_Interface( // @[:@1882.2] input clock, // @[:@1883.4] input reset, // @[:@1884.4]