commit: f60b9730c4242276bcd61cc1847a798dd0f971ad
[log] [tgz]
author: ALI11-2000 <ali1120001@outlook.com>
Tue Apr 05 16:48:28 2022 +0500
committer: ALI11-2000 <ali1120001@outlook.com>
Tue Apr 05 16:48:28 2022 +0500
tree: e2fe1bf7966dd009387c9f8d7a254af6d6b1a712
parent: 080ca5b2a2738ab0133cfd7f750928c7ac93fa53 [diff]

SOC Hardened with three motor modules

def/Core.def[diff]
def/Motor_Top.def[diff]
def/WB_InterConnect.def[diff]
def/user_project_wrapper.def[diff]
gds/Core.gds[Added - diff]
gds/Motor_Top.gds[Added - diff]
gds/WB_InterConnect.gds[Added - diff]
gds/user_project_wrapper.gds[diff]
lef/Core.lef[Added - diff]
lef/Motor_Top.lef[Added - diff]
lef/WB_InterConnect.lef[Added - diff]
lef/user_project_wrapper.lef[diff]
lvs/Core.spice[Deleted - diff]
lvs/Motor_Top.spice[Deleted - diff]
lvs/WB_InterConnect.spice[Deleted - diff]
lvs/user_project_wrapper.spice[Deleted - diff]
mag/Core.mag[Added - diff]
mag/Motor_Top.mag[Added - diff]
mag/WB_InterConnect.mag[Added - diff]
mag/user_project_wrapper.mag[diff]
maglef/Core.mag[diff]
maglef/Motor_Top.mag[diff]
maglef/WB_InterConnect.mag[diff]
maglef/user_project_wrapper.mag[diff]
openlane/Motor_Top/config.tcl[diff]
openlane/Motor_Top/pin_order.cfg[diff]
openlane/Wishbone_InterConnect/config.tcl[diff]
openlane/user_project_wrapper/config.tcl[diff]
openlane/user_project_wrapper/macro.cfg[diff]
sdc/Core.sdc[Added - diff]
sdc/Motor_Top.sdc[Added - diff]
sdc/WB_InterConnect.sdc[Added - diff]
sdc/user_project_wrapper.sdc[diff]
sdf/Core.sdf[Added - diff]
sdf/Motor_Top.sdf[Added - diff]
sdf/WB_InterConnect.sdf[Added - diff]
sdf/user_project_wrapper.sdf[diff]
signoff/Core/final_summary_report.csv[diff]
signoff/Motor_Top/final_summary_report.csv[diff]
signoff/Wishbone_InterConnect/final_summary_report.csv[diff]
signoff/user_project_wrapper/final_summary_report.csv[diff]
spef/Core.spef[Added - diff]
spef/Motor_Top.spef[Added - diff]
spef/WB_InterConnect.spef[Added - diff]
spef/user_project_wrapper.spef[diff]
spi/lvs/Core.spice[diff]
spi/lvs/Motor_Top.spice[diff]
spi/lvs/WB_InterConnect.spice[diff]
spi/lvs/user_project_wrapper.spice[diff]
verilog/gl/Core.v[diff]
verilog/gl/Motor_Top.v[diff]
verilog/gl/WB_InterConnect.v[diff]
verilog/gl/user_project_wrapper.v[diff]
verilog/rtl/Core.v[diff]
verilog/rtl/Motor_Top.v[diff]
verilog/rtl/WB_InterConnect.v[diff]
verilog/rtl/user_project_wrapper.v[diff]

57 files changed

tree: e2fe1bf7966dd009387c9f8d7a254af6d6b1a712

README.md

UETRV-ecore

Here is the toplevel block diagram of ECORE.

alt text