- minimize dv makefiles by exporting variables when running docker
- add dv_all target to run all simulation targets
- gitignore simulation artificats
- increase la_test1 test duration
diff --git a/.gitignore b/.gitignore
index f4e486c..9ccca4b 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1 +1,5 @@
-precheck_results
\ No newline at end of file
+precheck_results
+*.hex*
+*.lst
+*.vcd
+*.gtkw
diff --git a/Makefile b/Makefile
index fa42afe..9e50d32 100644
--- a/Makefile
+++ b/Makefile
@@ -54,14 +54,20 @@
DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
TARGET_PATH=$(shell pwd)
VERIFY_COMMAND="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} && make"
-$(DV_PATTERNS): verify-% : ./verilog/dv/%
+
+.PHONY: dv_all
+dv_all:$(DV_PATTERNS)
+
+$(DV_PATTERNS): verify-% : ./verilog/dv/% check-env
docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \
- -v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
- -e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \
- -e CARAVEL_ROOT=${CARAVEL_ROOT} \
- -e MCW_ROOT=$(MCW_ROOT) \
- -u $(id -u $$USER):$(id -g $$USER) efabless/dv_setup:latest \
- sh -c $(VERIFY_COMMAND)
+ -v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
+ -e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \
+ -e CARAVEL_ROOT=${CARAVEL_ROOT} \
+ -e TOOLS=/opt/riscv32i \
+ -e DESIGNS=$(TARGET_PATH) \
+ -e MCW_ROOT=$(MCW_ROOT) \
+ -u $$(id -u $$USER):$$(id -g $$USER) efabless/dv_setup:latest \
+ sh -c $(VERIFY_COMMAND)
# Openlane Makefile Targets
BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
diff --git a/caravel b/caravel
deleted file mode 160000
index e7ade82..0000000
--- a/caravel
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit e7ade8203d82c5604c7542d161765090838e5e7f
diff --git a/verilog/dv/io_ports/Makefile b/verilog/dv/io_ports/Makefile
index ea1b0e0..3fd0b56 100644
--- a/verilog/dv/io_ports/Makefile
+++ b/verilog/dv/io_ports/Makefile
@@ -21,11 +21,6 @@
# ---- Include Partitioned Makefiles ----
-$(info $(TARGET_PATH))
-
-export DESIGNS = $(TARGET_PATH)
-export TOOLS = /opt/riscv32i/
-
CONFIG = caravel_user_project
diff --git a/verilog/dv/la_test1/Makefile b/verilog/dv/la_test1/Makefile
index ea1b0e0..3fd0b56 100644
--- a/verilog/dv/la_test1/Makefile
+++ b/verilog/dv/la_test1/Makefile
@@ -21,11 +21,6 @@
# ---- Include Partitioned Makefiles ----
-$(info $(TARGET_PATH))
-
-export DESIGNS = $(TARGET_PATH)
-export TOOLS = /opt/riscv32i/
-
CONFIG = caravel_user_project
diff --git a/verilog/dv/la_test1/la_test1_tb.v b/verilog/dv/la_test1/la_test1_tb.v
index 4f251fa..d7e4b52 100644
--- a/verilog/dv/la_test1/la_test1_tb.v
+++ b/verilog/dv/la_test1/la_test1_tb.v
@@ -50,7 +50,7 @@
$dumpvars(0, la_test1_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (200) begin
+ repeat (250) begin
repeat (1000) @(posedge clock);
// $display("+1000 cycles");
end
diff --git a/verilog/dv/la_test2/Makefile b/verilog/dv/la_test2/Makefile
index ea1b0e0..3fd0b56 100644
--- a/verilog/dv/la_test2/Makefile
+++ b/verilog/dv/la_test2/Makefile
@@ -21,11 +21,6 @@
# ---- Include Partitioned Makefiles ----
-$(info $(TARGET_PATH))
-
-export DESIGNS = $(TARGET_PATH)
-export TOOLS = /opt/riscv32i/
-
CONFIG = caravel_user_project
diff --git a/verilog/dv/mprj_stimulus/Makefile b/verilog/dv/mprj_stimulus/Makefile
index ea1b0e0..3fd0b56 100644
--- a/verilog/dv/mprj_stimulus/Makefile
+++ b/verilog/dv/mprj_stimulus/Makefile
@@ -21,11 +21,6 @@
# ---- Include Partitioned Makefiles ----
-$(info $(TARGET_PATH))
-
-export DESIGNS = $(TARGET_PATH)
-export TOOLS = /opt/riscv32i/
-
CONFIG = caravel_user_project
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile
index ea1b0e0..3fd0b56 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/wb_port/Makefile
@@ -21,11 +21,6 @@
# ---- Include Partitioned Makefiles ----
-$(info $(TARGET_PATH))
-
-export DESIGNS = $(TARGET_PATH)
-export TOOLS = /opt/riscv32i/
-
CONFIG = caravel_user_project
