commit: 658214eff988d90c560d03a8e05f71036ddb95a8
[log]
author: Ali Imran <ali112000@pop-os.localdomain>
Sun Apr 03 05:11:21 2022 +0500
committer: Ali Imran <ali112000@pop-os.localdomain>
Sun Apr 03 05:11:21 2022 +0500
tree: 04735113d55d5fa7d0dfa5e0d26490c288fb7d1a
parent: b2d138ef25724ddc600c4c9c5dc98707c7fe4bad [diff]

Verilog files Updated

gds/Core.gds[Deleted - diff]
gds/Motor_Top.gds[Deleted - diff]
gds/WB_InterConnect.gds[Deleted - diff]
gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds[Deleted - diff]
lef/Core.lef[Deleted - diff]
lef/Motor_Top.lef[Deleted - diff]
lef/WB_InterConnect.lef[Deleted - diff]
lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef[Deleted - diff]
mag/Core.mag[Deleted - diff]
mag/Motor_Top.mag[Deleted - diff]
mag/WB_InterConnect.mag[Deleted - diff]
mag/tmp/extract_BMem.log[Deleted - diff]
mag/tmp/extract_BMem.tcl[Deleted - diff]
sdc/Core.sdc[Deleted - diff]
sdc/Motor_Top.sdc[Deleted - diff]
sdc/WB_InterConnect.sdc[Deleted - diff]
sdf/Core.sdf[Deleted - diff]
sdf/Motor_Top.sdf[Deleted - diff]
sdf/WB_InterConnect.sdf[Deleted - diff]
spef/Core.spef[Deleted - diff]
spef/Motor_Top.spef[Deleted - diff]
spef/WB_InterConnect.spef[Deleted - diff]
verilog/rtl/Core.v[diff]
verilog/rtl/DMem.v[Deleted - diff]
verilog/rtl/IMem.v[Deleted - diff]
verilog/rtl/Motor_Top.v[diff]
verilog/rtl/Processor_Tile.v[Deleted - diff]
verilog/rtl/WB_InterConnect.v[diff]
verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v[Deleted - diff]
verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v[Deleted - diff]

30 files changed

tree: 04735113d55d5fa7d0dfa5e0d26490c288fb7d1a

README.md

UETRV-ecore

Here is the toplevel block diagram of ECORE.

alt text