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foss-eda-tools / third_party / shuttle / sky130 / mpw-005 / slot-036 / 63707093d5fc606e8151e288d32070134f043aa7
commit63707093d5fc606e8151e288d32070134f043aa7[log] [tgz]
authorAli Imran <59641896+ALI11-2000@users.noreply.github.com>Fri Apr 29 20:05:43 2022 +0500
committerGitHub <noreply@github.com>Fri Apr 29 20:05:43 2022 +0500
treead662dd31b5d1881f65a65c6f586361e88fb5352
parentd049e23c9aa344ab475324838c89607288af4317 [diff]
parentaec3a8a7718fef55e7a5a53bec2aeee10a45bde4 [diff]
Merge pull request #4 from ee-uet/development

Merging the updated version of SoC
tree: ad662dd31b5d1881f65a65c6f586361e88fb5352
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. sdc/
  10. sdf/
  11. signoff/
  12. spef/
  13. spi/
  14. verilog/
  15. caravel
  16. .gitignore
  17. LICENSE
  18. Makefile
  19. README.md
README.md

UETRV-ECORE

UETRV-ECORE is a RISC-V based SoC integrating 3-stage pipelined core with multiple peripherals for embedded applications. Currently, the core implements RV32I ISA based on User-level ISA Version 2.0 and Privileged Architecture Version 1.11 supporting machine mode only. The core does not have any structural hazards, while data hazards are resolved using forwarding and stalling. Following is the status of current implementation:

  • Machine level interrupts has been added, including the support for vectored interrupts.
  • External interrupts are supported using bits 16 and above of MIP & MIE CSRs as provisioned by Privileged Architecture Version 1.11.
  • Data hazards are resolved using forwarding, while Load-Use hazard leads to one cycle stall.
  • Memory and peripherals are integrated through Wishbone Interconnect.
  • The SoC has on-chip pre-initialized boot memory with a simple boot loader.
  • The system boots from external flash using SPI interface.
  • A motor control module, capable of controlling dc-servo motor with encoder feedback.

Block Diagram

The verilog rtl used in this repo is generated from Scala source which is available in a separate repository here. Further details bout the peripheral memory map, bootloader, example programs, testbenches etc. are also provided in that repo.