Verilog files Updated
42 files changed
tree: 1f98fa546e9605aef8821c13428fa3dbcd2ee836
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. sdc/
  8. sdf/
  9. spef/
  10. verilog/
  11. .gitignore
  12. LICENSE
  13. Makefile
  14. README.md
README.md

UETRV-ecore

Here is the toplevel block diagram of ECORE.

alt text