commit: 47617a4cfb40aa6f7537858a7c185e3c0eefc164
[log] [tgz]
author: Ali Imran <ali112000@pop-os.localdomain>
Sun Apr 03 05:12:52 2022 +0500
committer: Ali Imran <ali112000@pop-os.localdomain>
Sun Apr 03 05:12:52 2022 +0500
tree: 1f98fa546e9605aef8821c13428fa3dbcd2ee836
parent: 658214eff988d90c560d03a8e05f71036ddb95a8 [diff]

Verilog files Updated

maglef/Core.mag[Deleted - diff]
maglef/Motor_Top.mag[Deleted - diff]
maglef/WB_InterConnect.mag[Deleted - diff]
maglef/user_proj_example.mag[Deleted - diff]
maglef/user_project_wrapper.mag[Deleted - diff]
openlane/.gitignore[Deleted - diff]
openlane/Core/config.tcl[Deleted - diff]
openlane/Core/pin_order.cfg[Deleted - diff]
openlane/Makefile[Deleted - diff]
openlane/Motor_Top/config.tcl[Deleted - diff]
openlane/Motor_Top/pin_order.cfg[Deleted - diff]
openlane/Wishbone_InterConnect/config.tcl[Deleted - diff]
openlane/Wishbone_InterConnect/pin_order.cfg[Deleted - diff]
openlane/user_proj_example/config.json[Deleted - diff]
openlane/user_proj_example/config.tcl[Deleted - diff]
openlane/user_proj_example/pin_order.cfg[Deleted - diff]
openlane/user_project_wrapper/config.json[Deleted - diff]
openlane/user_project_wrapper/config.tcl[Deleted - diff]
openlane/user_project_wrapper/macro.cfg[Deleted - diff]
openlane/user_project_wrapper/pin_order.cfg[Deleted - diff]
signoff/Core/OPENLANE_VERSION[Deleted - diff]
signoff/Core/PDK_SOURCES[Deleted - diff]
signoff/Core/final_summary_report.csv[Deleted - diff]
signoff/Motor_Top/OPENLANE_VERSION[Deleted - diff]
signoff/Motor_Top/PDK_SOURCES[Deleted - diff]
signoff/Motor_Top/final_summary_report.csv[Deleted - diff]
signoff/Wishbone_InterConnect/OPENLANE_VERSION[Deleted - diff]
signoff/Wishbone_InterConnect/PDK_SOURCES[Deleted - diff]
signoff/Wishbone_InterConnect/final_summary_report.csv[Deleted - diff]
signoff/user_proj_example/OPENLANE_VERSION[Deleted - diff]
signoff/user_proj_example/PDK_SOURCES[Deleted - diff]
signoff/user_proj_example/final_summary_report.csv[Deleted - diff]
signoff/user_project_wrapper/OPENLANE_VERSION[Deleted - diff]
signoff/user_project_wrapper/PDK_SOURCES[Deleted - diff]
signoff/user_project_wrapper/final_summary_report.csv[Deleted - diff]
spi/lvs/Core.spice[Deleted - diff]
spi/lvs/Motor_Top.spice[Deleted - diff]
spi/lvs/WB_InterConnect.spice[Deleted - diff]
spi/lvs/user_project_wrapper.spice[Deleted - diff]
verilog/rtl/Core.v[diff]
verilog/rtl/Motor_Top.v[diff]
verilog/rtl/WB_InterConnect.v[diff]

42 files changed

tree: 1f98fa546e9605aef8821c13428fa3dbcd2ee836

README.md

UETRV-ecore

Here is the toplevel block diagram of ECORE.

alt text