Google Git
Sign in
foss-eda-tools/third_party/shuttle/sky130/mpw-005/slot-036/393f260c0d2fcda2e0df6a36fa04b020e8eb26e2/./verilog/rtl
tree: 762cefbf7adaab2f057501f8f7d7ee2de0f19fd7 [path history] [tgz]
  1. BMem.v
  2. Core.v
  3. DMem_Interface.v
  4. IMem_Interface.v
  5. Motor_Top.v
  6. Processor_Tile.v
  7. sky130_sram_1kbyte_1rw1r_32x256_8.v
  8. sky130_sram_2kbyte_1rw1r_32x512_8.v
  9. SPI.v
  10. UART.v
  11. uprj_netlists.v
  12. user_proj_example.v
  13. user_project_wrapper.v
  14. WB_Interconnect.v
  15. WBM_DBus.v