commit	6757540dc259f6dd2cf877b920c65725921b13e6	[log] [tgz]
author	Ali Imran <ali1120001@outlook.com>	Sun Mar 20 09:55:07 2022 +0500
committer	Ali Imran <ali1120001@outlook.com>	Sun Mar 20 09:55:07 2022 +0500
tree	d28d85a3698cb7433d55cfc99aa5ab2cf55aef78
parent	f0972d5de4fac9f2e94004dc5db917fbd80eefb1 [diff]

WB_Interconnect Verilog updated

verilog/rtl/WB_InterConnect.v[Renamed from verilog/dv/WB_InterConnect.v - diff]

1 file changed

tree: d28d85a3698cb7433d55cfc99aa5ab2cf55aef78

README.md

UETRV-ecore

Here is the toplevel block diagram of ECORE

alt text

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for a quick start of how to use caravel_user_project

Refer to README for this sample project documentation.