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foss-eda-tools / third_party / shuttle / sky130 / mpw-005 / slot-036 / 333db4364fd4e89840832e9d165fb161b6851f56
commit333db4364fd4e89840832e9d165fb161b6851f56[log] [tgz]
authorAli Imran <ali1120001@outlook.com>Fri Mar 18 16:40:57 2022 +0500
committerAli Imran <ali1120001@outlook.com>Fri Mar 18 16:40:57 2022 +0500
tree2fa204fb2eeb981f48b77e6bceb34be8020b44ed
parent30864c733615b95fca915e6e1bd7ec7d7b9875ab [diff]
SPI Verilog added
1 file changed
tree: 2fa204fb2eeb981f48b77e6bceb34be8020b44ed
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. sdc/
  10. sdf/
  11. signoff/
  12. spef/
  13. spi/
  14. verilog/
  15. caravel
  16. .gitignore
  17. LICENSE
  18. Makefile
  19. README.md
README.md

UETRV-ecore

Here is the toplevel block diagram of ECORE

alt text

Caravel User Project

License UPRJ_CI Caravel Build

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for a quick start of how to use caravel_user_project

Refer to README for this sample project documentation.